src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "pipebuffer/pb_bufmgr.h"
  39 #include "util/u_memory.h"
  40
  41 #include <xf86drm.h>
  42 #include <stdio.h>
  43
  44 #ifndef RADEON_INFO_TILING_CONFIG
  45 #define RADEON_INFO_TILING_CONFIG 6
  46 #endif
  47
  48 #ifndef RADEON_INFO_WANT_HYPERZ
  49 #define RADEON_INFO_WANT_HYPERZ 7
  50 #endif
  51
  52 #ifndef RADEON_INFO_WANT_CMASK
  53 #define RADEON_INFO_WANT_CMASK 8
  54 #endif
  55
  56 #ifndef RADEON_INFO_CLOCK_CRYSTAL_FREQ
  57 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 9
  58 #endif
  59
  60 #ifndef RADEON_INFO_NUM_BACKENDS
  61 #define RADEON_INFO_NUM_BACKENDS 0xa
  62 #endif
  63
  64 #ifndef RADEON_INFO_NUM_TILE_PIPES
  65 #define RADEON_INFO_NUM_TILE_PIPES 0xb
  66 #endif
  67
  68 #ifndef RADEON_INFO_BACKEND_MAP
  69 #define RADEON_INFO_BACKEND_MAP 0xd
  70 #endif
  71
  72 /* Enable/disable feature access for one command stream.
  73  * If enable == TRUE, return TRUE on success.
  74  * Otherwise, return FALSE.
  75  *
  76  * We basically do the same thing kernel does, because we have to deal
  77  * with multiple contexts (here command streams) backed by one winsys. */
  78 static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
  79                                     struct radeon_drm_cs **owner,
  80                                     pipe_mutex *mutex,
  81                                     unsigned request, boolean enable)
  82 {
  83     struct drm_radeon_info info;
  84     unsigned value = enable ? 1 : 0;
  85
  86     memset(&info, 0, sizeof(info));
  87
  88     pipe_mutex_lock(*mutex);
  89
  90     /* Early exit if we are sure the request will fail. */
  91     if (enable) {
  92         if (*owner) {
  93             pipe_mutex_unlock(*mutex);
  94             return FALSE;
  95         }
  96     } else {
  97         if (*owner != applier) {
  98             pipe_mutex_unlock(*mutex);
  99             return FALSE;
 100         }
 101     }
 102
 103     /* Pass through the request to the kernel. */
 104     info.value = (unsigned long)&value;
 105     info.request = request;
 106     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
 107                             &info, sizeof(info)) != 0) {
 108         pipe_mutex_unlock(*mutex);
 109         return FALSE;
 110     }
 111
 112     /* Update the rights in the winsys. */
 113     if (enable) {
 114         if (value) {
 115             *owner = applier;
 116             fprintf(stderr, "radeon: Acquired Hyper-Z.\n");
 117             pipe_mutex_unlock(*mutex);
 118             return TRUE;
 119         }
 120     } else {
 121         *owner = NULL;
 122         fprintf(stderr, "radeon: Released Hyper-Z.\n");
 123     }
 124
 125     pipe_mutex_unlock(*mutex);
 126     return FALSE;
 127 }
 128
 129 static boolean radeon_get_drm_value(int fd, unsigned request,
 130                                     const char *errname, uint32_t *out)
 131 {
 132     struct drm_radeon_info info;
 133     int retval;
 134
 135     memset(&info, 0, sizeof(info));
 136
 137     info.value = (unsigned long)out;
 138     info.request = request;
 139
 140     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 141     if (retval && errname) {
 142         fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 143                 errname, retval);
 144         return FALSE;
 145     }
 146     return TRUE;
 147 }
 148
 149 /* Helper function to do the ioctls needed for setup and init. */
 150 static boolean do_winsys_init(struct radeon_drm_winsys *ws)
 151 {
 152     struct drm_radeon_gem_info gem_info;
 153     int retval;
 154     drmVersionPtr version;
 155
 156     memset(&gem_info, 0, sizeof(gem_info));
 157
 158     /* We do things in a specific order here.
 159      *
 160      * DRM version first. We need to be sure we're running on a KMS chipset.
 161      * This is also for some features.
 162      *
 163      * Then, the PCI ID. This is essential and should return usable numbers
 164      * for all Radeons. If this fails, we probably got handed an FD for some
 165      * non-Radeon card.
 166      *
 167      * The GEM info is actually bogus on the kernel side, as well as our side
 168      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 169      * we don't actually use the info for anything yet.
 170      *
 171      * The GB and Z pipe requests should always succeed, but they might not
 172      * return sensical values for all chipsets, but that's alright because
 173      * the pipe drivers already know that.
 174      */
 175
 176     /* Get DRM version. */
 177     version = drmGetVersion(ws->fd);
 178     if (version->version_major != 2 ||
 179         version->version_minor < 3) {
 180         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 181                 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
 182                 __FUNCTION__,
 183                 version->version_major,
 184                 version->version_minor,
 185                 version->version_patchlevel);
 186         drmFreeVersion(version);
 187         return FALSE;
 188     }
 189
 190     ws->info.drm_major = version->version_major;
 191     ws->info.drm_minor = version->version_minor;
 192     ws->info.drm_patchlevel = version->version_patchlevel;
 193     drmFreeVersion(version);
 194
 195     /* Get PCI ID. */
 196     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 197                               &ws->info.pci_id))
 198         return FALSE;
 199
 200     /* Check PCI ID. */
 201     switch (ws->info.pci_id) {
 202 #define CHIPSET(pci_id, name, family) case pci_id:
 203 #include "pci_ids/r300_pci_ids.h"
 204 #undef CHIPSET
 205         ws->gen = R300;
 206         break;
 207
 208 #define CHIPSET(pci_id, name, family) case pci_id:
 209 #include "pci_ids/r600_pci_ids.h"
 210 #undef CHIPSET
 211         ws->gen = R600;
 212         break;
 213
 214     default:
 215         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 216         return FALSE;
 217     }
 218
 219     /* Get GEM info. */
 220     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 221             &gem_info, sizeof(gem_info));
 222     if (retval) {
 223         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 224                 retval);
 225         return FALSE;
 226     }
 227     ws->info.gart_size = gem_info.gart_size;
 228     ws->info.vram_size = gem_info.vram_size;
 229
 230     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 231
 232     /* Generation-specific queries. */
 233     if (ws->gen == R300) {
 234         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 235                                   "GB pipe count",
 236                                   &ws->info.r300_num_gb_pipes))
 237             return FALSE;
 238
 239         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 240                                   "Z pipe count",
 241                                   &ws->info.r300_num_z_pipes))
 242             return FALSE;
 243     }
 244     else if (ws->gen == R600) {
 245         if (ws->info.drm_minor >= 9 &&
 246             !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 247                                   "num backends",
 248                                   &ws->info.r600_num_backends))
 249             return FALSE;
 250
 251         /* get the GPU counter frequency, failure is not fatal */
 252         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 253                              &ws->info.r600_clock_crystal_freq);
 254
 255         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 256                              &ws->info.r600_tiling_config);
 257
 258         if (ws->info.drm_minor >= 11) {
 259             radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 260                                  &ws->info.r600_num_tile_pipes);
 261
 262             if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 263                                       &ws->info.r600_backend_map))
 264                 ws->info.r600_backend_map_valid = TRUE;
 265         }
 266     }
 267
 268     return TRUE;
 269 }
 270
 271 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 272 {
 273     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 274
 275     pipe_mutex_destroy(ws->hyperz_owner_mutex);
 276     pipe_mutex_destroy(ws->cmask_owner_mutex);
 277
 278     ws->cman->destroy(ws->cman);
 279     ws->kman->destroy(ws->kman);
 280     FREE(rws);
 281 }
 282
 283 static void radeon_query_info(struct radeon_winsys *rws,
 284                               struct radeon_info *info)
 285 {
 286     *info = ((struct radeon_drm_winsys *)rws)->info;
 287 }
 288
 289 static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 290                                          enum radeon_feature_id fid,
 291                                          boolean enable)
 292 {
 293     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 294
 295     switch (fid) {
 296     case RADEON_FID_R300_HYPERZ_ACCESS:
 297         if (debug_get_bool_option("RADEON_HYPERZ", FALSE)) {
 298             return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 299                                         &cs->ws->hyperz_owner_mutex,
 300                                         RADEON_INFO_WANT_HYPERZ, enable);
 301         } else {
 302             return FALSE;
 303         }
 304
 305     case RADEON_FID_R300_CMASK_ACCESS:
 306         if (debug_get_bool_option("RADEON_CMASK", FALSE)) {
 307             return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 308                                         &cs->ws->cmask_owner_mutex,
 309                                         RADEON_INFO_WANT_CMASK, enable);
 310         } else {
 311             return FALSE;
 312         }
 313     }
 314     return FALSE;
 315 }
 316
 317 struct radeon_winsys *radeon_drm_winsys_create(int fd)
 318 {
 319     struct radeon_drm_winsys *ws = CALLOC_STRUCT(radeon_drm_winsys);
 320     if (!ws) {
 321         return NULL;
 322     }
 323
 324     ws->fd = fd;
 325
 326     if (!do_winsys_init(ws))
 327         goto fail;
 328
 329     /* Create managers. */
 330     ws->kman = radeon_bomgr_create(ws);
 331     if (!ws->kman)
 332         goto fail;
 333     ws->cman = pb_cache_manager_create(ws->kman, 1000000);
 334     if (!ws->cman)
 335         goto fail;
 336
 337     /* Set functions. */
 338     ws->base.destroy = radeon_winsys_destroy;
 339     ws->base.query_info = radeon_query_info;
 340     ws->base.cs_request_feature = radeon_cs_request_feature;
 341
 342     radeon_bomgr_init_functions(ws);
 343     radeon_drm_cs_init_functions(ws);
 344
 345     pipe_mutex_init(ws->hyperz_owner_mutex);
 346     pipe_mutex_init(ws->cmask_owner_mutex);
 347
 348     return &ws->base;
 349
 350 fail:
 351     if (ws->cman)
 352         ws->cman->destroy(ws->cman);
 353     if (ws->kman)
 354         ws->kman->destroy(ws->kman);
 355     FREE(ws);
 356     return NULL;
 357 }