src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27
  28 #include "radeon_drm_bo.h"
  29 #include "radeon_drm_cs.h"
  30 #include "radeon_drm_public.h"
  31
  32 #include "util/u_memory.h"
  33 #include "util/u_hash_table.h"
  34
  35 #include <xf86drm.h>
  36 #include <stdio.h>
  37 #include <sys/types.h>
  38 #include <sys/stat.h>
  39 #include <unistd.h>
  40 #include <fcntl.h>
  41 #include <radeon_surface.h>
  42
  43 static struct util_hash_table *fd_tab = NULL;
  44 static mtx_t fd_tab_mutex = _MTX_INITIALIZER_NP;
  45
  46 /* Enable/disable feature access for one command stream.
  47  * If enable == true, return true on success.
  48  * Otherwise, return false.
  49  *
  50  * We basically do the same thing kernel does, because we have to deal
  51  * with multiple contexts (here command streams) backed by one winsys. */
  52 static bool radeon_set_fd_access(struct radeon_drm_cs *applier,
  53                                  struct radeon_drm_cs **owner,
  54                                  mtx_t *mutex,
  55                                  unsigned request, const char *request_name,
  56                                  bool enable)
  57 {
  58     struct drm_radeon_info info;
  59     unsigned value = enable ? 1 : 0;
  60
  61     memset(&info, 0, sizeof(info));
  62
  63     mtx_lock(&*mutex);
  64
  65     /* Early exit if we are sure the request will fail. */
  66     if (enable) {
  67         if (*owner) {
  68             mtx_unlock(&*mutex);
  69             return false;
  70         }
  71     } else {
  72         if (*owner != applier) {
  73             mtx_unlock(&*mutex);
  74             return false;
  75         }
  76     }
  77
  78     /* Pass through the request to the kernel. */
  79     info.value = (unsigned long)&value;
  80     info.request = request;
  81     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
  82                             &info, sizeof(info)) != 0) {
  83         mtx_unlock(&*mutex);
  84         return false;
  85     }
  86
  87     /* Update the rights in the winsys. */
  88     if (enable) {
  89         if (value) {
  90             *owner = applier;
  91             mtx_unlock(&*mutex);
  92             return true;
  93         }
  94     } else {
  95         *owner = NULL;
  96     }
  97
  98     mtx_unlock(&*mutex);
  99     return false;
 100 }
 101
 102 static bool radeon_get_drm_value(int fd, unsigned request,
 103                                  const char *errname, uint32_t *out)
 104 {
 105     struct drm_radeon_info info;
 106     int retval;
 107
 108     memset(&info, 0, sizeof(info));
 109
 110     info.value = (unsigned long)out;
 111     info.request = request;
 112
 113     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 114     if (retval) {
 115         if (errname) {
 116             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 117                     errname, retval);
 118         }
 119         return false;
 120     }
 121     return true;
 122 }
 123
 124 /* Helper function to do the ioctls needed for setup and init. */
 125 static bool do_winsys_init(struct radeon_drm_winsys *ws)
 126 {
 127     struct drm_radeon_gem_info gem_info;
 128     int retval;
 129     drmVersionPtr version;
 130
 131     memset(&gem_info, 0, sizeof(gem_info));
 132
 133     /* We do things in a specific order here.
 134      *
 135      * DRM version first. We need to be sure we're running on a KMS chipset.
 136      * This is also for some features.
 137      *
 138      * Then, the PCI ID. This is essential and should return usable numbers
 139      * for all Radeons. If this fails, we probably got handed an FD for some
 140      * non-Radeon card.
 141      *
 142      * The GEM info is actually bogus on the kernel side, as well as our side
 143      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 144      * we don't actually use the info for anything yet.
 145      *
 146      * The GB and Z pipe requests should always succeed, but they might not
 147      * return sensical values for all chipsets, but that's alright because
 148      * the pipe drivers already know that.
 149      */
 150
 151     /* Get DRM version. */
 152     version = drmGetVersion(ws->fd);
 153     if (version->version_major != 2 ||
 154         version->version_minor < 12) {
 155         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 156                 "only compatible with 2.12.0 (kernel 3.2) or later.\n",
 157                 __FUNCTION__,
 158                 version->version_major,
 159                 version->version_minor,
 160                 version->version_patchlevel);
 161         drmFreeVersion(version);
 162         return false;
 163     }
 164
 165     ws->info.drm_major = version->version_major;
 166     ws->info.drm_minor = version->version_minor;
 167     ws->info.drm_patchlevel = version->version_patchlevel;
 168     drmFreeVersion(version);
 169
 170     /* Get PCI ID. */
 171     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 172                               &ws->info.pci_id))
 173         return false;
 174
 175     /* Check PCI ID. */
 176     switch (ws->info.pci_id) {
 177 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 178 #include "pci_ids/r300_pci_ids.h"
 179 #undef CHIPSET
 180
 181 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 182 #include "pci_ids/r600_pci_ids.h"
 183 #undef CHIPSET
 184
 185 #define CHIPSET(pci_id, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 186 #include "pci_ids/radeonsi_pci_ids.h"
 187 #undef CHIPSET
 188
 189     default:
 190         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 191         return false;
 192     }
 193
 194     switch (ws->info.family) {
 195     default:
 196     case CHIP_UNKNOWN:
 197         fprintf(stderr, "radeon: Unknown family.\n");
 198         return false;
 199     case CHIP_R300:
 200     case CHIP_R350:
 201     case CHIP_RV350:
 202     case CHIP_RV370:
 203     case CHIP_RV380:
 204     case CHIP_RS400:
 205     case CHIP_RC410:
 206     case CHIP_RS480:
 207         ws->info.chip_class = R300;
 208         break;
 209     case CHIP_R420:     /* R4xx-based cores. */
 210     case CHIP_R423:
 211     case CHIP_R430:
 212     case CHIP_R480:
 213     case CHIP_R481:
 214     case CHIP_RV410:
 215     case CHIP_RS600:
 216     case CHIP_RS690:
 217     case CHIP_RS740:
 218         ws->info.chip_class = R400;
 219         break;
 220     case CHIP_RV515:    /* R5xx-based cores. */
 221     case CHIP_R520:
 222     case CHIP_RV530:
 223     case CHIP_R580:
 224     case CHIP_RV560:
 225     case CHIP_RV570:
 226         ws->info.chip_class = R500;
 227         break;
 228     case CHIP_R600:
 229     case CHIP_RV610:
 230     case CHIP_RV630:
 231     case CHIP_RV670:
 232     case CHIP_RV620:
 233     case CHIP_RV635:
 234     case CHIP_RS780:
 235     case CHIP_RS880:
 236         ws->info.chip_class = R600;
 237         break;
 238     case CHIP_RV770:
 239     case CHIP_RV730:
 240     case CHIP_RV710:
 241     case CHIP_RV740:
 242         ws->info.chip_class = R700;
 243         break;
 244     case CHIP_CEDAR:
 245     case CHIP_REDWOOD:
 246     case CHIP_JUNIPER:
 247     case CHIP_CYPRESS:
 248     case CHIP_HEMLOCK:
 249     case CHIP_PALM:
 250     case CHIP_SUMO:
 251     case CHIP_SUMO2:
 252     case CHIP_BARTS:
 253     case CHIP_TURKS:
 254     case CHIP_CAICOS:
 255         ws->info.chip_class = EVERGREEN;
 256         break;
 257     case CHIP_CAYMAN:
 258     case CHIP_ARUBA:
 259         ws->info.chip_class = CAYMAN;
 260         break;
 261     case CHIP_TAHITI:
 262     case CHIP_PITCAIRN:
 263     case CHIP_VERDE:
 264     case CHIP_OLAND:
 265     case CHIP_HAINAN:
 266         ws->info.chip_class = SI;
 267         break;
 268     case CHIP_BONAIRE:
 269     case CHIP_KAVERI:
 270     case CHIP_KABINI:
 271     case CHIP_HAWAII:
 272     case CHIP_MULLINS:
 273         ws->info.chip_class = CIK;
 274         break;
 275     }
 276
 277     /* Set which chips don't have dedicated VRAM. */
 278     switch (ws->info.family) {
 279     case CHIP_RS400:
 280     case CHIP_RC410:
 281     case CHIP_RS480:
 282     case CHIP_RS600:
 283     case CHIP_RS690:
 284     case CHIP_RS740:
 285     case CHIP_RS780:
 286     case CHIP_RS880:
 287     case CHIP_PALM:
 288     case CHIP_SUMO:
 289     case CHIP_SUMO2:
 290     case CHIP_ARUBA:
 291     case CHIP_KAVERI:
 292     case CHIP_KABINI:
 293     case CHIP_MULLINS:
 294        ws->info.has_dedicated_vram = false;
 295        break;
 296
 297     default:
 298        ws->info.has_dedicated_vram = true;
 299     }
 300
 301     /* Check for dma */
 302     ws->info.num_sdma_rings = 0;
 303     /* DMA is disabled on R700. There is IB corruption and hangs. */
 304     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 305         ws->info.num_sdma_rings = 1;
 306     }
 307
 308     /* Check for UVD and VCE */
 309     ws->info.has_hw_decode = false;
 310     ws->info.vce_fw_version = 0x00000000;
 311     if (ws->info.drm_minor >= 32) {
 312         uint32_t value = RADEON_CS_RING_UVD;
 313         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 314                                  "UVD Ring working", &value))
 315             ws->info.has_hw_decode = value;
 316
 317         value = RADEON_CS_RING_VCE;
 318         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 319                                  NULL, &value) && value) {
 320
 321             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 322                                      "VCE FW version", &value))
 323                 ws->info.vce_fw_version = value;
 324         }
 325     }
 326
 327     /* Check for userptr support. */
 328     {
 329         struct drm_radeon_gem_userptr args = {0};
 330
 331         /* If the ioctl doesn't exist, -EINVAL is returned.
 332          *
 333          * If the ioctl exists, it should return -EACCES
 334          * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
 335          * aren't set.
 336          */
 337         ws->info.has_userptr =
 338             drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
 339                                 &args, sizeof(args)) == -EACCES;
 340     }
 341
 342     /* Get GEM info. */
 343     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 344             &gem_info, sizeof(gem_info));
 345     if (retval) {
 346         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 347                 retval);
 348         return false;
 349     }
 350     ws->info.gart_size = gem_info.gart_size;
 351     ws->info.vram_size = gem_info.vram_size;
 352     ws->info.vram_vis_size = gem_info.vram_visible;
 353     /* Older versions of the kernel driver reported incorrect values, and
 354      * didn't support more than 256MB of visible VRAM anyway
 355      */
 356     if (ws->info.drm_minor < 49)
 357         ws->info.vram_vis_size = MIN2(ws->info.vram_vis_size, 256*1024*1024);
 358
 359     /* Radeon allocates all buffers as contigous, which makes large allocations
 360      * unlikely to succeed. */
 361     ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 0.7;
 362     if (ws->info.has_dedicated_vram)
 363         ws->info.max_alloc_size = MIN2(ws->info.vram_size * 0.7, ws->info.max_alloc_size);
 364     if (ws->info.drm_minor < 40)
 365         ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
 366     /* Both 32-bit and 64-bit address spaces only have 4GB. */
 367     ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 3ull*1024*1024*1024);
 368
 369     /* Get max clock frequency info and convert it to MHz */
 370     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 371                          &ws->info.max_shader_clock);
 372     ws->info.max_shader_clock /= 1000;
 373
 374     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 375
 376     /* Generation-specific queries. */
 377     if (ws->gen == DRV_R300) {
 378         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 379                                   "GB pipe count",
 380                                   &ws->info.r300_num_gb_pipes))
 381             return false;
 382
 383         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 384                                   "Z pipe count",
 385                                   &ws->info.r300_num_z_pipes))
 386             return false;
 387     }
 388     else if (ws->gen >= DRV_R600) {
 389         uint32_t tiling_config = 0;
 390
 391         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 392                                   "num backends",
 393                                   &ws->info.num_render_backends))
 394             return false;
 395
 396         /* get the GPU counter frequency, failure is not fatal */
 397         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 398                              &ws->info.clock_crystal_freq);
 399
 400         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 401                              &tiling_config);
 402
 403         ws->info.r600_num_banks =
 404             ws->info.chip_class >= EVERGREEN ?
 405                 4 << ((tiling_config & 0xf0) >> 4) :
 406                 4 << ((tiling_config & 0x30) >> 4);
 407
 408         ws->info.pipe_interleave_bytes =
 409             ws->info.chip_class >= EVERGREEN ?
 410                 256 << ((tiling_config & 0xf00) >> 8) :
 411                 256 << ((tiling_config & 0xc0) >> 6);
 412
 413         if (!ws->info.pipe_interleave_bytes)
 414             ws->info.pipe_interleave_bytes =
 415                 ws->info.chip_class >= EVERGREEN ? 512 : 256;
 416
 417         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 418                              &ws->info.num_tile_pipes);
 419
 420         /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
 421          * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
 422          * reports a different value (12). Fix it by setting what's in the
 423          * GB_TILE_MODE array (8).
 424          */
 425         if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
 426             ws->info.num_tile_pipes = 8;
 427
 428         if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 429                                   &ws->info.r600_gb_backend_map))
 430             ws->info.r600_gb_backend_map_valid = true;
 431
 432         /* Default value. */
 433         ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.num_render_backends);
 434         /*
 435          * This fails (silently) on non-GCN or older kernels, overwriting the
 436          * default enabled_rb_mask with the result of the last query.
 437         */
 438         if (ws->gen >= DRV_SI)
 439             radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
 440                                  &ws->info.enabled_rb_mask);
 441
 442         ws->info.r600_has_virtual_memory = false;
 443         if (ws->info.drm_minor >= 13) {
 444             uint32_t ib_vm_max_size;
 445
 446             ws->info.r600_has_virtual_memory = true;
 447             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 448                                       &ws->va_start))
 449                 ws->info.r600_has_virtual_memory = false;
 450             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 451                                       &ib_vm_max_size))
 452                 ws->info.r600_has_virtual_memory = false;
 453             radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
 454                                  &ws->va_unmap_working);
 455         }
 456         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false))
 457                 ws->info.r600_has_virtual_memory = false;
 458     }
 459
 460     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 461      * chips have at least 2 pipes, so we use 2 as a default. */
 462     ws->info.r600_max_quad_pipes = 2;
 463     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 464                          &ws->info.r600_max_quad_pipes);
 465
 466     /* All GPUs have at least one compute unit */
 467     ws->info.num_good_compute_units = 1;
 468     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 469                          &ws->info.num_good_compute_units);
 470
 471     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 472                          &ws->info.max_se);
 473
 474     switch (ws->info.family) {
 475     case CHIP_HAINAN:
 476     case CHIP_KABINI:
 477     case CHIP_MULLINS:
 478         ws->info.num_tcc_blocks = 2;
 479         break;
 480     case CHIP_VERDE:
 481     case CHIP_OLAND:
 482     case CHIP_BONAIRE:
 483     case CHIP_KAVERI:
 484         ws->info.num_tcc_blocks = 4;
 485         break;
 486     case CHIP_PITCAIRN:
 487         ws->info.num_tcc_blocks = 8;
 488         break;
 489     case CHIP_TAHITI:
 490         ws->info.num_tcc_blocks = 12;
 491         break;
 492     case CHIP_HAWAII:
 493         ws->info.num_tcc_blocks = 16;
 494         break;
 495     default:
 496         ws->info.num_tcc_blocks = 0;
 497         break;
 498     }
 499
 500     if (!ws->info.max_se) {
 501         switch (ws->info.family) {
 502         default:
 503             ws->info.max_se = 1;
 504             break;
 505         case CHIP_CYPRESS:
 506         case CHIP_HEMLOCK:
 507         case CHIP_BARTS:
 508         case CHIP_CAYMAN:
 509         case CHIP_TAHITI:
 510         case CHIP_PITCAIRN:
 511         case CHIP_BONAIRE:
 512             ws->info.max_se = 2;
 513             break;
 514         case CHIP_HAWAII:
 515             ws->info.max_se = 4;
 516             break;
 517         }
 518     }
 519
 520     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 521                          &ws->info.max_sh_per_se);
 522
 523     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 524                          &ws->accel_working2);
 525     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 526         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 527                 "returned accel_working2 value %u is smaller than 2. "
 528                 "Please install a newer kernel.\n",
 529                 ws->accel_working2);
 530         return false;
 531     }
 532
 533     if (ws->info.chip_class == CIK) {
 534         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 535                                   ws->info.cik_macrotile_mode_array)) {
 536             fprintf(stderr, "radeon: Kernel 3.13 is required for CIK support.\n");
 537             return false;
 538         }
 539     }
 540
 541     if (ws->info.chip_class >= SI) {
 542         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 543                                   ws->info.si_tile_mode_array)) {
 544             fprintf(stderr, "radeon: Kernel 3.10 is required for SI support.\n");
 545             return false;
 546         }
 547     }
 548
 549     /* Hawaii with old firmware needs type2 nop packet.
 550      * accel_working2 with value 3 indicates the new firmware.
 551      */
 552     ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI ||
 553                                      (ws->info.family == CHIP_HAWAII &&
 554                                       ws->accel_working2 < 3);
 555     ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
 556     ws->info.ib_start_alignment = 4096;
 557     ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
 558     /* HTILE is broken with 1D tiling on old kernels and CIK. */
 559     ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
 560                                              ws->info.drm_minor >= 38;
 561     ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
 562     ws->info.has_bo_metadata = false;
 563     ws->info.has_gpu_reset_status_query = false;
 564     ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
 565     ws->info.has_eqaa_surface_allocator = false;
 566     ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
 567     ws->info.kernel_flushes_tc_l2_after_ib = true;
 568     /* Old kernels disallowed register writes via COPY_DATA
 569      * that are used for indirect compute dispatches. */
 570     ws->info.has_indirect_compute_dispatch = ws->info.chip_class == CIK ||
 571                                              (ws->info.chip_class == SI &&
 572                                               ws->info.drm_minor >= 45);
 573     /* SI doesn't support unaligned loads. */
 574     ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK &&
 575                                           ws->info.drm_minor >= 50;
 576     ws->info.has_sparse_vm_mappings = false;
 577     /* 2D tiling on CIK is supported since DRM 2.35.0 */
 578     ws->info.has_2d_tiling = ws->info.chip_class <= SI || ws->info.drm_minor >= 35;
 579     ws->info.has_read_registers_query = ws->info.drm_minor >= 42;
 580
 581     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
 582
 583     return true;
 584 }
 585
 586 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 587 {
 588     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 589
 590     if (util_queue_is_initialized(&ws->cs_queue))
 591         util_queue_destroy(&ws->cs_queue);
 592
 593     mtx_destroy(&ws->hyperz_owner_mutex);
 594     mtx_destroy(&ws->cmask_owner_mutex);
 595
 596     if (ws->info.r600_has_virtual_memory)
 597         pb_slabs_deinit(&ws->bo_slabs);
 598     pb_cache_deinit(&ws->bo_cache);
 599
 600     if (ws->gen >= DRV_R600) {
 601         radeon_surface_manager_free(ws->surf_man);
 602     }
 603
 604     util_hash_table_destroy(ws->bo_names);
 605     util_hash_table_destroy(ws->bo_handles);
 606     util_hash_table_destroy(ws->bo_vas);
 607     mtx_destroy(&ws->bo_handles_mutex);
 608     mtx_destroy(&ws->vm32.mutex);
 609     mtx_destroy(&ws->vm64.mutex);
 610     mtx_destroy(&ws->bo_fence_lock);
 611
 612     if (ws->fd >= 0)
 613         close(ws->fd);
 614
 615     FREE(rws);
 616 }
 617
 618 static void radeon_query_info(struct radeon_winsys *rws,
 619                               struct radeon_info *info)
 620 {
 621     *info = ((struct radeon_drm_winsys *)rws)->info;
 622 }
 623
 624 static bool radeon_cs_request_feature(struct radeon_cmdbuf *rcs,
 625                                       enum radeon_feature_id fid,
 626                                       bool enable)
 627 {
 628     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 629
 630     switch (fid) {
 631     case RADEON_FID_R300_HYPERZ_ACCESS:
 632         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 633                                     &cs->ws->hyperz_owner_mutex,
 634                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 635                                     enable);
 636
 637     case RADEON_FID_R300_CMASK_ACCESS:
 638         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 639                                     &cs->ws->cmask_owner_mutex,
 640                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 641                                     enable);
 642     }
 643     return false;
 644 }
 645
 646 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 647                                    enum radeon_value_id value)
 648 {
 649     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 650     uint64_t retval = 0;
 651
 652     switch (value) {
 653     case RADEON_REQUESTED_VRAM_MEMORY:
 654         return ws->allocated_vram;
 655     case RADEON_REQUESTED_GTT_MEMORY:
 656         return ws->allocated_gtt;
 657     case RADEON_MAPPED_VRAM:
 658        return ws->mapped_vram;
 659     case RADEON_MAPPED_GTT:
 660        return ws->mapped_gtt;
 661     case RADEON_BUFFER_WAIT_TIME_NS:
 662         return ws->buffer_wait_time;
 663     case RADEON_NUM_MAPPED_BUFFERS:
 664         return ws->num_mapped_buffers;
 665     case RADEON_TIMESTAMP:
 666         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 667             assert(0);
 668             return 0;
 669         }
 670
 671         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 672                              (uint32_t*)&retval);
 673         return retval;
 674     case RADEON_NUM_GFX_IBS:
 675         return ws->num_gfx_IBs;
 676     case RADEON_NUM_SDMA_IBS:
 677         return ws->num_sdma_IBs;
 678     case RADEON_NUM_BYTES_MOVED:
 679         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 680                              "num-bytes-moved", (uint32_t*)&retval);
 681         return retval;
 682     case RADEON_NUM_EVICTIONS:
 683     case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 684     case RADEON_VRAM_VIS_USAGE:
 685     case RADEON_GFX_BO_LIST_COUNTER:
 686     case RADEON_GFX_IB_SIZE_COUNTER:
 687         return 0; /* unimplemented */
 688     case RADEON_VRAM_USAGE:
 689         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 690                              "vram-usage", (uint32_t*)&retval);
 691         return retval;
 692     case RADEON_GTT_USAGE:
 693         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 694                              "gtt-usage", (uint32_t*)&retval);
 695         return retval;
 696     case RADEON_GPU_TEMPERATURE:
 697         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
 698                              "gpu-temp", (uint32_t*)&retval);
 699         return retval;
 700     case RADEON_CURRENT_SCLK:
 701         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
 702                              "current-gpu-sclk", (uint32_t*)&retval);
 703         return retval;
 704     case RADEON_CURRENT_MCLK:
 705         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
 706                              "current-gpu-mclk", (uint32_t*)&retval);
 707         return retval;
 708     case RADEON_GPU_RESET_COUNTER:
 709         radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
 710                              "gpu-reset-counter", (uint32_t*)&retval);
 711         return retval;
 712     case RADEON_CS_THREAD_TIME:
 713         return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 714     }
 715     return 0;
 716 }
 717
 718 static bool radeon_read_registers(struct radeon_winsys *rws,
 719                                   unsigned reg_offset,
 720                                   unsigned num_registers, uint32_t *out)
 721 {
 722     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 723     unsigned i;
 724
 725     for (i = 0; i < num_registers; i++) {
 726         uint32_t reg = reg_offset + i*4;
 727
 728         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg))
 729             return false;
 730         out[i] = reg;
 731     }
 732     return true;
 733 }
 734
 735 static unsigned hash_fd(void *key)
 736 {
 737     int fd = pointer_to_intptr(key);
 738     struct stat stat;
 739     fstat(fd, &stat);
 740
 741     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 742 }
 743
 744 static int compare_fd(void *key1, void *key2)
 745 {
 746     int fd1 = pointer_to_intptr(key1);
 747     int fd2 = pointer_to_intptr(key2);
 748     struct stat stat1, stat2;
 749     fstat(fd1, &stat1);
 750     fstat(fd2, &stat2);
 751
 752     return stat1.st_dev != stat2.st_dev ||
 753            stat1.st_ino != stat2.st_ino ||
 754            stat1.st_rdev != stat2.st_rdev;
 755 }
 756
 757 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", true)
 758
 759 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 760 {
 761     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 762     bool destroy;
 763
 764     /* When the reference counter drops to zero, remove the fd from the table.
 765      * This must happen while the mutex is locked, so that
 766      * radeon_drm_winsys_create in another thread doesn't get the winsys
 767      * from the table when the counter drops to 0. */
 768     mtx_lock(&fd_tab_mutex);
 769
 770     destroy = pipe_reference(&rws->reference, NULL);
 771     if (destroy && fd_tab) {
 772         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 773         if (util_hash_table_count(fd_tab) == 0) {
 774            util_hash_table_destroy(fd_tab);
 775            fd_tab = NULL;
 776         }
 777     }
 778
 779     mtx_unlock(&fd_tab_mutex);
 780     return destroy;
 781 }
 782
 783 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 784
 785 static unsigned handle_hash(void *key)
 786 {
 787     return PTR_TO_UINT(key);
 788 }
 789
 790 static int handle_compare(void *key1, void *key2)
 791 {
 792     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 793 }
 794
 795 PUBLIC struct radeon_winsys *
 796 radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
 797                          radeon_screen_create_t screen_create)
 798 {
 799     struct radeon_drm_winsys *ws;
 800
 801     mtx_lock(&fd_tab_mutex);
 802     if (!fd_tab) {
 803         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 804     }
 805
 806     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 807     if (ws) {
 808         pipe_reference(NULL, &ws->reference);
 809         mtx_unlock(&fd_tab_mutex);
 810         return &ws->base;
 811     }
 812
 813     ws = CALLOC_STRUCT(radeon_drm_winsys);
 814     if (!ws) {
 815         mtx_unlock(&fd_tab_mutex);
 816         return NULL;
 817     }
 818
 819     ws->fd = fcntl(fd, F_DUPFD_CLOEXEC, 3);
 820
 821     if (!do_winsys_init(ws))
 822         goto fail1;
 823
 824     pb_cache_init(&ws->bo_cache, RADEON_MAX_CACHED_HEAPS,
 825                   500000, ws->check_vm ? 1.0f : 2.0f, 0,
 826                   MIN2(ws->info.vram_size, ws->info.gart_size),
 827                   radeon_bo_destroy,
 828                   radeon_bo_can_reclaim);
 829
 830     if (ws->info.r600_has_virtual_memory) {
 831         /* There is no fundamental obstacle to using slab buffer allocation
 832          * without GPUVM, but enabling it requires making sure that the drivers
 833          * honor the address offset.
 834          */
 835         if (!pb_slabs_init(&ws->bo_slabs,
 836                            RADEON_SLAB_MIN_SIZE_LOG2, RADEON_SLAB_MAX_SIZE_LOG2,
 837                            RADEON_MAX_SLAB_HEAPS,
 838                            ws,
 839                            radeon_bo_can_reclaim_slab,
 840                            radeon_bo_slab_alloc,
 841                            radeon_bo_slab_free))
 842             goto fail_cache;
 843
 844         ws->info.min_alloc_size = 1 << RADEON_SLAB_MIN_SIZE_LOG2;
 845     } else {
 846         ws->info.min_alloc_size = ws->info.gart_page_size;
 847     }
 848
 849     if (ws->gen >= DRV_R600) {
 850         ws->surf_man = radeon_surface_manager_new(ws->fd);
 851         if (!ws->surf_man)
 852             goto fail_slab;
 853     }
 854
 855     /* init reference */
 856     pipe_reference_init(&ws->reference, 1);
 857
 858     /* Set functions. */
 859     ws->base.unref = radeon_winsys_unref;
 860     ws->base.destroy = radeon_winsys_destroy;
 861     ws->base.query_info = radeon_query_info;
 862     ws->base.cs_request_feature = radeon_cs_request_feature;
 863     ws->base.query_value = radeon_query_value;
 864     ws->base.read_registers = radeon_read_registers;
 865
 866     radeon_drm_bo_init_functions(ws);
 867     radeon_drm_cs_init_functions(ws);
 868     radeon_surface_init_functions(ws);
 869
 870     (void) mtx_init(&ws->hyperz_owner_mutex, mtx_plain);
 871     (void) mtx_init(&ws->cmask_owner_mutex, mtx_plain);
 872
 873     ws->bo_names = util_hash_table_create(handle_hash, handle_compare);
 874     ws->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 875     ws->bo_vas = util_hash_table_create(handle_hash, handle_compare);
 876     (void) mtx_init(&ws->bo_handles_mutex, mtx_plain);
 877     (void) mtx_init(&ws->vm32.mutex, mtx_plain);
 878     (void) mtx_init(&ws->vm64.mutex, mtx_plain);
 879     (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
 880     list_inithead(&ws->vm32.holes);
 881     list_inithead(&ws->vm64.holes);
 882
 883     /* The kernel currently returns 8MB. Make sure this doesn't change. */
 884     if (ws->va_start > 8 * 1024 * 1024) {
 885         /* Not enough 32-bit address space. */
 886         radeon_winsys_destroy(&ws->base);
 887         mtx_unlock(&fd_tab_mutex);
 888         return NULL;
 889     }
 890
 891     ws->vm32.start = ws->va_start;
 892     ws->vm32.end = 1ull << 32;
 893
 894     /* The maximum is 8GB of virtual address space limited by the kernel.
 895      * It's obviously not enough for bigger cards, like Hawaiis with 4GB
 896      * and 8GB of physical memory and 4GB of GART.
 897      *
 898      * Older kernels set the limit to 4GB, which is even worse, so they only
 899      * have 32-bit address space.
 900      */
 901     if (ws->info.drm_minor >= 41) {
 902         ws->vm64.start = 1ull << 32;
 903         ws->vm64.end = 1ull << 33;
 904     }
 905
 906     /* TTM aligns the BO size to the CPU page size */
 907     ws->info.gart_page_size = sysconf(_SC_PAGESIZE);
 908
 909     if (ws->num_cpus > 1 && debug_get_option_thread())
 910         util_queue_init(&ws->cs_queue, "radeon_cs", 8, 1, 0);
 911
 912     /* Create the screen at the end. The winsys must be initialized
 913      * completely.
 914      *
 915      * Alternatively, we could create the screen based on "ws->gen"
 916      * and link all drivers into one binary blob. */
 917     ws->base.screen = screen_create(&ws->base, config);
 918     if (!ws->base.screen) {
 919         radeon_winsys_destroy(&ws->base);
 920         mtx_unlock(&fd_tab_mutex);
 921         return NULL;
 922     }
 923
 924     util_hash_table_set(fd_tab, intptr_to_pointer(ws->fd), ws);
 925
 926     /* We must unlock the mutex once the winsys is fully initialized, so that
 927      * other threads attempting to create the winsys from the same fd will
 928      * get a fully initialized winsys and not just half-way initialized. */
 929     mtx_unlock(&fd_tab_mutex);
 930
 931     return &ws->base;
 932
 933 fail_slab:
 934     if (ws->info.r600_has_virtual_memory)
 935         pb_slabs_deinit(&ws->bo_slabs);
 936 fail_cache:
 937     pb_cache_deinit(&ws->bo_cache);
 938 fail1:
 939     mtx_unlock(&fd_tab_mutex);
 940     if (ws->surf_man)
 941         radeon_surface_manager_free(ws->surf_man);
 942     if (ws->fd >= 0)
 943         close(ws->fd);
 944
 945     FREE(ws);
 946     return NULL;
 947 }