src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "util/u_memory.h"
  39 #include "util/u_hash_table.h"
  40
  41 #include <xf86drm.h>
  42 #include <stdio.h>
  43 #include <sys/types.h>
  44 #include <sys/stat.h>
  45 #include <unistd.h>
  46 #include <fcntl.h>
  47 #include <radeon_surface.h>
  48
  49 static struct util_hash_table *fd_tab = NULL;
  50 static mtx_t fd_tab_mutex = _MTX_INITIALIZER_NP;
  51
  52 /* Enable/disable feature access for one command stream.
  53  * If enable == true, return true on success.
  54  * Otherwise, return false.
  55  *
  56  * We basically do the same thing kernel does, because we have to deal
  57  * with multiple contexts (here command streams) backed by one winsys. */
  58 static bool radeon_set_fd_access(struct radeon_drm_cs *applier,
  59                                  struct radeon_drm_cs **owner,
  60                                  mtx_t *mutex,
  61                                  unsigned request, const char *request_name,
  62                                  bool enable)
  63 {
  64     struct drm_radeon_info info;
  65     unsigned value = enable ? 1 : 0;
  66
  67     memset(&info, 0, sizeof(info));
  68
  69     mtx_lock(&*mutex);
  70
  71     /* Early exit if we are sure the request will fail. */
  72     if (enable) {
  73         if (*owner) {
  74             mtx_unlock(&*mutex);
  75             return false;
  76         }
  77     } else {
  78         if (*owner != applier) {
  79             mtx_unlock(&*mutex);
  80             return false;
  81         }
  82     }
  83
  84     /* Pass through the request to the kernel. */
  85     info.value = (unsigned long)&value;
  86     info.request = request;
  87     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
  88                             &info, sizeof(info)) != 0) {
  89         mtx_unlock(&*mutex);
  90         return false;
  91     }
  92
  93     /* Update the rights in the winsys. */
  94     if (enable) {
  95         if (value) {
  96             *owner = applier;
  97             mtx_unlock(&*mutex);
  98             return true;
  99         }
 100     } else {
 101         *owner = NULL;
 102     }
 103
 104     mtx_unlock(&*mutex);
 105     return false;
 106 }
 107
 108 static bool radeon_get_drm_value(int fd, unsigned request,
 109                                  const char *errname, uint32_t *out)
 110 {
 111     struct drm_radeon_info info;
 112     int retval;
 113
 114     memset(&info, 0, sizeof(info));
 115
 116     info.value = (unsigned long)out;
 117     info.request = request;
 118
 119     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 120     if (retval) {
 121         if (errname) {
 122             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 123                     errname, retval);
 124         }
 125         return false;
 126     }
 127     return true;
 128 }
 129
 130 /* Helper function to do the ioctls needed for setup and init. */
 131 static bool do_winsys_init(struct radeon_drm_winsys *ws)
 132 {
 133     struct drm_radeon_gem_info gem_info;
 134     int retval;
 135     drmVersionPtr version;
 136
 137     memset(&gem_info, 0, sizeof(gem_info));
 138
 139     /* We do things in a specific order here.
 140      *
 141      * DRM version first. We need to be sure we're running on a KMS chipset.
 142      * This is also for some features.
 143      *
 144      * Then, the PCI ID. This is essential and should return usable numbers
 145      * for all Radeons. If this fails, we probably got handed an FD for some
 146      * non-Radeon card.
 147      *
 148      * The GEM info is actually bogus on the kernel side, as well as our side
 149      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 150      * we don't actually use the info for anything yet.
 151      *
 152      * The GB and Z pipe requests should always succeed, but they might not
 153      * return sensical values for all chipsets, but that's alright because
 154      * the pipe drivers already know that.
 155      */
 156
 157     /* Get DRM version. */
 158     version = drmGetVersion(ws->fd);
 159     if (version->version_major != 2 ||
 160         version->version_minor < 12) {
 161         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 162                 "only compatible with 2.12.0 (kernel 3.2) or later.\n",
 163                 __FUNCTION__,
 164                 version->version_major,
 165                 version->version_minor,
 166                 version->version_patchlevel);
 167         drmFreeVersion(version);
 168         return false;
 169     }
 170
 171     ws->info.drm_major = version->version_major;
 172     ws->info.drm_minor = version->version_minor;
 173     ws->info.drm_patchlevel = version->version_patchlevel;
 174     drmFreeVersion(version);
 175
 176     /* Get PCI ID. */
 177     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 178                               &ws->info.pci_id))
 179         return false;
 180
 181     /* Check PCI ID. */
 182     switch (ws->info.pci_id) {
 183 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 184 #include "pci_ids/r300_pci_ids.h"
 185 #undef CHIPSET
 186
 187 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 188 #include "pci_ids/r600_pci_ids.h"
 189 #undef CHIPSET
 190
 191 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 192 #include "pci_ids/radeonsi_pci_ids.h"
 193 #undef CHIPSET
 194
 195     default:
 196         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 197         return false;
 198     }
 199
 200     switch (ws->info.family) {
 201     default:
 202     case CHIP_UNKNOWN:
 203         fprintf(stderr, "radeon: Unknown family.\n");
 204         return false;
 205     case CHIP_R300:
 206     case CHIP_R350:
 207     case CHIP_RV350:
 208     case CHIP_RV370:
 209     case CHIP_RV380:
 210     case CHIP_RS400:
 211     case CHIP_RC410:
 212     case CHIP_RS480:
 213         ws->info.chip_class = R300;
 214         break;
 215     case CHIP_R420:     /* R4xx-based cores. */
 216     case CHIP_R423:
 217     case CHIP_R430:
 218     case CHIP_R480:
 219     case CHIP_R481:
 220     case CHIP_RV410:
 221     case CHIP_RS600:
 222     case CHIP_RS690:
 223     case CHIP_RS740:
 224         ws->info.chip_class = R400;
 225         break;
 226     case CHIP_RV515:    /* R5xx-based cores. */
 227     case CHIP_R520:
 228     case CHIP_RV530:
 229     case CHIP_R580:
 230     case CHIP_RV560:
 231     case CHIP_RV570:
 232         ws->info.chip_class = R500;
 233         break;
 234     case CHIP_R600:
 235     case CHIP_RV610:
 236     case CHIP_RV630:
 237     case CHIP_RV670:
 238     case CHIP_RV620:
 239     case CHIP_RV635:
 240     case CHIP_RS780:
 241     case CHIP_RS880:
 242         ws->info.chip_class = R600;
 243         break;
 244     case CHIP_RV770:
 245     case CHIP_RV730:
 246     case CHIP_RV710:
 247     case CHIP_RV740:
 248         ws->info.chip_class = R700;
 249         break;
 250     case CHIP_CEDAR:
 251     case CHIP_REDWOOD:
 252     case CHIP_JUNIPER:
 253     case CHIP_CYPRESS:
 254     case CHIP_HEMLOCK:
 255     case CHIP_PALM:
 256     case CHIP_SUMO:
 257     case CHIP_SUMO2:
 258     case CHIP_BARTS:
 259     case CHIP_TURKS:
 260     case CHIP_CAICOS:
 261         ws->info.chip_class = EVERGREEN;
 262         break;
 263     case CHIP_CAYMAN:
 264     case CHIP_ARUBA:
 265         ws->info.chip_class = CAYMAN;
 266         break;
 267     case CHIP_TAHITI:
 268     case CHIP_PITCAIRN:
 269     case CHIP_VERDE:
 270     case CHIP_OLAND:
 271     case CHIP_HAINAN:
 272         ws->info.chip_class = SI;
 273         break;
 274     case CHIP_BONAIRE:
 275     case CHIP_KAVERI:
 276     case CHIP_KABINI:
 277     case CHIP_HAWAII:
 278     case CHIP_MULLINS:
 279         ws->info.chip_class = CIK;
 280         break;
 281     }
 282
 283     /* Set which chips don't have dedicated VRAM. */
 284     switch (ws->info.family) {
 285     case CHIP_RS400:
 286     case CHIP_RC410:
 287     case CHIP_RS480:
 288     case CHIP_RS600:
 289     case CHIP_RS690:
 290     case CHIP_RS740:
 291     case CHIP_RS780:
 292     case CHIP_RS880:
 293     case CHIP_PALM:
 294     case CHIP_SUMO:
 295     case CHIP_SUMO2:
 296     case CHIP_ARUBA:
 297     case CHIP_KAVERI:
 298     case CHIP_KABINI:
 299     case CHIP_MULLINS:
 300        ws->info.has_dedicated_vram = false;
 301        break;
 302
 303     default:
 304        ws->info.has_dedicated_vram = true;
 305     }
 306
 307     /* Check for dma */
 308     ws->info.num_sdma_rings = 0;
 309     /* DMA is disabled on R700. There is IB corruption and hangs. */
 310     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 311         ws->info.num_sdma_rings = 1;
 312     }
 313
 314     /* Check for UVD and VCE */
 315     ws->info.has_hw_decode = false;
 316     ws->info.vce_fw_version = 0x00000000;
 317     if (ws->info.drm_minor >= 32) {
 318         uint32_t value = RADEON_CS_RING_UVD;
 319         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 320                                  "UVD Ring working", &value))
 321             ws->info.has_hw_decode = value;
 322
 323         value = RADEON_CS_RING_VCE;
 324         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 325                                  NULL, &value) && value) {
 326
 327             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 328                                      "VCE FW version", &value))
 329                 ws->info.vce_fw_version = value;
 330         }
 331     }
 332
 333     /* Check for userptr support. */
 334     {
 335         struct drm_radeon_gem_userptr args = {0};
 336
 337         /* If the ioctl doesn't exist, -EINVAL is returned.
 338          *
 339          * If the ioctl exists, it should return -EACCES
 340          * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
 341          * aren't set.
 342          */
 343         ws->info.has_userptr =
 344             drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
 345                                 &args, sizeof(args)) == -EACCES;
 346     }
 347
 348     /* Get GEM info. */
 349     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 350             &gem_info, sizeof(gem_info));
 351     if (retval) {
 352         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 353                 retval);
 354         return false;
 355     }
 356     ws->info.gart_size = gem_info.gart_size;
 357     ws->info.vram_size = gem_info.vram_size;
 358     ws->info.vram_vis_size = gem_info.vram_visible;
 359     /* Older versions of the kernel driver reported incorrect values, and
 360      * didn't support more than 256MB of visible VRAM anyway
 361      */
 362     if (ws->info.drm_minor < 49)
 363         ws->info.vram_vis_size = MIN2(ws->info.vram_vis_size, 256*1024*1024);
 364
 365     /* Radeon allocates all buffers as contigous, which makes large allocations
 366      * unlikely to succeed. */
 367     ws->info.max_alloc_size = MAX2(ws->info.vram_size, ws->info.gart_size) * 0.7;
 368     if (ws->info.has_dedicated_vram)
 369         ws->info.max_alloc_size = MIN2(ws->info.vram_size * 0.7, ws->info.max_alloc_size);
 370     if (ws->info.drm_minor < 40)
 371         ws->info.max_alloc_size = MIN2(ws->info.max_alloc_size, 256*1024*1024);
 372
 373     /* Get max clock frequency info and convert it to MHz */
 374     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 375                          &ws->info.max_shader_clock);
 376     ws->info.max_shader_clock /= 1000;
 377
 378     /* Default value. */
 379     ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.num_render_backends);
 380     /* This fails on non-GCN or older kernels: */
 381     radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
 382                          &ws->info.enabled_rb_mask);
 383
 384     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 385
 386     /* Generation-specific queries. */
 387     if (ws->gen == DRV_R300) {
 388         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 389                                   "GB pipe count",
 390                                   &ws->info.r300_num_gb_pipes))
 391             return false;
 392
 393         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 394                                   "Z pipe count",
 395                                   &ws->info.r300_num_z_pipes))
 396             return false;
 397     }
 398     else if (ws->gen >= DRV_R600) {
 399         uint32_t tiling_config = 0;
 400
 401         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 402                                   "num backends",
 403                                   &ws->info.num_render_backends))
 404             return false;
 405
 406         /* get the GPU counter frequency, failure is not fatal */
 407         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 408                              &ws->info.clock_crystal_freq);
 409
 410         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 411                              &tiling_config);
 412
 413         ws->info.r600_num_banks =
 414             ws->info.chip_class >= EVERGREEN ?
 415                 4 << ((tiling_config & 0xf0) >> 4) :
 416                 4 << ((tiling_config & 0x30) >> 4);
 417
 418         ws->info.pipe_interleave_bytes =
 419             ws->info.chip_class >= EVERGREEN ?
 420                 256 << ((tiling_config & 0xf00) >> 8) :
 421                 256 << ((tiling_config & 0xc0) >> 6);
 422
 423         if (!ws->info.pipe_interleave_bytes)
 424             ws->info.pipe_interleave_bytes =
 425                 ws->info.chip_class >= EVERGREEN ? 512 : 256;
 426
 427         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 428                              &ws->info.num_tile_pipes);
 429
 430         /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
 431          * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
 432          * reports a different value (12). Fix it by setting what's in the
 433          * GB_TILE_MODE array (8).
 434          */
 435         if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
 436             ws->info.num_tile_pipes = 8;
 437
 438         if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 439                                   &ws->info.r600_gb_backend_map))
 440             ws->info.r600_gb_backend_map_valid = true;
 441
 442         ws->info.has_virtual_memory = false;
 443         if (ws->info.drm_minor >= 13) {
 444             uint32_t ib_vm_max_size;
 445
 446             ws->info.has_virtual_memory = true;
 447             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 448                                       &ws->va_start))
 449                 ws->info.has_virtual_memory = false;
 450             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 451                                       &ib_vm_max_size))
 452                 ws->info.has_virtual_memory = false;
 453             radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
 454                                  &ws->va_unmap_working);
 455         }
 456         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", false))
 457                 ws->info.has_virtual_memory = false;
 458     }
 459
 460     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 461      * chips have at least 2 pipes, so we use 2 as a default. */
 462     ws->info.r600_max_quad_pipes = 2;
 463     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 464                          &ws->info.r600_max_quad_pipes);
 465
 466     /* All GPUs have at least one compute unit */
 467     ws->info.num_good_compute_units = 1;
 468     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 469                          &ws->info.num_good_compute_units);
 470
 471     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 472                          &ws->info.max_se);
 473
 474     if (!ws->info.max_se) {
 475         switch (ws->info.family) {
 476         default:
 477             ws->info.max_se = 1;
 478             break;
 479         case CHIP_CYPRESS:
 480         case CHIP_HEMLOCK:
 481         case CHIP_BARTS:
 482         case CHIP_CAYMAN:
 483         case CHIP_TAHITI:
 484         case CHIP_PITCAIRN:
 485         case CHIP_BONAIRE:
 486             ws->info.max_se = 2;
 487             break;
 488         case CHIP_HAWAII:
 489             ws->info.max_se = 4;
 490             break;
 491         }
 492     }
 493
 494     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 495                          &ws->info.max_sh_per_se);
 496
 497     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 498                          &ws->accel_working2);
 499     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 500         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 501                 "returned accel_working2 value %u is smaller than 2. "
 502                 "Please install a newer kernel.\n",
 503                 ws->accel_working2);
 504         return false;
 505     }
 506
 507     if (ws->info.chip_class == CIK) {
 508         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 509                                   ws->info.cik_macrotile_mode_array)) {
 510             fprintf(stderr, "radeon: Kernel 3.13 is required for CIK support.\n");
 511             return false;
 512         }
 513     }
 514
 515     if (ws->info.chip_class >= SI) {
 516         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 517                                   ws->info.si_tile_mode_array)) {
 518             fprintf(stderr, "radeon: Kernel 3.10 is required for SI support.\n");
 519             return false;
 520         }
 521     }
 522
 523     /* Hawaii with old firmware needs type2 nop packet.
 524      * accel_working2 with value 3 indicates the new firmware.
 525      */
 526     ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI ||
 527                                      (ws->info.family == CHIP_HAWAII &&
 528                                       ws->accel_working2 < 3);
 529     ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
 530
 531     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;
 532
 533     return true;
 534 }
 535
 536 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 537 {
 538     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 539
 540     if (util_queue_is_initialized(&ws->cs_queue))
 541         util_queue_destroy(&ws->cs_queue);
 542
 543     mtx_destroy(&ws->hyperz_owner_mutex);
 544     mtx_destroy(&ws->cmask_owner_mutex);
 545
 546     if (ws->info.has_virtual_memory)
 547         pb_slabs_deinit(&ws->bo_slabs);
 548     pb_cache_deinit(&ws->bo_cache);
 549
 550     if (ws->gen >= DRV_R600) {
 551         radeon_surface_manager_free(ws->surf_man);
 552     }
 553
 554     util_hash_table_destroy(ws->bo_names);
 555     util_hash_table_destroy(ws->bo_handles);
 556     util_hash_table_destroy(ws->bo_vas);
 557     mtx_destroy(&ws->bo_handles_mutex);
 558     mtx_destroy(&ws->bo_va_mutex);
 559     mtx_destroy(&ws->bo_fence_lock);
 560
 561     if (ws->fd >= 0)
 562         close(ws->fd);
 563
 564     FREE(rws);
 565 }
 566
 567 static void radeon_query_info(struct radeon_winsys *rws,
 568                               struct radeon_info *info)
 569 {
 570     *info = ((struct radeon_drm_winsys *)rws)->info;
 571 }
 572
 573 static bool radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 574                                       enum radeon_feature_id fid,
 575                                       bool enable)
 576 {
 577     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 578
 579     switch (fid) {
 580     case RADEON_FID_R300_HYPERZ_ACCESS:
 581         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 582                                     &cs->ws->hyperz_owner_mutex,
 583                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 584                                     enable);
 585
 586     case RADEON_FID_R300_CMASK_ACCESS:
 587         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 588                                     &cs->ws->cmask_owner_mutex,
 589                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 590                                     enable);
 591     }
 592     return false;
 593 }
 594
 595 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 596                                    enum radeon_value_id value)
 597 {
 598     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 599     uint64_t retval = 0;
 600
 601     switch (value) {
 602     case RADEON_REQUESTED_VRAM_MEMORY:
 603         return ws->allocated_vram;
 604     case RADEON_REQUESTED_GTT_MEMORY:
 605         return ws->allocated_gtt;
 606     case RADEON_MAPPED_VRAM:
 607        return ws->mapped_vram;
 608     case RADEON_MAPPED_GTT:
 609        return ws->mapped_gtt;
 610     case RADEON_BUFFER_WAIT_TIME_NS:
 611         return ws->buffer_wait_time;
 612     case RADEON_NUM_MAPPED_BUFFERS:
 613         return ws->num_mapped_buffers;
 614     case RADEON_TIMESTAMP:
 615         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 616             assert(0);
 617             return 0;
 618         }
 619
 620         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 621                              (uint32_t*)&retval);
 622         return retval;
 623     case RADEON_NUM_GFX_IBS:
 624         return ws->num_gfx_IBs;
 625     case RADEON_NUM_SDMA_IBS:
 626         return ws->num_sdma_IBs;
 627     case RADEON_NUM_BYTES_MOVED:
 628         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 629                              "num-bytes-moved", (uint32_t*)&retval);
 630         return retval;
 631     case RADEON_NUM_EVICTIONS:
 632     case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
 633     case RADEON_VRAM_VIS_USAGE:
 634         return 0; /* unimplemented */
 635     case RADEON_VRAM_USAGE:
 636         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 637                              "vram-usage", (uint32_t*)&retval);
 638         return retval;
 639     case RADEON_GTT_USAGE:
 640         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 641                              "gtt-usage", (uint32_t*)&retval);
 642         return retval;
 643     case RADEON_GPU_TEMPERATURE:
 644         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
 645                              "gpu-temp", (uint32_t*)&retval);
 646         return retval;
 647     case RADEON_CURRENT_SCLK:
 648         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
 649                              "current-gpu-sclk", (uint32_t*)&retval);
 650         return retval;
 651     case RADEON_CURRENT_MCLK:
 652         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
 653                              "current-gpu-mclk", (uint32_t*)&retval);
 654         return retval;
 655     case RADEON_GPU_RESET_COUNTER:
 656         radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
 657                              "gpu-reset-counter", (uint32_t*)&retval);
 658         return retval;
 659     case RADEON_CS_THREAD_TIME:
 660         return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
 661     }
 662     return 0;
 663 }
 664
 665 static bool radeon_read_registers(struct radeon_winsys *rws,
 666                                   unsigned reg_offset,
 667                                   unsigned num_registers, uint32_t *out)
 668 {
 669     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 670     unsigned i;
 671
 672     for (i = 0; i < num_registers; i++) {
 673         uint32_t reg = reg_offset + i*4;
 674
 675         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg))
 676             return false;
 677         out[i] = reg;
 678     }
 679     return true;
 680 }
 681
 682 static unsigned hash_fd(void *key)
 683 {
 684     int fd = pointer_to_intptr(key);
 685     struct stat stat;
 686     fstat(fd, &stat);
 687
 688     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 689 }
 690
 691 static int compare_fd(void *key1, void *key2)
 692 {
 693     int fd1 = pointer_to_intptr(key1);
 694     int fd2 = pointer_to_intptr(key2);
 695     struct stat stat1, stat2;
 696     fstat(fd1, &stat1);
 697     fstat(fd2, &stat2);
 698
 699     return stat1.st_dev != stat2.st_dev ||
 700            stat1.st_ino != stat2.st_ino ||
 701            stat1.st_rdev != stat2.st_rdev;
 702 }
 703
 704 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", true)
 705
 706 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 707 {
 708     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 709     bool destroy;
 710
 711     /* When the reference counter drops to zero, remove the fd from the table.
 712      * This must happen while the mutex is locked, so that
 713      * radeon_drm_winsys_create in another thread doesn't get the winsys
 714      * from the table when the counter drops to 0. */
 715     mtx_lock(&fd_tab_mutex);
 716
 717     destroy = pipe_reference(&rws->reference, NULL);
 718     if (destroy && fd_tab)
 719         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 720
 721     mtx_unlock(&fd_tab_mutex);
 722     return destroy;
 723 }
 724
 725 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 726
 727 static unsigned handle_hash(void *key)
 728 {
 729     return PTR_TO_UINT(key);
 730 }
 731
 732 static int handle_compare(void *key1, void *key2)
 733 {
 734     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 735 }
 736
 737 PUBLIC struct radeon_winsys *
 738 radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
 739 {
 740     struct radeon_drm_winsys *ws;
 741
 742     mtx_lock(&fd_tab_mutex);
 743     if (!fd_tab) {
 744         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 745     }
 746
 747     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 748     if (ws) {
 749         pipe_reference(NULL, &ws->reference);
 750         mtx_unlock(&fd_tab_mutex);
 751         return &ws->base;
 752     }
 753
 754     ws = CALLOC_STRUCT(radeon_drm_winsys);
 755     if (!ws) {
 756         mtx_unlock(&fd_tab_mutex);
 757         return NULL;
 758     }
 759
 760     ws->fd = fcntl(fd, F_DUPFD_CLOEXEC, 3);
 761
 762     if (!do_winsys_init(ws))
 763         goto fail1;
 764
 765     pb_cache_init(&ws->bo_cache, 500000, ws->check_vm ? 1.0f : 2.0f, 0,
 766                   MIN2(ws->info.vram_size, ws->info.gart_size),
 767                   radeon_bo_destroy,
 768                   radeon_bo_can_reclaim);
 769
 770     if (ws->info.has_virtual_memory) {
 771         /* There is no fundamental obstacle to using slab buffer allocation
 772          * without GPUVM, but enabling it requires making sure that the drivers
 773          * honor the address offset.
 774          */
 775         if (!pb_slabs_init(&ws->bo_slabs,
 776                            RADEON_SLAB_MIN_SIZE_LOG2, RADEON_SLAB_MAX_SIZE_LOG2,
 777                            12,
 778                            ws,
 779                            radeon_bo_can_reclaim_slab,
 780                            radeon_bo_slab_alloc,
 781                            radeon_bo_slab_free))
 782             goto fail_cache;
 783
 784         ws->info.min_alloc_size = 1 << RADEON_SLAB_MIN_SIZE_LOG2;
 785     } else {
 786         ws->info.min_alloc_size = ws->info.gart_page_size;
 787     }
 788
 789     if (ws->gen >= DRV_R600) {
 790         ws->surf_man = radeon_surface_manager_new(ws->fd);
 791         if (!ws->surf_man)
 792             goto fail_slab;
 793     }
 794
 795     /* init reference */
 796     pipe_reference_init(&ws->reference, 1);
 797
 798     /* Set functions. */
 799     ws->base.unref = radeon_winsys_unref;
 800     ws->base.destroy = radeon_winsys_destroy;
 801     ws->base.query_info = radeon_query_info;
 802     ws->base.cs_request_feature = radeon_cs_request_feature;
 803     ws->base.query_value = radeon_query_value;
 804     ws->base.read_registers = radeon_read_registers;
 805
 806     radeon_drm_bo_init_functions(ws);
 807     radeon_drm_cs_init_functions(ws);
 808     radeon_surface_init_functions(ws);
 809
 810     (void) mtx_init(&ws->hyperz_owner_mutex, mtx_plain);
 811     (void) mtx_init(&ws->cmask_owner_mutex, mtx_plain);
 812
 813     ws->bo_names = util_hash_table_create(handle_hash, handle_compare);
 814     ws->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 815     ws->bo_vas = util_hash_table_create(handle_hash, handle_compare);
 816     (void) mtx_init(&ws->bo_handles_mutex, mtx_plain);
 817     (void) mtx_init(&ws->bo_va_mutex, mtx_plain);
 818     (void) mtx_init(&ws->bo_fence_lock, mtx_plain);
 819     ws->va_offset = ws->va_start;
 820     list_inithead(&ws->va_holes);
 821
 822     /* TTM aligns the BO size to the CPU page size */
 823     ws->info.gart_page_size = sysconf(_SC_PAGESIZE);
 824
 825     if (ws->num_cpus > 1 && debug_get_option_thread())
 826         util_queue_init(&ws->cs_queue, "radeon_cs", 8, 1, 0);
 827
 828     /* Create the screen at the end. The winsys must be initialized
 829      * completely.
 830      *
 831      * Alternatively, we could create the screen based on "ws->gen"
 832      * and link all drivers into one binary blob. */
 833     ws->base.screen = screen_create(&ws->base);
 834     if (!ws->base.screen) {
 835         radeon_winsys_destroy(&ws->base);
 836         mtx_unlock(&fd_tab_mutex);
 837         return NULL;
 838     }
 839
 840     util_hash_table_set(fd_tab, intptr_to_pointer(ws->fd), ws);
 841
 842     /* We must unlock the mutex once the winsys is fully initialized, so that
 843      * other threads attempting to create the winsys from the same fd will
 844      * get a fully initialized winsys and not just half-way initialized. */
 845     mtx_unlock(&fd_tab_mutex);
 846
 847     return &ws->base;
 848
 849 fail_slab:
 850     if (ws->info.has_virtual_memory)
 851         pb_slabs_deinit(&ws->bo_slabs);
 852 fail_cache:
 853     pb_cache_deinit(&ws->bo_cache);
 854 fail1:
 855     mtx_unlock(&fd_tab_mutex);
 856     if (ws->surf_man)
 857         radeon_surface_manager_free(ws->surf_man);
 858     if (ws->fd >= 0)
 859         close(ws->fd);
 860
 861     FREE(ws);
 862     return NULL;
 863 }