src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "pipebuffer/pb_bufmgr.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_hash_table.h"
  41
  42 #include <xf86drm.h>
  43 #include <stdio.h>
  44 #include <sys/types.h>
  45 #include <sys/stat.h>
  46 #include <unistd.h>
  47
  48 #ifndef RADEON_INFO_ACTIVE_CU_COUNT
  49 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
  50 #endif
  51
  52 #ifndef RADEON_INFO_CURRENT_GPU_TEMP
  53 #define RADEON_INFO_CURRENT_GPU_TEMP    0x21
  54 #define RADEON_INFO_CURRENT_GPU_SCLK    0x22
  55 #define RADEON_INFO_CURRENT_GPU_MCLK    0x23
  56 #define RADEON_INFO_READ_REG            0x24
  57 #endif
  58
  59 static struct util_hash_table *fd_tab = NULL;
  60 pipe_static_mutex(fd_tab_mutex);
  61
  62 /* Enable/disable feature access for one command stream.
  63  * If enable == TRUE, return TRUE on success.
  64  * Otherwise, return FALSE.
  65  *
  66  * We basically do the same thing kernel does, because we have to deal
  67  * with multiple contexts (here command streams) backed by one winsys. */
  68 static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
  69                                     struct radeon_drm_cs **owner,
  70                                     pipe_mutex *mutex,
  71                                     unsigned request, const char *request_name,
  72                                     boolean enable)
  73 {
  74     struct drm_radeon_info info;
  75     unsigned value = enable ? 1 : 0;
  76
  77     memset(&info, 0, sizeof(info));
  78
  79     pipe_mutex_lock(*mutex);
  80
  81     /* Early exit if we are sure the request will fail. */
  82     if (enable) {
  83         if (*owner) {
  84             pipe_mutex_unlock(*mutex);
  85             return FALSE;
  86         }
  87     } else {
  88         if (*owner != applier) {
  89             pipe_mutex_unlock(*mutex);
  90             return FALSE;
  91         }
  92     }
  93
  94     /* Pass through the request to the kernel. */
  95     info.value = (unsigned long)&value;
  96     info.request = request;
  97     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
  98                             &info, sizeof(info)) != 0) {
  99         pipe_mutex_unlock(*mutex);
 100         return FALSE;
 101     }
 102
 103     /* Update the rights in the winsys. */
 104     if (enable) {
 105         if (value) {
 106             *owner = applier;
 107             pipe_mutex_unlock(*mutex);
 108             return TRUE;
 109         }
 110     } else {
 111         *owner = NULL;
 112     }
 113
 114     pipe_mutex_unlock(*mutex);
 115     return FALSE;
 116 }
 117
 118 static boolean radeon_get_drm_value(int fd, unsigned request,
 119                                     const char *errname, uint32_t *out)
 120 {
 121     struct drm_radeon_info info;
 122     int retval;
 123
 124     memset(&info, 0, sizeof(info));
 125
 126     info.value = (unsigned long)out;
 127     info.request = request;
 128
 129     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 130     if (retval) {
 131         if (errname) {
 132             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 133                     errname, retval);
 134         }
 135         return FALSE;
 136     }
 137     return TRUE;
 138 }
 139
 140 /* Helper function to do the ioctls needed for setup and init. */
 141 static boolean do_winsys_init(struct radeon_drm_winsys *ws)
 142 {
 143     struct drm_radeon_gem_info gem_info;
 144     int retval;
 145     drmVersionPtr version;
 146
 147     memset(&gem_info, 0, sizeof(gem_info));
 148
 149     /* We do things in a specific order here.
 150      *
 151      * DRM version first. We need to be sure we're running on a KMS chipset.
 152      * This is also for some features.
 153      *
 154      * Then, the PCI ID. This is essential and should return usable numbers
 155      * for all Radeons. If this fails, we probably got handed an FD for some
 156      * non-Radeon card.
 157      *
 158      * The GEM info is actually bogus on the kernel side, as well as our side
 159      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 160      * we don't actually use the info for anything yet.
 161      *
 162      * The GB and Z pipe requests should always succeed, but they might not
 163      * return sensical values for all chipsets, but that's alright because
 164      * the pipe drivers already know that.
 165      */
 166
 167     /* Get DRM version. */
 168     version = drmGetVersion(ws->fd);
 169     if (version->version_major != 2 ||
 170         version->version_minor < 3) {
 171         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 172                 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
 173                 __FUNCTION__,
 174                 version->version_major,
 175                 version->version_minor,
 176                 version->version_patchlevel);
 177         drmFreeVersion(version);
 178         return FALSE;
 179     }
 180
 181     ws->info.drm_major = version->version_major;
 182     ws->info.drm_minor = version->version_minor;
 183     ws->info.drm_patchlevel = version->version_patchlevel;
 184     drmFreeVersion(version);
 185
 186     /* Get PCI ID. */
 187     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 188                               &ws->info.pci_id))
 189         return FALSE;
 190
 191     /* Check PCI ID. */
 192     switch (ws->info.pci_id) {
 193 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 194 #include "pci_ids/r300_pci_ids.h"
 195 #undef CHIPSET
 196
 197 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 198 #include "pci_ids/r600_pci_ids.h"
 199 #undef CHIPSET
 200
 201 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 202 #include "pci_ids/radeonsi_pci_ids.h"
 203 #undef CHIPSET
 204
 205     default:
 206         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 207         return FALSE;
 208     }
 209
 210     switch (ws->info.family) {
 211     default:
 212     case CHIP_UNKNOWN:
 213         fprintf(stderr, "radeon: Unknown family.\n");
 214         return FALSE;
 215     case CHIP_R300:
 216     case CHIP_R350:
 217     case CHIP_RV350:
 218     case CHIP_RV370:
 219     case CHIP_RV380:
 220     case CHIP_RS400:
 221     case CHIP_RC410:
 222     case CHIP_RS480:
 223         ws->info.chip_class = R300;
 224         break;
 225     case CHIP_R420:     /* R4xx-based cores. */
 226     case CHIP_R423:
 227     case CHIP_R430:
 228     case CHIP_R480:
 229     case CHIP_R481:
 230     case CHIP_RV410:
 231     case CHIP_RS600:
 232     case CHIP_RS690:
 233     case CHIP_RS740:
 234         ws->info.chip_class = R400;
 235         break;
 236     case CHIP_RV515:    /* R5xx-based cores. */
 237     case CHIP_R520:
 238     case CHIP_RV530:
 239     case CHIP_R580:
 240     case CHIP_RV560:
 241     case CHIP_RV570:
 242         ws->info.chip_class = R500;
 243         break;
 244     case CHIP_R600:
 245     case CHIP_RV610:
 246     case CHIP_RV630:
 247     case CHIP_RV670:
 248     case CHIP_RV620:
 249     case CHIP_RV635:
 250     case CHIP_RS780:
 251     case CHIP_RS880:
 252         ws->info.chip_class = R600;
 253         break;
 254     case CHIP_RV770:
 255     case CHIP_RV730:
 256     case CHIP_RV710:
 257     case CHIP_RV740:
 258         ws->info.chip_class = R700;
 259         break;
 260     case CHIP_CEDAR:
 261     case CHIP_REDWOOD:
 262     case CHIP_JUNIPER:
 263     case CHIP_CYPRESS:
 264     case CHIP_HEMLOCK:
 265     case CHIP_PALM:
 266     case CHIP_SUMO:
 267     case CHIP_SUMO2:
 268     case CHIP_BARTS:
 269     case CHIP_TURKS:
 270     case CHIP_CAICOS:
 271         ws->info.chip_class = EVERGREEN;
 272         break;
 273     case CHIP_CAYMAN:
 274     case CHIP_ARUBA:
 275         ws->info.chip_class = CAYMAN;
 276         break;
 277     case CHIP_TAHITI:
 278     case CHIP_PITCAIRN:
 279     case CHIP_VERDE:
 280     case CHIP_OLAND:
 281     case CHIP_HAINAN:
 282         ws->info.chip_class = SI;
 283         break;
 284     case CHIP_BONAIRE:
 285     case CHIP_KAVERI:
 286     case CHIP_KABINI:
 287     case CHIP_HAWAII:
 288     case CHIP_MULLINS:
 289         ws->info.chip_class = CIK;
 290         break;
 291     }
 292
 293     /* Check for dma */
 294     ws->info.r600_has_dma = FALSE;
 295     /* DMA is disabled on R700. There is IB corruption and hangs. */
 296     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 297         ws->info.r600_has_dma = TRUE;
 298     }
 299
 300     /* Check for UVD and VCE */
 301     ws->info.has_uvd = FALSE;
 302     ws->info.vce_fw_version = 0x00000000;
 303     if (ws->info.drm_minor >= 32) {
 304         uint32_t value = RADEON_CS_RING_UVD;
 305         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 306                                  "UVD Ring working", &value))
 307             ws->info.has_uvd = value;
 308
 309         value = RADEON_CS_RING_VCE;
 310         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 311                                  NULL, &value) && value) {
 312
 313             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 314                                      "VCE FW version", &value))
 315                 ws->info.vce_fw_version = value;
 316         }
 317     }
 318
 319     /* Check for userptr support. */
 320     {
 321         struct drm_radeon_gem_userptr args = {0};
 322
 323         /* If the ioctl doesn't exist, -EINVAL is returned.
 324          *
 325          * If the ioctl exists, it should return -EACCES
 326          * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
 327          * aren't set.
 328          */
 329         ws->info.has_userptr =
 330             drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
 331                                 &args, sizeof(args)) == -EACCES;
 332     }
 333
 334     /* Get GEM info. */
 335     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 336             &gem_info, sizeof(gem_info));
 337     if (retval) {
 338         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 339                 retval);
 340         return FALSE;
 341     }
 342     ws->info.gart_size = gem_info.gart_size;
 343     ws->info.vram_size = gem_info.vram_size;
 344
 345     /* Get max clock frequency info and convert it to MHz */
 346     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 347                          &ws->info.max_sclk);
 348     ws->info.max_sclk /= 1000;
 349
 350     radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
 351                          &ws->info.si_backend_enabled_mask);
 352
 353     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 354
 355     /* Generation-specific queries. */
 356     if (ws->gen == DRV_R300) {
 357         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 358                                   "GB pipe count",
 359                                   &ws->info.r300_num_gb_pipes))
 360             return FALSE;
 361
 362         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 363                                   "Z pipe count",
 364                                   &ws->info.r300_num_z_pipes))
 365             return FALSE;
 366     }
 367     else if (ws->gen >= DRV_R600) {
 368         if (ws->info.drm_minor >= 9 &&
 369             !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 370                                   "num backends",
 371                                   &ws->info.r600_num_backends))
 372             return FALSE;
 373
 374         /* get the GPU counter frequency, failure is not fatal */
 375         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 376                              &ws->info.r600_clock_crystal_freq);
 377
 378         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 379                              &ws->info.r600_tiling_config);
 380
 381         if (ws->info.drm_minor >= 11) {
 382             radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 383                                  &ws->info.r600_num_tile_pipes);
 384
 385             if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 386                                       &ws->info.r600_backend_map))
 387                 ws->info.r600_backend_map_valid = TRUE;
 388         }
 389
 390         ws->info.r600_virtual_address = FALSE;
 391         if (ws->info.drm_minor >= 13) {
 392             uint32_t ib_vm_max_size;
 393
 394             ws->info.r600_virtual_address = TRUE;
 395             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 396                                       &ws->va_start))
 397                 ws->info.r600_virtual_address = FALSE;
 398             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 399                                       &ib_vm_max_size))
 400                 ws->info.r600_virtual_address = FALSE;
 401         }
 402         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", FALSE))
 403                 ws->info.r600_virtual_address = FALSE;
 404     }
 405
 406     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 407      * chips have at least 2 pipes, so we use 2 as a default. */
 408     ws->info.r600_max_pipes = 2;
 409     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 410                          &ws->info.r600_max_pipes);
 411
 412     /* All GPUs have at least one compute unit */
 413     ws->info.max_compute_units = 1;
 414     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 415                          &ws->info.max_compute_units);
 416
 417     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 418                          &ws->info.max_se);
 419
 420     if (!ws->info.max_se) {
 421         switch (ws->info.family) {
 422         default:
 423             ws->info.max_se = 1;
 424             break;
 425         case CHIP_CYPRESS:
 426         case CHIP_HEMLOCK:
 427         case CHIP_BARTS:
 428         case CHIP_CAYMAN:
 429         case CHIP_TAHITI:
 430         case CHIP_PITCAIRN:
 431         case CHIP_BONAIRE:
 432             ws->info.max_se = 2;
 433             break;
 434         case CHIP_HAWAII:
 435             ws->info.max_se = 4;
 436             break;
 437         }
 438     }
 439
 440     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 441                          &ws->info.max_sh_per_se);
 442
 443     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 444                          &ws->accel_working2);
 445     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 446         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 447                 "returned accel_working2 value %u is smaller than 2. "
 448                 "Please install a newer kernel.\n",
 449                 ws->accel_working2);
 450         return FALSE;
 451     }
 452
 453     if (radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 454                              ws->info.si_tile_mode_array)) {
 455         ws->info.si_tile_mode_array_valid = TRUE;
 456     }
 457
 458     if (radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 459                              ws->info.cik_macrotile_mode_array)) {
 460         ws->info.cik_macrotile_mode_array_valid = TRUE;
 461     }
 462
 463     return TRUE;
 464 }
 465
 466 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 467 {
 468     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 469
 470     if (ws->thread) {
 471         ws->kill_thread = 1;
 472         pipe_semaphore_signal(&ws->cs_queued);
 473         pipe_thread_wait(ws->thread);
 474     }
 475     pipe_semaphore_destroy(&ws->cs_queued);
 476
 477     pipe_mutex_destroy(ws->hyperz_owner_mutex);
 478     pipe_mutex_destroy(ws->cmask_owner_mutex);
 479     pipe_mutex_destroy(ws->cs_stack_lock);
 480
 481     ws->cman->destroy(ws->cman);
 482     ws->kman->destroy(ws->kman);
 483     if (ws->gen >= DRV_R600) {
 484         radeon_surface_manager_free(ws->surf_man);
 485     }
 486     FREE(rws);
 487 }
 488
 489 static void radeon_query_info(struct radeon_winsys *rws,
 490                               struct radeon_info *info)
 491 {
 492     *info = ((struct radeon_drm_winsys *)rws)->info;
 493 }
 494
 495 static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 496                                          enum radeon_feature_id fid,
 497                                          boolean enable)
 498 {
 499     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 500
 501     switch (fid) {
 502     case RADEON_FID_R300_HYPERZ_ACCESS:
 503         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 504                                     &cs->ws->hyperz_owner_mutex,
 505                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 506                                     enable);
 507
 508     case RADEON_FID_R300_CMASK_ACCESS:
 509         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 510                                     &cs->ws->cmask_owner_mutex,
 511                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 512                                     enable);
 513     }
 514     return FALSE;
 515 }
 516
 517 static int radeon_drm_winsys_surface_init(struct radeon_winsys *rws,
 518                                           struct radeon_surface *surf)
 519 {
 520     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 521
 522     return radeon_surface_init(ws->surf_man, surf);
 523 }
 524
 525 static int radeon_drm_winsys_surface_best(struct radeon_winsys *rws,
 526                                           struct radeon_surface *surf)
 527 {
 528     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 529
 530     return radeon_surface_best(ws->surf_man, surf);
 531 }
 532
 533 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 534                                    enum radeon_value_id value)
 535 {
 536     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 537     uint64_t retval = 0;
 538
 539     switch (value) {
 540     case RADEON_REQUESTED_VRAM_MEMORY:
 541         return ws->allocated_vram;
 542     case RADEON_REQUESTED_GTT_MEMORY:
 543         return ws->allocated_gtt;
 544     case RADEON_BUFFER_WAIT_TIME_NS:
 545         return ws->buffer_wait_time;
 546     case RADEON_TIMESTAMP:
 547         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 548             assert(0);
 549             return 0;
 550         }
 551
 552         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 553                              (uint32_t*)&retval);
 554         return retval;
 555     case RADEON_NUM_CS_FLUSHES:
 556         return ws->num_cs_flushes;
 557     case RADEON_NUM_BYTES_MOVED:
 558         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 559                              "num-bytes-moved", (uint32_t*)&retval);
 560         return retval;
 561     case RADEON_VRAM_USAGE:
 562         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 563                              "vram-usage", (uint32_t*)&retval);
 564         return retval;
 565     case RADEON_GTT_USAGE:
 566         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 567                              "gtt-usage", (uint32_t*)&retval);
 568         return retval;
 569     case RADEON_GPU_TEMPERATURE:
 570         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
 571                              "gpu-temp", (uint32_t*)&retval);
 572         return retval;
 573     case RADEON_CURRENT_SCLK:
 574         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
 575                              "current-gpu-sclk", (uint32_t*)&retval);
 576         return retval;
 577     case RADEON_CURRENT_MCLK:
 578         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
 579                              "current-gpu-mclk", (uint32_t*)&retval);
 580         return retval;
 581     }
 582     return 0;
 583 }
 584
 585 static void radeon_read_registers(struct radeon_winsys *rws,
 586                                   unsigned reg_offset,
 587                                   unsigned num_registers, uint32_t *out)
 588 {
 589     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 590     unsigned i;
 591
 592     for (i = 0; i < num_registers; i++) {
 593         uint32_t reg = reg_offset + i*4;
 594
 595         radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, "read-reg", &reg);
 596         out[i] = reg;
 597     }
 598 }
 599
 600 static unsigned hash_fd(void *key)
 601 {
 602     int fd = pointer_to_intptr(key);
 603     struct stat stat;
 604     fstat(fd, &stat);
 605
 606     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 607 }
 608
 609 static int compare_fd(void *key1, void *key2)
 610 {
 611     int fd1 = pointer_to_intptr(key1);
 612     int fd2 = pointer_to_intptr(key2);
 613     struct stat stat1, stat2;
 614     fstat(fd1, &stat1);
 615     fstat(fd2, &stat2);
 616
 617     return stat1.st_dev != stat2.st_dev ||
 618            stat1.st_ino != stat2.st_ino ||
 619            stat1.st_rdev != stat2.st_rdev;
 620 }
 621
 622 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys *ws, struct radeon_drm_cs *cs)
 623 {
 624 retry:
 625     pipe_mutex_lock(ws->cs_stack_lock);
 626     if (ws->ncs >= RING_LAST) {
 627         /* no room left for a flush */
 628         pipe_mutex_unlock(ws->cs_stack_lock);
 629         goto retry;
 630     }
 631     ws->cs_stack[ws->ncs++] = cs;
 632     pipe_mutex_unlock(ws->cs_stack_lock);
 633     pipe_semaphore_signal(&ws->cs_queued);
 634 }
 635
 636 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param)
 637 {
 638     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys *)param;
 639     struct radeon_drm_cs *cs;
 640     unsigned i;
 641
 642     while (1) {
 643         pipe_semaphore_wait(&ws->cs_queued);
 644         if (ws->kill_thread)
 645             break;
 646
 647         pipe_mutex_lock(ws->cs_stack_lock);
 648         cs = ws->cs_stack[0];
 649         for (i = 1; i < ws->ncs; i++)
 650             ws->cs_stack[i - 1] = ws->cs_stack[i];
 651         ws->cs_stack[--ws->ncs] = NULL;
 652         pipe_mutex_unlock(ws->cs_stack_lock);
 653
 654         if (cs) {
 655             radeon_drm_cs_emit_ioctl_oneshot(cs, cs->cst);
 656             pipe_semaphore_signal(&cs->flush_completed);
 657         }
 658     }
 659     pipe_mutex_lock(ws->cs_stack_lock);
 660     for (i = 0; i < ws->ncs; i++) {
 661         pipe_semaphore_signal(&ws->cs_stack[i]->flush_completed);
 662         ws->cs_stack[i] = NULL;
 663     }
 664     ws->ncs = 0;
 665     pipe_mutex_unlock(ws->cs_stack_lock);
 666     return 0;
 667 }
 668
 669 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", TRUE)
 670 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param);
 671
 672 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 673 {
 674     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 675     bool destroy;
 676
 677     /* When the reference counter drops to zero, remove the fd from the table.
 678      * This must happen while the mutex is locked, so that
 679      * radeon_drm_winsys_create in another thread doesn't get the winsys
 680      * from the table when the counter drops to 0. */
 681     pipe_mutex_lock(fd_tab_mutex);
 682
 683     destroy = pipe_reference(&rws->reference, NULL);
 684     if (destroy && fd_tab)
 685         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 686
 687     pipe_mutex_unlock(fd_tab_mutex);
 688     return destroy;
 689 }
 690
 691 PUBLIC struct radeon_winsys *
 692 radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
 693 {
 694     struct radeon_drm_winsys *ws;
 695
 696     pipe_mutex_lock(fd_tab_mutex);
 697     if (!fd_tab) {
 698         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 699     }
 700
 701     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 702     if (ws) {
 703         pipe_reference(NULL, &ws->reference);
 704         pipe_mutex_unlock(fd_tab_mutex);
 705         return &ws->base;
 706     }
 707
 708     ws = CALLOC_STRUCT(radeon_drm_winsys);
 709     if (!ws) {
 710         pipe_mutex_unlock(fd_tab_mutex);
 711         return NULL;
 712     }
 713
 714     ws->fd = fd;
 715
 716     if (!do_winsys_init(ws))
 717         goto fail;
 718
 719     /* Create managers. */
 720     ws->kman = radeon_bomgr_create(ws);
 721     if (!ws->kman)
 722         goto fail;
 723
 724     ws->cman = pb_cache_manager_create(ws->kman, 1000000, 2.0f, 0,
 725                                        MIN2(ws->info.vram_size, ws->info.gart_size));
 726     if (!ws->cman)
 727         goto fail;
 728
 729     if (ws->gen >= DRV_R600) {
 730         ws->surf_man = radeon_surface_manager_new(fd);
 731         if (!ws->surf_man)
 732             goto fail;
 733     }
 734
 735     /* init reference */
 736     pipe_reference_init(&ws->reference, 1);
 737
 738     /* Set functions. */
 739     ws->base.unref = radeon_winsys_unref;
 740     ws->base.destroy = radeon_winsys_destroy;
 741     ws->base.query_info = radeon_query_info;
 742     ws->base.cs_request_feature = radeon_cs_request_feature;
 743     ws->base.surface_init = radeon_drm_winsys_surface_init;
 744     ws->base.surface_best = radeon_drm_winsys_surface_best;
 745     ws->base.query_value = radeon_query_value;
 746     ws->base.read_registers = radeon_read_registers;
 747
 748     radeon_bomgr_init_functions(ws);
 749     radeon_drm_cs_init_functions(ws);
 750
 751     pipe_mutex_init(ws->hyperz_owner_mutex);
 752     pipe_mutex_init(ws->cmask_owner_mutex);
 753     pipe_mutex_init(ws->cs_stack_lock);
 754
 755     ws->ncs = 0;
 756     pipe_semaphore_init(&ws->cs_queued, 0);
 757     if (ws->num_cpus > 1 && debug_get_option_thread())
 758         ws->thread = pipe_thread_create(radeon_drm_cs_emit_ioctl, ws);
 759
 760     /* Create the screen at the end. The winsys must be initialized
 761      * completely.
 762      *
 763      * Alternatively, we could create the screen based on "ws->gen"
 764      * and link all drivers into one binary blob. */
 765     ws->base.screen = screen_create(&ws->base);
 766     if (!ws->base.screen) {
 767         radeon_winsys_destroy(&ws->base);
 768         pipe_mutex_unlock(fd_tab_mutex);
 769         return NULL;
 770     }
 771
 772     util_hash_table_set(fd_tab, intptr_to_pointer(fd), ws);
 773
 774     /* We must unlock the mutex once the winsys is fully initialized, so that
 775      * other threads attempting to create the winsys from the same fd will
 776      * get a fully initialized winsys and not just half-way initialized. */
 777     pipe_mutex_unlock(fd_tab_mutex);
 778
 779     return &ws->base;
 780
 781 fail:
 782     pipe_mutex_unlock(fd_tab_mutex);
 783     if (ws->cman)
 784         ws->cman->destroy(ws->cman);
 785     if (ws->kman)
 786         ws->kman->destroy(ws->kman);
 787     if (ws->surf_man)
 788         radeon_surface_manager_free(ws->surf_man);
 789     FREE(ws);
 790     return NULL;
 791 }