src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "pipebuffer/pb_bufmgr.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_hash_table.h"
  41
  42 #include <xf86drm.h>
  43 #include <stdio.h>
  44 #include <sys/types.h>
  45 #include <sys/stat.h>
  46 #include <unistd.h>
  47 #include <radeon_surface.h>
  48
  49 #ifndef RADEON_INFO_ACTIVE_CU_COUNT
  50 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
  51 #endif
  52
  53 #ifndef RADEON_INFO_CURRENT_GPU_TEMP
  54 #define RADEON_INFO_CURRENT_GPU_TEMP    0x21
  55 #define RADEON_INFO_CURRENT_GPU_SCLK    0x22
  56 #define RADEON_INFO_CURRENT_GPU_MCLK    0x23
  57 #define RADEON_INFO_READ_REG            0x24
  58 #endif
  59
  60 #define RADEON_INFO_VA_UNMAP_WORKING    0x25
  61
  62 #ifndef RADEON_INFO_GPU_RESET_COUNTER
  63 #define RADEON_INFO_GPU_RESET_COUNTER   0x26
  64 #endif
  65
  66 static struct util_hash_table *fd_tab = NULL;
  67 pipe_static_mutex(fd_tab_mutex);
  68
  69 /* Enable/disable feature access for one command stream.
  70  * If enable == TRUE, return TRUE on success.
  71  * Otherwise, return FALSE.
  72  *
  73  * We basically do the same thing kernel does, because we have to deal
  74  * with multiple contexts (here command streams) backed by one winsys. */
  75 static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
  76                                     struct radeon_drm_cs **owner,
  77                                     pipe_mutex *mutex,
  78                                     unsigned request, const char *request_name,
  79                                     boolean enable)
  80 {
  81     struct drm_radeon_info info;
  82     unsigned value = enable ? 1 : 0;
  83
  84     memset(&info, 0, sizeof(info));
  85
  86     pipe_mutex_lock(*mutex);
  87
  88     /* Early exit if we are sure the request will fail. */
  89     if (enable) {
  90         if (*owner) {
  91             pipe_mutex_unlock(*mutex);
  92             return FALSE;
  93         }
  94     } else {
  95         if (*owner != applier) {
  96             pipe_mutex_unlock(*mutex);
  97             return FALSE;
  98         }
  99     }
 100
 101     /* Pass through the request to the kernel. */
 102     info.value = (unsigned long)&value;
 103     info.request = request;
 104     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
 105                             &info, sizeof(info)) != 0) {
 106         pipe_mutex_unlock(*mutex);
 107         return FALSE;
 108     }
 109
 110     /* Update the rights in the winsys. */
 111     if (enable) {
 112         if (value) {
 113             *owner = applier;
 114             pipe_mutex_unlock(*mutex);
 115             return TRUE;
 116         }
 117     } else {
 118         *owner = NULL;
 119     }
 120
 121     pipe_mutex_unlock(*mutex);
 122     return FALSE;
 123 }
 124
 125 static boolean radeon_get_drm_value(int fd, unsigned request,
 126                                     const char *errname, uint32_t *out)
 127 {
 128     struct drm_radeon_info info;
 129     int retval;
 130
 131     memset(&info, 0, sizeof(info));
 132
 133     info.value = (unsigned long)out;
 134     info.request = request;
 135
 136     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 137     if (retval) {
 138         if (errname) {
 139             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 140                     errname, retval);
 141         }
 142         return FALSE;
 143     }
 144     return TRUE;
 145 }
 146
 147 /* Helper function to do the ioctls needed for setup and init. */
 148 static boolean do_winsys_init(struct radeon_drm_winsys *ws)
 149 {
 150     struct drm_radeon_gem_info gem_info;
 151     int retval;
 152     drmVersionPtr version;
 153
 154     memset(&gem_info, 0, sizeof(gem_info));
 155
 156     /* We do things in a specific order here.
 157      *
 158      * DRM version first. We need to be sure we're running on a KMS chipset.
 159      * This is also for some features.
 160      *
 161      * Then, the PCI ID. This is essential and should return usable numbers
 162      * for all Radeons. If this fails, we probably got handed an FD for some
 163      * non-Radeon card.
 164      *
 165      * The GEM info is actually bogus on the kernel side, as well as our side
 166      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 167      * we don't actually use the info for anything yet.
 168      *
 169      * The GB and Z pipe requests should always succeed, but they might not
 170      * return sensical values for all chipsets, but that's alright because
 171      * the pipe drivers already know that.
 172      */
 173
 174     /* Get DRM version. */
 175     version = drmGetVersion(ws->fd);
 176     if (version->version_major != 2 ||
 177         version->version_minor < 3) {
 178         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 179                 "only compatible with 2.3.x (kernel 2.6.34) or later.\n",
 180                 __FUNCTION__,
 181                 version->version_major,
 182                 version->version_minor,
 183                 version->version_patchlevel);
 184         drmFreeVersion(version);
 185         return FALSE;
 186     }
 187
 188     ws->info.drm_major = version->version_major;
 189     ws->info.drm_minor = version->version_minor;
 190     ws->info.drm_patchlevel = version->version_patchlevel;
 191     drmFreeVersion(version);
 192
 193     /* Get PCI ID. */
 194     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 195                               &ws->info.pci_id))
 196         return FALSE;
 197
 198     /* Check PCI ID. */
 199     switch (ws->info.pci_id) {
 200 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 201 #include "pci_ids/r300_pci_ids.h"
 202 #undef CHIPSET
 203
 204 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 205 #include "pci_ids/r600_pci_ids.h"
 206 #undef CHIPSET
 207
 208 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 209 #include "pci_ids/radeonsi_pci_ids.h"
 210 #undef CHIPSET
 211
 212     default:
 213         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 214         return FALSE;
 215     }
 216
 217     switch (ws->info.family) {
 218     default:
 219     case CHIP_UNKNOWN:
 220         fprintf(stderr, "radeon: Unknown family.\n");
 221         return FALSE;
 222     case CHIP_R300:
 223     case CHIP_R350:
 224     case CHIP_RV350:
 225     case CHIP_RV370:
 226     case CHIP_RV380:
 227     case CHIP_RS400:
 228     case CHIP_RC410:
 229     case CHIP_RS480:
 230         ws->info.chip_class = R300;
 231         break;
 232     case CHIP_R420:     /* R4xx-based cores. */
 233     case CHIP_R423:
 234     case CHIP_R430:
 235     case CHIP_R480:
 236     case CHIP_R481:
 237     case CHIP_RV410:
 238     case CHIP_RS600:
 239     case CHIP_RS690:
 240     case CHIP_RS740:
 241         ws->info.chip_class = R400;
 242         break;
 243     case CHIP_RV515:    /* R5xx-based cores. */
 244     case CHIP_R520:
 245     case CHIP_RV530:
 246     case CHIP_R580:
 247     case CHIP_RV560:
 248     case CHIP_RV570:
 249         ws->info.chip_class = R500;
 250         break;
 251     case CHIP_R600:
 252     case CHIP_RV610:
 253     case CHIP_RV630:
 254     case CHIP_RV670:
 255     case CHIP_RV620:
 256     case CHIP_RV635:
 257     case CHIP_RS780:
 258     case CHIP_RS880:
 259         ws->info.chip_class = R600;
 260         break;
 261     case CHIP_RV770:
 262     case CHIP_RV730:
 263     case CHIP_RV710:
 264     case CHIP_RV740:
 265         ws->info.chip_class = R700;
 266         break;
 267     case CHIP_CEDAR:
 268     case CHIP_REDWOOD:
 269     case CHIP_JUNIPER:
 270     case CHIP_CYPRESS:
 271     case CHIP_HEMLOCK:
 272     case CHIP_PALM:
 273     case CHIP_SUMO:
 274     case CHIP_SUMO2:
 275     case CHIP_BARTS:
 276     case CHIP_TURKS:
 277     case CHIP_CAICOS:
 278         ws->info.chip_class = EVERGREEN;
 279         break;
 280     case CHIP_CAYMAN:
 281     case CHIP_ARUBA:
 282         ws->info.chip_class = CAYMAN;
 283         break;
 284     case CHIP_TAHITI:
 285     case CHIP_PITCAIRN:
 286     case CHIP_VERDE:
 287     case CHIP_OLAND:
 288     case CHIP_HAINAN:
 289         ws->info.chip_class = SI;
 290         break;
 291     case CHIP_BONAIRE:
 292     case CHIP_KAVERI:
 293     case CHIP_KABINI:
 294     case CHIP_HAWAII:
 295     case CHIP_MULLINS:
 296         ws->info.chip_class = CIK;
 297         break;
 298     }
 299
 300     /* Check for dma */
 301     ws->info.r600_has_dma = FALSE;
 302     /* DMA is disabled on R700. There is IB corruption and hangs. */
 303     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 304         ws->info.r600_has_dma = TRUE;
 305     }
 306
 307     /* Check for UVD and VCE */
 308     ws->info.has_uvd = FALSE;
 309     ws->info.vce_fw_version = 0x00000000;
 310     if (ws->info.drm_minor >= 32) {
 311         uint32_t value = RADEON_CS_RING_UVD;
 312         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 313                                  "UVD Ring working", &value))
 314             ws->info.has_uvd = value;
 315
 316         value = RADEON_CS_RING_VCE;
 317         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 318                                  NULL, &value) && value) {
 319
 320             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 321                                      "VCE FW version", &value))
 322                 ws->info.vce_fw_version = value;
 323         }
 324     }
 325
 326     /* Check for userptr support. */
 327     {
 328         struct drm_radeon_gem_userptr args = {0};
 329
 330         /* If the ioctl doesn't exist, -EINVAL is returned.
 331          *
 332          * If the ioctl exists, it should return -EACCES
 333          * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
 334          * aren't set.
 335          */
 336         ws->info.has_userptr =
 337             drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
 338                                 &args, sizeof(args)) == -EACCES;
 339     }
 340
 341     /* Get GEM info. */
 342     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 343             &gem_info, sizeof(gem_info));
 344     if (retval) {
 345         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 346                 retval);
 347         return FALSE;
 348     }
 349     ws->info.gart_size = gem_info.gart_size;
 350     ws->info.vram_size = gem_info.vram_size;
 351
 352     /* Get max clock frequency info and convert it to MHz */
 353     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 354                          &ws->info.max_sclk);
 355     ws->info.max_sclk /= 1000;
 356
 357     radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
 358                          &ws->info.si_backend_enabled_mask);
 359
 360     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 361
 362     /* Generation-specific queries. */
 363     if (ws->gen == DRV_R300) {
 364         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 365                                   "GB pipe count",
 366                                   &ws->info.r300_num_gb_pipes))
 367             return FALSE;
 368
 369         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 370                                   "Z pipe count",
 371                                   &ws->info.r300_num_z_pipes))
 372             return FALSE;
 373     }
 374     else if (ws->gen >= DRV_R600) {
 375         if (ws->info.drm_minor >= 9 &&
 376             !radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 377                                   "num backends",
 378                                   &ws->info.r600_num_backends))
 379             return FALSE;
 380
 381         /* get the GPU counter frequency, failure is not fatal */
 382         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 383                              &ws->info.r600_clock_crystal_freq);
 384
 385         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 386                              &ws->info.r600_tiling_config);
 387
 388         if (ws->info.drm_minor >= 11) {
 389             radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 390                                  &ws->info.r600_num_tile_pipes);
 391
 392             if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 393                                       &ws->info.r600_backend_map))
 394                 ws->info.r600_backend_map_valid = TRUE;
 395         }
 396
 397         ws->info.r600_virtual_address = FALSE;
 398         if (ws->info.drm_minor >= 13) {
 399             uint32_t ib_vm_max_size;
 400
 401             ws->info.r600_virtual_address = TRUE;
 402             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 403                                       &ws->va_start))
 404                 ws->info.r600_virtual_address = FALSE;
 405             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 406                                       &ib_vm_max_size))
 407                 ws->info.r600_virtual_address = FALSE;
 408             radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
 409                                  &ws->va_unmap_working);
 410         }
 411         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", FALSE))
 412                 ws->info.r600_virtual_address = FALSE;
 413     }
 414
 415     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 416      * chips have at least 2 pipes, so we use 2 as a default. */
 417     ws->info.r600_max_pipes = 2;
 418     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 419                          &ws->info.r600_max_pipes);
 420
 421     /* All GPUs have at least one compute unit */
 422     ws->info.num_good_compute_units = 1;
 423     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 424                          &ws->info.num_good_compute_units);
 425
 426     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 427                          &ws->info.max_se);
 428
 429     if (!ws->info.max_se) {
 430         switch (ws->info.family) {
 431         default:
 432             ws->info.max_se = 1;
 433             break;
 434         case CHIP_CYPRESS:
 435         case CHIP_HEMLOCK:
 436         case CHIP_BARTS:
 437         case CHIP_CAYMAN:
 438         case CHIP_TAHITI:
 439         case CHIP_PITCAIRN:
 440         case CHIP_BONAIRE:
 441             ws->info.max_se = 2;
 442             break;
 443         case CHIP_HAWAII:
 444             ws->info.max_se = 4;
 445             break;
 446         }
 447     }
 448
 449     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 450                          &ws->info.max_sh_per_se);
 451
 452     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 453                          &ws->accel_working2);
 454     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 455         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 456                 "returned accel_working2 value %u is smaller than 2. "
 457                 "Please install a newer kernel.\n",
 458                 ws->accel_working2);
 459         return FALSE;
 460     }
 461
 462     if (radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 463                              ws->info.si_tile_mode_array)) {
 464         ws->info.si_tile_mode_array_valid = TRUE;
 465     }
 466
 467     if (radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 468                              ws->info.cik_macrotile_mode_array)) {
 469         ws->info.cik_macrotile_mode_array_valid = TRUE;
 470     }
 471
 472     /* Hawaii with old firmware needs type2 nop packet.
 473      * accel_working2 with value 3 indicates the new firmware.
 474      */
 475     ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI ||
 476                                      (ws->info.family == CHIP_HAWAII &&
 477                                       ws->accel_working2 < 3);
 478
 479     return TRUE;
 480 }
 481
 482 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 483 {
 484     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 485
 486     if (ws->thread) {
 487         ws->kill_thread = 1;
 488         pipe_semaphore_signal(&ws->cs_queued);
 489         pipe_thread_wait(ws->thread);
 490     }
 491     pipe_semaphore_destroy(&ws->cs_queued);
 492
 493     pipe_mutex_destroy(ws->hyperz_owner_mutex);
 494     pipe_mutex_destroy(ws->cmask_owner_mutex);
 495     pipe_mutex_destroy(ws->cs_stack_lock);
 496
 497     pb_cache_deinit(&ws->bo_cache);
 498
 499     if (ws->gen >= DRV_R600) {
 500         radeon_surface_manager_free(ws->surf_man);
 501     }
 502
 503     util_hash_table_destroy(ws->bo_names);
 504     util_hash_table_destroy(ws->bo_handles);
 505     util_hash_table_destroy(ws->bo_vas);
 506     pipe_mutex_destroy(ws->bo_handles_mutex);
 507     pipe_mutex_destroy(ws->bo_va_mutex);
 508
 509     if (ws->fd >= 0)
 510         close(ws->fd);
 511
 512     FREE(rws);
 513 }
 514
 515 static void radeon_query_info(struct radeon_winsys *rws,
 516                               struct radeon_info *info)
 517 {
 518     *info = ((struct radeon_drm_winsys *)rws)->info;
 519 }
 520
 521 static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 522                                          enum radeon_feature_id fid,
 523                                          boolean enable)
 524 {
 525     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 526
 527     switch (fid) {
 528     case RADEON_FID_R300_HYPERZ_ACCESS:
 529         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 530                                     &cs->ws->hyperz_owner_mutex,
 531                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 532                                     enable);
 533
 534     case RADEON_FID_R300_CMASK_ACCESS:
 535         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 536                                     &cs->ws->cmask_owner_mutex,
 537                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 538                                     enable);
 539     }
 540     return FALSE;
 541 }
 542
 543 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 544                                    enum radeon_value_id value)
 545 {
 546     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 547     uint64_t retval = 0;
 548
 549     switch (value) {
 550     case RADEON_REQUESTED_VRAM_MEMORY:
 551         return ws->allocated_vram;
 552     case RADEON_REQUESTED_GTT_MEMORY:
 553         return ws->allocated_gtt;
 554     case RADEON_BUFFER_WAIT_TIME_NS:
 555         return ws->buffer_wait_time;
 556     case RADEON_TIMESTAMP:
 557         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 558             assert(0);
 559             return 0;
 560         }
 561
 562         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 563                              (uint32_t*)&retval);
 564         return retval;
 565     case RADEON_NUM_CS_FLUSHES:
 566         return ws->num_cs_flushes;
 567     case RADEON_NUM_BYTES_MOVED:
 568         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 569                              "num-bytes-moved", (uint32_t*)&retval);
 570         return retval;
 571     case RADEON_VRAM_USAGE:
 572         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 573                              "vram-usage", (uint32_t*)&retval);
 574         return retval;
 575     case RADEON_GTT_USAGE:
 576         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 577                              "gtt-usage", (uint32_t*)&retval);
 578         return retval;
 579     case RADEON_GPU_TEMPERATURE:
 580         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
 581                              "gpu-temp", (uint32_t*)&retval);
 582         return retval;
 583     case RADEON_CURRENT_SCLK:
 584         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
 585                              "current-gpu-sclk", (uint32_t*)&retval);
 586         return retval;
 587     case RADEON_CURRENT_MCLK:
 588         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
 589                              "current-gpu-mclk", (uint32_t*)&retval);
 590         return retval;
 591     case RADEON_GPU_RESET_COUNTER:
 592         radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
 593                              "gpu-reset-counter", (uint32_t*)&retval);
 594         return retval;
 595     }
 596     return 0;
 597 }
 598
 599 static bool radeon_read_registers(struct radeon_winsys *rws,
 600                                   unsigned reg_offset,
 601                                   unsigned num_registers, uint32_t *out)
 602 {
 603     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 604     unsigned i;
 605
 606     for (i = 0; i < num_registers; i++) {
 607         uint32_t reg = reg_offset + i*4;
 608
 609         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg))
 610             return false;
 611         out[i] = reg;
 612     }
 613     return true;
 614 }
 615
 616 static unsigned hash_fd(void *key)
 617 {
 618     int fd = pointer_to_intptr(key);
 619     struct stat stat;
 620     fstat(fd, &stat);
 621
 622     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 623 }
 624
 625 static int compare_fd(void *key1, void *key2)
 626 {
 627     int fd1 = pointer_to_intptr(key1);
 628     int fd2 = pointer_to_intptr(key2);
 629     struct stat stat1, stat2;
 630     fstat(fd1, &stat1);
 631     fstat(fd2, &stat2);
 632
 633     return stat1.st_dev != stat2.st_dev ||
 634            stat1.st_ino != stat2.st_ino ||
 635            stat1.st_rdev != stat2.st_rdev;
 636 }
 637
 638 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys *ws, struct radeon_drm_cs *cs)
 639 {
 640 retry:
 641     pipe_mutex_lock(ws->cs_stack_lock);
 642     if (ws->ncs >= RING_LAST) {
 643         /* no room left for a flush */
 644         pipe_mutex_unlock(ws->cs_stack_lock);
 645         goto retry;
 646     }
 647     ws->cs_stack[ws->ncs++] = cs;
 648     pipe_mutex_unlock(ws->cs_stack_lock);
 649     pipe_semaphore_signal(&ws->cs_queued);
 650 }
 651
 652 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param)
 653 {
 654     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys *)param;
 655     struct radeon_drm_cs *cs;
 656     unsigned i;
 657
 658     while (1) {
 659         pipe_semaphore_wait(&ws->cs_queued);
 660         if (ws->kill_thread)
 661             break;
 662
 663         pipe_mutex_lock(ws->cs_stack_lock);
 664         cs = ws->cs_stack[0];
 665         for (i = 1; i < ws->ncs; i++)
 666             ws->cs_stack[i - 1] = ws->cs_stack[i];
 667         ws->cs_stack[--ws->ncs] = NULL;
 668         pipe_mutex_unlock(ws->cs_stack_lock);
 669
 670         if (cs) {
 671             radeon_drm_cs_emit_ioctl_oneshot(cs, cs->cst);
 672             pipe_semaphore_signal(&cs->flush_completed);
 673         }
 674     }
 675     pipe_mutex_lock(ws->cs_stack_lock);
 676     for (i = 0; i < ws->ncs; i++) {
 677         pipe_semaphore_signal(&ws->cs_stack[i]->flush_completed);
 678         ws->cs_stack[i] = NULL;
 679     }
 680     ws->ncs = 0;
 681     pipe_mutex_unlock(ws->cs_stack_lock);
 682     return 0;
 683 }
 684
 685 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", TRUE)
 686 static PIPE_THREAD_ROUTINE(radeon_drm_cs_emit_ioctl, param);
 687
 688 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 689 {
 690     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 691     bool destroy;
 692
 693     /* When the reference counter drops to zero, remove the fd from the table.
 694      * This must happen while the mutex is locked, so that
 695      * radeon_drm_winsys_create in another thread doesn't get the winsys
 696      * from the table when the counter drops to 0. */
 697     pipe_mutex_lock(fd_tab_mutex);
 698
 699     destroy = pipe_reference(&rws->reference, NULL);
 700     if (destroy && fd_tab)
 701         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 702
 703     pipe_mutex_unlock(fd_tab_mutex);
 704     return destroy;
 705 }
 706
 707 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 708
 709 static unsigned handle_hash(void *key)
 710 {
 711     return PTR_TO_UINT(key);
 712 }
 713
 714 static int handle_compare(void *key1, void *key2)
 715 {
 716     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 717 }
 718
 719 PUBLIC struct radeon_winsys *
 720 radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
 721 {
 722     struct radeon_drm_winsys *ws;
 723
 724     pipe_mutex_lock(fd_tab_mutex);
 725     if (!fd_tab) {
 726         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 727     }
 728
 729     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 730     if (ws) {
 731         pipe_reference(NULL, &ws->reference);
 732         pipe_mutex_unlock(fd_tab_mutex);
 733         return &ws->base;
 734     }
 735
 736     ws = CALLOC_STRUCT(radeon_drm_winsys);
 737     if (!ws) {
 738         pipe_mutex_unlock(fd_tab_mutex);
 739         return NULL;
 740     }
 741
 742     ws->fd = dup(fd);
 743
 744     if (!do_winsys_init(ws))
 745         goto fail;
 746
 747     pb_cache_init(&ws->bo_cache, 500000, 2.0f, 0,
 748                   MIN2(ws->info.vram_size, ws->info.gart_size),
 749                   radeon_bo_destroy,
 750                   radeon_bo_can_reclaim);
 751
 752     if (ws->gen >= DRV_R600) {
 753         ws->surf_man = radeon_surface_manager_new(ws->fd);
 754         if (!ws->surf_man)
 755             goto fail;
 756     }
 757
 758     /* init reference */
 759     pipe_reference_init(&ws->reference, 1);
 760
 761     /* Set functions. */
 762     ws->base.unref = radeon_winsys_unref;
 763     ws->base.destroy = radeon_winsys_destroy;
 764     ws->base.query_info = radeon_query_info;
 765     ws->base.cs_request_feature = radeon_cs_request_feature;
 766     ws->base.query_value = radeon_query_value;
 767     ws->base.read_registers = radeon_read_registers;
 768
 769     radeon_drm_bo_init_functions(ws);
 770     radeon_drm_cs_init_functions(ws);
 771     radeon_surface_init_functions(ws);
 772
 773     pipe_mutex_init(ws->hyperz_owner_mutex);
 774     pipe_mutex_init(ws->cmask_owner_mutex);
 775     pipe_mutex_init(ws->cs_stack_lock);
 776
 777     ws->bo_names = util_hash_table_create(handle_hash, handle_compare);
 778     ws->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 779     ws->bo_vas = util_hash_table_create(handle_hash, handle_compare);
 780     pipe_mutex_init(ws->bo_handles_mutex);
 781     pipe_mutex_init(ws->bo_va_mutex);
 782     ws->va_offset = ws->va_start;
 783     list_inithead(&ws->va_holes);
 784
 785     /* TTM aligns the BO size to the CPU page size */
 786     ws->size_align = sysconf(_SC_PAGESIZE);
 787
 788     ws->ncs = 0;
 789     pipe_semaphore_init(&ws->cs_queued, 0);
 790     if (ws->num_cpus > 1 && debug_get_option_thread())
 791         ws->thread = pipe_thread_create(radeon_drm_cs_emit_ioctl, ws);
 792
 793     /* Create the screen at the end. The winsys must be initialized
 794      * completely.
 795      *
 796      * Alternatively, we could create the screen based on "ws->gen"
 797      * and link all drivers into one binary blob. */
 798     ws->base.screen = screen_create(&ws->base);
 799     if (!ws->base.screen) {
 800         radeon_winsys_destroy(&ws->base);
 801         pipe_mutex_unlock(fd_tab_mutex);
 802         return NULL;
 803     }
 804
 805     util_hash_table_set(fd_tab, intptr_to_pointer(ws->fd), ws);
 806
 807     /* We must unlock the mutex once the winsys is fully initialized, so that
 808      * other threads attempting to create the winsys from the same fd will
 809      * get a fully initialized winsys and not just half-way initialized. */
 810     pipe_mutex_unlock(fd_tab_mutex);
 811
 812     return &ws->base;
 813
 814 fail:
 815     pipe_mutex_unlock(fd_tab_mutex);
 816     pb_cache_deinit(&ws->bo_cache);
 817     if (ws->surf_man)
 818         radeon_surface_manager_free(ws->surf_man);
 819     if (ws->fd >= 0)
 820         close(ws->fd);
 821
 822     FREE(ws);
 823     return NULL;
 824 }