src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  15  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  16  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  17  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  18  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * The above copyright notice and this permission notice (including the
  24  * next paragraph) shall be included in all copies or substantial portions
  25  * of the Software.
  26  */
  27 /*
  28  * Authors:
  29  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  30  *      Joakim Sindholt <opensource@zhasha.com>
  31  *      Marek Olšák <maraeo@gmail.com>
  32  */
  33
  34 #include "radeon_drm_bo.h"
  35 #include "radeon_drm_cs.h"
  36 #include "radeon_drm_public.h"
  37
  38 #include "pipebuffer/pb_bufmgr.h"
  39 #include "util/u_memory.h"
  40 #include "util/u_hash_table.h"
  41
  42 #include <xf86drm.h>
  43 #include <stdio.h>
  44 #include <sys/types.h>
  45 #include <sys/stat.h>
  46 #include <unistd.h>
  47 #include <radeon_surface.h>
  48
  49 #ifndef RADEON_INFO_ACTIVE_CU_COUNT
  50 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
  51 #endif
  52
  53 #ifndef RADEON_INFO_CURRENT_GPU_TEMP
  54 #define RADEON_INFO_CURRENT_GPU_TEMP    0x21
  55 #define RADEON_INFO_CURRENT_GPU_SCLK    0x22
  56 #define RADEON_INFO_CURRENT_GPU_MCLK    0x23
  57 #define RADEON_INFO_READ_REG            0x24
  58 #endif
  59
  60 #define RADEON_INFO_VA_UNMAP_WORKING    0x25
  61
  62 #ifndef RADEON_INFO_GPU_RESET_COUNTER
  63 #define RADEON_INFO_GPU_RESET_COUNTER   0x26
  64 #endif
  65
  66 static struct util_hash_table *fd_tab = NULL;
  67 pipe_static_mutex(fd_tab_mutex);
  68
  69 /* Enable/disable feature access for one command stream.
  70  * If enable == TRUE, return TRUE on success.
  71  * Otherwise, return FALSE.
  72  *
  73  * We basically do the same thing kernel does, because we have to deal
  74  * with multiple contexts (here command streams) backed by one winsys. */
  75 static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
  76                                     struct radeon_drm_cs **owner,
  77                                     pipe_mutex *mutex,
  78                                     unsigned request, const char *request_name,
  79                                     boolean enable)
  80 {
  81     struct drm_radeon_info info;
  82     unsigned value = enable ? 1 : 0;
  83
  84     memset(&info, 0, sizeof(info));
  85
  86     pipe_mutex_lock(*mutex);
  87
  88     /* Early exit if we are sure the request will fail. */
  89     if (enable) {
  90         if (*owner) {
  91             pipe_mutex_unlock(*mutex);
  92             return FALSE;
  93         }
  94     } else {
  95         if (*owner != applier) {
  96             pipe_mutex_unlock(*mutex);
  97             return FALSE;
  98         }
  99     }
 100
 101     /* Pass through the request to the kernel. */
 102     info.value = (unsigned long)&value;
 103     info.request = request;
 104     if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
 105                             &info, sizeof(info)) != 0) {
 106         pipe_mutex_unlock(*mutex);
 107         return FALSE;
 108     }
 109
 110     /* Update the rights in the winsys. */
 111     if (enable) {
 112         if (value) {
 113             *owner = applier;
 114             pipe_mutex_unlock(*mutex);
 115             return TRUE;
 116         }
 117     } else {
 118         *owner = NULL;
 119     }
 120
 121     pipe_mutex_unlock(*mutex);
 122     return FALSE;
 123 }
 124
 125 static boolean radeon_get_drm_value(int fd, unsigned request,
 126                                     const char *errname, uint32_t *out)
 127 {
 128     struct drm_radeon_info info;
 129     int retval;
 130
 131     memset(&info, 0, sizeof(info));
 132
 133     info.value = (unsigned long)out;
 134     info.request = request;
 135
 136     retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info));
 137     if (retval) {
 138         if (errname) {
 139             fprintf(stderr, "radeon: Failed to get %s, error number %d\n",
 140                     errname, retval);
 141         }
 142         return FALSE;
 143     }
 144     return TRUE;
 145 }
 146
 147 /* Helper function to do the ioctls needed for setup and init. */
 148 static boolean do_winsys_init(struct radeon_drm_winsys *ws)
 149 {
 150     struct drm_radeon_gem_info gem_info;
 151     int retval;
 152     drmVersionPtr version;
 153
 154     memset(&gem_info, 0, sizeof(gem_info));
 155
 156     /* We do things in a specific order here.
 157      *
 158      * DRM version first. We need to be sure we're running on a KMS chipset.
 159      * This is also for some features.
 160      *
 161      * Then, the PCI ID. This is essential and should return usable numbers
 162      * for all Radeons. If this fails, we probably got handed an FD for some
 163      * non-Radeon card.
 164      *
 165      * The GEM info is actually bogus on the kernel side, as well as our side
 166      * (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
 167      * we don't actually use the info for anything yet.
 168      *
 169      * The GB and Z pipe requests should always succeed, but they might not
 170      * return sensical values for all chipsets, but that's alright because
 171      * the pipe drivers already know that.
 172      */
 173
 174     /* Get DRM version. */
 175     version = drmGetVersion(ws->fd);
 176     if (version->version_major != 2 ||
 177         version->version_minor < 12) {
 178         fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 179                 "only compatible with 2.12.0 (kernel 3.2) or later.\n",
 180                 __FUNCTION__,
 181                 version->version_major,
 182                 version->version_minor,
 183                 version->version_patchlevel);
 184         drmFreeVersion(version);
 185         return FALSE;
 186     }
 187
 188     ws->info.drm_major = version->version_major;
 189     ws->info.drm_minor = version->version_minor;
 190     ws->info.drm_patchlevel = version->version_patchlevel;
 191     drmFreeVersion(version);
 192
 193     /* Get PCI ID. */
 194     if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
 195                               &ws->info.pci_id))
 196         return FALSE;
 197
 198     /* Check PCI ID. */
 199     switch (ws->info.pci_id) {
 200 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
 201 #include "pci_ids/r300_pci_ids.h"
 202 #undef CHIPSET
 203
 204 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
 205 #include "pci_ids/r600_pci_ids.h"
 206 #undef CHIPSET
 207
 208 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
 209 #include "pci_ids/radeonsi_pci_ids.h"
 210 #undef CHIPSET
 211
 212     default:
 213         fprintf(stderr, "radeon: Invalid PCI ID.\n");
 214         return FALSE;
 215     }
 216
 217     switch (ws->info.family) {
 218     default:
 219     case CHIP_UNKNOWN:
 220         fprintf(stderr, "radeon: Unknown family.\n");
 221         return FALSE;
 222     case CHIP_R300:
 223     case CHIP_R350:
 224     case CHIP_RV350:
 225     case CHIP_RV370:
 226     case CHIP_RV380:
 227     case CHIP_RS400:
 228     case CHIP_RC410:
 229     case CHIP_RS480:
 230         ws->info.chip_class = R300;
 231         break;
 232     case CHIP_R420:     /* R4xx-based cores. */
 233     case CHIP_R423:
 234     case CHIP_R430:
 235     case CHIP_R480:
 236     case CHIP_R481:
 237     case CHIP_RV410:
 238     case CHIP_RS600:
 239     case CHIP_RS690:
 240     case CHIP_RS740:
 241         ws->info.chip_class = R400;
 242         break;
 243     case CHIP_RV515:    /* R5xx-based cores. */
 244     case CHIP_R520:
 245     case CHIP_RV530:
 246     case CHIP_R580:
 247     case CHIP_RV560:
 248     case CHIP_RV570:
 249         ws->info.chip_class = R500;
 250         break;
 251     case CHIP_R600:
 252     case CHIP_RV610:
 253     case CHIP_RV630:
 254     case CHIP_RV670:
 255     case CHIP_RV620:
 256     case CHIP_RV635:
 257     case CHIP_RS780:
 258     case CHIP_RS880:
 259         ws->info.chip_class = R600;
 260         break;
 261     case CHIP_RV770:
 262     case CHIP_RV730:
 263     case CHIP_RV710:
 264     case CHIP_RV740:
 265         ws->info.chip_class = R700;
 266         break;
 267     case CHIP_CEDAR:
 268     case CHIP_REDWOOD:
 269     case CHIP_JUNIPER:
 270     case CHIP_CYPRESS:
 271     case CHIP_HEMLOCK:
 272     case CHIP_PALM:
 273     case CHIP_SUMO:
 274     case CHIP_SUMO2:
 275     case CHIP_BARTS:
 276     case CHIP_TURKS:
 277     case CHIP_CAICOS:
 278         ws->info.chip_class = EVERGREEN;
 279         break;
 280     case CHIP_CAYMAN:
 281     case CHIP_ARUBA:
 282         ws->info.chip_class = CAYMAN;
 283         break;
 284     case CHIP_TAHITI:
 285     case CHIP_PITCAIRN:
 286     case CHIP_VERDE:
 287     case CHIP_OLAND:
 288     case CHIP_HAINAN:
 289         ws->info.chip_class = SI;
 290         break;
 291     case CHIP_BONAIRE:
 292     case CHIP_KAVERI:
 293     case CHIP_KABINI:
 294     case CHIP_HAWAII:
 295     case CHIP_MULLINS:
 296         ws->info.chip_class = CIK;
 297         break;
 298     }
 299
 300     /* Set which chips don't have dedicated VRAM. */
 301     switch (ws->info.family) {
 302     case CHIP_RS400:
 303     case CHIP_RC410:
 304     case CHIP_RS480:
 305     case CHIP_RS600:
 306     case CHIP_RS690:
 307     case CHIP_RS740:
 308     case CHIP_RS780:
 309     case CHIP_RS880:
 310     case CHIP_PALM:
 311     case CHIP_SUMO:
 312     case CHIP_SUMO2:
 313     case CHIP_ARUBA:
 314     case CHIP_KAVERI:
 315     case CHIP_KABINI:
 316     case CHIP_MULLINS:
 317        ws->info.has_dedicated_vram = false;
 318        break;
 319
 320     default:
 321        ws->info.has_dedicated_vram = true;
 322     }
 323
 324     /* Check for dma */
 325     ws->info.has_sdma = FALSE;
 326     /* DMA is disabled on R700. There is IB corruption and hangs. */
 327     if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
 328         ws->info.has_sdma = TRUE;
 329     }
 330
 331     /* Check for UVD and VCE */
 332     ws->info.has_uvd = FALSE;
 333     ws->info.vce_fw_version = 0x00000000;
 334     if (ws->info.drm_minor >= 32) {
 335         uint32_t value = RADEON_CS_RING_UVD;
 336         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 337                                  "UVD Ring working", &value))
 338             ws->info.has_uvd = value;
 339
 340         value = RADEON_CS_RING_VCE;
 341         if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
 342                                  NULL, &value) && value) {
 343
 344             if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
 345                                      "VCE FW version", &value))
 346                 ws->info.vce_fw_version = value;
 347         }
 348     }
 349
 350     /* Check for userptr support. */
 351     {
 352         struct drm_radeon_gem_userptr args = {0};
 353
 354         /* If the ioctl doesn't exist, -EINVAL is returned.
 355          *
 356          * If the ioctl exists, it should return -EACCES
 357          * if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
 358          * aren't set.
 359          */
 360         ws->info.has_userptr =
 361             drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
 362                                 &args, sizeof(args)) == -EACCES;
 363     }
 364
 365     /* Get GEM info. */
 366     retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
 367             &gem_info, sizeof(gem_info));
 368     if (retval) {
 369         fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
 370                 retval);
 371         return FALSE;
 372     }
 373     ws->info.gart_size = gem_info.gart_size;
 374     ws->info.vram_size = gem_info.vram_size;
 375
 376     /* Get max clock frequency info and convert it to MHz */
 377     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
 378                          &ws->info.max_shader_clock);
 379     ws->info.max_shader_clock /= 1000;
 380
 381     radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
 382                          &ws->info.enabled_rb_mask);
 383
 384     ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 385
 386     /* Generation-specific queries. */
 387     if (ws->gen == DRV_R300) {
 388         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
 389                                   "GB pipe count",
 390                                   &ws->info.r300_num_gb_pipes))
 391             return FALSE;
 392
 393         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
 394                                   "Z pipe count",
 395                                   &ws->info.r300_num_z_pipes))
 396             return FALSE;
 397     }
 398     else if (ws->gen >= DRV_R600) {
 399         uint32_t tiling_config = 0;
 400
 401         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
 402                                   "num backends",
 403                                   &ws->info.num_render_backends))
 404             return FALSE;
 405
 406         /* get the GPU counter frequency, failure is not fatal */
 407         radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
 408                              &ws->info.clock_crystal_freq);
 409
 410         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
 411                              &tiling_config);
 412
 413         ws->info.r600_num_banks =
 414             ws->info.chip_class >= EVERGREEN ?
 415                 4 << ((tiling_config & 0xf0) >> 4) :
 416                 4 << ((tiling_config & 0x30) >> 4);
 417
 418         ws->info.pipe_interleave_bytes =
 419             ws->info.chip_class >= EVERGREEN ?
 420                 256 << ((tiling_config & 0xf00) >> 8) :
 421                 256 << ((tiling_config & 0xc0) >> 6);
 422
 423         if (!ws->info.pipe_interleave_bytes)
 424             ws->info.pipe_interleave_bytes =
 425                 ws->info.chip_class >= EVERGREEN ? 512 : 256;
 426
 427         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
 428                              &ws->info.num_tile_pipes);
 429
 430         /* "num_tiles_pipes" must be equal to the number of pipes (Px) in the
 431          * pipe config field of the GB_TILE_MODE array. Only one card (Tahiti)
 432          * reports a different value (12). Fix it by setting what's in the
 433          * GB_TILE_MODE array (8).
 434          */
 435         if (ws->gen == DRV_SI && ws->info.num_tile_pipes == 12)
 436             ws->info.num_tile_pipes = 8;
 437
 438         if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
 439                                   &ws->info.r600_gb_backend_map))
 440             ws->info.r600_gb_backend_map_valid = TRUE;
 441
 442         ws->info.has_virtual_memory = FALSE;
 443         if (ws->info.drm_minor >= 13) {
 444             uint32_t ib_vm_max_size;
 445
 446             ws->info.has_virtual_memory = TRUE;
 447             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
 448                                       &ws->va_start))
 449                 ws->info.has_virtual_memory = FALSE;
 450             if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
 451                                       &ib_vm_max_size))
 452                 ws->info.has_virtual_memory = FALSE;
 453             radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
 454                                  &ws->va_unmap_working);
 455         }
 456         if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", FALSE))
 457                 ws->info.has_virtual_memory = FALSE;
 458     }
 459
 460     /* Get max pipes, this is only needed for compute shaders.  All evergreen+
 461      * chips have at least 2 pipes, so we use 2 as a default. */
 462     ws->info.r600_max_quad_pipes = 2;
 463     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
 464                          &ws->info.r600_max_quad_pipes);
 465
 466     /* All GPUs have at least one compute unit */
 467     ws->info.num_good_compute_units = 1;
 468     radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
 469                          &ws->info.num_good_compute_units);
 470
 471     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
 472                          &ws->info.max_se);
 473
 474     if (!ws->info.max_se) {
 475         switch (ws->info.family) {
 476         default:
 477             ws->info.max_se = 1;
 478             break;
 479         case CHIP_CYPRESS:
 480         case CHIP_HEMLOCK:
 481         case CHIP_BARTS:
 482         case CHIP_CAYMAN:
 483         case CHIP_TAHITI:
 484         case CHIP_PITCAIRN:
 485         case CHIP_BONAIRE:
 486             ws->info.max_se = 2;
 487             break;
 488         case CHIP_HAWAII:
 489             ws->info.max_se = 4;
 490             break;
 491         }
 492     }
 493
 494     radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
 495                          &ws->info.max_sh_per_se);
 496
 497     radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
 498                          &ws->accel_working2);
 499     if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
 500         fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
 501                 "returned accel_working2 value %u is smaller than 2. "
 502                 "Please install a newer kernel.\n",
 503                 ws->accel_working2);
 504         return FALSE;
 505     }
 506
 507     if (ws->info.chip_class == CIK) {
 508         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
 509                                   ws->info.cik_macrotile_mode_array)) {
 510             fprintf(stderr, "radeon: Kernel 3.13 is required for CIK support.\n");
 511             return FALSE;
 512         }
 513     }
 514
 515     if (ws->info.chip_class >= SI) {
 516         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
 517                                   ws->info.si_tile_mode_array)) {
 518             fprintf(stderr, "radeon: Kernel 3.10 is required for SI support.\n");
 519             return FALSE;
 520         }
 521     }
 522
 523     /* Hawaii with old firmware needs type2 nop packet.
 524      * accel_working2 with value 3 indicates the new firmware.
 525      */
 526     ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= SI ||
 527                                      (ws->info.family == CHIP_HAWAII &&
 528                                       ws->accel_working2 < 3);
 529
 530     return TRUE;
 531 }
 532
 533 static void radeon_winsys_destroy(struct radeon_winsys *rws)
 534 {
 535     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 536
 537     if (util_queue_is_initialized(&ws->cs_queue))
 538         util_queue_destroy(&ws->cs_queue);
 539
 540     pipe_mutex_destroy(ws->hyperz_owner_mutex);
 541     pipe_mutex_destroy(ws->cmask_owner_mutex);
 542
 543     pb_cache_deinit(&ws->bo_cache);
 544
 545     if (ws->gen >= DRV_R600) {
 546         radeon_surface_manager_free(ws->surf_man);
 547     }
 548
 549     util_hash_table_destroy(ws->bo_names);
 550     util_hash_table_destroy(ws->bo_handles);
 551     util_hash_table_destroy(ws->bo_vas);
 552     pipe_mutex_destroy(ws->bo_handles_mutex);
 553     pipe_mutex_destroy(ws->bo_va_mutex);
 554
 555     if (ws->fd >= 0)
 556         close(ws->fd);
 557
 558     FREE(rws);
 559 }
 560
 561 static void radeon_query_info(struct radeon_winsys *rws,
 562                               struct radeon_info *info)
 563 {
 564     *info = ((struct radeon_drm_winsys *)rws)->info;
 565 }
 566
 567 static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
 568                                          enum radeon_feature_id fid,
 569                                          boolean enable)
 570 {
 571     struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 572
 573     switch (fid) {
 574     case RADEON_FID_R300_HYPERZ_ACCESS:
 575         return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
 576                                     &cs->ws->hyperz_owner_mutex,
 577                                     RADEON_INFO_WANT_HYPERZ, "Hyper-Z",
 578                                     enable);
 579
 580     case RADEON_FID_R300_CMASK_ACCESS:
 581         return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
 582                                     &cs->ws->cmask_owner_mutex,
 583                                     RADEON_INFO_WANT_CMASK, "AA optimizations",
 584                                     enable);
 585     }
 586     return FALSE;
 587 }
 588
 589 static uint64_t radeon_query_value(struct radeon_winsys *rws,
 590                                    enum radeon_value_id value)
 591 {
 592     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 593     uint64_t retval = 0;
 594
 595     switch (value) {
 596     case RADEON_REQUESTED_VRAM_MEMORY:
 597         return ws->allocated_vram;
 598     case RADEON_REQUESTED_GTT_MEMORY:
 599         return ws->allocated_gtt;
 600     case RADEON_BUFFER_WAIT_TIME_NS:
 601         return ws->buffer_wait_time;
 602     case RADEON_TIMESTAMP:
 603         if (ws->info.drm_minor < 20 || ws->gen < DRV_R600) {
 604             assert(0);
 605             return 0;
 606         }
 607
 608         radeon_get_drm_value(ws->fd, RADEON_INFO_TIMESTAMP, "timestamp",
 609                              (uint32_t*)&retval);
 610         return retval;
 611     case RADEON_NUM_CS_FLUSHES:
 612         return ws->num_cs_flushes;
 613     case RADEON_NUM_BYTES_MOVED:
 614         radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BYTES_MOVED,
 615                              "num-bytes-moved", (uint32_t*)&retval);
 616         return retval;
 617     case RADEON_VRAM_USAGE:
 618         radeon_get_drm_value(ws->fd, RADEON_INFO_VRAM_USAGE,
 619                              "vram-usage", (uint32_t*)&retval);
 620         return retval;
 621     case RADEON_GTT_USAGE:
 622         radeon_get_drm_value(ws->fd, RADEON_INFO_GTT_USAGE,
 623                              "gtt-usage", (uint32_t*)&retval);
 624         return retval;
 625     case RADEON_GPU_TEMPERATURE:
 626         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_TEMP,
 627                              "gpu-temp", (uint32_t*)&retval);
 628         return retval;
 629     case RADEON_CURRENT_SCLK:
 630         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_SCLK,
 631                              "current-gpu-sclk", (uint32_t*)&retval);
 632         return retval;
 633     case RADEON_CURRENT_MCLK:
 634         radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
 635                              "current-gpu-mclk", (uint32_t*)&retval);
 636         return retval;
 637     case RADEON_GPU_RESET_COUNTER:
 638         radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
 639                              "gpu-reset-counter", (uint32_t*)&retval);
 640         return retval;
 641     }
 642     return 0;
 643 }
 644
 645 static bool radeon_read_registers(struct radeon_winsys *rws,
 646                                   unsigned reg_offset,
 647                                   unsigned num_registers, uint32_t *out)
 648 {
 649     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 650     unsigned i;
 651
 652     for (i = 0; i < num_registers; i++) {
 653         uint32_t reg = reg_offset + i*4;
 654
 655         if (!radeon_get_drm_value(ws->fd, RADEON_INFO_READ_REG, NULL, &reg))
 656             return false;
 657         out[i] = reg;
 658     }
 659     return true;
 660 }
 661
 662 static unsigned hash_fd(void *key)
 663 {
 664     int fd = pointer_to_intptr(key);
 665     struct stat stat;
 666     fstat(fd, &stat);
 667
 668     return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
 669 }
 670
 671 static int compare_fd(void *key1, void *key2)
 672 {
 673     int fd1 = pointer_to_intptr(key1);
 674     int fd2 = pointer_to_intptr(key2);
 675     struct stat stat1, stat2;
 676     fstat(fd1, &stat1);
 677     fstat(fd2, &stat2);
 678
 679     return stat1.st_dev != stat2.st_dev ||
 680            stat1.st_ino != stat2.st_ino ||
 681            stat1.st_rdev != stat2.st_rdev;
 682 }
 683
 684 DEBUG_GET_ONCE_BOOL_OPTION(thread, "RADEON_THREAD", TRUE)
 685
 686 static bool radeon_winsys_unref(struct radeon_winsys *ws)
 687 {
 688     struct radeon_drm_winsys *rws = (struct radeon_drm_winsys*)ws;
 689     bool destroy;
 690
 691     /* When the reference counter drops to zero, remove the fd from the table.
 692      * This must happen while the mutex is locked, so that
 693      * radeon_drm_winsys_create in another thread doesn't get the winsys
 694      * from the table when the counter drops to 0. */
 695     pipe_mutex_lock(fd_tab_mutex);
 696
 697     destroy = pipe_reference(&rws->reference, NULL);
 698     if (destroy && fd_tab)
 699         util_hash_table_remove(fd_tab, intptr_to_pointer(rws->fd));
 700
 701     pipe_mutex_unlock(fd_tab_mutex);
 702     return destroy;
 703 }
 704
 705 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 706
 707 static unsigned handle_hash(void *key)
 708 {
 709     return PTR_TO_UINT(key);
 710 }
 711
 712 static int handle_compare(void *key1, void *key2)
 713 {
 714     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 715 }
 716
 717 PUBLIC struct radeon_winsys *
 718 radeon_drm_winsys_create(int fd, radeon_screen_create_t screen_create)
 719 {
 720     struct radeon_drm_winsys *ws;
 721
 722     pipe_mutex_lock(fd_tab_mutex);
 723     if (!fd_tab) {
 724         fd_tab = util_hash_table_create(hash_fd, compare_fd);
 725     }
 726
 727     ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
 728     if (ws) {
 729         pipe_reference(NULL, &ws->reference);
 730         pipe_mutex_unlock(fd_tab_mutex);
 731         return &ws->base;
 732     }
 733
 734     ws = CALLOC_STRUCT(radeon_drm_winsys);
 735     if (!ws) {
 736         pipe_mutex_unlock(fd_tab_mutex);
 737         return NULL;
 738     }
 739
 740     ws->fd = dup(fd);
 741
 742     if (!do_winsys_init(ws))
 743         goto fail1;
 744
 745     pb_cache_init(&ws->bo_cache, 500000, 2.0f, 0,
 746                   MIN2(ws->info.vram_size, ws->info.gart_size),
 747                   radeon_bo_destroy,
 748                   radeon_bo_can_reclaim);
 749
 750     if (ws->gen >= DRV_R600) {
 751         ws->surf_man = radeon_surface_manager_new(ws->fd);
 752         if (!ws->surf_man)
 753             goto fail;
 754     }
 755
 756     /* init reference */
 757     pipe_reference_init(&ws->reference, 1);
 758
 759     /* Set functions. */
 760     ws->base.unref = radeon_winsys_unref;
 761     ws->base.destroy = radeon_winsys_destroy;
 762     ws->base.query_info = radeon_query_info;
 763     ws->base.cs_request_feature = radeon_cs_request_feature;
 764     ws->base.query_value = radeon_query_value;
 765     ws->base.read_registers = radeon_read_registers;
 766
 767     radeon_drm_bo_init_functions(ws);
 768     radeon_drm_cs_init_functions(ws);
 769     radeon_surface_init_functions(ws);
 770
 771     pipe_mutex_init(ws->hyperz_owner_mutex);
 772     pipe_mutex_init(ws->cmask_owner_mutex);
 773
 774     ws->bo_names = util_hash_table_create(handle_hash, handle_compare);
 775     ws->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 776     ws->bo_vas = util_hash_table_create(handle_hash, handle_compare);
 777     pipe_mutex_init(ws->bo_handles_mutex);
 778     pipe_mutex_init(ws->bo_va_mutex);
 779     ws->va_offset = ws->va_start;
 780     list_inithead(&ws->va_holes);
 781
 782     /* TTM aligns the BO size to the CPU page size */
 783     ws->info.gart_page_size = sysconf(_SC_PAGESIZE);
 784
 785     if (ws->num_cpus > 1 && debug_get_option_thread())
 786         util_queue_init(&ws->cs_queue, "radeon_cs", 8, 1);
 787
 788     /* Create the screen at the end. The winsys must be initialized
 789      * completely.
 790      *
 791      * Alternatively, we could create the screen based on "ws->gen"
 792      * and link all drivers into one binary blob. */
 793     ws->base.screen = screen_create(&ws->base);
 794     if (!ws->base.screen) {
 795         radeon_winsys_destroy(&ws->base);
 796         pipe_mutex_unlock(fd_tab_mutex);
 797         return NULL;
 798     }
 799
 800     util_hash_table_set(fd_tab, intptr_to_pointer(ws->fd), ws);
 801
 802     /* We must unlock the mutex once the winsys is fully initialized, so that
 803      * other threads attempting to create the winsys from the same fd will
 804      * get a fully initialized winsys and not just half-way initialized. */
 805     pipe_mutex_unlock(fd_tab_mutex);
 806
 807     return &ws->base;
 808
 809 fail:
 810     pb_cache_deinit(&ws->bo_cache);
 811 fail1:
 812     pipe_mutex_unlock(fd_tab_mutex);
 813     if (ws->surf_man)
 814         radeon_surface_manager_free(ws->surf_man);
 815     if (ws->fd >= 0)
 816         close(ws->fd);
 817
 818     FREE(ws);
 819     return NULL;
 820 }