src/gallium/winsys/radeon/drm/radeon_drm_winsys.h

   1 /*
   2  * Copyright © 2009 Corbin Simpson
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26 /*
  27  * Authors:
  28  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  29  */
  30 #ifndef RADEON_DRM_WINSYS_H
  31 #define RADEON_DRM_WINSYS_H
  32
  33 #include "radeon_winsys.h"
  34 #include "os/os_thread.h"
  35
  36 struct radeon_drm_cs;
  37
  38 enum radeon_generation {
  39     DRV_R300,
  40     DRV_R600,
  41     DRV_SI
  42 };
  43
  44 #define RADEON_NUM_CACHE_MANAGERS 8
  45
  46 struct radeon_drm_winsys {
  47     struct radeon_winsys base;
  48     struct pipe_reference reference;
  49
  50     int fd; /* DRM file descriptor */
  51     int num_cs; /* The number of command streams created. */
  52     uint64_t allocated_vram;
  53     uint64_t allocated_gtt;
  54     uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
  55     uint64_t num_cs_flushes;
  56
  57     enum radeon_generation gen;
  58     struct radeon_info info;
  59     uint32_t va_start;
  60     uint32_t accel_working2;
  61
  62     struct pb_manager *kman;
  63     struct pb_manager *cman_vram[RADEON_NUM_CACHE_MANAGERS];
  64     struct pb_manager *cman_gtt[RADEON_NUM_CACHE_MANAGERS];
  65     struct radeon_surface_manager *surf_man;
  66
  67     uint32_t num_cpus;      /* Number of CPUs. */
  68
  69     struct radeon_drm_cs *hyperz_owner;
  70     pipe_mutex hyperz_owner_mutex;
  71     struct radeon_drm_cs *cmask_owner;
  72     pipe_mutex cmask_owner_mutex;
  73
  74     /* rings submission thread */
  75     pipe_mutex cs_stack_lock;
  76     pipe_semaphore cs_queued;
  77     pipe_thread thread;
  78     int kill_thread;
  79     int ncs;
  80     struct radeon_drm_cs *cs_stack[RING_LAST];
  81 };
  82
  83 static INLINE struct radeon_drm_winsys *
  84 radeon_drm_winsys(struct radeon_winsys *base)
  85 {
  86     return (struct radeon_drm_winsys*)base;
  87 }
  88
  89 void radeon_drm_ws_queue_cs(struct radeon_drm_winsys *ws, struct radeon_drm_cs *cs);
  90
  91 #endif