virgl: fix checking fences
[mesa.git] / src / gallium / winsys / virgl / drm / virgl_drm_winsys.c
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <errno.h>
25 #include <fcntl.h>
26 #include <stdio.h>
27 #include <sys/ioctl.h>
28 #include <sys/stat.h>
29
30 #include "os/os_mman.h"
31 #include "os/os_time.h"
32 #include "util/u_memory.h"
33 #include "util/u_format.h"
34 #include "util/u_hash_table.h"
35 #include "util/u_inlines.h"
36 #include "state_tracker/drm_driver.h"
37 #include "virgl/virgl_screen.h"
38 #include "virgl/virgl_public.h"
39
40 #include <xf86drm.h>
41 #include "virtgpu_drm.h"
42
43 #include "virgl_drm_winsys.h"
44 #include "virgl_drm_public.h"
45
46 static inline boolean can_cache_resource(struct virgl_hw_res *res)
47 {
48 return res->cacheable == TRUE;
49 }
50
51 static void virgl_hw_res_destroy(struct virgl_drm_winsys *qdws,
52 struct virgl_hw_res *res)
53 {
54 struct drm_gem_close args;
55
56 if (res->flinked) {
57 pipe_mutex_lock(qdws->bo_handles_mutex);
58 util_hash_table_remove(qdws->bo_names,
59 (void *)(uintptr_t)res->flink);
60 pipe_mutex_unlock(qdws->bo_handles_mutex);
61 }
62
63 if (res->bo_handle) {
64 pipe_mutex_lock(qdws->bo_handles_mutex);
65 util_hash_table_remove(qdws->bo_handles,
66 (void *)(uintptr_t)res->bo_handle);
67 pipe_mutex_unlock(qdws->bo_handles_mutex);
68 }
69
70 if (res->ptr)
71 os_munmap(res->ptr, res->size);
72
73 memset(&args, 0, sizeof(args));
74 args.handle = res->bo_handle;
75 drmIoctl(qdws->fd, DRM_IOCTL_GEM_CLOSE, &args);
76 FREE(res);
77 }
78
79 static boolean virgl_drm_resource_is_busy(struct virgl_drm_winsys *qdws,
80 struct virgl_hw_res *res)
81 {
82 struct drm_virtgpu_3d_wait waitcmd;
83 int ret;
84
85 memset(&waitcmd, 0, sizeof(waitcmd));
86 waitcmd.handle = res->bo_handle;
87 waitcmd.flags = VIRTGPU_WAIT_NOWAIT;
88
89 ret = drmIoctl(qdws->fd, DRM_IOCTL_VIRTGPU_WAIT, &waitcmd);
90 if (ret && errno == EBUSY)
91 return TRUE;
92 return FALSE;
93 }
94
95 static void
96 virgl_cache_flush(struct virgl_drm_winsys *qdws)
97 {
98 struct list_head *curr, *next;
99 struct virgl_hw_res *res;
100
101 pipe_mutex_lock(qdws->mutex);
102 curr = qdws->delayed.next;
103 next = curr->next;
104
105 while (curr != &qdws->delayed) {
106 res = LIST_ENTRY(struct virgl_hw_res, curr, head);
107 LIST_DEL(&res->head);
108 virgl_hw_res_destroy(qdws, res);
109 curr = next;
110 next = curr->next;
111 }
112 pipe_mutex_unlock(qdws->mutex);
113 }
114 static void
115 virgl_drm_winsys_destroy(struct virgl_winsys *qws)
116 {
117 struct virgl_drm_winsys *qdws = virgl_drm_winsys(qws);
118
119 virgl_cache_flush(qdws);
120
121 util_hash_table_destroy(qdws->bo_handles);
122 util_hash_table_destroy(qdws->bo_names);
123 pipe_mutex_destroy(qdws->bo_handles_mutex);
124 pipe_mutex_destroy(qdws->mutex);
125
126 FREE(qdws);
127 }
128
129 static void
130 virgl_cache_list_check_free(struct virgl_drm_winsys *qdws)
131 {
132 struct list_head *curr, *next;
133 struct virgl_hw_res *res;
134 int64_t now;
135
136 now = os_time_get();
137 curr = qdws->delayed.next;
138 next = curr->next;
139 while (curr != &qdws->delayed) {
140 res = LIST_ENTRY(struct virgl_hw_res, curr, head);
141 if (!os_time_timeout(res->start, res->end, now))
142 break;
143
144 LIST_DEL(&res->head);
145 virgl_hw_res_destroy(qdws, res);
146 curr = next;
147 next = curr->next;
148 }
149 }
150
151 static void virgl_drm_resource_reference(struct virgl_drm_winsys *qdws,
152 struct virgl_hw_res **dres,
153 struct virgl_hw_res *sres)
154 {
155 struct virgl_hw_res *old = *dres;
156 if (pipe_reference(&(*dres)->reference, &sres->reference)) {
157
158 if (!can_cache_resource(old)) {
159 virgl_hw_res_destroy(qdws, old);
160 } else {
161 pipe_mutex_lock(qdws->mutex);
162 virgl_cache_list_check_free(qdws);
163
164 old->start = os_time_get();
165 old->end = old->start + qdws->usecs;
166 LIST_ADDTAIL(&old->head, &qdws->delayed);
167 qdws->num_delayed++;
168 pipe_mutex_unlock(qdws->mutex);
169 }
170 }
171 *dres = sres;
172 }
173
174 static struct virgl_hw_res *
175 virgl_drm_winsys_resource_create(struct virgl_winsys *qws,
176 enum pipe_texture_target target,
177 uint32_t format,
178 uint32_t bind,
179 uint32_t width,
180 uint32_t height,
181 uint32_t depth,
182 uint32_t array_size,
183 uint32_t last_level,
184 uint32_t nr_samples,
185 uint32_t size)
186 {
187 struct virgl_drm_winsys *qdws = virgl_drm_winsys(qws);
188 struct drm_virtgpu_resource_create createcmd;
189 int ret;
190 struct virgl_hw_res *res;
191 uint32_t stride = width * util_format_get_blocksize(format);
192
193 res = CALLOC_STRUCT(virgl_hw_res);
194 if (!res)
195 return NULL;
196
197 memset(&createcmd, 0, sizeof(createcmd));
198 createcmd.target = target;
199 createcmd.format = format;
200 createcmd.bind = bind;
201 createcmd.width = width;
202 createcmd.height = height;
203 createcmd.depth = depth;
204 createcmd.array_size = array_size;
205 createcmd.last_level = last_level;
206 createcmd.nr_samples = nr_samples;
207 createcmd.stride = stride;
208 createcmd.size = size;
209
210 ret = drmIoctl(qdws->fd, DRM_IOCTL_VIRTGPU_RESOURCE_CREATE, &createcmd);
211 if (ret != 0) {
212 FREE(res);
213 return NULL;
214 }
215
216 res->bind = bind;
217 res->format = format;
218
219 res->res_handle = createcmd.res_handle;
220 res->bo_handle = createcmd.bo_handle;
221 res->size = size;
222 res->stride = stride;
223 pipe_reference_init(&res->reference, 1);
224 res->num_cs_references = 0;
225 return res;
226 }
227
228 static inline int virgl_is_res_compat(struct virgl_drm_winsys *qdws,
229 struct virgl_hw_res *res,
230 uint32_t size, uint32_t bind,
231 uint32_t format)
232 {
233 if (res->bind != bind)
234 return 0;
235 if (res->format != format)
236 return 0;
237 if (res->size < size)
238 return 0;
239 if (res->size > size * 2)
240 return 0;
241
242 if (virgl_drm_resource_is_busy(qdws, res)) {
243 return -1;
244 }
245
246 return 1;
247 }
248
249 static int
250 virgl_bo_transfer_put(struct virgl_winsys *vws,
251 struct virgl_hw_res *res,
252 const struct pipe_box *box,
253 uint32_t stride, uint32_t layer_stride,
254 uint32_t buf_offset, uint32_t level)
255 {
256 struct virgl_drm_winsys *vdws = virgl_drm_winsys(vws);
257 struct drm_virtgpu_3d_transfer_to_host tohostcmd;
258
259 memset(&tohostcmd, 0, sizeof(tohostcmd));
260 tohostcmd.bo_handle = res->bo_handle;
261 tohostcmd.box = *(struct drm_virtgpu_3d_box *)box;
262 tohostcmd.offset = buf_offset;
263 tohostcmd.level = level;
264 // tohostcmd.stride = stride;
265 // tohostcmd.layer_stride = stride;
266 return drmIoctl(vdws->fd, DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST, &tohostcmd);
267 }
268
269 static int
270 virgl_bo_transfer_get(struct virgl_winsys *vws,
271 struct virgl_hw_res *res,
272 const struct pipe_box *box,
273 uint32_t stride, uint32_t layer_stride,
274 uint32_t buf_offset, uint32_t level)
275 {
276 struct virgl_drm_winsys *vdws = virgl_drm_winsys(vws);
277 struct drm_virtgpu_3d_transfer_from_host fromhostcmd;
278
279 memset(&fromhostcmd, 0, sizeof(fromhostcmd));
280 fromhostcmd.bo_handle = res->bo_handle;
281 fromhostcmd.level = level;
282 fromhostcmd.offset = buf_offset;
283 // fromhostcmd.stride = stride;
284 // fromhostcmd.layer_stride = layer_stride;
285 fromhostcmd.box = *(struct drm_virtgpu_3d_box *)box;
286 return drmIoctl(vdws->fd, DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST, &fromhostcmd);
287 }
288
289 static struct virgl_hw_res *
290 virgl_drm_winsys_resource_cache_create(struct virgl_winsys *qws,
291 enum pipe_texture_target target,
292 uint32_t format,
293 uint32_t bind,
294 uint32_t width,
295 uint32_t height,
296 uint32_t depth,
297 uint32_t array_size,
298 uint32_t last_level,
299 uint32_t nr_samples,
300 uint32_t size)
301 {
302 struct virgl_drm_winsys *qdws = virgl_drm_winsys(qws);
303 struct virgl_hw_res *res, *curr_res;
304 struct list_head *curr, *next;
305 int64_t now;
306 int ret;
307
308 /* only store binds for vertex/index/const buffers */
309 if (bind != VIRGL_BIND_CONSTANT_BUFFER && bind != VIRGL_BIND_INDEX_BUFFER &&
310 bind != VIRGL_BIND_VERTEX_BUFFER && bind != VIRGL_BIND_CUSTOM)
311 goto alloc;
312
313 pipe_mutex_lock(qdws->mutex);
314
315 res = NULL;
316 curr = qdws->delayed.next;
317 next = curr->next;
318
319 now = os_time_get();
320 while (curr != &qdws->delayed) {
321 curr_res = LIST_ENTRY(struct virgl_hw_res, curr, head);
322
323 if (!res && ((ret = virgl_is_res_compat(qdws, curr_res, size, bind, format)) > 0))
324 res = curr_res;
325 else if (os_time_timeout(curr_res->start, curr_res->end, now)) {
326 LIST_DEL(&curr_res->head);
327 virgl_hw_res_destroy(qdws, curr_res);
328 } else
329 break;
330
331 if (ret == -1)
332 break;
333
334 curr = next;
335 next = curr->next;
336 }
337
338 if (!res && ret != -1) {
339 while (curr != &qdws->delayed) {
340 curr_res = LIST_ENTRY(struct virgl_hw_res, curr, head);
341 ret = virgl_is_res_compat(qdws, curr_res, size, bind, format);
342 if (ret > 0) {
343 res = curr_res;
344 break;
345 }
346 if (ret == -1)
347 break;
348 curr = next;
349 next = curr->next;
350 }
351 }
352
353 if (res) {
354 LIST_DEL(&res->head);
355 --qdws->num_delayed;
356 pipe_mutex_unlock(qdws->mutex);
357 pipe_reference_init(&res->reference, 1);
358 return res;
359 }
360
361 pipe_mutex_unlock(qdws->mutex);
362
363 alloc:
364 res = virgl_drm_winsys_resource_create(qws, target, format, bind,
365 width, height, depth, array_size,
366 last_level, nr_samples, size);
367 if (bind == VIRGL_BIND_CONSTANT_BUFFER || bind == VIRGL_BIND_INDEX_BUFFER ||
368 bind == VIRGL_BIND_VERTEX_BUFFER)
369 res->cacheable = TRUE;
370 return res;
371 }
372
373 static struct virgl_hw_res *
374 virgl_drm_winsys_resource_create_handle(struct virgl_winsys *qws,
375 struct winsys_handle *whandle)
376 {
377 struct virgl_drm_winsys *qdws = virgl_drm_winsys(qws);
378 struct drm_gem_open open_arg = {};
379 struct drm_virtgpu_resource_info info_arg = {};
380 struct virgl_hw_res *res;
381 uint32_t handle = whandle->handle;
382
383 if (whandle->offset != 0) {
384 fprintf(stderr, "attempt to import unsupported winsys offset %u\n",
385 whandle->offset);
386 return NULL;
387 }
388
389 pipe_mutex_lock(qdws->bo_handles_mutex);
390
391 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
392 res = util_hash_table_get(qdws->bo_names, (void*)(uintptr_t)handle);
393 if (res) {
394 struct virgl_hw_res *r = NULL;
395 virgl_drm_resource_reference(qdws, &r, res);
396 goto done;
397 }
398 }
399
400 if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
401 int r;
402 r = drmPrimeFDToHandle(qdws->fd, whandle->handle, &handle);
403 if (r) {
404 res = NULL;
405 goto done;
406 }
407 }
408
409 res = util_hash_table_get(qdws->bo_handles, (void*)(uintptr_t)handle);
410 fprintf(stderr, "resource %p for handle %d, pfd=%d\n", res, handle, whandle->handle);
411 if (res) {
412 struct virgl_hw_res *r = NULL;
413 virgl_drm_resource_reference(qdws, &r, res);
414 goto done;
415 }
416
417 res = CALLOC_STRUCT(virgl_hw_res);
418 if (!res)
419 goto done;
420
421 if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
422 res->bo_handle = handle;
423 } else {
424 fprintf(stderr, "gem open handle %d\n", handle);
425 memset(&open_arg, 0, sizeof(open_arg));
426 open_arg.name = whandle->handle;
427 if (drmIoctl(qdws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
428 FREE(res);
429 res = NULL;
430 goto done;
431 }
432 res->bo_handle = open_arg.handle;
433 }
434 res->name = handle;
435
436 memset(&info_arg, 0, sizeof(info_arg));
437 info_arg.bo_handle = res->bo_handle;
438
439 if (drmIoctl(qdws->fd, DRM_IOCTL_VIRTGPU_RESOURCE_INFO, &info_arg)) {
440 /* close */
441 FREE(res);
442 res = NULL;
443 goto done;
444 }
445
446 res->res_handle = info_arg.res_handle;
447
448 res->size = info_arg.size;
449 res->stride = info_arg.stride;
450 pipe_reference_init(&res->reference, 1);
451 res->num_cs_references = 0;
452
453 util_hash_table_set(qdws->bo_handles, (void *)(uintptr_t)handle, res);
454
455 done:
456 pipe_mutex_unlock(qdws->bo_handles_mutex);
457 return res;
458 }
459
460 static boolean virgl_drm_winsys_resource_get_handle(struct virgl_winsys *qws,
461 struct virgl_hw_res *res,
462 uint32_t stride,
463 struct winsys_handle *whandle)
464 {
465 struct virgl_drm_winsys *qdws = virgl_drm_winsys(qws);
466 struct drm_gem_flink flink;
467
468 if (!res)
469 return FALSE;
470
471 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
472 if (!res->flinked) {
473 memset(&flink, 0, sizeof(flink));
474 flink.handle = res->bo_handle;
475
476 if (drmIoctl(qdws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
477 return FALSE;
478 }
479 res->flinked = TRUE;
480 res->flink = flink.name;
481
482 pipe_mutex_lock(qdws->bo_handles_mutex);
483 util_hash_table_set(qdws->bo_names, (void *)(uintptr_t)res->flink, res);
484 pipe_mutex_unlock(qdws->bo_handles_mutex);
485 }
486 whandle->handle = res->flink;
487 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
488 whandle->handle = res->bo_handle;
489 } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
490 if (drmPrimeHandleToFD(qdws->fd, res->bo_handle, DRM_CLOEXEC, (int*)&whandle->handle))
491 return FALSE;
492 }
493 whandle->stride = stride;
494 return TRUE;
495 }
496
497 static void virgl_drm_winsys_resource_unref(struct virgl_winsys *qws,
498 struct virgl_hw_res *hres)
499 {
500 struct virgl_drm_winsys *qdws = virgl_drm_winsys(qws);
501
502 virgl_drm_resource_reference(qdws, &hres, NULL);
503 }
504
505 static void *virgl_drm_resource_map(struct virgl_winsys *qws,
506 struct virgl_hw_res *res)
507 {
508 struct virgl_drm_winsys *qdws = virgl_drm_winsys(qws);
509 struct drm_virtgpu_map mmap_arg;
510 void *ptr;
511
512 if (res->ptr)
513 return res->ptr;
514
515 memset(&mmap_arg, 0, sizeof(mmap_arg));
516 mmap_arg.handle = res->bo_handle;
517 if (drmIoctl(qdws->fd, DRM_IOCTL_VIRTGPU_MAP, &mmap_arg))
518 return NULL;
519
520 ptr = os_mmap(0, res->size, PROT_READ|PROT_WRITE, MAP_SHARED,
521 qdws->fd, mmap_arg.offset);
522 if (ptr == MAP_FAILED)
523 return NULL;
524
525 res->ptr = ptr;
526 return ptr;
527
528 }
529
530 static void virgl_drm_resource_wait(struct virgl_winsys *qws,
531 struct virgl_hw_res *res)
532 {
533 struct virgl_drm_winsys *qdws = virgl_drm_winsys(qws);
534 struct drm_virtgpu_3d_wait waitcmd;
535 int ret;
536
537 memset(&waitcmd, 0, sizeof(waitcmd));
538 waitcmd.handle = res->bo_handle;
539 again:
540 ret = drmIoctl(qdws->fd, DRM_IOCTL_VIRTGPU_WAIT, &waitcmd);
541 if (ret == -EAGAIN)
542 goto again;
543 }
544
545 static struct virgl_cmd_buf *virgl_drm_cmd_buf_create(struct virgl_winsys *qws)
546 {
547 struct virgl_drm_cmd_buf *cbuf;
548
549 cbuf = CALLOC_STRUCT(virgl_drm_cmd_buf);
550 if (!cbuf)
551 return NULL;
552
553 cbuf->ws = qws;
554
555 cbuf->nres = 512;
556 cbuf->res_bo = CALLOC(cbuf->nres, sizeof(struct virgl_hw_buf*));
557 if (!cbuf->res_bo) {
558 FREE(cbuf);
559 return NULL;
560 }
561 cbuf->res_hlist = MALLOC(cbuf->nres * sizeof(uint32_t));
562 if (!cbuf->res_hlist) {
563 FREE(cbuf->res_bo);
564 FREE(cbuf);
565 return NULL;
566 }
567
568 cbuf->base.buf = cbuf->buf;
569 return &cbuf->base;
570 }
571
572 static void virgl_drm_cmd_buf_destroy(struct virgl_cmd_buf *_cbuf)
573 {
574 struct virgl_drm_cmd_buf *cbuf = virgl_drm_cmd_buf(_cbuf);
575
576 FREE(cbuf->res_hlist);
577 FREE(cbuf->res_bo);
578 FREE(cbuf);
579
580 }
581
582 static boolean virgl_drm_lookup_res(struct virgl_drm_cmd_buf *cbuf,
583 struct virgl_hw_res *res)
584 {
585 unsigned hash = res->res_handle & (sizeof(cbuf->is_handle_added)-1);
586 int i;
587
588 if (cbuf->is_handle_added[hash]) {
589 i = cbuf->reloc_indices_hashlist[hash];
590 if (cbuf->res_bo[i] == res)
591 return true;
592
593 for (i = 0; i < cbuf->cres; i++) {
594 if (cbuf->res_bo[i] == res) {
595 cbuf->reloc_indices_hashlist[hash] = i;
596 return true;
597 }
598 }
599 }
600 return false;
601 }
602
603 static void virgl_drm_add_res(struct virgl_drm_winsys *qdws,
604 struct virgl_drm_cmd_buf *cbuf,
605 struct virgl_hw_res *res)
606 {
607 unsigned hash = res->res_handle & (sizeof(cbuf->is_handle_added)-1);
608
609 if (cbuf->cres > cbuf->nres) {
610 fprintf(stderr,"failure to add relocation\n");
611 return;
612 }
613
614 cbuf->res_bo[cbuf->cres] = NULL;
615 virgl_drm_resource_reference(qdws, &cbuf->res_bo[cbuf->cres], res);
616 cbuf->res_hlist[cbuf->cres] = res->bo_handle;
617 cbuf->is_handle_added[hash] = TRUE;
618
619 cbuf->reloc_indices_hashlist[hash] = cbuf->cres;
620 p_atomic_inc(&res->num_cs_references);
621 cbuf->cres++;
622 }
623
624 static void virgl_drm_release_all_res(struct virgl_drm_winsys *qdws,
625 struct virgl_drm_cmd_buf *cbuf)
626 {
627 int i;
628
629 for (i = 0; i < cbuf->cres; i++) {
630 p_atomic_dec(&cbuf->res_bo[i]->num_cs_references);
631 virgl_drm_resource_reference(qdws, &cbuf->res_bo[i], NULL);
632 }
633 cbuf->cres = 0;
634 }
635
636 static void virgl_drm_emit_res(struct virgl_winsys *qws,
637 struct virgl_cmd_buf *_cbuf,
638 struct virgl_hw_res *res, boolean write_buf)
639 {
640 struct virgl_drm_winsys *qdws = virgl_drm_winsys(qws);
641 struct virgl_drm_cmd_buf *cbuf = virgl_drm_cmd_buf(_cbuf);
642 boolean already_in_list = virgl_drm_lookup_res(cbuf, res);
643
644 if (write_buf)
645 cbuf->base.buf[cbuf->base.cdw++] = res->res_handle;
646
647 if (!already_in_list)
648 virgl_drm_add_res(qdws, cbuf, res);
649 }
650
651 static boolean virgl_drm_res_is_ref(struct virgl_winsys *qws,
652 struct virgl_cmd_buf *_cbuf,
653 struct virgl_hw_res *res)
654 {
655 if (!res->num_cs_references)
656 return FALSE;
657
658 return TRUE;
659 }
660
661 static int virgl_drm_winsys_submit_cmd(struct virgl_winsys *qws,
662 struct virgl_cmd_buf *_cbuf)
663 {
664 struct virgl_drm_winsys *qdws = virgl_drm_winsys(qws);
665 struct virgl_drm_cmd_buf *cbuf = virgl_drm_cmd_buf(_cbuf);
666 struct drm_virtgpu_execbuffer eb;
667 int ret;
668
669 if (cbuf->base.cdw == 0)
670 return 0;
671
672 memset(&eb, 0, sizeof(struct drm_virtgpu_execbuffer));
673 eb.command = (unsigned long)(void*)cbuf->buf;
674 eb.size = cbuf->base.cdw * 4;
675 eb.num_bo_handles = cbuf->cres;
676 eb.bo_handles = (unsigned long)(void *)cbuf->res_hlist;
677
678 ret = drmIoctl(qdws->fd, DRM_IOCTL_VIRTGPU_EXECBUFFER, &eb);
679 if (ret == -1)
680 fprintf(stderr,"got error from kernel - expect bad rendering %d\n", errno);
681 cbuf->base.cdw = 0;
682
683 virgl_drm_release_all_res(qdws, cbuf);
684
685 memset(cbuf->is_handle_added, 0, sizeof(cbuf->is_handle_added));
686 return ret;
687 }
688
689 static int virgl_drm_get_caps(struct virgl_winsys *vws,
690 struct virgl_drm_caps *caps)
691 {
692 struct virgl_drm_winsys *vdws = virgl_drm_winsys(vws);
693 struct drm_virtgpu_get_caps args;
694
695 memset(&args, 0, sizeof(args));
696
697 args.cap_set_id = 1;
698 args.addr = (unsigned long)&caps->caps;
699 args.size = sizeof(union virgl_caps);
700 return drmIoctl(vdws->fd, DRM_IOCTL_VIRTGPU_GET_CAPS, &args);
701 }
702
703 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
704
705 static unsigned handle_hash(void *key)
706 {
707 return PTR_TO_UINT(key);
708 }
709
710 static int handle_compare(void *key1, void *key2)
711 {
712 return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
713 }
714
715 static struct pipe_fence_handle *
716 virgl_cs_create_fence(struct virgl_winsys *vws)
717 {
718 struct virgl_hw_res *res;
719
720 res = virgl_drm_winsys_resource_cache_create(vws,
721 PIPE_BUFFER,
722 PIPE_FORMAT_R8_UNORM,
723 VIRGL_BIND_CUSTOM,
724 8, 1, 1, 0, 0, 0, 8);
725
726 return (struct pipe_fence_handle *)res;
727 }
728
729 static bool virgl_fence_wait(struct virgl_winsys *vws,
730 struct pipe_fence_handle *fence,
731 uint64_t timeout)
732 {
733 struct virgl_drm_winsys *vdws = virgl_drm_winsys(vws);
734 struct virgl_hw_res *res = virgl_hw_res(fence);
735
736 if (timeout == 0)
737 return !virgl_drm_resource_is_busy(vdws, res);
738
739 if (timeout != PIPE_TIMEOUT_INFINITE) {
740 int64_t start_time = os_time_get();
741 timeout /= 1000;
742 while (virgl_drm_resource_is_busy(vdws, res)) {
743 if (os_time_get() - start_time >= timeout)
744 return FALSE;
745 os_time_sleep(10);
746 }
747 return TRUE;
748 }
749 virgl_drm_resource_wait(vws, res);
750 return TRUE;
751 }
752
753 static void virgl_fence_reference(struct virgl_winsys *vws,
754 struct pipe_fence_handle **dst,
755 struct pipe_fence_handle *src)
756 {
757 struct virgl_drm_winsys *vdws = virgl_drm_winsys(vws);
758 virgl_drm_resource_reference(vdws, (struct virgl_hw_res **)dst,
759 virgl_hw_res(src));
760 }
761
762
763 static struct virgl_winsys *
764 virgl_drm_winsys_create(int drmFD)
765 {
766 struct virgl_drm_winsys *qdws;
767
768 qdws = CALLOC_STRUCT(virgl_drm_winsys);
769 if (!qdws)
770 return NULL;
771
772 qdws->fd = drmFD;
773 qdws->num_delayed = 0;
774 qdws->usecs = 1000000;
775 LIST_INITHEAD(&qdws->delayed);
776 pipe_mutex_init(qdws->mutex);
777 pipe_mutex_init(qdws->bo_handles_mutex);
778 qdws->bo_handles = util_hash_table_create(handle_hash, handle_compare);
779 qdws->bo_names = util_hash_table_create(handle_hash, handle_compare);
780 qdws->base.destroy = virgl_drm_winsys_destroy;
781
782 qdws->base.transfer_put = virgl_bo_transfer_put;
783 qdws->base.transfer_get = virgl_bo_transfer_get;
784 qdws->base.resource_create = virgl_drm_winsys_resource_cache_create;
785 qdws->base.resource_unref = virgl_drm_winsys_resource_unref;
786 qdws->base.resource_create_from_handle = virgl_drm_winsys_resource_create_handle;
787 qdws->base.resource_get_handle = virgl_drm_winsys_resource_get_handle;
788 qdws->base.resource_map = virgl_drm_resource_map;
789 qdws->base.resource_wait = virgl_drm_resource_wait;
790 qdws->base.cmd_buf_create = virgl_drm_cmd_buf_create;
791 qdws->base.cmd_buf_destroy = virgl_drm_cmd_buf_destroy;
792 qdws->base.submit_cmd = virgl_drm_winsys_submit_cmd;
793 qdws->base.emit_res = virgl_drm_emit_res;
794 qdws->base.res_is_referenced = virgl_drm_res_is_ref;
795
796 qdws->base.cs_create_fence = virgl_cs_create_fence;
797 qdws->base.fence_wait = virgl_fence_wait;
798 qdws->base.fence_reference = virgl_fence_reference;
799
800 qdws->base.get_caps = virgl_drm_get_caps;
801 return &qdws->base;
802
803 }
804
805 static struct util_hash_table *fd_tab = NULL;
806 pipe_static_mutex(virgl_screen_mutex);
807
808 static void
809 virgl_drm_screen_destroy(struct pipe_screen *pscreen)
810 {
811 struct virgl_screen *screen = virgl_screen(pscreen);
812 boolean destroy;
813
814 pipe_mutex_lock(virgl_screen_mutex);
815 destroy = --screen->refcnt == 0;
816 if (destroy) {
817 int fd = virgl_drm_winsys(screen->vws)->fd;
818 util_hash_table_remove(fd_tab, intptr_to_pointer(fd));
819 }
820 pipe_mutex_unlock(virgl_screen_mutex);
821
822 if (destroy) {
823 pscreen->destroy = screen->winsys_priv;
824 pscreen->destroy(pscreen);
825 }
826 }
827
828 static unsigned hash_fd(void *key)
829 {
830 int fd = pointer_to_intptr(key);
831 struct stat stat;
832 fstat(fd, &stat);
833
834 return stat.st_dev ^ stat.st_ino ^ stat.st_rdev;
835 }
836
837 static int compare_fd(void *key1, void *key2)
838 {
839 int fd1 = pointer_to_intptr(key1);
840 int fd2 = pointer_to_intptr(key2);
841 struct stat stat1, stat2;
842 fstat(fd1, &stat1);
843 fstat(fd2, &stat2);
844
845 return stat1.st_dev != stat2.st_dev ||
846 stat1.st_ino != stat2.st_ino ||
847 stat1.st_rdev != stat2.st_rdev;
848 }
849
850 struct pipe_screen *
851 virgl_drm_screen_create(int fd)
852 {
853 struct pipe_screen *pscreen = NULL;
854
855 pipe_mutex_lock(virgl_screen_mutex);
856 if (!fd_tab) {
857 fd_tab = util_hash_table_create(hash_fd, compare_fd);
858 if (!fd_tab)
859 goto unlock;
860 }
861
862 pscreen = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
863 if (pscreen) {
864 virgl_screen(pscreen)->refcnt++;
865 } else {
866 struct virgl_winsys *vws;
867 int dup_fd = dup(fd);
868
869 vws = virgl_drm_winsys_create(dup_fd);
870
871 pscreen = virgl_create_screen(vws);
872 if (pscreen) {
873 util_hash_table_set(fd_tab, intptr_to_pointer(dup_fd), pscreen);
874
875 /* Bit of a hack, to avoid circular linkage dependency,
876 * ie. pipe driver having to call in to winsys, we
877 * override the pipe drivers screen->destroy():
878 */
879 virgl_screen(pscreen)->winsys_priv = pscreen->destroy;
880 pscreen->destroy = virgl_drm_screen_destroy;
881 }
882 }
883
884 unlock:
885 pipe_mutex_unlock(virgl_screen_mutex);
886 return pscreen;
887 }