src/intel/blorp/blorp.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <errno.h>
  25
  26 #include "program/prog_instruction.h"
  27
  28 #include "blorp_priv.h"
  29 #include "brw_compiler.h"
  30 #include "brw_nir.h"
  31
  32 void
  33 blorp_init(struct blorp_context *blorp, void *driver_ctx,
  34            struct isl_device *isl_dev)
  35 {
  36    blorp->driver_ctx = driver_ctx;
  37    blorp->isl_dev = isl_dev;
  38 }
  39
  40 void
  41 blorp_finish(struct blorp_context *blorp)
  42 {
  43    blorp->driver_ctx = NULL;
  44 }
  45
  46 void
  47 blorp_batch_init(struct blorp_context *blorp,
  48                  struct blorp_batch *batch, void *driver_batch)
  49 {
  50    batch->blorp = blorp;
  51    batch->driver_batch = driver_batch;
  52 }
  53
  54 void
  55 blorp_batch_finish(struct blorp_batch *batch)
  56 {
  57    batch->blorp = NULL;
  58 }
  59
  60 void
  61 brw_blorp_surface_info_init(struct blorp_context *blorp,
  62                             struct brw_blorp_surface_info *info,
  63                             const struct blorp_surf *surf,
  64                             unsigned int level, unsigned int layer,
  65                             enum isl_format format, bool is_render_target)
  66 {
  67    if (format == ISL_FORMAT_UNSUPPORTED)
  68       format = surf->surf->format;
  69
  70    if (format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
  71       /* Unfortunately, ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as
  72        * a render target, which would prevent us from blitting to 24-bit
  73        * depth.  The miptree consists of 32 bits per pixel, arranged as 24-bit
  74        * depth values interleaved with 8 "don't care" bits.  Since depth
  75        * values don't require any blending, it doesn't matter how we interpret
  76        * the bit pattern as long as we copy the right amount of data, so just
  77        * map it as 8-bit BGRA.
  78        */
  79       format = ISL_FORMAT_B8G8R8A8_UNORM;
  80    } else if (surf->surf->usage & ISL_SURF_USAGE_STENCIL_BIT) {
  81       assert(surf->surf->format == ISL_FORMAT_R8_UINT);
  82       /* Prior to Broadwell, we can't render to R8_UINT */
  83       if (blorp->isl_dev->info->gen < 8)
  84          format = ISL_FORMAT_R8_UNORM;
  85    }
  86
  87    info->surf = *surf->surf;
  88    info->addr = surf->addr;
  89
  90    info->aux_usage = surf->aux_usage;
  91    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
  92       info->aux_surf = *surf->aux_surf;
  93       info->aux_addr = surf->aux_addr;
  94    }
  95
  96    info->clear_color = surf->clear_color;
  97
  98    info->view = (struct isl_view) {
  99       .usage = is_render_target ? ISL_SURF_USAGE_RENDER_TARGET_BIT :
 100                                   ISL_SURF_USAGE_TEXTURE_BIT,
 101       .format = format,
 102       .base_level = level,
 103       .levels = 1,
 104       .swizzle = ISL_SWIZZLE_IDENTITY,
 105    };
 106
 107    info->view.array_len = MAX2(info->surf.logical_level0_px.depth,
 108                                info->surf.logical_level0_px.array_len);
 109
 110    if (!is_render_target &&
 111        (info->surf.dim == ISL_SURF_DIM_3D ||
 112         info->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)) {
 113       /* 3-D textures don't support base_array layer and neither do 2-D
 114        * multisampled textures on IVB so we need to pass it through the
 115        * sampler in those cases.  These are also two cases where we are
 116        * guaranteed that we won't be doing any funny surface hacks.
 117        */
 118       info->view.base_array_layer = 0;
 119       info->z_offset = layer;
 120    } else {
 121       info->view.base_array_layer = layer;
 122
 123       assert(info->view.array_len >= info->view.base_array_layer);
 124       info->view.array_len -= info->view.base_array_layer;
 125       info->z_offset = 0;
 126    }
 127
 128    /* Sandy Bridge has a limit of a maximum of 512 layers for layered
 129     * rendering.
 130     */
 131    if (is_render_target && blorp->isl_dev->info->gen == 6)
 132       info->view.array_len = MIN2(info->view.array_len, 512);
 133 }
 134
 135
 136 void
 137 blorp_params_init(struct blorp_params *params)
 138 {
 139    memset(params, 0, sizeof(*params));
 140    params->num_draw_buffers = 1;
 141    params->num_layers = 1;
 142 }
 143
 144 void
 145 brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key)
 146 {
 147    memset(wm_key, 0, sizeof(*wm_key));
 148    wm_key->nr_color_regions = 1;
 149    for (int i = 0; i < MAX_SAMPLERS; i++)
 150       wm_key->tex.swizzles[i] = SWIZZLE_XYZW;
 151 }
 152
 153 static int
 154 nir_uniform_type_size(const struct glsl_type *type)
 155 {
 156    /* Only very basic types are allowed */
 157    assert(glsl_type_is_vector_or_scalar(type));
 158    assert(glsl_get_bit_size(type) == 32);
 159
 160    return glsl_get_vector_elements(type) * 4;
 161 }
 162
 163 const unsigned *
 164 brw_blorp_compile_nir_shader(struct blorp_context *blorp, struct nir_shader *nir,
 165                              const struct brw_wm_prog_key *wm_key,
 166                              bool use_repclear,
 167                              struct brw_blorp_prog_data *prog_data,
 168                              unsigned *program_size)
 169 {
 170    const struct brw_compiler *compiler = blorp->compiler;
 171
 172    void *mem_ctx = ralloc_context(NULL);
 173
 174    /* Calling brw_preprocess_nir and friends is destructive and, if cloning is
 175     * enabled, may end up completely replacing the nir_shader.  Therefore, we
 176     * own it and might as well put it in our context for easy cleanup.
 177     */
 178    ralloc_steal(mem_ctx, nir);
 179    nir->options =
 180       compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions;
 181
 182    struct brw_wm_prog_data wm_prog_data;
 183    memset(&wm_prog_data, 0, sizeof(wm_prog_data));
 184
 185    wm_prog_data.base.nr_params = 0;
 186    wm_prog_data.base.param = NULL;
 187
 188    /* BLORP always just uses the first two binding table entries */
 189    wm_prog_data.binding_table.render_target_start = BLORP_RENDERBUFFER_BT_INDEX;
 190    wm_prog_data.base.binding_table.texture_start = BLORP_TEXTURE_BT_INDEX;
 191
 192    nir = brw_preprocess_nir(compiler, nir);
 193    nir_remove_dead_variables(nir, nir_var_shader_in);
 194    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 195
 196    /* Uniforms are required to be lowered before going into compile_fs.  For
 197     * BLORP, we'll assume that whoever builds the shader sets the location
 198     * they want so we just need to lower them and figure out how many we have
 199     * in total.
 200     */
 201    nir->num_uniforms = 0;
 202    nir_foreach_variable(var, &nir->uniforms) {
 203       var->data.driver_location = var->data.location;
 204       unsigned end = var->data.location + nir_uniform_type_size(var->type);
 205       nir->num_uniforms = MAX2(nir->num_uniforms, end);
 206    }
 207    nir_lower_io(nir, nir_var_uniform, nir_uniform_type_size, 0);
 208
 209    const unsigned *program =
 210       brw_compile_fs(compiler, blorp->driver_ctx, mem_ctx,
 211                      wm_key, &wm_prog_data, nir,
 212                      NULL, -1, -1, false, use_repclear, program_size, NULL);
 213
 214    /* Copy the relavent bits of wm_prog_data over into the blorp prog data */
 215    prog_data->dispatch_8 = wm_prog_data.dispatch_8;
 216    prog_data->dispatch_16 = wm_prog_data.dispatch_16;
 217    prog_data->first_curbe_grf_0 = wm_prog_data.base.dispatch_grf_start_reg;
 218    prog_data->first_curbe_grf_2 = wm_prog_data.dispatch_grf_start_reg_2;
 219    prog_data->ksp_offset_2 = wm_prog_data.prog_offset_2;
 220    prog_data->persample_msaa_dispatch = wm_prog_data.persample_dispatch;
 221    prog_data->flat_inputs = wm_prog_data.flat_inputs;
 222    prog_data->num_varying_inputs = wm_prog_data.num_varying_inputs;
 223    prog_data->inputs_read = nir->info.inputs_read;
 224
 225    assert(wm_prog_data.base.nr_params == 0);
 226
 227    return program;
 228 }
 229
 230 void
 231 blorp_gen6_hiz_op(struct blorp_batch *batch,
 232                   struct blorp_surf *surf, unsigned level, unsigned layer,
 233                   enum blorp_hiz_op op)
 234 {
 235    struct blorp_params params;
 236    blorp_params_init(&params);
 237
 238    params.hiz_op = op;
 239
 240    brw_blorp_surface_info_init(batch->blorp, &params.depth, surf, level, layer,
 241                                surf->surf->format, true);
 242
 243    /* Align the rectangle primitive to 8x4 pixels.
 244     *
 245     * During fast depth clears, the emitted rectangle primitive  must be
 246     * aligned to 8x4 pixels.  From the Ivybridge PRM, Vol 2 Part 1 Section
 247     * 11.5.3.1 Depth Buffer Clear (and the matching section in the Sandybridge
 248     * PRM):
 249     *     If Number of Multisamples is NUMSAMPLES_1, the rectangle must be
 250     *     aligned to an 8x4 pixel block relative to the upper left corner
 251     *     of the depth buffer [...]
 252     *
 253     * For hiz resolves, the rectangle must also be 8x4 aligned. Item
 254     * WaHizAmbiguate8x4Aligned from the Haswell workarounds page and the
 255     * Ivybridge simulator require the alignment.
 256     *
 257     * To be safe, let's just align the rect for all hiz operations and all
 258     * hardware generations.
 259     *
 260     * However, for some miptree slices of a Z24 texture, emitting an 8x4
 261     * aligned rectangle that covers the slice may clobber adjacent slices if
 262     * we strictly adhered to the texture alignments specified in the PRM.  The
 263     * Ivybridge PRM, Section "Alignment Unit Size", states that
 264     * SURFACE_STATE.Surface_Horizontal_Alignment should be 4 for Z24 surfaces,
 265     * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
 266     * prevents the clobbering.
 267     */
 268    params.x1 = minify(params.depth.surf.logical_level0_px.width,
 269                       params.depth.view.base_level);
 270    params.y1 = minify(params.depth.surf.logical_level0_px.height,
 271                       params.depth.view.base_level);
 272    params.x1 = ALIGN(params.x1, 8);
 273    params.y1 = ALIGN(params.y1, 4);
 274
 275    if (params.depth.view.base_level == 0) {
 276       /* TODO: What about MSAA? */
 277       params.depth.surf.logical_level0_px.width = params.x1;
 278       params.depth.surf.logical_level0_px.height = params.y1;
 279    }
 280
 281    params.dst.surf.samples = params.depth.surf.samples;
 282    params.dst.surf.logical_level0_px = params.depth.surf.logical_level0_px;
 283    params.depth_format = isl_format_get_depth_format(surf->surf->format, false);
 284
 285    batch->blorp->exec(batch, &params);
 286 }