2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "blorp_nir_builder.h"
25 #include "compiler/nir/nir_format_convert.h"
27 #include "blorp_priv.h"
29 #include "util/format_rgb9e5.h"
30 /* header-only include needed for _mesa_unorm_to_float and friends. */
31 #include "mesa/main/format_utils.h"
33 #define FILE_DEBUG_FLAG DEBUG_BLORP
35 static const bool split_blorp_blit_debug
= false;
38 * Enum to specify the order of arguments in a sampler message
40 enum sampler_message_arg
42 SAMPLER_MESSAGE_ARG_U_FLOAT
,
43 SAMPLER_MESSAGE_ARG_V_FLOAT
,
44 SAMPLER_MESSAGE_ARG_U_INT
,
45 SAMPLER_MESSAGE_ARG_V_INT
,
46 SAMPLER_MESSAGE_ARG_R_INT
,
47 SAMPLER_MESSAGE_ARG_SI_INT
,
48 SAMPLER_MESSAGE_ARG_MCS_INT
,
49 SAMPLER_MESSAGE_ARG_ZERO_INT
,
52 struct brw_blorp_blit_vars
{
53 /* Input values from brw_blorp_wm_inputs */
54 nir_variable
*v_discard_rect
;
55 nir_variable
*v_rect_grid
;
56 nir_variable
*v_coord_transform
;
57 nir_variable
*v_src_z
;
58 nir_variable
*v_src_offset
;
59 nir_variable
*v_dst_offset
;
60 nir_variable
*v_src_inv_size
;
63 nir_variable
*frag_coord
;
66 nir_variable
*color_out
;
70 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
71 const struct brw_blorp_blit_prog_key
*key
)
73 /* Blended and scaled blits never use pixel discard. */
74 assert(!key
->use_kill
|| !(key
->blend
&& key
->blit_scaled
));
76 #define LOAD_INPUT(name, type)\
77 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
79 LOAD_INPUT(discard_rect
, glsl_vec4_type())
80 LOAD_INPUT(rect_grid
, glsl_vec4_type())
81 LOAD_INPUT(coord_transform
, glsl_vec4_type())
82 LOAD_INPUT(src_z
, glsl_uint_type())
83 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
84 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
85 LOAD_INPUT(src_inv_size
, glsl_vector_type(GLSL_TYPE_FLOAT
, 2))
89 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
90 glsl_vec4_type(), "gl_FragCoord");
91 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
92 v
->frag_coord
->data
.origin_upper_left
= true;
94 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
95 glsl_vec4_type(), "gl_FragColor");
96 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
100 blorp_blit_get_frag_coords(nir_builder
*b
,
101 const struct brw_blorp_blit_prog_key
*key
,
102 struct brw_blorp_blit_vars
*v
)
104 nir_ssa_def
*coord
= nir_f2i32(b
, nir_load_var(b
, v
->frag_coord
));
106 /* Account for destination surface intratile offset
108 * Transformation parameters giving translation from destination to source
109 * coordinates don't take into account possible intra-tile destination
110 * offset. Therefore it has to be first subtracted from the incoming
111 * coordinates. Vertices are set up based on coordinates containing the
114 if (key
->need_dst_offset
)
115 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
117 if (key
->persample_msaa_dispatch
) {
118 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
119 nir_load_sample_id(b
));
121 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
126 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
130 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
131 struct brw_blorp_blit_vars
*v
)
133 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
135 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
136 nir_channel(b
, coord_transform
, 3));
137 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
138 nir_channel(b
, coord_transform
, 2));
140 return nir_fadd(b
, nir_fmul(b
, src_pos
, mul
), offset
);
144 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
145 struct brw_blorp_blit_vars
*v
)
147 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
148 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
149 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
150 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
151 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
152 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
154 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
155 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
156 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
157 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
159 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
161 nir_intrinsic_instr
*discard
=
162 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
163 discard
->src
[0] = nir_src_for_ssa(oob
);
164 nir_builder_instr_insert(b
, &discard
->instr
);
167 static nir_tex_instr
*
168 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
169 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
170 nir_alu_type dst_type
)
172 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
176 tex
->dest_type
= dst_type
;
177 tex
->is_array
= false;
178 tex
->is_shadow
= false;
180 /* Blorp only has one texture and it's bound at unit 0 */
181 tex
->texture_index
= 0;
182 tex
->sampler_index
= 0;
184 /* To properly handle 3-D and 2-D array textures, we pull the Z component
185 * from an input. TODO: This is a bit magic; we should probably make this
186 * more explicit in the future.
188 assert(pos
->num_components
>= 2);
189 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
190 nir_load_var(b
, v
->v_src_z
));
192 tex
->src
[0].src_type
= nir_tex_src_coord
;
193 tex
->src
[0].src
= nir_src_for_ssa(pos
);
194 tex
->coord_components
= 3;
196 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
202 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
203 const struct brw_blorp_blit_prog_key
*key
, nir_ssa_def
*pos
)
205 if (key
->need_src_offset
)
206 pos
= nir_fadd(b
, pos
, nir_i2f32(b
, nir_load_var(b
, v
->v_src_offset
)));
208 /* If the sampler requires normalized coordinates, we need to compensate. */
209 if (key
->src_coords_normalized
)
210 pos
= nir_fmul(b
, pos
, nir_load_var(b
, v
->v_src_inv_size
));
213 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2,
214 key
->texture_data_type
);
216 assert(pos
->num_components
== 2);
217 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
218 tex
->src
[1].src_type
= nir_tex_src_lod
;
219 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
221 nir_builder_instr_insert(b
, &tex
->instr
);
223 return &tex
->dest
.ssa
;
227 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
228 nir_ssa_def
*pos
, nir_alu_type dst_type
)
231 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
233 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
234 tex
->src
[1].src_type
= nir_tex_src_lod
;
235 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
237 nir_builder_instr_insert(b
, &tex
->instr
);
239 return &tex
->dest
.ssa
;
243 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
244 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
247 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
248 mcs
!= NULL
? 3 : 2, dst_type
);
250 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
252 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
253 if (pos
->num_components
== 2) {
254 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
256 assert(pos
->num_components
== 3);
257 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
261 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
262 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
265 nir_builder_instr_insert(b
, &tex
->instr
);
267 return &tex
->dest
.ssa
;
271 blorp_blit_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
275 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
276 pos
, 1, nir_type_int
);
278 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
280 nir_builder_instr_insert(b
, &tex
->instr
);
282 return &tex
->dest
.ssa
;
286 * Emit code to compensate for the difference between Y and W tiling.
288 * This code modifies the X and Y coordinates according to the formula:
290 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
292 * (See brw_blorp_build_nir_shader).
294 static inline nir_ssa_def
*
295 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
297 assert(pos
->num_components
== 2);
298 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
299 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
301 /* Given X and Y coordinates that describe an address using Y tiling,
302 * translate to the X and Y coordinates that describe the same address
305 * If we break down the low order bits of X and Y, using a
306 * single letter to represent each low-order bit:
308 * X = A << 7 | 0bBCDEFGH
309 * Y = J << 5 | 0bKLMNP (1)
311 * Then we can apply the Y tiling formula to see the memory offset being
314 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
316 * If we apply the W detiling formula to this memory location, that the
317 * corresponding X' and Y' coordinates are:
319 * X' = A << 6 | 0bBCDPFH (3)
320 * Y' = J << 6 | 0bKLMNEG
322 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
323 * we need to make the following computation:
325 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
326 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
328 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
329 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
330 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
331 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
333 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
334 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
335 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
336 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
338 return nir_vec2(b
, x_W
, y_W
);
342 * Emit code to compensate for the difference between Y and W tiling.
344 * This code modifies the X and Y coordinates according to the formula:
346 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
348 * (See brw_blorp_build_nir_shader).
350 static inline nir_ssa_def
*
351 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
353 assert(pos
->num_components
== 2);
354 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
355 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
357 /* Applying the same logic as above, but in reverse, we obtain the
360 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
361 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
363 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
364 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
365 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
366 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
367 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
369 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
370 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
371 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
373 return nir_vec2(b
, x_Y
, y_Y
);
377 * Emit code to compensate for the difference between MSAA and non-MSAA
380 * This code modifies the X and Y coordinates according to the formula:
382 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
384 * (See brw_blorp_blit_program).
386 static inline nir_ssa_def
*
387 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
388 unsigned num_samples
, enum isl_msaa_layout layout
)
390 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
393 case ISL_MSAA_LAYOUT_NONE
:
394 assert(pos
->num_components
== 2);
396 case ISL_MSAA_LAYOUT_ARRAY
:
397 /* No translation needed */
399 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
400 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
401 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
402 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
403 nir_channel(b
, pos
, 2);
405 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
406 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
407 switch (num_samples
) {
410 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
411 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
414 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
415 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
416 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
418 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
419 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
420 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
421 if (num_samples
== 2) {
424 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
425 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
426 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
431 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
432 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
434 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
436 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
437 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
438 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
439 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
440 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
441 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
442 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
446 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
447 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
449 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
452 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
453 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
454 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
455 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
456 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
457 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
458 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
459 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
463 unreachable("Invalid number of samples for IMS layout");
466 return nir_vec2(b
, x_out
, y_out
);
470 unreachable("Invalid MSAA layout");
475 * Emit code to compensate for the difference between MSAA and non-MSAA
478 * This code modifies the X and Y coordinates according to the formula:
480 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
482 * (See brw_blorp_blit_program).
484 static inline nir_ssa_def
*
485 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
486 unsigned num_samples
, enum isl_msaa_layout layout
)
488 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
491 case ISL_MSAA_LAYOUT_NONE
:
492 /* No translation necessary, and S should already be zero. */
493 assert(pos
->num_components
== 2);
495 case ISL_MSAA_LAYOUT_ARRAY
:
496 /* No translation necessary. */
498 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
499 assert(pos
->num_components
== 2);
501 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
502 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
504 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
505 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
506 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
507 switch (num_samples
) {
510 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
511 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
512 * S = (X & 0b10) >> 1
514 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
515 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
516 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
517 * S = (Y & 0b10) | (X & 0b10) >> 1
519 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
520 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
521 if (num_samples
== 2) {
523 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
525 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
526 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
527 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
528 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
533 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
534 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
535 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
536 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
538 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
539 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
540 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
541 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
542 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
543 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
544 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
548 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
549 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
550 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
551 * S = (Y & 0b100) << 1 | (X & 0b100) |
552 * (Y & 0b10) | (X & 0b10) >> 1
554 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
555 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
556 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
557 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
558 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
559 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
560 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
561 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
565 unreachable("Invalid number of samples for IMS layout");
568 return nir_vec3(b
, x_out
, y_out
, s_out
);
572 unreachable("Invalid MSAA layout");
577 * Count the number of trailing 1 bits in the given value. For example:
579 * count_trailing_one_bits(0) == 0
580 * count_trailing_one_bits(7) == 3
581 * count_trailing_one_bits(11) == 2
583 static inline int count_trailing_one_bits(unsigned value
)
585 #ifdef HAVE___BUILTIN_CTZ
586 return __builtin_ctz(~value
);
588 return _mesa_bitcount(value
& ~(value
+ 1));
593 blorp_nir_manual_blend_average(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
594 nir_ssa_def
*pos
, unsigned tex_samples
,
595 enum isl_aux_usage tex_aux_usage
,
596 nir_alu_type dst_type
)
598 /* If non-null, this is the outer-most if statement */
599 nir_if
*outer_if
= NULL
;
601 nir_variable
*color
=
602 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
604 nir_ssa_def
*mcs
= NULL
;
605 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
606 mcs
= blorp_blit_txf_ms_mcs(b
, v
, pos
);
608 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
610 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
612 * This ensures that when all samples have the same value, no numerical
613 * precision is lost, since each addition operation always adds two equal
614 * values, and summing two equal floating point values does not lose
617 * We perform this computation by treating the texture_data array as a
618 * stack and performing the following operations:
620 * - push sample 0 onto stack
621 * - push sample 1 onto stack
622 * - add top two stack entries
623 * - push sample 2 onto stack
624 * - push sample 3 onto stack
625 * - add top two stack entries
626 * - add top two stack entries
627 * - divide top stack entry by 4
629 * Note that after pushing sample i onto the stack, the number of add
630 * operations we do is equal to the number of trailing 1 bits in i. This
631 * works provided the total number of samples is a power of two, which it
632 * always is for i965.
634 * For integer formats, we replace the add operations with average
635 * operations and skip the final division.
637 nir_ssa_def
*texture_data
[5];
638 unsigned stack_depth
= 0;
639 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
640 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
642 /* Push sample i onto the stack */
643 assert(stack_depth
< ARRAY_SIZE(texture_data
));
645 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
646 nir_channel(b
, pos
, 1),
648 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
650 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
651 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
652 * suggests an optimization:
654 * "A simple optimization with probable large return in
655 * performance is to compare the MCS value to zero (indicating
656 * all samples are on sample slice 0), and sample only from
657 * sample slice 0 using ld2dss if MCS is zero."
659 * Note that in the case where the MCS value is zero, sampling from
660 * sample slice 0 using ld2dss and sampling from sample 0 using
661 * ld2dms are equivalent (since all samples are on sample slice 0).
662 * Since we have already sampled from sample 0, all we need to do is
663 * skip the remaining fetches and averaging if MCS is zero.
665 * It's also trivial to detect when the MCS has the magic clear color
666 * value. In this case, the txf we did on sample 0 will return the
667 * clear color and we can skip the remaining fetches just like we do
670 nir_ssa_def
*mcs_zero
=
671 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
672 if (tex_samples
== 16) {
673 mcs_zero
= nir_iand(b
, mcs_zero
,
674 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
676 nir_ssa_def
*mcs_clear
=
677 blorp_nir_mcs_is_clear_color(b
, mcs
, tex_samples
);
679 nir_if
*if_stmt
= nir_if_create(b
->shader
);
680 if_stmt
->condition
= nir_src_for_ssa(nir_ior(b
, mcs_zero
, mcs_clear
));
681 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
683 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
684 nir_store_var(b
, color
, texture_data
[0], 0xf);
686 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
690 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
691 assert(stack_depth
>= 2);
694 assert(dst_type
== nir_type_float
);
695 texture_data
[stack_depth
- 1] =
696 nir_fadd(b
, texture_data
[stack_depth
- 1],
697 texture_data
[stack_depth
]);
701 /* We should have just 1 sample on the stack now. */
702 assert(stack_depth
== 1);
704 texture_data
[0] = nir_fmul(b
, texture_data
[0],
705 nir_imm_float(b
, 1.0 / tex_samples
));
707 nir_store_var(b
, color
, texture_data
[0], 0xf);
710 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
712 return nir_load_var(b
, color
);
715 static inline nir_ssa_def
*
716 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
720 memset(&v
, 0, sizeof(v
));
724 return nir_build_imm(build
, 4, 32, v
);
728 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
729 unsigned tex_samples
,
730 const struct brw_blorp_blit_prog_key
*key
,
731 struct brw_blorp_blit_vars
*v
)
733 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
734 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
735 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
737 /* Translate coordinates to lay out the samples in a rectangular grid
738 * roughly corresponding to sample locations.
740 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
741 /* Adjust coordinates so that integers represent pixel centers rather
744 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
745 /* Clamp the X, Y texture coordinates to properly handle the sampling of
746 * texels on texture edges.
748 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
749 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
750 nir_channel(b
, rect_grid
, 1)));
752 /* Store the fractional parts to be used as bilinear interpolation
755 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
756 /* Round the float coordinates down to nearest integer */
757 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
759 nir_ssa_def
*tex_data
[4];
760 for (unsigned i
= 0; i
< 4; ++i
) {
761 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
762 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
763 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
765 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
766 nir_ssa_def
*sample_coords_int
= nir_f2i32(b
, sample_coords
);
768 /* The MCS value we fetch has to match up with the pixel that we're
769 * sampling from. Since we sample from different pixels in each
770 * iteration of this "for" loop, the call to mcs_fetch() should be
771 * here inside the loop after computing the pixel coordinates.
773 nir_ssa_def
*mcs
= NULL
;
774 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
775 mcs
= blorp_blit_txf_ms_mcs(b
, v
, sample_coords_int
);
777 /* Compute sample index and map the sample index to a sample number.
778 * Sample index layout shows the numbering of slots in a rectangular
779 * grid of samples with in a pixel. Sample number layout shows the
780 * rectangular grid of samples roughly corresponding to the real sample
781 * locations with in a pixel.
782 * In case of 4x MSAA, layout of sample indices matches the layout of
790 * In case of 8x MSAA the two layouts don't match.
791 * sample index layout : --------- sample number layout : ---------
792 * | 0 | 1 | | 3 | 7 |
793 * --------- ---------
794 * | 2 | 3 | | 5 | 0 |
795 * --------- ---------
796 * | 4 | 5 | | 1 | 2 |
797 * --------- ---------
798 * | 6 | 7 | | 4 | 6 |
799 * --------- ---------
801 * Fortunately, this can be done fairly easily as:
802 * S' = (0x17306425 >> (S * 4)) & 0xf
804 * In the case of 16x MSAA the two layouts don't match.
805 * Sample index layout: Sample number layout:
806 * --------------------- ---------------------
807 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
808 * --------------------- ---------------------
809 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
810 * --------------------- ---------------------
811 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
812 * --------------------- ---------------------
813 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
814 * --------------------- ---------------------
816 * This is equivalent to
817 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
819 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
820 nir_ssa_def
*sample
=
821 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
822 key
->x_scale
* key
->y_scale
));
823 sample
= nir_f2i32(b
, sample
);
825 if (tex_samples
== 8) {
826 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
827 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
828 nir_imm_int(b
, 0xf));
829 } else if (tex_samples
== 16) {
830 nir_ssa_def
*sample_low
=
831 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
832 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
833 nir_imm_int(b
, 0xf));
834 nir_ssa_def
*sample_high
=
835 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
836 nir_ishl(b
, nir_iadd(b
, sample
,
839 nir_imm_int(b
, 0xf));
841 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
842 sample_low
, sample_high
);
844 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
845 nir_channel(b
, sample_coords_int
, 1),
847 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
850 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
851 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
852 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
853 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
857 /** Perform a color bit-cast operation
859 * For copy operations involving CCS, we may need to use different formats for
860 * the source and destination surfaces. The two formats must both be UINT
861 * formats and must have the same size but may have different bit layouts.
862 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
863 * to R16G16_UINT. This function generates code to shuffle bits around to get
864 * us from one to the other.
867 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
868 const struct brw_blorp_blit_prog_key
*key
)
870 assert(key
->texture_data_type
== nir_type_uint
);
872 if (key
->src_format
== key
->dst_format
)
875 const struct isl_format_layout
*src_fmtl
=
876 isl_format_get_layout(key
->src_format
);
877 const struct isl_format_layout
*dst_fmtl
=
878 isl_format_get_layout(key
->dst_format
);
880 /* They must be uint formats with the same bit size */
881 assert(src_fmtl
->bpb
== dst_fmtl
->bpb
);
882 assert(src_fmtl
->channels
.r
.type
== ISL_UINT
);
883 assert(dst_fmtl
->channels
.r
.type
== ISL_UINT
);
885 /* They must be in regular color formats (no luminance or alpha) */
886 assert(src_fmtl
->channels
.r
.bits
> 0);
887 assert(dst_fmtl
->channels
.r
.bits
> 0);
889 /* They must be in RGBA order (possibly with channels missing) */
890 assert(src_fmtl
->channels
.r
.start_bit
== 0);
891 assert(dst_fmtl
->channels
.r
.start_bit
== 0);
893 if (src_fmtl
->bpb
<= 32) {
894 const unsigned src_channels
=
895 isl_format_get_num_channels(key
->src_format
);
896 const unsigned src_bits
[4] = {
897 src_fmtl
->channels
.r
.bits
,
898 src_fmtl
->channels
.g
.bits
,
899 src_fmtl
->channels
.b
.bits
,
900 src_fmtl
->channels
.a
.bits
,
902 const unsigned dst_channels
=
903 isl_format_get_num_channels(key
->dst_format
);
904 const unsigned dst_bits
[4] = {
905 dst_fmtl
->channels
.r
.bits
,
906 dst_fmtl
->channels
.g
.bits
,
907 dst_fmtl
->channels
.b
.bits
,
908 dst_fmtl
->channels
.a
.bits
,
910 nir_ssa_def
*packed
=
911 nir_format_pack_uint_unmasked(b
, color
, src_bits
, src_channels
);
912 color
= nir_format_unpack_uint(b
, packed
, dst_bits
, dst_channels
);
914 const unsigned src_bpc
= src_fmtl
->channels
.r
.bits
;
915 const unsigned dst_bpc
= dst_fmtl
->channels
.r
.bits
;
917 assert(src_fmtl
->channels
.g
.bits
== 0 ||
918 src_fmtl
->channels
.g
.bits
== src_fmtl
->channels
.r
.bits
);
919 assert(src_fmtl
->channels
.b
.bits
== 0 ||
920 src_fmtl
->channels
.b
.bits
== src_fmtl
->channels
.r
.bits
);
921 assert(src_fmtl
->channels
.a
.bits
== 0 ||
922 src_fmtl
->channels
.a
.bits
== src_fmtl
->channels
.r
.bits
);
923 assert(dst_fmtl
->channels
.g
.bits
== 0 ||
924 dst_fmtl
->channels
.g
.bits
== dst_fmtl
->channels
.r
.bits
);
925 assert(dst_fmtl
->channels
.b
.bits
== 0 ||
926 dst_fmtl
->channels
.b
.bits
== dst_fmtl
->channels
.r
.bits
);
927 assert(dst_fmtl
->channels
.a
.bits
== 0 ||
928 dst_fmtl
->channels
.a
.bits
== dst_fmtl
->channels
.r
.bits
);
930 /* Restrict to only the channels we actually have */
931 const unsigned src_channels
=
932 isl_format_get_num_channels(key
->src_format
);
933 color
= nir_channels(b
, color
, (1 << src_channels
) - 1);
935 color
= nir_format_bitcast_uint_vec_unmasked(b
, color
, src_bpc
, dst_bpc
);
938 /* Blorp likes to assume that colors are vec4s */
939 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
940 nir_ssa_def
*chans
[4] = { u
, u
, u
, u
};
941 for (unsigned i
= 0; i
< color
->num_components
; i
++)
942 chans
[i
] = nir_channel(b
, color
, i
);
943 return nir_vec4(b
, chans
[0], chans
[1], chans
[2], chans
[3]);
947 select_color_channel(struct nir_builder
*b
, nir_ssa_def
*color
,
948 nir_alu_type data_type
,
949 enum isl_channel_select chan
)
951 if (chan
== ISL_CHANNEL_SELECT_ZERO
) {
952 return nir_imm_int(b
, 0);
953 } else if (chan
== ISL_CHANNEL_SELECT_ONE
) {
957 return nir_imm_int(b
, 1);
959 return nir_imm_float(b
, 1);
961 unreachable("Invalid data type");
964 assert((unsigned)(chan
- ISL_CHANNEL_SELECT_RED
) < 4);
965 return nir_channel(b
, color
, chan
- ISL_CHANNEL_SELECT_RED
);
970 swizzle_color(struct nir_builder
*b
, nir_ssa_def
*color
,
971 struct isl_swizzle swizzle
, nir_alu_type data_type
)
974 select_color_channel(b
, color
, data_type
, swizzle
.r
),
975 select_color_channel(b
, color
, data_type
, swizzle
.g
),
976 select_color_channel(b
, color
, data_type
, swizzle
.b
),
977 select_color_channel(b
, color
, data_type
, swizzle
.a
));
981 convert_color(struct nir_builder
*b
, nir_ssa_def
*color
,
982 const struct brw_blorp_blit_prog_key
*key
)
984 /* All of our color conversions end up generating a single-channel color
985 * value that we need to write out.
989 if (key
->dst_format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
990 /* The destination image is bound as R32_UNORM but the data needs to be
991 * in R24_UNORM_X8_TYPELESS. The bottom 24 are the actual data and the
992 * top 8 need to be zero. We can accomplish this by simply multiplying
993 * by a factor to scale things down.
995 float factor
= (float)((1 << 24) - 1) / (float)UINT32_MAX
;
996 value
= nir_fmul(b
, nir_fsat(b
, nir_channel(b
, color
, 0)),
997 nir_imm_float(b
, factor
));
998 } else if (key
->dst_format
== ISL_FORMAT_L8_UNORM_SRGB
) {
999 value
= nir_format_linear_to_srgb(b
, color
);
1000 } else if (key
->dst_format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
1001 value
= nir_format_pack_r9g9b9e5(b
, color
);
1003 unreachable("Unsupported format conversion");
1006 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
1007 return nir_vec4(b
, value
, u
, u
, u
);
1011 * Generator for WM programs used in BLORP blits.
1013 * The bulk of the work done by the WM program is to wrap and unwrap the
1014 * coordinate transformations used by the hardware to store surfaces in
1015 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
1016 * sample index for a multisampled surface) to a memory offset by the
1017 * following formulas:
1019 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
1020 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
1022 * For a single-sampled surface, or for a multisampled surface using
1023 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
1026 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1027 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
1028 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1029 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
1031 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1032 * embeds the sample number into bit 1 of the X and Y coordinates:
1034 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1035 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1036 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
1037 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1038 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1039 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1040 * S = (Y & 0b10) | (X & 0b10) >> 1
1042 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1043 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
1046 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1047 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
1048 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1049 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1050 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1051 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1052 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1054 * For X tiling, tile() combines together the low-order bits of the X and Y
1055 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
1056 * bytes wide and 8 rows high:
1058 * tile(x_tiled, X, Y, S) = A
1059 * where A = tile_num << 12 | offset
1060 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
1061 * offset = (Y' & 0b111) << 9
1062 * | (X & 0b111111111)
1064 * Y' = Y + S * qpitch
1065 * detile(x_tiled, A) = (X, Y, S)
1066 * where X = X' / cpp
1069 * Y' = (tile_num / tile_pitch) << 3
1070 * | (A & 0b111000000000) >> 9
1071 * X' = (tile_num % tile_pitch) << 9
1072 * | (A & 0b111111111)
1074 * (In all tiling formulas, cpp is the number of bytes occupied by a single
1075 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
1076 * to fill the width of the surface, and qpitch is the spacing (in rows)
1077 * between array slices).
1079 * For Y tiling, tile() combines together the low-order bits of the X and Y
1080 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
1081 * bytes wide and 32 rows high:
1083 * tile(y_tiled, X, Y, S) = A
1084 * where A = tile_num << 12 | offset
1085 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
1086 * offset = (X' & 0b1110000) << 5
1087 * | (Y' & 0b11111) << 4
1090 * Y' = Y + S * qpitch
1091 * detile(y_tiled, A) = (X, Y, S)
1092 * where X = X' / cpp
1095 * Y' = (tile_num / tile_pitch) << 5
1096 * | (A & 0b111110000) >> 4
1097 * X' = (tile_num % tile_pitch) << 7
1098 * | (A & 0b111000000000) >> 5
1101 * For W tiling, tile() combines together the low-order bits of the X and Y
1102 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1103 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1104 * buffers, which always have cpp = 1 and S=0):
1106 * tile(w_tiled, X, Y, S) = A
1107 * where A = tile_num << 12 | offset
1108 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1109 * offset = (X' & 0b111000) << 6
1110 * | (Y' & 0b111100) << 3
1111 * | (X' & 0b100) << 2
1112 * | (Y' & 0b10) << 2
1113 * | (X' & 0b10) << 1
1117 * Y' = Y + S * qpitch
1118 * detile(w_tiled, A) = (X, Y, S)
1119 * where X = X' / cpp = X'
1120 * Y = Y' % qpitch = Y'
1121 * S = Y / qpitch = 0
1122 * Y' = (tile_num / tile_pitch) << 6
1123 * | (A & 0b111100000) >> 3
1124 * | (A & 0b1000) >> 2
1126 * X' = (tile_num % tile_pitch) << 6
1127 * | (A & 0b111000000000) >> 6
1128 * | (A & 0b10000) >> 2
1129 * | (A & 0b100) >> 1
1132 * Finally, for a non-tiled surface, tile() simply combines together the X and
1133 * Y coordinates in the natural way:
1135 * tile(untiled, X, Y, S) = A
1136 * where A = Y * pitch + X'
1138 * Y' = Y + S * qpitch
1139 * detile(untiled, A) = (X, Y, S)
1140 * where X = X' / cpp
1146 * (In these formulas, pitch is the number of bytes occupied by a single row
1150 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1151 const struct brw_blorp_blit_prog_key
*key
)
1153 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1154 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1157 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1158 /* If the destination image is W tiled and multisampled, then the thread
1159 * must be dispatched once per sample, not once per pixel. This is
1160 * necessary because after conversion between W and Y tiling, there's no
1161 * guarantee that all samples corresponding to a single pixel will still
1164 assert(key
->persample_msaa_dispatch
);
1168 /* We are blending, which means we won't have an opportunity to
1169 * translate the tiling and sample count for the texture surface. So
1170 * the surface state for the texture must be configured with the correct
1171 * tiling and sample count.
1173 assert(!key
->src_tiled_w
);
1174 assert(key
->tex_samples
== key
->src_samples
);
1175 assert(key
->tex_layout
== key
->src_layout
);
1176 assert(key
->tex_samples
> 0);
1179 if (key
->persample_msaa_dispatch
) {
1180 /* It only makes sense to do persample dispatch if the render target is
1181 * configured as multisampled.
1183 assert(key
->rt_samples
> 0);
1186 /* Make sure layout is consistent with sample count */
1187 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1188 (key
->tex_samples
<= 1));
1189 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1190 (key
->rt_samples
<= 1));
1191 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1192 (key
->src_samples
<= 1));
1193 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1194 (key
->dst_samples
<= 1));
1197 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1199 struct brw_blorp_blit_vars v
;
1200 brw_blorp_blit_vars_init(&b
, &v
, key
);
1202 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1204 /* Render target and texture hardware don't support W tiling until Gen8. */
1205 const bool rt_tiled_w
= false;
1206 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1208 /* The address that data will be written to is determined by the
1209 * coordinates supplied to the WM thread and the tiling and sample count of
1210 * the render target, according to the formula:
1212 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1214 * If the actual tiling and sample count of the destination surface are not
1215 * the same as the configuration of the render target, then these
1216 * coordinates are wrong and we have to adjust them to compensate for the
1219 if (rt_tiled_w
!= key
->dst_tiled_w
||
1220 key
->rt_samples
!= key
->dst_samples
||
1221 key
->rt_layout
!= key
->dst_layout
) {
1222 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1224 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1225 if (rt_tiled_w
!= key
->dst_tiled_w
)
1226 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1227 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1228 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1232 nir_ssa_def
*comp
= NULL
;
1234 /* The destination image is bound as a red texture three times as wide
1235 * as the actual image. Our shader is effectively running one color
1236 * component at a time. We need to save off the component and adjust
1237 * the destination position.
1239 assert(dst_pos
->num_components
== 2);
1240 nir_ssa_def
*dst_x
= nir_channel(&b
, dst_pos
, 0);
1241 comp
= nir_umod(&b
, dst_x
, nir_imm_int(&b
, 3));
1242 dst_pos
= nir_vec2(&b
, nir_idiv(&b
, dst_x
, nir_imm_int(&b
, 3)),
1243 nir_channel(&b
, dst_pos
, 1));
1246 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1248 * That is: X, Y and S now contain the true coordinates and sample index of
1249 * the data that the WM thread should output.
1251 * If we need to kill pixels that are outside the destination rectangle,
1252 * now is the time to do it.
1254 if (key
->use_kill
) {
1255 assert(!(key
->blend
&& key
->blit_scaled
));
1256 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1259 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f32(&b
, dst_pos
), &v
);
1260 if (dst_pos
->num_components
== 3) {
1261 /* The sample coordinate is an integer that we want left alone but
1262 * blorp_blit_apply_transform() blindly applies the transform to all
1263 * three coordinates. Grab the original sample index.
1265 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1266 nir_channel(&b
, src_pos
, 1),
1267 nir_channel(&b
, dst_pos
, 2));
1270 /* If the source image is not multisampled, then we want to fetch sample
1271 * number 0, because that's the only sample there is.
1273 if (key
->src_samples
== 1)
1274 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1276 /* X, Y, and S are now the coordinates of the pixel in the source image
1277 * that we want to texture from. Exception: if we are blending, then S is
1278 * irrelevant, because we are going to fetch all samples.
1280 if (key
->blend
&& !key
->blit_scaled
) {
1281 /* Resolves (effecively) use texelFetch, so we need integers and we
1282 * don't care about the sample index if we got one.
1284 src_pos
= nir_f2i32(&b
, nir_channels(&b
, src_pos
, 0x3));
1286 if (devinfo
->gen
== 6) {
1287 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1288 * blending we need with a single linear-interpolated texture lookup
1289 * at the center of the sample. The texture coordinates to be odd
1290 * integers so that they correspond to the center of a 2x2 block
1291 * representing the four samples that maxe up a pixel. So we need
1292 * to multiply our X and Y coordinates each by 2 and then add 1.
1294 assert(key
->src_coords_normalized
);
1295 src_pos
= nir_fadd(&b
,
1296 nir_i2f32(&b
, src_pos
),
1297 nir_imm_float(&b
, 0.5f
));
1298 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1300 /* Gen7+ hardware doesn't automaticaly blend. */
1301 color
= blorp_nir_manual_blend_average(&b
, &v
, src_pos
, key
->src_samples
,
1303 key
->texture_data_type
);
1305 } else if (key
->blend
&& key
->blit_scaled
) {
1306 assert(!key
->use_kill
);
1307 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
, key
, &v
);
1309 if (key
->bilinear_filter
) {
1310 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1312 /* We're going to use texelFetch, so we need integers */
1313 if (src_pos
->num_components
== 2) {
1314 src_pos
= nir_f2i32(&b
, src_pos
);
1316 assert(src_pos
->num_components
== 3);
1317 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i32(&b
, src_pos
), 0),
1318 nir_channel(&b
, nir_f2i32(&b
, src_pos
), 1),
1319 nir_channel(&b
, src_pos
, 2));
1322 /* We aren't blending, which means we just want to fetch a single
1323 * sample from the source surface. The address that we want to fetch
1324 * from is related to the X, Y and S values according to the formula:
1326 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1328 * If the actual tiling and sample count of the source surface are
1329 * not the same as the configuration of the texture, then we need to
1330 * adjust the coordinates to compensate for the difference.
1332 if (tex_tiled_w
!= key
->src_tiled_w
||
1333 key
->tex_samples
!= key
->src_samples
||
1334 key
->tex_layout
!= key
->src_layout
) {
1335 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1337 /* Now (X, Y, S) = detile(src_tiling, offset) */
1338 if (tex_tiled_w
!= key
->src_tiled_w
)
1339 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1340 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1341 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1345 if (key
->need_src_offset
)
1346 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1348 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1350 * In other words: X, Y, and S now contain values which, when passed to
1351 * the texturing unit, will cause data to be read from the correct
1352 * memory location. So we can fetch the texel now.
1354 if (key
->src_samples
== 1) {
1355 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1357 nir_ssa_def
*mcs
= NULL
;
1358 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1359 mcs
= blorp_blit_txf_ms_mcs(&b
, &v
, src_pos
);
1361 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1366 if (!isl_swizzle_is_identity(key
->src_swizzle
)) {
1367 color
= swizzle_color(&b
, color
, key
->src_swizzle
,
1368 key
->texture_data_type
);
1371 if (!isl_swizzle_is_identity(key
->dst_swizzle
)) {
1372 color
= swizzle_color(&b
, color
, isl_swizzle_invert(key
->dst_swizzle
),
1376 if (key
->format_bit_cast
) {
1377 assert(isl_swizzle_is_identity(key
->src_swizzle
));
1378 assert(isl_swizzle_is_identity(key
->dst_swizzle
));
1379 color
= bit_cast_color(&b
, color
, key
);
1380 } else if (key
->dst_format
) {
1381 color
= convert_color(&b
, color
, key
);
1385 /* The destination image is bound as a red texture three times as wide
1386 * as the actual image. Our shader is effectively running one color
1387 * component at a time. We need to pick off the appropriate component
1388 * from the source color and write that to destination red.
1390 assert(dst_pos
->num_components
== 2);
1392 nir_ssa_def
*color_component
=
1393 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1394 nir_channel(&b
, color
, 0),
1395 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1396 nir_channel(&b
, color
, 1),
1397 nir_channel(&b
, color
, 2)));
1399 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1400 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1403 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1409 brw_blorp_get_blit_kernel(struct blorp_context
*blorp
,
1410 struct blorp_params
*params
,
1411 const struct brw_blorp_blit_prog_key
*prog_key
)
1413 if (blorp
->lookup_shader(blorp
, prog_key
, sizeof(*prog_key
),
1414 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1417 void *mem_ctx
= ralloc_context(NULL
);
1419 const unsigned *program
;
1420 struct brw_wm_prog_data prog_data
;
1422 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1423 nir
->info
.name
= ralloc_strdup(nir
, "BLORP-blit");
1425 struct brw_wm_prog_key wm_key
;
1426 brw_blorp_init_wm_prog_key(&wm_key
);
1427 wm_key
.tex
.compressed_multisample_layout_mask
=
1428 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1429 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1430 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1432 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1436 blorp
->upload_shader(blorp
, prog_key
, sizeof(*prog_key
),
1437 program
, prog_data
.base
.program_size
,
1438 &prog_data
.base
, sizeof(prog_data
),
1439 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1441 ralloc_free(mem_ctx
);
1446 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1447 GLfloat src0
, GLfloat src1
,
1448 GLfloat dst0
, GLfloat dst1
,
1451 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1453 /* When not mirroring a coordinate (say, X), we need:
1454 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1456 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1458 * blorp program uses "round toward zero" to convert the
1459 * transformed floating point coordinates to integer coordinates,
1460 * whereas the behaviour we actually want is "round to nearest",
1461 * so 0.5 provides the necessary correction.
1463 xform
->multiplier
= scale
;
1464 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1466 /* When mirroring X we need:
1467 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1469 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1471 xform
->multiplier
= -scale
;
1472 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1477 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1478 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1480 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1481 struct isl_extent2d px_size_sa
=
1482 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1483 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1484 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1485 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1486 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1488 *tile_x_px
= info
->tile_x_sa
;
1489 *tile_y_px
= info
->tile_y_sa
;
1494 blorp_surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1495 struct brw_blorp_surface_info
*info
)
1499 /* Just bail if we have nothing to do. */
1500 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1501 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1502 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1505 /* If this gets triggered then we've gotten here twice which. This
1506 * shouldn't happen thanks to the above early return.
1508 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1510 uint32_t layer
= 0, z
= 0;
1511 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1512 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1514 layer
= info
->view
.base_array_layer
;
1516 uint32_t byte_offset
;
1517 isl_surf_get_image_surf(isl_dev
, &info
->surf
,
1518 info
->view
.base_level
, layer
, z
,
1520 &byte_offset
, &info
->tile_x_sa
, &info
->tile_y_sa
);
1521 info
->addr
.offset
+= byte_offset
;
1523 uint32_t tile_x_px
, tile_y_px
;
1524 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1526 /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we place
1527 * the image at the tile boundary and offset our sampling or rendering.
1528 * For this reason, we need to grow the image by the offset to ensure that
1529 * the hardware doesn't think we've gone past the edge.
1531 info
->surf
.logical_level0_px
.w
+= tile_x_px
;
1532 info
->surf
.logical_level0_px
.h
+= tile_y_px
;
1533 info
->surf
.phys_level0_sa
.w
+= info
->tile_x_sa
;
1534 info
->surf
.phys_level0_sa
.h
+= info
->tile_y_sa
;
1536 /* The view is also different now. */
1537 info
->view
.base_level
= 0;
1538 info
->view
.levels
= 1;
1539 info
->view
.base_array_layer
= 0;
1540 info
->view
.array_len
= 1;
1545 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1546 struct brw_blorp_surface_info
*info
)
1548 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1550 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1551 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1553 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1554 info
->surf
.samples
= 1;
1555 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1559 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1560 struct brw_blorp_surface_info
*info
)
1562 assert(info
->surf
.tiling
== ISL_TILING_W
);
1564 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1565 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1567 /* On gen7+, we don't have interleaved multisampling for color render
1568 * targets so we have to fake it.
1570 * TODO: Are we sure we don't also need to fake it on gen6?
1572 if (isl_dev
->info
->gen
> 6 &&
1573 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1574 surf_fake_interleaved_msaa(isl_dev
, info
);
1577 if (isl_dev
->info
->gen
== 6) {
1578 /* Gen6 stencil buffers have a very large alignment coming in from the
1579 * miptree. It's out-of-bounds for what the surface state can handle.
1580 * Since we have a single layer and level, it doesn't really matter as
1581 * long as we don't pass a bogus value into isl_surf_fill_state().
1583 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1586 /* Now that we've converted everything to a simple 2-D surface with only
1587 * one miplevel, we can go about retiling it.
1589 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1590 info
->surf
.tiling
= ISL_TILING_Y0
;
1591 info
->surf
.logical_level0_px
.width
=
1592 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1593 info
->surf
.logical_level0_px
.height
=
1594 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1595 info
->tile_x_sa
*= 2;
1596 info
->tile_y_sa
/= 2;
1600 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1602 /* The current code doesn't support offsets into the aux buffers. This
1603 * should be possible, but we need to make sure the offset is page
1604 * aligned for both the surface and the aux buffer surface. Generally
1605 * this mean using the page aligned offset for the aux buffer.
1607 * Currently the cases where we must split the blit are limited to cases
1608 * where we don't have a aux buffer.
1610 if (surf
->aux_addr
.buffer
!= NULL
)
1613 /* We can't support splitting the blit for gen <= 7, because the qpitch
1614 * size is calculated by the hardware based on the surface height for
1615 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1617 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1624 can_shrink_surfaces(const struct blorp_params
*params
)
1627 can_shrink_surface(¶ms
->src
) &&
1628 can_shrink_surface(¶ms
->dst
);
1632 get_max_surface_size(const struct gen_device_info
*devinfo
,
1633 const struct blorp_params
*params
)
1635 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1636 if (split_blorp_blit_debug
&& can_shrink_surfaces(params
))
1637 return max
>> 4; /* A smaller restriction when debug is enabled */
1643 double src0
, src1
, dst0
, dst1
;
1648 struct blt_axis x
, y
;
1651 static enum isl_format
1652 get_red_format_for_rgb_format(enum isl_format format
)
1654 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1656 switch (fmtl
->channels
.r
.bits
) {
1658 switch (fmtl
->channels
.r
.type
) {
1660 return ISL_FORMAT_R8_UNORM
;
1662 return ISL_FORMAT_R8_SNORM
;
1664 return ISL_FORMAT_R8_UINT
;
1666 return ISL_FORMAT_R8_SINT
;
1668 unreachable("Invalid 8-bit RGB channel type");
1671 switch (fmtl
->channels
.r
.type
) {
1673 return ISL_FORMAT_R16_UNORM
;
1675 return ISL_FORMAT_R16_SNORM
;
1677 return ISL_FORMAT_R16_FLOAT
;
1679 return ISL_FORMAT_R16_UINT
;
1681 return ISL_FORMAT_R16_SINT
;
1683 unreachable("Invalid 8-bit RGB channel type");
1686 switch (fmtl
->channels
.r
.type
) {
1688 return ISL_FORMAT_R32_FLOAT
;
1690 return ISL_FORMAT_R32_UINT
;
1692 return ISL_FORMAT_R32_SINT
;
1694 unreachable("Invalid 8-bit RGB channel type");
1697 unreachable("Invalid number of red channel bits");
1702 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1703 struct brw_blorp_surface_info
*info
)
1705 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1707 info
->surf
.logical_level0_px
.width
*= 3;
1708 info
->surf
.phys_level0_sa
.width
*= 3;
1709 info
->tile_x_sa
*= 3;
1711 enum isl_format red_format
=
1712 get_red_format_for_rgb_format(info
->view
.format
);
1714 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1715 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1716 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1717 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1719 info
->surf
.format
= info
->view
.format
= red_format
;
1722 enum blit_shrink_status
{
1724 BLIT_WIDTH_SHRINK
= 1,
1725 BLIT_HEIGHT_SHRINK
= 2,
1728 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1729 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1730 * returned, then the blit was successful.
1732 static enum blit_shrink_status
1733 try_blorp_blit(struct blorp_batch
*batch
,
1734 struct blorp_params
*params
,
1735 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1736 struct blt_coords
*coords
)
1738 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1740 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1741 wm_prog_key
->texture_data_type
= nir_type_int
;
1742 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1743 wm_prog_key
->texture_data_type
= nir_type_uint
;
1745 wm_prog_key
->texture_data_type
= nir_type_float
;
1748 /* src_samples and dst_samples are the true sample counts */
1749 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1750 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1752 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1754 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1757 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1758 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1760 /* Round floating point values to nearest integer to avoid "off by one texel"
1761 * kind of errors when blitting.
1763 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1764 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1765 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1766 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1768 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1769 coords
->x
.src0
, coords
->x
.src1
,
1770 coords
->x
.dst0
, coords
->x
.dst1
,
1772 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1773 coords
->y
.src0
, coords
->y
.src1
,
1774 coords
->y
.dst0
, coords
->y
.dst1
,
1778 if (devinfo
->gen
== 4) {
1779 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
1780 * Convert them to a single slice on gen4.
1782 if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1783 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1784 wm_prog_key
->need_dst_offset
= true;
1787 if (params
->src
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1788 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->src
);
1789 wm_prog_key
->need_src_offset
= true;
1793 if (devinfo
->gen
> 6 &&
1794 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1795 assert(params
->dst
.surf
.samples
> 1);
1797 /* We must expand the rectangle we send through the rendering pipeline,
1798 * to account for the fact that we are mapping the destination region as
1799 * single-sampled when it is in fact multisampled. We must also align
1800 * it to a multiple of the multisampling pattern, because the
1801 * differences between multisampled and single-sampled surface formats
1802 * will mean that pixels are scrambled within the multisampling pattern.
1803 * TODO: what if this makes the coordinates too large?
1805 * Note: this only works if the destination surface uses the IMS layout.
1806 * If it's UMS, then we have no choice but to set up the rendering
1807 * pipeline as multisampled.
1809 struct isl_extent2d px_size_sa
=
1810 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1811 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1812 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1813 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1814 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1816 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1818 wm_prog_key
->use_kill
= true;
1819 wm_prog_key
->need_dst_offset
= true;
1822 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1823 /* We must modify the rectangle we send through the rendering pipeline
1824 * (and the size and x/y offset of the destination surface), to account
1825 * for the fact that we are mapping it as Y-tiled when it is in fact
1828 * Both Y tiling and W tiling can be understood as organizations of
1829 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1830 * is different, but the layout of the 32-byte sub-tiles within the 4k
1831 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1832 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1833 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1835 * Therefore, to account for the layout differences within the 32-byte
1836 * sub-tiles, we must expand the rectangle so the X coordinates of its
1837 * edges are multiples of 8 (the W sub-tile width), and its Y
1838 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1839 * Then we need to scale the X and Y coordinates of the rectangle to
1840 * account for the differences in aspect ratio between the Y and W
1841 * sub-tiles. We need to modify the layer width and height similarly.
1843 * A correction needs to be applied when MSAA is in use: since
1844 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1845 * we need to align the Y coordinates to multiples of 8, so that when
1846 * they are divided by two they are still multiples of 4.
1848 * Note: Since the x/y offset of the surface will be applied using the
1849 * SURFACE_STATE command packet, it will be invisible to the swizzling
1850 * code in the shader; therefore it needs to be in a multiple of the
1851 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1852 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1853 * buffer), and the miplevel alignment used for stencil buffers is 8
1854 * pixels horizontally and either 4 or 8 pixels vertically (see
1855 * intel_horizontal_texture_alignment_unit() and
1856 * intel_vertical_texture_alignment_unit()).
1858 * Note: Also, since the SURFACE_STATE command packet can only apply
1859 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1860 * vertically, it is important that the offsets will be multiples of
1861 * these sizes after they are converted into Y-tiled coordinates.
1862 * Fortunately they will be, since we know from above that the offsets
1863 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1864 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1866 * TODO: what if this makes the coordinates (or the texture size) too
1869 const unsigned x_align
= 8;
1870 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1871 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1872 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1873 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1874 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1876 /* Retile the surface to Y-tiled */
1877 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1879 wm_prog_key
->dst_tiled_w
= true;
1880 wm_prog_key
->use_kill
= true;
1881 wm_prog_key
->need_dst_offset
= true;
1883 if (params
->dst
.surf
.samples
> 1) {
1884 /* If the destination surface is a W-tiled multisampled stencil
1885 * buffer that we're mapping as Y tiled, then we need to arrange for
1886 * the WM program to run once per sample rather than once per pixel,
1887 * because the memory layout of related samples doesn't match between
1890 wm_prog_key
->persample_msaa_dispatch
= true;
1894 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1895 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1896 * Broadwell adds support for sampling from stencil.
1898 * See the comments above concerning x/y offset alignment for the
1899 * destination surface.
1901 * TODO: what if this makes the texture size too large?
1903 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1905 wm_prog_key
->src_tiled_w
= true;
1906 wm_prog_key
->need_src_offset
= true;
1909 /* tex_samples and rt_samples are the sample counts that are set up in
1912 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1913 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1915 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1916 * use to access the source and destination surfaces.
1918 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1919 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1921 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1922 /* We are blitting from a multisample buffer to a multisample buffer, so
1923 * we must preserve samples within a pixel. This means we have to
1924 * arrange for the WM program to run once per sample rather than once
1927 wm_prog_key
->persample_msaa_dispatch
= true;
1930 params
->num_samples
= params
->dst
.surf
.samples
;
1932 if ((wm_prog_key
->bilinear_filter
||
1933 (wm_prog_key
->blend
&& !wm_prog_key
->blit_scaled
)) &&
1934 batch
->blorp
->isl_dev
->info
->gen
<= 6) {
1935 /* Gen4-5 don't support non-normalized texture coordinates */
1936 wm_prog_key
->src_coords_normalized
= true;
1937 params
->wm_inputs
.src_inv_size
[0] =
1938 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.width
,
1939 params
->src
.view
.base_level
);
1940 params
->wm_inputs
.src_inv_size
[1] =
1941 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.height
,
1942 params
->src
.view
.base_level
);
1945 if (isl_format_get_layout(params
->dst
.view
.format
)->bpb
% 3 == 0) {
1946 /* We can't render to RGB formats natively because they aren't a
1947 * power-of-two size. Instead, we fake them by using a red format
1948 * with the same channel type and size and emitting shader code to
1949 * only write one channel at a time.
1954 /* If it happens to be sRGB, we need to force a conversion */
1955 if (params
->dst
.view
.format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
)
1956 wm_prog_key
->dst_format
= ISL_FORMAT_R9G9B9E5_SHAREDEXP
;
1958 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1960 wm_prog_key
->dst_rgb
= true;
1961 wm_prog_key
->need_dst_offset
= true;
1962 } else if (isl_format_is_rgbx(params
->dst
.view
.format
)) {
1963 /* We can handle RGBX formats easily enough by treating them as RGBA */
1964 params
->dst
.view
.format
=
1965 isl_format_rgbx_to_rgba(params
->dst
.view
.format
);
1966 } else if (params
->dst
.view
.format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
) {
1967 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
1968 params
->dst
.view
.format
= ISL_FORMAT_R32_UNORM
;
1969 } else if (params
->dst
.view
.format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
1970 params
->dst
.view
.swizzle
=
1971 isl_swizzle_compose(params
->dst
.view
.swizzle
,
1972 ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
));
1973 params
->dst
.view
.format
= ISL_FORMAT_B4G4R4A4_UNORM
;
1974 } else if (params
->dst
.view
.format
== ISL_FORMAT_L8_UNORM_SRGB
) {
1975 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
1976 params
->dst
.view
.format
= ISL_FORMAT_R8_UNORM
;
1977 } else if (params
->dst
.view
.format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
1978 wm_prog_key
->dst_format
= params
->dst
.view
.format
;
1979 params
->dst
.view
.format
= ISL_FORMAT_R32_UINT
;
1982 if (devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
1983 !isl_swizzle_is_identity(params
->src
.view
.swizzle
)) {
1984 wm_prog_key
->src_swizzle
= params
->src
.view
.swizzle
;
1985 params
->src
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
1987 wm_prog_key
->src_swizzle
= ISL_SWIZZLE_IDENTITY
;
1990 if (!isl_swizzle_supports_rendering(devinfo
, params
->dst
.view
.swizzle
)) {
1991 wm_prog_key
->dst_swizzle
= params
->dst
.view
.swizzle
;
1992 params
->dst
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
1994 wm_prog_key
->dst_swizzle
= ISL_SWIZZLE_IDENTITY
;
1997 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
1998 assert(wm_prog_key
->need_src_offset
);
1999 surf_get_intratile_offset_px(¶ms
->src
,
2000 ¶ms
->wm_inputs
.src_offset
.x
,
2001 ¶ms
->wm_inputs
.src_offset
.y
);
2004 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
2005 assert(wm_prog_key
->need_dst_offset
);
2006 surf_get_intratile_offset_px(¶ms
->dst
,
2007 ¶ms
->wm_inputs
.dst_offset
.x
,
2008 ¶ms
->wm_inputs
.dst_offset
.y
);
2009 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
2010 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
2011 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
2012 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
2015 /* For some texture types, we need to pass the layer through the sampler. */
2016 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
2018 if (!brw_blorp_get_blit_kernel(batch
->blorp
, params
, wm_prog_key
))
2021 if (!blorp_ensure_sf_program(batch
->blorp
, params
))
2024 unsigned result
= 0;
2025 unsigned max_surface_size
= get_max_surface_size(devinfo
, params
);
2026 if (params
->src
.surf
.logical_level0_px
.width
> max_surface_size
||
2027 params
->dst
.surf
.logical_level0_px
.width
> max_surface_size
)
2028 result
|= BLIT_WIDTH_SHRINK
;
2029 if (params
->src
.surf
.logical_level0_px
.height
> max_surface_size
||
2030 params
->dst
.surf
.logical_level0_px
.height
> max_surface_size
)
2031 result
|= BLIT_HEIGHT_SHRINK
;
2034 batch
->blorp
->exec(batch
, params
);
2040 /* Adjust split blit source coordinates for the current destination
2044 adjust_split_source_coords(const struct blt_axis
*orig
,
2045 struct blt_axis
*split_coords
,
2048 /* When scale is greater than 0, then we are growing from the start, so
2049 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
2050 * source range shrinks from the end. In that case src0 is adjusted by
2051 * delta1, and src1 is adjusted by delta0.
2053 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
2054 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
2055 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
2056 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
2059 static struct isl_extent2d
2060 get_px_size_sa(const struct isl_surf
*surf
)
2062 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
2064 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
2067 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
2071 shrink_surface_params(const struct isl_device
*dev
,
2072 struct brw_blorp_surface_info
*info
,
2073 double *x0
, double *x1
, double *y0
, double *y1
)
2075 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
2076 struct isl_extent2d px_size_sa
;
2079 blorp_surf_convert_to_single_slice(dev
, info
);
2081 px_size_sa
= get_px_size_sa(&info
->surf
);
2083 /* Because this gets called after we lower compressed images, the tile
2084 * offsets may be non-zero and we need to incorporate them in our
2087 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
2088 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
2089 isl_tiling_get_intratile_offset_sa(info
->surf
.tiling
,
2090 info
->surf
.format
, info
->surf
.row_pitch
,
2091 x_offset_sa
, y_offset_sa
,
2093 &info
->tile_x_sa
, &info
->tile_y_sa
);
2095 info
->addr
.offset
+= byte_offset
;
2097 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
2100 info
->tile_x_sa
= 0;
2102 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
2105 info
->tile_y_sa
= 0;
2107 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
2108 info
->surf
.logical_level0_px
.width
= size
;
2109 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
2111 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
2112 info
->surf
.logical_level0_px
.height
= size
;
2113 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
2117 shrink_surfaces(const struct isl_device
*dev
,
2118 struct blorp_params
*params
,
2119 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2120 struct blt_coords
*coords
)
2122 /* Shrink source surface */
2123 shrink_surface_params(dev
, ¶ms
->src
, &coords
->x
.src0
, &coords
->x
.src1
,
2124 &coords
->y
.src0
, &coords
->y
.src1
);
2125 wm_prog_key
->need_src_offset
= false;
2127 /* Shrink destination surface */
2128 shrink_surface_params(dev
, ¶ms
->dst
, &coords
->x
.dst0
, &coords
->x
.dst1
,
2129 &coords
->y
.dst0
, &coords
->y
.dst1
);
2130 wm_prog_key
->need_dst_offset
= false;
2134 do_blorp_blit(struct blorp_batch
*batch
,
2135 const struct blorp_params
*orig_params
,
2136 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2137 const struct blt_coords
*orig
)
2139 struct blorp_params params
;
2140 struct blt_coords blit_coords
;
2141 struct blt_coords split_coords
= *orig
;
2142 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
2143 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
2144 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
2145 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
2151 bool x_done
, y_done
;
2152 bool shrink
= split_blorp_blit_debug
&& can_shrink_surfaces(orig_params
);
2154 params
= *orig_params
;
2155 blit_coords
= split_coords
;
2157 shrink_surfaces(batch
->blorp
->isl_dev
, ¶ms
, wm_prog_key
,
2159 enum blit_shrink_status result
=
2160 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
2162 if (result
& BLIT_WIDTH_SHRINK
) {
2165 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2166 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2168 if (result
& BLIT_HEIGHT_SHRINK
) {
2171 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2172 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2176 assert(can_shrink_surfaces(orig_params
));
2181 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
2182 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
2185 } else if (y_done
) {
2186 split_coords
.x
.dst0
+= w
;
2187 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2188 split_coords
.y
.dst0
= orig
->y
.dst0
;
2189 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2190 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2192 split_coords
.y
.dst0
+= h
;
2193 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2194 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2200 blorp_blit(struct blorp_batch
*batch
,
2201 const struct blorp_surf
*src_surf
,
2202 unsigned src_level
, unsigned src_layer
,
2203 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2204 const struct blorp_surf
*dst_surf
,
2205 unsigned dst_level
, unsigned dst_layer
,
2206 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2207 float src_x0
, float src_y0
,
2208 float src_x1
, float src_y1
,
2209 float dst_x0
, float dst_y0
,
2210 float dst_x1
, float dst_y1
,
2211 GLenum filter
, bool mirror_x
, bool mirror_y
)
2213 struct blorp_params params
;
2214 blorp_params_init(¶ms
);
2216 /* We cannot handle combined depth and stencil. */
2217 if (src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2218 assert(src_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2219 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2220 assert(dst_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2222 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
2223 assert(src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
);
2224 /* Prior to Broadwell, we can't render to R8_UINT */
2225 if (batch
->blorp
->isl_dev
->info
->gen
< 8) {
2226 src_format
= ISL_FORMAT_R8_UNORM
;
2227 dst_format
= ISL_FORMAT_R8_UNORM
;
2231 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2232 src_layer
, src_format
, false);
2233 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2234 dst_layer
, dst_format
, true);
2236 params
.src
.view
.swizzle
= src_swizzle
;
2237 params
.dst
.view
.swizzle
= dst_swizzle
;
2239 struct brw_blorp_blit_prog_key wm_prog_key
= {
2240 .shader_type
= BLORP_SHADER_TYPE_BLIT
2243 /* Scaled blitting or not. */
2244 wm_prog_key
.blit_scaled
=
2245 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2246 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2248 /* Scaling factors used for bilinear filtering in multisample scaled
2251 if (params
.src
.surf
.samples
== 16)
2252 wm_prog_key
.x_scale
= 4.0f
;
2254 wm_prog_key
.x_scale
= 2.0f
;
2255 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2257 if (filter
== GL_LINEAR
&&
2258 params
.src
.surf
.samples
<= 1 && params
.dst
.surf
.samples
<= 1) {
2259 wm_prog_key
.bilinear_filter
= true;
2262 if ((params
.src
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) == 0 &&
2263 (params
.src
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) == 0 &&
2264 !isl_format_has_int_channel(params
.src
.surf
.format
) &&
2265 params
.src
.surf
.samples
> 1 && params
.dst
.surf
.samples
<= 1) {
2266 /* We are downsampling a non-integer color buffer, so blend.
2268 * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
2270 * "If the source formats are integer types or stencil values, a
2271 * single sample's value is selected for each pixel."
2273 * This implies we should not blend in that case.
2275 wm_prog_key
.blend
= true;
2278 params
.wm_inputs
.rect_grid
.x1
=
2279 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2280 wm_prog_key
.x_scale
- 1.0f
;
2281 params
.wm_inputs
.rect_grid
.y1
=
2282 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2283 wm_prog_key
.y_scale
- 1.0f
;
2285 struct blt_coords coords
= {
2302 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2305 static enum isl_format
2306 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2308 /* The choice of UNORM and UINT formats is very intentional here. Most
2309 * of the time, we want to use a UINT format to avoid any rounding error
2310 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2311 * (It's the only format allowed in conjunction with W-tiling.) Also we
2312 * intentionally use the 4-channel formats whenever we can. This is so
2313 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2314 * even though one of them is 3/4 the size of the other. The choice of
2315 * UNORM vs. UINT is also very intentional because we don't have 8 or
2316 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2317 * Fortunately, the only time we should ever use two different formats in
2318 * the table below is for RGB -> RGBA blits and so we will never have any
2319 * UNORM/UINT mismatch.
2321 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2323 case 8: return ISL_FORMAT_R8_UINT
;
2324 case 16: return ISL_FORMAT_R8G8_UINT
;
2325 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2326 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2327 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2328 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2329 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2330 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2332 unreachable("Unknown format bpb");
2336 case 8: return ISL_FORMAT_R8_UINT
;
2337 case 16: return ISL_FORMAT_R8G8_UINT
;
2338 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2339 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2340 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2341 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2342 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2343 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2345 unreachable("Unknown format bpb");
2350 /** Returns a UINT format that is CCS-compatible with the given format
2352 * The PRM's say absolutely nothing about how render compression works. The
2353 * only thing they provide is a list of formats on which it is and is not
2354 * supported. Empirical testing indicates that the compression is only based
2355 * on the bit-layout of the format and the channel encoding doesn't matter.
2356 * So, while texture views don't work in general, you can create a view as
2357 * long as the bit-layout of the formats are the same.
2359 * Fortunately, for every render compression capable format, the UINT format
2360 * with the same bit layout also supports render compression. This means that
2361 * we only need to handle UINT formats for copy operations. In order to do
2362 * copies between formats with different bit layouts, we attach both with a
2363 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2364 * operation between the two bit layouts.
2366 static enum isl_format
2367 get_ccs_compatible_uint_format(const struct isl_format_layout
*fmtl
)
2369 switch (fmtl
->format
) {
2370 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2371 case ISL_FORMAT_R32G32B32A32_SINT
:
2372 case ISL_FORMAT_R32G32B32A32_UINT
:
2373 case ISL_FORMAT_R32G32B32A32_UNORM
:
2374 case ISL_FORMAT_R32G32B32A32_SNORM
:
2375 case ISL_FORMAT_R32G32B32X32_FLOAT
:
2376 return ISL_FORMAT_R32G32B32A32_UINT
;
2378 case ISL_FORMAT_R16G16B16A16_UNORM
:
2379 case ISL_FORMAT_R16G16B16A16_SNORM
:
2380 case ISL_FORMAT_R16G16B16A16_SINT
:
2381 case ISL_FORMAT_R16G16B16A16_UINT
:
2382 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2383 case ISL_FORMAT_R16G16B16X16_UNORM
:
2384 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2385 return ISL_FORMAT_R16G16B16A16_UINT
;
2387 case ISL_FORMAT_R32G32_FLOAT
:
2388 case ISL_FORMAT_R32G32_SINT
:
2389 case ISL_FORMAT_R32G32_UINT
:
2390 case ISL_FORMAT_R32G32_UNORM
:
2391 case ISL_FORMAT_R32G32_SNORM
:
2392 return ISL_FORMAT_R32G32_UINT
;
2394 case ISL_FORMAT_B8G8R8A8_UNORM
:
2395 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2396 case ISL_FORMAT_R8G8B8A8_UNORM
:
2397 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2398 case ISL_FORMAT_R8G8B8A8_SNORM
:
2399 case ISL_FORMAT_R8G8B8A8_SINT
:
2400 case ISL_FORMAT_R8G8B8A8_UINT
:
2401 case ISL_FORMAT_B8G8R8X8_UNORM
:
2402 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2403 case ISL_FORMAT_R8G8B8X8_UNORM
:
2404 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2405 return ISL_FORMAT_R8G8B8A8_UINT
;
2407 case ISL_FORMAT_R16G16_UNORM
:
2408 case ISL_FORMAT_R16G16_SNORM
:
2409 case ISL_FORMAT_R16G16_SINT
:
2410 case ISL_FORMAT_R16G16_UINT
:
2411 case ISL_FORMAT_R16G16_FLOAT
:
2412 return ISL_FORMAT_R16G16_UINT
;
2414 case ISL_FORMAT_R32_SINT
:
2415 case ISL_FORMAT_R32_UINT
:
2416 case ISL_FORMAT_R32_FLOAT
:
2417 case ISL_FORMAT_R32_UNORM
:
2418 case ISL_FORMAT_R32_SNORM
:
2419 return ISL_FORMAT_R32_UINT
;
2421 case ISL_FORMAT_B10G10R10A2_UNORM
:
2422 case ISL_FORMAT_B10G10R10A2_UNORM_SRGB
:
2423 case ISL_FORMAT_R10G10B10A2_UNORM
:
2424 case ISL_FORMAT_R10G10B10A2_UINT
:
2425 return ISL_FORMAT_R10G10B10A2_UINT
;
2428 unreachable("Not a compressible format");
2433 blorp_surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2434 struct brw_blorp_surface_info
*info
,
2435 uint32_t *x
, uint32_t *y
,
2436 uint32_t *width
, uint32_t *height
)
2438 const struct isl_format_layout
*fmtl
=
2439 isl_format_get_layout(info
->surf
.format
);
2441 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2443 /* This is a compressed surface. We need to convert it to a single
2444 * slice (because compressed layouts don't perfectly match uncompressed
2445 * ones with the same bpb) and divide x, y, width, and height by the
2448 blorp_surf_convert_to_single_slice(isl_dev
, info
);
2450 if (width
&& height
) {
2452 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2453 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2454 assert(*width
% fmtl
->bw
== 0 ||
2455 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2456 assert(*height
% fmtl
->bh
== 0 ||
2457 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2459 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2460 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2464 assert(*x
% fmtl
->bw
== 0);
2465 assert(*y
% fmtl
->bh
== 0);
2470 info
->surf
.logical_level0_px
.width
=
2471 DIV_ROUND_UP(info
->surf
.logical_level0_px
.width
, fmtl
->bw
);
2472 info
->surf
.logical_level0_px
.height
=
2473 DIV_ROUND_UP(info
->surf
.logical_level0_px
.height
, fmtl
->bh
);
2475 assert(info
->surf
.phys_level0_sa
.width
% fmtl
->bw
== 0);
2476 assert(info
->surf
.phys_level0_sa
.height
% fmtl
->bh
== 0);
2477 info
->surf
.phys_level0_sa
.width
/= fmtl
->bw
;
2478 info
->surf
.phys_level0_sa
.height
/= fmtl
->bh
;
2480 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2481 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2482 info
->tile_x_sa
/= fmtl
->bw
;
2483 info
->tile_y_sa
/= fmtl
->bh
;
2485 /* It's now an uncompressed surface so we need an uncompressed format */
2486 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2490 blorp_copy(struct blorp_batch
*batch
,
2491 const struct blorp_surf
*src_surf
,
2492 unsigned src_level
, unsigned src_layer
,
2493 const struct blorp_surf
*dst_surf
,
2494 unsigned dst_level
, unsigned dst_layer
,
2495 uint32_t src_x
, uint32_t src_y
,
2496 uint32_t dst_x
, uint32_t dst_y
,
2497 uint32_t src_width
, uint32_t src_height
)
2499 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2500 struct blorp_params params
;
2502 if (src_width
== 0 || src_height
== 0)
2505 blorp_params_init(¶ms
);
2506 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2507 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2508 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2509 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2511 struct brw_blorp_blit_prog_key wm_prog_key
= {
2512 .shader_type
= BLORP_SHADER_TYPE_BLIT
,
2513 .need_src_offset
= src_surf
->tile_x_sa
|| src_surf
->tile_y_sa
,
2514 .need_dst_offset
= dst_surf
->tile_x_sa
|| dst_surf
->tile_y_sa
,
2517 const struct isl_format_layout
*src_fmtl
=
2518 isl_format_get_layout(params
.src
.surf
.format
);
2519 const struct isl_format_layout
*dst_fmtl
=
2520 isl_format_get_layout(params
.dst
.surf
.format
);
2522 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2523 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2524 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2525 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
||
2526 params
.dst
.aux_usage
== ISL_AUX_USAGE_MCS
||
2527 params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2529 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2530 params
.dst
.view
.format
= get_ccs_compatible_uint_format(dst_fmtl
);
2531 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2532 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2533 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2534 params
.src
.view
.format
= params
.dst
.view
.format
;
2536 params
.src
.view
.format
=
2537 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2539 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2540 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2541 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2542 params
.dst
.view
.format
= params
.src
.view
.format
;
2544 params
.dst
.view
.format
=
2545 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2548 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2549 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2552 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2553 /* It's safe to do a blorp_copy between things which are sRGB with CCS_E
2554 * enabled even though CCS_E doesn't technically do sRGB on SKL because
2555 * we stomp everything to UINT anyway. The one thing we have to be
2556 * careful of is clear colors. Because fast clear colors for sRGB on
2557 * gen9 are encoded as the float values between format conversion and
2558 * sRGB curve application, a given clear color float will convert to the
2559 * same bits regardless of whether the format is UNORM or sRGB.
2560 * Therefore, we can handle sRGB without any special cases.
2562 UNUSED
enum isl_format linear_src_format
=
2563 isl_format_srgb_to_linear(src_surf
->surf
->format
);
2564 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2566 params
.src
.view
.format
));
2568 isl_color_value_pack(¶ms
.src
.clear_color
,
2569 linear_src_format
, packed
);
2570 isl_color_value_unpack(¶ms
.src
.clear_color
,
2571 params
.src
.view
.format
, packed
);
2574 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2575 /* See above where we handle linear_src_format */
2576 UNUSED
enum isl_format linear_dst_format
=
2577 isl_format_srgb_to_linear(dst_surf
->surf
->format
);
2578 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2580 params
.dst
.view
.format
));
2582 isl_color_value_pack(¶ms
.dst
.clear_color
,
2583 linear_dst_format
, packed
);
2584 isl_color_value_unpack(¶ms
.dst
.clear_color
,
2585 params
.dst
.view
.format
, packed
);
2588 if (params
.src
.view
.format
!= params
.dst
.view
.format
) {
2589 enum isl_format src_cast_format
= params
.src
.view
.format
;
2590 enum isl_format dst_cast_format
= params
.dst
.view
.format
;
2592 /* The BLORP bitcast code gets confused by RGB formats. Just treat them
2593 * as RGBA and then everything will be happy. This is perfectly safe
2594 * because BLORP likes to treat things as if they have vec4 colors all
2597 if (isl_format_is_rgb(src_cast_format
))
2598 src_cast_format
= isl_format_rgb_to_rgba(src_cast_format
);
2599 if (isl_format_is_rgb(dst_cast_format
))
2600 dst_cast_format
= isl_format_rgb_to_rgba(dst_cast_format
);
2602 if (src_cast_format
!= dst_cast_format
) {
2603 wm_prog_key
.format_bit_cast
= true;
2604 wm_prog_key
.src_format
= src_cast_format
;
2605 wm_prog_key
.dst_format
= dst_cast_format
;
2609 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2610 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2612 &src_width
, &src_height
);
2613 wm_prog_key
.need_src_offset
= true;
2616 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2617 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2618 &dst_x
, &dst_y
, NULL
, NULL
);
2619 wm_prog_key
.need_dst_offset
= true;
2622 /* Once both surfaces are stompped to uncompressed as needed, the
2623 * destination size is the same as the source size.
2625 uint32_t dst_width
= src_width
;
2626 uint32_t dst_height
= src_height
;
2628 struct blt_coords coords
= {
2631 .src1
= src_x
+ src_width
,
2633 .dst1
= dst_x
+ dst_width
,
2638 .src1
= src_y
+ src_height
,
2640 .dst1
= dst_y
+ dst_height
,
2645 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2648 static enum isl_format
2649 isl_format_for_size(unsigned size_B
)
2652 case 1: return ISL_FORMAT_R8_UINT
;
2653 case 2: return ISL_FORMAT_R8G8_UINT
;
2654 case 4: return ISL_FORMAT_R8G8B8A8_UINT
;
2655 case 8: return ISL_FORMAT_R16G16B16A16_UINT
;
2656 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
2658 unreachable("Not a power-of-two format size");
2663 * Returns the greatest common divisor of a and b that is a power of two.
2666 gcd_pow2_u64(uint64_t a
, uint64_t b
)
2668 assert(a
> 0 || b
> 0);
2670 unsigned a_log2
= ffsll(a
) - 1;
2671 unsigned b_log2
= ffsll(b
) - 1;
2673 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
2674 * case, the MIN2() will take the other one. If both are 0 then we will
2675 * hit the assert above.
2677 return 1 << MIN2(a_log2
, b_log2
);
2681 do_buffer_copy(struct blorp_batch
*batch
,
2682 struct blorp_address
*src
,
2683 struct blorp_address
*dst
,
2684 int width
, int height
, int block_size
)
2686 /* The actual format we pick doesn't matter as blorp will throw it away.
2687 * The only thing that actually matters is the size.
2689 enum isl_format format
= isl_format_for_size(block_size
);
2692 struct isl_surf surf
;
2693 ok
= isl_surf_init(batch
->blorp
->isl_dev
, &surf
,
2694 .dim
= ISL_SURF_DIM_2D
,
2702 .row_pitch
= width
* block_size
,
2703 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
2704 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
2705 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
2708 struct blorp_surf src_blorp_surf
= {
2713 struct blorp_surf dst_blorp_surf
= {
2718 blorp_copy(batch
, &src_blorp_surf
, 0, 0, &dst_blorp_surf
, 0, 0,
2719 0, 0, 0, 0, width
, height
);
2723 blorp_buffer_copy(struct blorp_batch
*batch
,
2724 struct blorp_address src
,
2725 struct blorp_address dst
,
2728 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
2729 uint64_t copy_size
= size
;
2731 /* This is maximum possible width/height our HW can handle */
2732 uint64_t max_surface_dim
= 1 << (devinfo
->gen
>= 7 ? 14 : 13);
2734 /* First, we compute the biggest format that can be used with the
2735 * given offsets and size.
2738 bs
= gcd_pow2_u64(bs
, src
.offset
);
2739 bs
= gcd_pow2_u64(bs
, dst
.offset
);
2740 bs
= gcd_pow2_u64(bs
, size
);
2742 /* First, we make a bunch of max-sized copies */
2743 uint64_t max_copy_size
= max_surface_dim
* max_surface_dim
* bs
;
2744 while (copy_size
>= max_copy_size
) {
2745 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, max_surface_dim
, bs
);
2746 copy_size
-= max_copy_size
;
2747 src
.offset
+= max_copy_size
;
2748 dst
.offset
+= max_copy_size
;
2751 /* Now make a max-width copy */
2752 uint64_t height
= copy_size
/ (max_surface_dim
* bs
);
2753 assert(height
< max_surface_dim
);
2755 uint64_t rect_copy_size
= height
* max_surface_dim
* bs
;
2756 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, height
, bs
);
2757 copy_size
-= rect_copy_size
;
2758 src
.offset
+= rect_copy_size
;
2759 dst
.offset
+= rect_copy_size
;
2762 /* Finally, make a small copy to finish it off */
2763 if (copy_size
!= 0) {
2764 do_buffer_copy(batch
, &src
, &dst
, copy_size
/ bs
, 1, bs
);