2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "blorp_nir_builder.h"
26 #include "blorp_priv.h"
28 /* header-only include needed for _mesa_unorm_to_float and friends. */
29 #include "mesa/main/format_utils.h"
31 #define FILE_DEBUG_FLAG DEBUG_BLORP
33 static const bool split_blorp_blit_debug
= false;
36 * Enum to specify the order of arguments in a sampler message
38 enum sampler_message_arg
40 SAMPLER_MESSAGE_ARG_U_FLOAT
,
41 SAMPLER_MESSAGE_ARG_V_FLOAT
,
42 SAMPLER_MESSAGE_ARG_U_INT
,
43 SAMPLER_MESSAGE_ARG_V_INT
,
44 SAMPLER_MESSAGE_ARG_R_INT
,
45 SAMPLER_MESSAGE_ARG_SI_INT
,
46 SAMPLER_MESSAGE_ARG_MCS_INT
,
47 SAMPLER_MESSAGE_ARG_ZERO_INT
,
50 struct brw_blorp_blit_vars
{
51 /* Input values from brw_blorp_wm_inputs */
52 nir_variable
*v_discard_rect
;
53 nir_variable
*v_rect_grid
;
54 nir_variable
*v_coord_transform
;
55 nir_variable
*v_src_z
;
56 nir_variable
*v_src_offset
;
57 nir_variable
*v_dst_offset
;
58 nir_variable
*v_src_inv_size
;
61 nir_variable
*frag_coord
;
64 nir_variable
*color_out
;
68 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
69 const struct brw_blorp_blit_prog_key
*key
)
71 /* Blended and scaled blits never use pixel discard. */
72 assert(!key
->use_kill
|| !(key
->blend
&& key
->blit_scaled
));
74 #define LOAD_INPUT(name, type)\
75 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
77 LOAD_INPUT(discard_rect
, glsl_vec4_type())
78 LOAD_INPUT(rect_grid
, glsl_vec4_type())
79 LOAD_INPUT(coord_transform
, glsl_vec4_type())
80 LOAD_INPUT(src_z
, glsl_uint_type())
81 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
82 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
83 LOAD_INPUT(src_inv_size
, glsl_vector_type(GLSL_TYPE_FLOAT
, 2))
87 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
88 glsl_vec4_type(), "gl_FragCoord");
89 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
90 v
->frag_coord
->data
.origin_upper_left
= true;
92 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
93 glsl_vec4_type(), "gl_FragColor");
94 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
98 blorp_blit_get_frag_coords(nir_builder
*b
,
99 const struct brw_blorp_blit_prog_key
*key
,
100 struct brw_blorp_blit_vars
*v
)
102 nir_ssa_def
*coord
= nir_f2i32(b
, nir_load_var(b
, v
->frag_coord
));
104 /* Account for destination surface intratile offset
106 * Transformation parameters giving translation from destination to source
107 * coordinates don't take into account possible intra-tile destination
108 * offset. Therefore it has to be first subtracted from the incoming
109 * coordinates. Vertices are set up based on coordinates containing the
112 if (key
->need_dst_offset
)
113 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
115 if (key
->persample_msaa_dispatch
) {
116 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
117 nir_load_sample_id(b
));
119 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
124 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
128 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
129 struct brw_blorp_blit_vars
*v
)
131 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
133 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
134 nir_channel(b
, coord_transform
, 3));
135 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
136 nir_channel(b
, coord_transform
, 2));
138 return nir_fadd(b
, nir_fmul(b
, src_pos
, mul
), offset
);
142 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
143 struct brw_blorp_blit_vars
*v
)
145 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
146 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
147 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
148 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
149 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
150 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
152 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
153 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
154 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
155 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
157 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
159 nir_intrinsic_instr
*discard
=
160 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
161 discard
->src
[0] = nir_src_for_ssa(oob
);
162 nir_builder_instr_insert(b
, &discard
->instr
);
165 static nir_tex_instr
*
166 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
167 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
168 nir_alu_type dst_type
)
170 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
174 tex
->dest_type
= dst_type
;
175 tex
->is_array
= false;
176 tex
->is_shadow
= false;
178 /* Blorp only has one texture and it's bound at unit 0 */
181 tex
->texture_index
= 0;
182 tex
->sampler_index
= 0;
184 /* To properly handle 3-D and 2-D array textures, we pull the Z component
185 * from an input. TODO: This is a bit magic; we should probably make this
186 * more explicit in the future.
188 assert(pos
->num_components
>= 2);
189 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
190 nir_load_var(b
, v
->v_src_z
));
192 tex
->src
[0].src_type
= nir_tex_src_coord
;
193 tex
->src
[0].src
= nir_src_for_ssa(pos
);
194 tex
->coord_components
= 3;
196 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
202 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
203 const struct brw_blorp_blit_prog_key
*key
, nir_ssa_def
*pos
)
205 if (key
->need_src_offset
)
206 pos
= nir_fadd(b
, pos
, nir_i2f32(b
, nir_load_var(b
, v
->v_src_offset
)));
208 /* If the sampler requires normalized coordinates, we need to compensate. */
209 if (key
->src_coords_normalized
)
210 pos
= nir_fmul(b
, pos
, nir_load_var(b
, v
->v_src_inv_size
));
213 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2,
214 key
->texture_data_type
);
216 assert(pos
->num_components
== 2);
217 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
218 tex
->src
[1].src_type
= nir_tex_src_lod
;
219 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
221 nir_builder_instr_insert(b
, &tex
->instr
);
223 return &tex
->dest
.ssa
;
227 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
228 nir_ssa_def
*pos
, nir_alu_type dst_type
)
231 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
233 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
234 tex
->src
[1].src_type
= nir_tex_src_lod
;
235 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
237 nir_builder_instr_insert(b
, &tex
->instr
);
239 return &tex
->dest
.ssa
;
243 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
244 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
247 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
248 mcs
!= NULL
? 3 : 2, dst_type
);
250 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
252 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
253 if (pos
->num_components
== 2) {
254 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
256 assert(pos
->num_components
== 3);
257 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
261 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
262 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
265 nir_builder_instr_insert(b
, &tex
->instr
);
267 return &tex
->dest
.ssa
;
271 blorp_blit_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
275 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
276 pos
, 1, nir_type_int
);
278 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
280 nir_builder_instr_insert(b
, &tex
->instr
);
282 return &tex
->dest
.ssa
;
286 nir_mask_shift_or(struct nir_builder
*b
, nir_ssa_def
*dst
, nir_ssa_def
*src
,
287 uint32_t src_mask
, int src_left_shift
)
289 nir_ssa_def
*masked
= nir_iand(b
, src
, nir_imm_int(b
, src_mask
));
291 nir_ssa_def
*shifted
;
292 if (src_left_shift
> 0) {
293 shifted
= nir_ishl(b
, masked
, nir_imm_int(b
, src_left_shift
));
294 } else if (src_left_shift
< 0) {
295 shifted
= nir_ushr(b
, masked
, nir_imm_int(b
, -src_left_shift
));
297 assert(src_left_shift
== 0);
301 return nir_ior(b
, dst
, shifted
);
305 * Emit code to compensate for the difference between Y and W tiling.
307 * This code modifies the X and Y coordinates according to the formula:
309 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
311 * (See brw_blorp_build_nir_shader).
313 static inline nir_ssa_def
*
314 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
316 assert(pos
->num_components
== 2);
317 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
318 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
320 /* Given X and Y coordinates that describe an address using Y tiling,
321 * translate to the X and Y coordinates that describe the same address
324 * If we break down the low order bits of X and Y, using a
325 * single letter to represent each low-order bit:
327 * X = A << 7 | 0bBCDEFGH
328 * Y = J << 5 | 0bKLMNP (1)
330 * Then we can apply the Y tiling formula to see the memory offset being
333 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
335 * If we apply the W detiling formula to this memory location, that the
336 * corresponding X' and Y' coordinates are:
338 * X' = A << 6 | 0bBCDPFH (3)
339 * Y' = J << 6 | 0bKLMNEG
341 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
342 * we need to make the following computation:
344 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
345 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
347 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
348 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
349 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
350 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
352 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
353 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
354 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
355 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
357 return nir_vec2(b
, x_W
, y_W
);
361 * Emit code to compensate for the difference between Y and W tiling.
363 * This code modifies the X and Y coordinates according to the formula:
365 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
367 * (See brw_blorp_build_nir_shader).
369 static inline nir_ssa_def
*
370 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
372 assert(pos
->num_components
== 2);
373 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
374 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
376 /* Applying the same logic as above, but in reverse, we obtain the
379 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
380 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
382 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
383 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
384 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
385 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
386 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
388 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
389 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
390 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
392 return nir_vec2(b
, x_Y
, y_Y
);
396 * Emit code to compensate for the difference between MSAA and non-MSAA
399 * This code modifies the X and Y coordinates according to the formula:
401 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
403 * (See brw_blorp_blit_program).
405 static inline nir_ssa_def
*
406 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
407 unsigned num_samples
, enum isl_msaa_layout layout
)
409 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
412 case ISL_MSAA_LAYOUT_NONE
:
413 assert(pos
->num_components
== 2);
415 case ISL_MSAA_LAYOUT_ARRAY
:
416 /* No translation needed */
418 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
419 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
420 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
421 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
422 nir_channel(b
, pos
, 2);
424 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
425 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
426 switch (num_samples
) {
429 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
430 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
433 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
434 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
435 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
437 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
438 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
439 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
440 if (num_samples
== 2) {
443 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
444 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
445 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
450 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
451 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
453 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
455 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
456 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
457 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
458 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
459 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
460 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
461 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
465 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
466 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
468 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
471 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
472 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
473 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
474 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
475 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
476 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
477 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
478 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
482 unreachable("Invalid number of samples for IMS layout");
485 return nir_vec2(b
, x_out
, y_out
);
489 unreachable("Invalid MSAA layout");
494 * Emit code to compensate for the difference between MSAA and non-MSAA
497 * This code modifies the X and Y coordinates according to the formula:
499 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
501 * (See brw_blorp_blit_program).
503 static inline nir_ssa_def
*
504 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
505 unsigned num_samples
, enum isl_msaa_layout layout
)
507 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
510 case ISL_MSAA_LAYOUT_NONE
:
511 /* No translation necessary, and S should already be zero. */
512 assert(pos
->num_components
== 2);
514 case ISL_MSAA_LAYOUT_ARRAY
:
515 /* No translation necessary. */
517 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
518 assert(pos
->num_components
== 2);
520 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
521 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
523 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
524 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
525 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
526 switch (num_samples
) {
529 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
530 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
531 * S = (X & 0b10) >> 1
533 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
534 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
535 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
536 * S = (Y & 0b10) | (X & 0b10) >> 1
538 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
539 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
540 if (num_samples
== 2) {
542 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
544 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
545 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
546 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
547 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
552 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
553 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
554 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
555 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
557 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
558 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
559 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
560 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
561 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
562 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
563 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
567 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
568 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
569 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
570 * S = (Y & 0b100) << 1 | (X & 0b100) |
571 * (Y & 0b10) | (X & 0b10) >> 1
573 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
574 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
575 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
576 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
577 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
578 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
579 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
580 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
584 unreachable("Invalid number of samples for IMS layout");
587 return nir_vec3(b
, x_out
, y_out
, s_out
);
591 unreachable("Invalid MSAA layout");
596 * Count the number of trailing 1 bits in the given value. For example:
598 * count_trailing_one_bits(0) == 0
599 * count_trailing_one_bits(7) == 3
600 * count_trailing_one_bits(11) == 2
602 static inline int count_trailing_one_bits(unsigned value
)
604 #ifdef HAVE___BUILTIN_CTZ
605 return __builtin_ctz(~value
);
607 return _mesa_bitcount(value
& ~(value
+ 1));
612 blorp_nir_manual_blend_average(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
613 nir_ssa_def
*pos
, unsigned tex_samples
,
614 enum isl_aux_usage tex_aux_usage
,
615 nir_alu_type dst_type
)
617 /* If non-null, this is the outer-most if statement */
618 nir_if
*outer_if
= NULL
;
620 nir_variable
*color
=
621 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
623 nir_ssa_def
*mcs
= NULL
;
624 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
625 mcs
= blorp_blit_txf_ms_mcs(b
, v
, pos
);
627 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
629 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
631 * This ensures that when all samples have the same value, no numerical
632 * precision is lost, since each addition operation always adds two equal
633 * values, and summing two equal floating point values does not lose
636 * We perform this computation by treating the texture_data array as a
637 * stack and performing the following operations:
639 * - push sample 0 onto stack
640 * - push sample 1 onto stack
641 * - add top two stack entries
642 * - push sample 2 onto stack
643 * - push sample 3 onto stack
644 * - add top two stack entries
645 * - add top two stack entries
646 * - divide top stack entry by 4
648 * Note that after pushing sample i onto the stack, the number of add
649 * operations we do is equal to the number of trailing 1 bits in i. This
650 * works provided the total number of samples is a power of two, which it
651 * always is for i965.
653 * For integer formats, we replace the add operations with average
654 * operations and skip the final division.
656 nir_ssa_def
*texture_data
[5];
657 unsigned stack_depth
= 0;
658 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
659 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
661 /* Push sample i onto the stack */
662 assert(stack_depth
< ARRAY_SIZE(texture_data
));
664 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
665 nir_channel(b
, pos
, 1),
667 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
669 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
670 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
671 * suggests an optimization:
673 * "A simple optimization with probable large return in
674 * performance is to compare the MCS value to zero (indicating
675 * all samples are on sample slice 0), and sample only from
676 * sample slice 0 using ld2dss if MCS is zero."
678 * Note that in the case where the MCS value is zero, sampling from
679 * sample slice 0 using ld2dss and sampling from sample 0 using
680 * ld2dms are equivalent (since all samples are on sample slice 0).
681 * Since we have already sampled from sample 0, all we need to do is
682 * skip the remaining fetches and averaging if MCS is zero.
684 * It's also trivial to detect when the MCS has the magic clear color
685 * value. In this case, the txf we did on sample 0 will return the
686 * clear color and we can skip the remaining fetches just like we do
689 nir_ssa_def
*mcs_zero
=
690 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
691 if (tex_samples
== 16) {
692 mcs_zero
= nir_iand(b
, mcs_zero
,
693 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
695 nir_ssa_def
*mcs_clear
=
696 blorp_nir_mcs_is_clear_color(b
, mcs
, tex_samples
);
698 nir_if
*if_stmt
= nir_if_create(b
->shader
);
699 if_stmt
->condition
= nir_src_for_ssa(nir_ior(b
, mcs_zero
, mcs_clear
));
700 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
702 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
703 nir_store_var(b
, color
, texture_data
[0], 0xf);
705 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
709 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
710 assert(stack_depth
>= 2);
713 assert(dst_type
== nir_type_float
);
714 texture_data
[stack_depth
- 1] =
715 nir_fadd(b
, texture_data
[stack_depth
- 1],
716 texture_data
[stack_depth
]);
720 /* We should have just 1 sample on the stack now. */
721 assert(stack_depth
== 1);
723 texture_data
[0] = nir_fmul(b
, texture_data
[0],
724 nir_imm_float(b
, 1.0 / tex_samples
));
726 nir_store_var(b
, color
, texture_data
[0], 0xf);
729 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
731 return nir_load_var(b
, color
);
734 static inline nir_ssa_def
*
735 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
739 memset(&v
, 0, sizeof(v
));
743 return nir_build_imm(build
, 4, 32, v
);
747 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
748 unsigned tex_samples
,
749 const struct brw_blorp_blit_prog_key
*key
,
750 struct brw_blorp_blit_vars
*v
)
752 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
753 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
754 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
756 /* Translate coordinates to lay out the samples in a rectangular grid
757 * roughly corresponding to sample locations.
759 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
760 /* Adjust coordinates so that integers represent pixel centers rather
763 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
764 /* Clamp the X, Y texture coordinates to properly handle the sampling of
765 * texels on texture edges.
767 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
768 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
769 nir_channel(b
, rect_grid
, 1)));
771 /* Store the fractional parts to be used as bilinear interpolation
774 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
775 /* Round the float coordinates down to nearest integer */
776 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
778 nir_ssa_def
*tex_data
[4];
779 for (unsigned i
= 0; i
< 4; ++i
) {
780 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
781 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
782 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
784 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
785 nir_ssa_def
*sample_coords_int
= nir_f2i32(b
, sample_coords
);
787 /* The MCS value we fetch has to match up with the pixel that we're
788 * sampling from. Since we sample from different pixels in each
789 * iteration of this "for" loop, the call to mcs_fetch() should be
790 * here inside the loop after computing the pixel coordinates.
792 nir_ssa_def
*mcs
= NULL
;
793 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
794 mcs
= blorp_blit_txf_ms_mcs(b
, v
, sample_coords_int
);
796 /* Compute sample index and map the sample index to a sample number.
797 * Sample index layout shows the numbering of slots in a rectangular
798 * grid of samples with in a pixel. Sample number layout shows the
799 * rectangular grid of samples roughly corresponding to the real sample
800 * locations with in a pixel.
801 * In case of 4x MSAA, layout of sample indices matches the layout of
809 * In case of 8x MSAA the two layouts don't match.
810 * sample index layout : --------- sample number layout : ---------
811 * | 0 | 1 | | 3 | 7 |
812 * --------- ---------
813 * | 2 | 3 | | 5 | 0 |
814 * --------- ---------
815 * | 4 | 5 | | 1 | 2 |
816 * --------- ---------
817 * | 6 | 7 | | 4 | 6 |
818 * --------- ---------
820 * Fortunately, this can be done fairly easily as:
821 * S' = (0x17306425 >> (S * 4)) & 0xf
823 * In the case of 16x MSAA the two layouts don't match.
824 * Sample index layout: Sample number layout:
825 * --------------------- ---------------------
826 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
827 * --------------------- ---------------------
828 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
829 * --------------------- ---------------------
830 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
831 * --------------------- ---------------------
832 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
833 * --------------------- ---------------------
835 * This is equivalent to
836 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
838 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
839 nir_ssa_def
*sample
=
840 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
841 key
->x_scale
* key
->y_scale
));
842 sample
= nir_f2i32(b
, sample
);
844 if (tex_samples
== 8) {
845 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
846 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
847 nir_imm_int(b
, 0xf));
848 } else if (tex_samples
== 16) {
849 nir_ssa_def
*sample_low
=
850 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
851 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
852 nir_imm_int(b
, 0xf));
853 nir_ssa_def
*sample_high
=
854 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
855 nir_ishl(b
, nir_iadd(b
, sample
,
858 nir_imm_int(b
, 0xf));
860 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
861 sample_low
, sample_high
);
863 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
864 nir_channel(b
, sample_coords_int
, 1),
866 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
869 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
870 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
871 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
872 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
876 /** Perform a color bit-cast operation
878 * For copy operations involving CCS, we may need to use different formats for
879 * the source and destination surfaces. The two formats must both be UINT
880 * formats and must have the same size but may have different bit layouts.
881 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
882 * to R16G16_UINT. This function generates code to shuffle bits around to get
883 * us from one to the other.
886 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
887 const struct brw_blorp_blit_prog_key
*key
)
889 assert(key
->texture_data_type
== nir_type_uint
);
891 if (key
->dst_bpc
> key
->src_bpc
) {
892 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
893 nir_ssa_def
*dst_chan
[2] = { u
, u
};
895 unsigned dst_idx
= 0;
896 for (unsigned i
= 0; i
< 4; i
++) {
897 nir_ssa_def
*shifted
= nir_ishl(b
, nir_channel(b
, color
, i
),
898 nir_imm_int(b
, shift
));
900 dst_chan
[dst_idx
] = shifted
;
902 dst_chan
[dst_idx
] = nir_ior(b
, dst_chan
[dst_idx
], shifted
);
905 shift
+= key
->src_bpc
;
906 if (shift
>= key
->dst_bpc
) {
912 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], u
, u
);
914 assert(key
->dst_bpc
< key
->src_bpc
);
916 nir_ssa_def
*mask
= nir_imm_int(b
, ~0u >> (32 - key
->dst_bpc
));
918 nir_ssa_def
*dst_chan
[4];
919 unsigned src_idx
= 0;
921 for (unsigned i
= 0; i
< 4; i
++) {
922 dst_chan
[i
] = nir_iand(b
, nir_ushr(b
, nir_channel(b
, color
, src_idx
),
923 nir_imm_int(b
, shift
)),
925 shift
+= key
->dst_bpc
;
926 if (shift
>= key
->src_bpc
) {
932 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], dst_chan
[2], dst_chan
[3]);
937 select_color_channel(struct nir_builder
*b
, nir_ssa_def
*color
,
938 nir_alu_type data_type
,
939 enum isl_channel_select chan
)
941 if (chan
== ISL_CHANNEL_SELECT_ZERO
) {
942 return nir_imm_int(b
, 0);
943 } else if (chan
== ISL_CHANNEL_SELECT_ONE
) {
947 return nir_imm_int(b
, 1);
949 return nir_imm_float(b
, 1);
951 unreachable("Invalid data type");
954 assert((unsigned)(chan
- ISL_CHANNEL_SELECT_RED
) < 4);
955 return nir_channel(b
, color
, chan
- ISL_CHANNEL_SELECT_RED
);
960 swizzle_color(struct nir_builder
*b
, nir_ssa_def
*color
,
961 struct isl_swizzle swizzle
, nir_alu_type data_type
)
964 select_color_channel(b
, color
, data_type
, swizzle
.r
),
965 select_color_channel(b
, color
, data_type
, swizzle
.g
),
966 select_color_channel(b
, color
, data_type
, swizzle
.b
),
967 select_color_channel(b
, color
, data_type
, swizzle
.a
));
971 * Generator for WM programs used in BLORP blits.
973 * The bulk of the work done by the WM program is to wrap and unwrap the
974 * coordinate transformations used by the hardware to store surfaces in
975 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
976 * sample index for a multisampled surface) to a memory offset by the
977 * following formulas:
979 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
980 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
982 * For a single-sampled surface, or for a multisampled surface using
983 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
986 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
987 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
988 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
989 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
991 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
992 * embeds the sample number into bit 1 of the X and Y coordinates:
994 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
995 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
996 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
997 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
998 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
999 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1000 * S = (Y & 0b10) | (X & 0b10) >> 1
1002 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
1003 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
1006 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1007 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
1008 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1009 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1010 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1011 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1012 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1014 * For X tiling, tile() combines together the low-order bits of the X and Y
1015 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
1016 * bytes wide and 8 rows high:
1018 * tile(x_tiled, X, Y, S) = A
1019 * where A = tile_num << 12 | offset
1020 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
1021 * offset = (Y' & 0b111) << 9
1022 * | (X & 0b111111111)
1024 * Y' = Y + S * qpitch
1025 * detile(x_tiled, A) = (X, Y, S)
1026 * where X = X' / cpp
1029 * Y' = (tile_num / tile_pitch) << 3
1030 * | (A & 0b111000000000) >> 9
1031 * X' = (tile_num % tile_pitch) << 9
1032 * | (A & 0b111111111)
1034 * (In all tiling formulas, cpp is the number of bytes occupied by a single
1035 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
1036 * to fill the width of the surface, and qpitch is the spacing (in rows)
1037 * between array slices).
1039 * For Y tiling, tile() combines together the low-order bits of the X and Y
1040 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
1041 * bytes wide and 32 rows high:
1043 * tile(y_tiled, X, Y, S) = A
1044 * where A = tile_num << 12 | offset
1045 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
1046 * offset = (X' & 0b1110000) << 5
1047 * | (Y' & 0b11111) << 4
1050 * Y' = Y + S * qpitch
1051 * detile(y_tiled, A) = (X, Y, S)
1052 * where X = X' / cpp
1055 * Y' = (tile_num / tile_pitch) << 5
1056 * | (A & 0b111110000) >> 4
1057 * X' = (tile_num % tile_pitch) << 7
1058 * | (A & 0b111000000000) >> 5
1061 * For W tiling, tile() combines together the low-order bits of the X and Y
1062 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1063 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1064 * buffers, which always have cpp = 1 and S=0):
1066 * tile(w_tiled, X, Y, S) = A
1067 * where A = tile_num << 12 | offset
1068 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1069 * offset = (X' & 0b111000) << 6
1070 * | (Y' & 0b111100) << 3
1071 * | (X' & 0b100) << 2
1072 * | (Y' & 0b10) << 2
1073 * | (X' & 0b10) << 1
1077 * Y' = Y + S * qpitch
1078 * detile(w_tiled, A) = (X, Y, S)
1079 * where X = X' / cpp = X'
1080 * Y = Y' % qpitch = Y'
1081 * S = Y / qpitch = 0
1082 * Y' = (tile_num / tile_pitch) << 6
1083 * | (A & 0b111100000) >> 3
1084 * | (A & 0b1000) >> 2
1086 * X' = (tile_num % tile_pitch) << 6
1087 * | (A & 0b111000000000) >> 6
1088 * | (A & 0b10000) >> 2
1089 * | (A & 0b100) >> 1
1092 * Finally, for a non-tiled surface, tile() simply combines together the X and
1093 * Y coordinates in the natural way:
1095 * tile(untiled, X, Y, S) = A
1096 * where A = Y * pitch + X'
1098 * Y' = Y + S * qpitch
1099 * detile(untiled, A) = (X, Y, S)
1100 * where X = X' / cpp
1106 * (In these formulas, pitch is the number of bytes occupied by a single row
1110 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1111 const struct brw_blorp_blit_prog_key
*key
)
1113 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1114 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1117 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1118 /* If the destination image is W tiled and multisampled, then the thread
1119 * must be dispatched once per sample, not once per pixel. This is
1120 * necessary because after conversion between W and Y tiling, there's no
1121 * guarantee that all samples corresponding to a single pixel will still
1124 assert(key
->persample_msaa_dispatch
);
1128 /* We are blending, which means we won't have an opportunity to
1129 * translate the tiling and sample count for the texture surface. So
1130 * the surface state for the texture must be configured with the correct
1131 * tiling and sample count.
1133 assert(!key
->src_tiled_w
);
1134 assert(key
->tex_samples
== key
->src_samples
);
1135 assert(key
->tex_layout
== key
->src_layout
);
1136 assert(key
->tex_samples
> 0);
1139 if (key
->persample_msaa_dispatch
) {
1140 /* It only makes sense to do persample dispatch if the render target is
1141 * configured as multisampled.
1143 assert(key
->rt_samples
> 0);
1146 /* Make sure layout is consistent with sample count */
1147 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1148 (key
->tex_samples
<= 1));
1149 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1150 (key
->rt_samples
<= 1));
1151 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1152 (key
->src_samples
<= 1));
1153 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1154 (key
->dst_samples
<= 1));
1157 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1159 struct brw_blorp_blit_vars v
;
1160 brw_blorp_blit_vars_init(&b
, &v
, key
);
1162 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1164 /* Render target and texture hardware don't support W tiling until Gen8. */
1165 const bool rt_tiled_w
= false;
1166 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1168 /* The address that data will be written to is determined by the
1169 * coordinates supplied to the WM thread and the tiling and sample count of
1170 * the render target, according to the formula:
1172 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1174 * If the actual tiling and sample count of the destination surface are not
1175 * the same as the configuration of the render target, then these
1176 * coordinates are wrong and we have to adjust them to compensate for the
1179 if (rt_tiled_w
!= key
->dst_tiled_w
||
1180 key
->rt_samples
!= key
->dst_samples
||
1181 key
->rt_layout
!= key
->dst_layout
) {
1182 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1184 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1185 if (rt_tiled_w
!= key
->dst_tiled_w
)
1186 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1187 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1188 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1192 nir_ssa_def
*comp
= NULL
;
1194 /* The destination image is bound as a red texture three times as wide
1195 * as the actual image. Our shader is effectively running one color
1196 * component at a time. We need to save off the component and adjust
1197 * the destination position.
1199 assert(dst_pos
->num_components
== 2);
1200 nir_ssa_def
*dst_x
= nir_channel(&b
, dst_pos
, 0);
1201 comp
= nir_umod(&b
, dst_x
, nir_imm_int(&b
, 3));
1202 dst_pos
= nir_vec2(&b
, nir_idiv(&b
, dst_x
, nir_imm_int(&b
, 3)),
1203 nir_channel(&b
, dst_pos
, 1));
1206 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1208 * That is: X, Y and S now contain the true coordinates and sample index of
1209 * the data that the WM thread should output.
1211 * If we need to kill pixels that are outside the destination rectangle,
1212 * now is the time to do it.
1214 if (key
->use_kill
) {
1215 assert(!(key
->blend
&& key
->blit_scaled
));
1216 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1219 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f32(&b
, dst_pos
), &v
);
1220 if (dst_pos
->num_components
== 3) {
1221 /* The sample coordinate is an integer that we want left alone but
1222 * blorp_blit_apply_transform() blindly applies the transform to all
1223 * three coordinates. Grab the original sample index.
1225 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1226 nir_channel(&b
, src_pos
, 1),
1227 nir_channel(&b
, dst_pos
, 2));
1230 /* If the source image is not multisampled, then we want to fetch sample
1231 * number 0, because that's the only sample there is.
1233 if (key
->src_samples
== 1)
1234 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1236 /* X, Y, and S are now the coordinates of the pixel in the source image
1237 * that we want to texture from. Exception: if we are blending, then S is
1238 * irrelevant, because we are going to fetch all samples.
1240 if (key
->blend
&& !key
->blit_scaled
) {
1241 /* Resolves (effecively) use texelFetch, so we need integers and we
1242 * don't care about the sample index if we got one.
1244 src_pos
= nir_f2i32(&b
, nir_channels(&b
, src_pos
, 0x3));
1246 if (devinfo
->gen
== 6) {
1247 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1248 * blending we need with a single linear-interpolated texture lookup
1249 * at the center of the sample. The texture coordinates to be odd
1250 * integers so that they correspond to the center of a 2x2 block
1251 * representing the four samples that maxe up a pixel. So we need
1252 * to multiply our X and Y coordinates each by 2 and then add 1.
1254 assert(key
->src_coords_normalized
);
1255 src_pos
= nir_fadd(&b
,
1256 nir_i2f32(&b
, src_pos
),
1257 nir_imm_float(&b
, 0.5f
));
1258 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1260 /* Gen7+ hardware doesn't automaticaly blend. */
1261 color
= blorp_nir_manual_blend_average(&b
, &v
, src_pos
, key
->src_samples
,
1263 key
->texture_data_type
);
1265 } else if (key
->blend
&& key
->blit_scaled
) {
1266 assert(!key
->use_kill
);
1267 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
, key
, &v
);
1269 if (key
->bilinear_filter
) {
1270 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1272 /* We're going to use texelFetch, so we need integers */
1273 if (src_pos
->num_components
== 2) {
1274 src_pos
= nir_f2i32(&b
, src_pos
);
1276 assert(src_pos
->num_components
== 3);
1277 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i32(&b
, src_pos
), 0),
1278 nir_channel(&b
, nir_f2i32(&b
, src_pos
), 1),
1279 nir_channel(&b
, src_pos
, 2));
1282 /* We aren't blending, which means we just want to fetch a single
1283 * sample from the source surface. The address that we want to fetch
1284 * from is related to the X, Y and S values according to the formula:
1286 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1288 * If the actual tiling and sample count of the source surface are
1289 * not the same as the configuration of the texture, then we need to
1290 * adjust the coordinates to compensate for the difference.
1292 if (tex_tiled_w
!= key
->src_tiled_w
||
1293 key
->tex_samples
!= key
->src_samples
||
1294 key
->tex_layout
!= key
->src_layout
) {
1295 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1297 /* Now (X, Y, S) = detile(src_tiling, offset) */
1298 if (tex_tiled_w
!= key
->src_tiled_w
)
1299 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1300 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1301 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1305 if (key
->need_src_offset
)
1306 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1308 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1310 * In other words: X, Y, and S now contain values which, when passed to
1311 * the texturing unit, will cause data to be read from the correct
1312 * memory location. So we can fetch the texel now.
1314 if (key
->src_samples
== 1) {
1315 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1317 nir_ssa_def
*mcs
= NULL
;
1318 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1319 mcs
= blorp_blit_txf_ms_mcs(&b
, &v
, src_pos
);
1321 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1326 if (!isl_swizzle_is_identity(key
->src_swizzle
)) {
1327 color
= swizzle_color(&b
, color
, key
->src_swizzle
,
1328 key
->texture_data_type
);
1331 if (!isl_swizzle_is_identity(key
->dst_swizzle
)) {
1332 color
= swizzle_color(&b
, color
, isl_swizzle_invert(key
->dst_swizzle
),
1336 if (key
->dst_bpc
!= key
->src_bpc
) {
1337 assert(isl_swizzle_is_identity(key
->src_swizzle
));
1338 assert(isl_swizzle_is_identity(key
->dst_swizzle
));
1339 color
= bit_cast_color(&b
, color
, key
);
1343 /* The destination image is bound as a red texture three times as wide
1344 * as the actual image. Our shader is effectively running one color
1345 * component at a time. We need to pick off the appropriate component
1346 * from the source color and write that to destination red.
1348 assert(dst_pos
->num_components
== 2);
1350 nir_ssa_def
*color_component
=
1351 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1352 nir_channel(&b
, color
, 0),
1353 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1354 nir_channel(&b
, color
, 1),
1355 nir_channel(&b
, color
, 2)));
1357 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1358 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1361 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1367 brw_blorp_get_blit_kernel(struct blorp_context
*blorp
,
1368 struct blorp_params
*params
,
1369 const struct brw_blorp_blit_prog_key
*prog_key
)
1371 if (blorp
->lookup_shader(blorp
, prog_key
, sizeof(*prog_key
),
1372 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1375 void *mem_ctx
= ralloc_context(NULL
);
1377 const unsigned *program
;
1378 struct brw_wm_prog_data prog_data
;
1380 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1381 nir
->info
.name
= ralloc_strdup(nir
, "BLORP-blit");
1383 struct brw_wm_prog_key wm_key
;
1384 brw_blorp_init_wm_prog_key(&wm_key
);
1385 wm_key
.tex
.compressed_multisample_layout_mask
=
1386 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1387 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1388 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1390 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1394 blorp
->upload_shader(blorp
, prog_key
, sizeof(*prog_key
),
1395 program
, prog_data
.base
.program_size
,
1396 &prog_data
.base
, sizeof(prog_data
),
1397 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1399 ralloc_free(mem_ctx
);
1404 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1405 GLfloat src0
, GLfloat src1
,
1406 GLfloat dst0
, GLfloat dst1
,
1409 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1411 /* When not mirroring a coordinate (say, X), we need:
1412 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1414 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1416 * blorp program uses "round toward zero" to convert the
1417 * transformed floating point coordinates to integer coordinates,
1418 * whereas the behaviour we actually want is "round to nearest",
1419 * so 0.5 provides the necessary correction.
1421 xform
->multiplier
= scale
;
1422 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1424 /* When mirroring X we need:
1425 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1427 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1429 xform
->multiplier
= -scale
;
1430 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1435 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1436 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1438 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1439 struct isl_extent2d px_size_sa
=
1440 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1441 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1442 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1443 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1444 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1446 *tile_x_px
= info
->tile_x_sa
;
1447 *tile_y_px
= info
->tile_y_sa
;
1452 blorp_surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1453 struct brw_blorp_surface_info
*info
)
1457 /* Just bail if we have nothing to do. */
1458 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1459 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1460 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1463 /* If this gets triggered then we've gotten here twice which. This
1464 * shouldn't happen thanks to the above early return.
1466 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1468 uint32_t layer
= 0, z
= 0;
1469 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1470 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1472 layer
= info
->view
.base_array_layer
;
1474 uint32_t byte_offset
;
1475 isl_surf_get_image_surf(isl_dev
, &info
->surf
,
1476 info
->view
.base_level
, layer
, z
,
1478 &byte_offset
, &info
->tile_x_sa
, &info
->tile_y_sa
);
1479 info
->addr
.offset
+= byte_offset
;
1481 uint32_t tile_x_px
, tile_y_px
;
1482 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1484 /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we place
1485 * the image at the tile boundary and offset our sampling or rendering.
1486 * For this reason, we need to grow the image by the offset to ensure that
1487 * the hardware doesn't think we've gone past the edge.
1489 info
->surf
.logical_level0_px
.w
+= tile_x_px
;
1490 info
->surf
.logical_level0_px
.h
+= tile_y_px
;
1491 info
->surf
.phys_level0_sa
.w
+= info
->tile_x_sa
;
1492 info
->surf
.phys_level0_sa
.h
+= info
->tile_y_sa
;
1494 /* The view is also different now. */
1495 info
->view
.base_level
= 0;
1496 info
->view
.levels
= 1;
1497 info
->view
.base_array_layer
= 0;
1498 info
->view
.array_len
= 1;
1503 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1504 struct brw_blorp_surface_info
*info
)
1506 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1508 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1509 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1511 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1512 info
->surf
.samples
= 1;
1513 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1517 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1518 struct brw_blorp_surface_info
*info
)
1520 assert(info
->surf
.tiling
== ISL_TILING_W
);
1522 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1523 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1525 /* On gen7+, we don't have interleaved multisampling for color render
1526 * targets so we have to fake it.
1528 * TODO: Are we sure we don't also need to fake it on gen6?
1530 if (isl_dev
->info
->gen
> 6 &&
1531 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1532 surf_fake_interleaved_msaa(isl_dev
, info
);
1535 if (isl_dev
->info
->gen
== 6) {
1536 /* Gen6 stencil buffers have a very large alignment coming in from the
1537 * miptree. It's out-of-bounds for what the surface state can handle.
1538 * Since we have a single layer and level, it doesn't really matter as
1539 * long as we don't pass a bogus value into isl_surf_fill_state().
1541 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1544 /* Now that we've converted everything to a simple 2-D surface with only
1545 * one miplevel, we can go about retiling it.
1547 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1548 info
->surf
.tiling
= ISL_TILING_Y0
;
1549 info
->surf
.logical_level0_px
.width
=
1550 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1551 info
->surf
.logical_level0_px
.height
=
1552 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1553 info
->tile_x_sa
*= 2;
1554 info
->tile_y_sa
/= 2;
1558 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1560 /* The current code doesn't support offsets into the aux buffers. This
1561 * should be possible, but we need to make sure the offset is page
1562 * aligned for both the surface and the aux buffer surface. Generally
1563 * this mean using the page aligned offset for the aux buffer.
1565 * Currently the cases where we must split the blit are limited to cases
1566 * where we don't have a aux buffer.
1568 if (surf
->aux_addr
.buffer
!= NULL
)
1571 /* We can't support splitting the blit for gen <= 7, because the qpitch
1572 * size is calculated by the hardware based on the surface height for
1573 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1575 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1582 can_shrink_surfaces(const struct blorp_params
*params
)
1585 can_shrink_surface(¶ms
->src
) &&
1586 can_shrink_surface(¶ms
->dst
);
1590 get_max_surface_size(const struct gen_device_info
*devinfo
,
1591 const struct blorp_params
*params
)
1593 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1594 if (split_blorp_blit_debug
&& can_shrink_surfaces(params
))
1595 return max
>> 4; /* A smaller restriction when debug is enabled */
1601 double src0
, src1
, dst0
, dst1
;
1606 struct blt_axis x
, y
;
1610 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1611 struct brw_blorp_surface_info
*info
)
1613 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1615 info
->surf
.logical_level0_px
.width
*= 3;
1616 info
->surf
.phys_level0_sa
.width
*= 3;
1617 info
->tile_x_sa
*= 3;
1619 enum isl_format red_format
;
1620 switch (info
->view
.format
) {
1621 case ISL_FORMAT_R8G8B8_UNORM
:
1622 red_format
= ISL_FORMAT_R8_UNORM
;
1624 case ISL_FORMAT_R8G8B8_UINT
:
1625 red_format
= ISL_FORMAT_R8_UINT
;
1627 case ISL_FORMAT_R16G16B16_UNORM
:
1628 red_format
= ISL_FORMAT_R16_UNORM
;
1630 case ISL_FORMAT_R16G16B16_UINT
:
1631 red_format
= ISL_FORMAT_R16_UINT
;
1633 case ISL_FORMAT_R32G32B32_UINT
:
1634 red_format
= ISL_FORMAT_R32_UINT
;
1637 unreachable("Invalid RGB copy destination format");
1639 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1640 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1641 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1642 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1644 info
->surf
.format
= info
->view
.format
= red_format
;
1647 enum blit_shrink_status
{
1649 BLIT_WIDTH_SHRINK
= 1,
1650 BLIT_HEIGHT_SHRINK
= 2,
1653 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1654 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1655 * returned, then the blit was successful.
1657 static enum blit_shrink_status
1658 try_blorp_blit(struct blorp_batch
*batch
,
1659 struct blorp_params
*params
,
1660 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1661 struct blt_coords
*coords
)
1663 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1665 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1666 wm_prog_key
->texture_data_type
= nir_type_int
;
1667 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1668 wm_prog_key
->texture_data_type
= nir_type_uint
;
1670 wm_prog_key
->texture_data_type
= nir_type_float
;
1673 /* src_samples and dst_samples are the true sample counts */
1674 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1675 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1677 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1679 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1682 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1683 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1685 /* Round floating point values to nearest integer to avoid "off by one texel"
1686 * kind of errors when blitting.
1688 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1689 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1690 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1691 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1693 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1694 coords
->x
.src0
, coords
->x
.src1
,
1695 coords
->x
.dst0
, coords
->x
.dst1
,
1697 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1698 coords
->y
.src0
, coords
->y
.src1
,
1699 coords
->y
.dst0
, coords
->y
.dst1
,
1703 if (devinfo
->gen
== 4) {
1704 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
1705 * Convert them to a single slice on gen4.
1707 if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1708 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1709 wm_prog_key
->need_dst_offset
= true;
1712 if (params
->src
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1713 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->src
);
1714 wm_prog_key
->need_src_offset
= true;
1718 if (devinfo
->gen
> 6 &&
1719 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1720 assert(params
->dst
.surf
.samples
> 1);
1722 /* We must expand the rectangle we send through the rendering pipeline,
1723 * to account for the fact that we are mapping the destination region as
1724 * single-sampled when it is in fact multisampled. We must also align
1725 * it to a multiple of the multisampling pattern, because the
1726 * differences between multisampled and single-sampled surface formats
1727 * will mean that pixels are scrambled within the multisampling pattern.
1728 * TODO: what if this makes the coordinates too large?
1730 * Note: this only works if the destination surface uses the IMS layout.
1731 * If it's UMS, then we have no choice but to set up the rendering
1732 * pipeline as multisampled.
1734 struct isl_extent2d px_size_sa
=
1735 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1736 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1737 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1738 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1739 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1741 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1743 wm_prog_key
->use_kill
= true;
1744 wm_prog_key
->need_dst_offset
= true;
1747 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1748 /* We must modify the rectangle we send through the rendering pipeline
1749 * (and the size and x/y offset of the destination surface), to account
1750 * for the fact that we are mapping it as Y-tiled when it is in fact
1753 * Both Y tiling and W tiling can be understood as organizations of
1754 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1755 * is different, but the layout of the 32-byte sub-tiles within the 4k
1756 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1757 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1758 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1760 * Therefore, to account for the layout differences within the 32-byte
1761 * sub-tiles, we must expand the rectangle so the X coordinates of its
1762 * edges are multiples of 8 (the W sub-tile width), and its Y
1763 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1764 * Then we need to scale the X and Y coordinates of the rectangle to
1765 * account for the differences in aspect ratio between the Y and W
1766 * sub-tiles. We need to modify the layer width and height similarly.
1768 * A correction needs to be applied when MSAA is in use: since
1769 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1770 * we need to align the Y coordinates to multiples of 8, so that when
1771 * they are divided by two they are still multiples of 4.
1773 * Note: Since the x/y offset of the surface will be applied using the
1774 * SURFACE_STATE command packet, it will be invisible to the swizzling
1775 * code in the shader; therefore it needs to be in a multiple of the
1776 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1777 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1778 * buffer), and the miplevel alignment used for stencil buffers is 8
1779 * pixels horizontally and either 4 or 8 pixels vertically (see
1780 * intel_horizontal_texture_alignment_unit() and
1781 * intel_vertical_texture_alignment_unit()).
1783 * Note: Also, since the SURFACE_STATE command packet can only apply
1784 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1785 * vertically, it is important that the offsets will be multiples of
1786 * these sizes after they are converted into Y-tiled coordinates.
1787 * Fortunately they will be, since we know from above that the offsets
1788 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1789 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1791 * TODO: what if this makes the coordinates (or the texture size) too
1794 const unsigned x_align
= 8;
1795 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1796 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1797 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1798 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1799 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1801 /* Retile the surface to Y-tiled */
1802 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1804 wm_prog_key
->dst_tiled_w
= true;
1805 wm_prog_key
->use_kill
= true;
1806 wm_prog_key
->need_dst_offset
= true;
1808 if (params
->dst
.surf
.samples
> 1) {
1809 /* If the destination surface is a W-tiled multisampled stencil
1810 * buffer that we're mapping as Y tiled, then we need to arrange for
1811 * the WM program to run once per sample rather than once per pixel,
1812 * because the memory layout of related samples doesn't match between
1815 wm_prog_key
->persample_msaa_dispatch
= true;
1819 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1820 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1821 * Broadwell adds support for sampling from stencil.
1823 * See the comments above concerning x/y offset alignment for the
1824 * destination surface.
1826 * TODO: what if this makes the texture size too large?
1828 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1830 wm_prog_key
->src_tiled_w
= true;
1831 wm_prog_key
->need_src_offset
= true;
1834 /* tex_samples and rt_samples are the sample counts that are set up in
1837 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1838 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1840 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1841 * use to access the source and destination surfaces.
1843 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1844 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1846 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1847 /* We are blitting from a multisample buffer to a multisample buffer, so
1848 * we must preserve samples within a pixel. This means we have to
1849 * arrange for the WM program to run once per sample rather than once
1852 wm_prog_key
->persample_msaa_dispatch
= true;
1855 params
->num_samples
= params
->dst
.surf
.samples
;
1857 if ((wm_prog_key
->bilinear_filter
||
1858 (wm_prog_key
->blend
&& !wm_prog_key
->blit_scaled
)) &&
1859 batch
->blorp
->isl_dev
->info
->gen
<= 6) {
1860 /* Gen4-5 don't support non-normalized texture coordinates */
1861 wm_prog_key
->src_coords_normalized
= true;
1862 params
->wm_inputs
.src_inv_size
[0] =
1863 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.width
,
1864 params
->src
.view
.base_level
);
1865 params
->wm_inputs
.src_inv_size
[1] =
1866 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.height
,
1867 params
->src
.view
.base_level
);
1870 if (isl_format_get_layout(params
->dst
.view
.format
)->bpb
% 3 == 0) {
1871 /* We can't render to RGB formats natively because they aren't a
1872 * power-of-two size. Instead, we fake them by using a red format
1873 * with the same channel type and size and emitting shader code to
1874 * only write one channel at a time.
1879 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1881 wm_prog_key
->dst_rgb
= true;
1882 wm_prog_key
->need_dst_offset
= true;
1885 if (devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
1886 !isl_swizzle_is_identity(params
->src
.view
.swizzle
)) {
1887 wm_prog_key
->src_swizzle
= params
->src
.view
.swizzle
;
1888 params
->src
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
1890 wm_prog_key
->src_swizzle
= ISL_SWIZZLE_IDENTITY
;
1893 if (!isl_swizzle_supports_rendering(devinfo
, params
->dst
.view
.swizzle
)) {
1894 wm_prog_key
->dst_swizzle
= params
->dst
.view
.swizzle
;
1895 params
->dst
.view
.swizzle
= ISL_SWIZZLE_IDENTITY
;
1897 wm_prog_key
->dst_swizzle
= ISL_SWIZZLE_IDENTITY
;
1900 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
1901 assert(wm_prog_key
->need_src_offset
);
1902 surf_get_intratile_offset_px(¶ms
->src
,
1903 ¶ms
->wm_inputs
.src_offset
.x
,
1904 ¶ms
->wm_inputs
.src_offset
.y
);
1907 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
1908 assert(wm_prog_key
->need_dst_offset
);
1909 surf_get_intratile_offset_px(¶ms
->dst
,
1910 ¶ms
->wm_inputs
.dst_offset
.x
,
1911 ¶ms
->wm_inputs
.dst_offset
.y
);
1912 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
1913 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
1914 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
1915 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
1918 /* For some texture types, we need to pass the layer through the sampler. */
1919 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
1921 if (!brw_blorp_get_blit_kernel(batch
->blorp
, params
, wm_prog_key
))
1924 if (!blorp_ensure_sf_program(batch
->blorp
, params
))
1927 unsigned result
= 0;
1928 unsigned max_surface_size
= get_max_surface_size(devinfo
, params
);
1929 if (params
->src
.surf
.logical_level0_px
.width
> max_surface_size
||
1930 params
->dst
.surf
.logical_level0_px
.width
> max_surface_size
)
1931 result
|= BLIT_WIDTH_SHRINK
;
1932 if (params
->src
.surf
.logical_level0_px
.height
> max_surface_size
||
1933 params
->dst
.surf
.logical_level0_px
.height
> max_surface_size
)
1934 result
|= BLIT_HEIGHT_SHRINK
;
1937 batch
->blorp
->exec(batch
, params
);
1943 /* Adjust split blit source coordinates for the current destination
1947 adjust_split_source_coords(const struct blt_axis
*orig
,
1948 struct blt_axis
*split_coords
,
1951 /* When scale is greater than 0, then we are growing from the start, so
1952 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
1953 * source range shrinks from the end. In that case src0 is adjusted by
1954 * delta1, and src1 is adjusted by delta0.
1956 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
1957 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
1958 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
1959 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
1962 static struct isl_extent2d
1963 get_px_size_sa(const struct isl_surf
*surf
)
1965 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
1967 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
1970 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
1974 shrink_surface_params(const struct isl_device
*dev
,
1975 struct brw_blorp_surface_info
*info
,
1976 double *x0
, double *x1
, double *y0
, double *y1
)
1978 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
1979 struct isl_extent2d px_size_sa
;
1982 blorp_surf_convert_to_single_slice(dev
, info
);
1984 px_size_sa
= get_px_size_sa(&info
->surf
);
1986 /* Because this gets called after we lower compressed images, the tile
1987 * offsets may be non-zero and we need to incorporate them in our
1990 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
1991 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
1992 isl_tiling_get_intratile_offset_sa(info
->surf
.tiling
,
1993 info
->surf
.format
, info
->surf
.row_pitch
,
1994 x_offset_sa
, y_offset_sa
,
1996 &info
->tile_x_sa
, &info
->tile_y_sa
);
1998 info
->addr
.offset
+= byte_offset
;
2000 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
2003 info
->tile_x_sa
= 0;
2005 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
2008 info
->tile_y_sa
= 0;
2010 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
2011 info
->surf
.logical_level0_px
.width
= size
;
2012 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
2014 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
2015 info
->surf
.logical_level0_px
.height
= size
;
2016 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
2020 shrink_surfaces(const struct isl_device
*dev
,
2021 struct blorp_params
*params
,
2022 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2023 struct blt_coords
*coords
)
2025 /* Shrink source surface */
2026 shrink_surface_params(dev
, ¶ms
->src
, &coords
->x
.src0
, &coords
->x
.src1
,
2027 &coords
->y
.src0
, &coords
->y
.src1
);
2028 wm_prog_key
->need_src_offset
= false;
2030 /* Shrink destination surface */
2031 shrink_surface_params(dev
, ¶ms
->dst
, &coords
->x
.dst0
, &coords
->x
.dst1
,
2032 &coords
->y
.dst0
, &coords
->y
.dst1
);
2033 wm_prog_key
->need_dst_offset
= false;
2037 do_blorp_blit(struct blorp_batch
*batch
,
2038 const struct blorp_params
*orig_params
,
2039 struct brw_blorp_blit_prog_key
*wm_prog_key
,
2040 const struct blt_coords
*orig
)
2042 struct blorp_params params
;
2043 struct blt_coords blit_coords
;
2044 struct blt_coords split_coords
= *orig
;
2045 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
2046 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
2047 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
2048 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
2054 bool x_done
, y_done
;
2055 bool shrink
= split_blorp_blit_debug
&& can_shrink_surfaces(orig_params
);
2057 params
= *orig_params
;
2058 blit_coords
= split_coords
;
2060 shrink_surfaces(batch
->blorp
->isl_dev
, ¶ms
, wm_prog_key
,
2062 enum blit_shrink_status result
=
2063 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
2065 if (result
& BLIT_WIDTH_SHRINK
) {
2068 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2069 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2071 if (result
& BLIT_HEIGHT_SHRINK
) {
2074 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2075 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2079 assert(can_shrink_surfaces(orig_params
));
2084 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
2085 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
2088 } else if (y_done
) {
2089 split_coords
.x
.dst0
+= w
;
2090 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2091 split_coords
.y
.dst0
= orig
->y
.dst0
;
2092 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2093 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2095 split_coords
.y
.dst0
+= h
;
2096 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2097 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2103 blorp_blit(struct blorp_batch
*batch
,
2104 const struct blorp_surf
*src_surf
,
2105 unsigned src_level
, unsigned src_layer
,
2106 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2107 const struct blorp_surf
*dst_surf
,
2108 unsigned dst_level
, unsigned dst_layer
,
2109 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2110 float src_x0
, float src_y0
,
2111 float src_x1
, float src_y1
,
2112 float dst_x0
, float dst_y0
,
2113 float dst_x1
, float dst_y1
,
2114 GLenum filter
, bool mirror_x
, bool mirror_y
)
2116 struct blorp_params params
;
2117 blorp_params_init(¶ms
);
2119 /* We cannot handle combined depth and stencil. */
2120 if (src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2121 assert(src_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2122 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2123 assert(dst_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2125 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
2126 assert(src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
);
2127 /* Prior to Broadwell, we can't render to R8_UINT */
2128 if (batch
->blorp
->isl_dev
->info
->gen
< 8) {
2129 src_format
= ISL_FORMAT_R8_UNORM
;
2130 dst_format
= ISL_FORMAT_R8_UNORM
;
2134 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2135 src_layer
, src_format
, false);
2136 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2137 dst_layer
, dst_format
, true);
2139 params
.src
.view
.swizzle
= src_swizzle
;
2140 params
.dst
.view
.swizzle
= dst_swizzle
;
2142 struct brw_blorp_blit_prog_key wm_prog_key
= {
2143 .shader_type
= BLORP_SHADER_TYPE_BLIT
2146 /* Scaled blitting or not. */
2147 wm_prog_key
.blit_scaled
=
2148 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2149 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2151 /* Scaling factors used for bilinear filtering in multisample scaled
2154 if (params
.src
.surf
.samples
== 16)
2155 wm_prog_key
.x_scale
= 4.0f
;
2157 wm_prog_key
.x_scale
= 2.0f
;
2158 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2160 if (filter
== GL_LINEAR
&&
2161 params
.src
.surf
.samples
<= 1 && params
.dst
.surf
.samples
<= 1) {
2162 wm_prog_key
.bilinear_filter
= true;
2165 if ((params
.src
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) == 0 &&
2166 (params
.src
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) == 0 &&
2167 !isl_format_has_int_channel(params
.src
.surf
.format
) &&
2168 params
.src
.surf
.samples
> 1 && params
.dst
.surf
.samples
<= 1) {
2169 /* We are downsampling a non-integer color buffer, so blend.
2171 * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
2173 * "If the source formats are integer types or stencil values, a
2174 * single sample's value is selected for each pixel."
2176 * This implies we should not blend in that case.
2178 wm_prog_key
.blend
= true;
2181 params
.wm_inputs
.rect_grid
.x1
=
2182 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2183 wm_prog_key
.x_scale
- 1.0f
;
2184 params
.wm_inputs
.rect_grid
.y1
=
2185 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2186 wm_prog_key
.y_scale
- 1.0f
;
2188 struct blt_coords coords
= {
2205 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2208 static enum isl_format
2209 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2211 /* The choice of UNORM and UINT formats is very intentional here. Most
2212 * of the time, we want to use a UINT format to avoid any rounding error
2213 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2214 * (It's the only format allowed in conjunction with W-tiling.) Also we
2215 * intentionally use the 4-channel formats whenever we can. This is so
2216 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2217 * even though one of them is 3/4 the size of the other. The choice of
2218 * UNORM vs. UINT is also very intentional because we don't have 8 or
2219 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2220 * Fortunately, the only time we should ever use two different formats in
2221 * the table below is for RGB -> RGBA blits and so we will never have any
2222 * UNORM/UINT mismatch.
2224 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2226 case 8: return ISL_FORMAT_R8_UINT
;
2227 case 16: return ISL_FORMAT_R8G8_UINT
;
2228 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2229 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2230 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2231 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2232 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2233 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2235 unreachable("Unknown format bpb");
2239 case 8: return ISL_FORMAT_R8_UINT
;
2240 case 16: return ISL_FORMAT_R8G8_UINT
;
2241 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2242 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2243 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2244 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2245 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2246 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2248 unreachable("Unknown format bpb");
2253 /** Returns a UINT format that is CCS-compatible with the given format
2255 * The PRM's say absolutely nothing about how render compression works. The
2256 * only thing they provide is a list of formats on which it is and is not
2257 * supported. Empirical testing indicates that the compression is only based
2258 * on the bit-layout of the format and the channel encoding doesn't matter.
2259 * So, while texture views don't work in general, you can create a view as
2260 * long as the bit-layout of the formats are the same.
2262 * Fortunately, for every render compression capable format, the UINT format
2263 * with the same bit layout also supports render compression. This means that
2264 * we only need to handle UINT formats for copy operations. In order to do
2265 * copies between formats with different bit layouts, we attach both with a
2266 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2267 * operation between the two bit layouts.
2269 static enum isl_format
2270 get_ccs_compatible_uint_format(const struct isl_format_layout
*fmtl
)
2272 switch (fmtl
->format
) {
2273 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2274 case ISL_FORMAT_R32G32B32A32_SINT
:
2275 case ISL_FORMAT_R32G32B32A32_UINT
:
2276 case ISL_FORMAT_R32G32B32A32_UNORM
:
2277 case ISL_FORMAT_R32G32B32A32_SNORM
:
2278 case ISL_FORMAT_R32G32B32X32_FLOAT
:
2279 return ISL_FORMAT_R32G32B32A32_UINT
;
2281 case ISL_FORMAT_R16G16B16A16_UNORM
:
2282 case ISL_FORMAT_R16G16B16A16_SNORM
:
2283 case ISL_FORMAT_R16G16B16A16_SINT
:
2284 case ISL_FORMAT_R16G16B16A16_UINT
:
2285 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2286 case ISL_FORMAT_R16G16B16X16_UNORM
:
2287 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2288 return ISL_FORMAT_R16G16B16A16_UINT
;
2290 case ISL_FORMAT_R32G32_FLOAT
:
2291 case ISL_FORMAT_R32G32_SINT
:
2292 case ISL_FORMAT_R32G32_UINT
:
2293 case ISL_FORMAT_R32G32_UNORM
:
2294 case ISL_FORMAT_R32G32_SNORM
:
2295 return ISL_FORMAT_R32G32_UINT
;
2297 case ISL_FORMAT_B8G8R8A8_UNORM
:
2298 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2299 case ISL_FORMAT_R8G8B8A8_UNORM
:
2300 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2301 case ISL_FORMAT_R8G8B8A8_SNORM
:
2302 case ISL_FORMAT_R8G8B8A8_SINT
:
2303 case ISL_FORMAT_R8G8B8A8_UINT
:
2304 case ISL_FORMAT_B8G8R8X8_UNORM
:
2305 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2306 case ISL_FORMAT_R8G8B8X8_UNORM
:
2307 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2308 return ISL_FORMAT_R8G8B8A8_UINT
;
2310 case ISL_FORMAT_R16G16_UNORM
:
2311 case ISL_FORMAT_R16G16_SNORM
:
2312 case ISL_FORMAT_R16G16_SINT
:
2313 case ISL_FORMAT_R16G16_UINT
:
2314 case ISL_FORMAT_R16G16_FLOAT
:
2315 return ISL_FORMAT_R16G16_UINT
;
2317 case ISL_FORMAT_R32_SINT
:
2318 case ISL_FORMAT_R32_UINT
:
2319 case ISL_FORMAT_R32_FLOAT
:
2320 case ISL_FORMAT_R32_UNORM
:
2321 case ISL_FORMAT_R32_SNORM
:
2322 return ISL_FORMAT_R32_UINT
;
2325 unreachable("Not a compressible format");
2329 /* Takes an isl_color_value and returns a color value that is the original
2330 * color value only bit-casted to a UINT format. This value, together with
2331 * the format from get_ccs_compatible_uint_format, will yield the same bit
2332 * value as the original color and format.
2334 static union isl_color_value
2335 bitcast_color_value_to_uint(union isl_color_value color
,
2336 const struct isl_format_layout
*fmtl
)
2338 /* All CCS formats have the same number of bits in each channel */
2339 const struct isl_channel_layout
*chan
= &fmtl
->channels
.r
;
2341 union isl_color_value bits
;
2342 switch (chan
->type
) {
2345 /* Hardware will ignore the high bits so there's no need to cast */
2350 for (unsigned i
= 0; i
< 4; i
++)
2351 bits
.u32
[i
] = _mesa_float_to_unorm(color
.f32
[i
], chan
->bits
);
2355 for (unsigned i
= 0; i
< 4; i
++)
2356 bits
.i32
[i
] = _mesa_float_to_snorm(color
.f32
[i
], chan
->bits
);
2360 switch (chan
->bits
) {
2362 for (unsigned i
= 0; i
< 4; i
++)
2363 bits
.u32
[i
] = _mesa_float_to_half(color
.f32
[i
]);
2371 unreachable("Invalid float format size");
2376 unreachable("Invalid channel type");
2379 switch (fmtl
->format
) {
2380 case ISL_FORMAT_B8G8R8A8_UNORM
:
2381 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2382 case ISL_FORMAT_B8G8R8X8_UNORM
:
2383 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
: {
2384 /* If it's a BGRA format, we need to swap blue and red */
2385 uint32_t tmp
= bits
.u32
[0];
2386 bits
.u32
[0] = bits
.u32
[2];
2392 break; /* Nothing to do */
2399 blorp_surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2400 struct brw_blorp_surface_info
*info
,
2401 uint32_t *x
, uint32_t *y
,
2402 uint32_t *width
, uint32_t *height
)
2404 const struct isl_format_layout
*fmtl
=
2405 isl_format_get_layout(info
->surf
.format
);
2407 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2409 /* This is a compressed surface. We need to convert it to a single
2410 * slice (because compressed layouts don't perfectly match uncompressed
2411 * ones with the same bpb) and divide x, y, width, and height by the
2414 blorp_surf_convert_to_single_slice(isl_dev
, info
);
2416 if (width
&& height
) {
2418 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2419 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2420 assert(*width
% fmtl
->bw
== 0 ||
2421 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2422 assert(*height
% fmtl
->bh
== 0 ||
2423 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2425 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2426 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2430 assert(*x
% fmtl
->bw
== 0);
2431 assert(*y
% fmtl
->bh
== 0);
2436 info
->surf
.logical_level0_px
.width
=
2437 DIV_ROUND_UP(info
->surf
.logical_level0_px
.width
, fmtl
->bw
);
2438 info
->surf
.logical_level0_px
.height
=
2439 DIV_ROUND_UP(info
->surf
.logical_level0_px
.height
, fmtl
->bh
);
2441 assert(info
->surf
.phys_level0_sa
.width
% fmtl
->bw
== 0);
2442 assert(info
->surf
.phys_level0_sa
.height
% fmtl
->bh
== 0);
2443 info
->surf
.phys_level0_sa
.width
/= fmtl
->bw
;
2444 info
->surf
.phys_level0_sa
.height
/= fmtl
->bh
;
2446 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2447 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2448 info
->tile_x_sa
/= fmtl
->bw
;
2449 info
->tile_y_sa
/= fmtl
->bh
;
2451 /* It's now an uncompressed surface so we need an uncompressed format */
2452 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2456 blorp_copy(struct blorp_batch
*batch
,
2457 const struct blorp_surf
*src_surf
,
2458 unsigned src_level
, unsigned src_layer
,
2459 const struct blorp_surf
*dst_surf
,
2460 unsigned dst_level
, unsigned dst_layer
,
2461 uint32_t src_x
, uint32_t src_y
,
2462 uint32_t dst_x
, uint32_t dst_y
,
2463 uint32_t src_width
, uint32_t src_height
)
2465 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2466 struct blorp_params params
;
2468 if (src_width
== 0 || src_height
== 0)
2471 blorp_params_init(¶ms
);
2472 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2473 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2474 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2475 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2477 struct brw_blorp_blit_prog_key wm_prog_key
= {
2478 .shader_type
= BLORP_SHADER_TYPE_BLIT
2481 const struct isl_format_layout
*src_fmtl
=
2482 isl_format_get_layout(params
.src
.surf
.format
);
2483 const struct isl_format_layout
*dst_fmtl
=
2484 isl_format_get_layout(params
.dst
.surf
.format
);
2486 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2487 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2488 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2489 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
||
2490 params
.dst
.aux_usage
== ISL_AUX_USAGE_MCS
||
2491 params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2493 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2494 params
.dst
.view
.format
= get_ccs_compatible_uint_format(dst_fmtl
);
2495 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2496 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2497 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2498 params
.src
.view
.format
= params
.dst
.view
.format
;
2500 params
.src
.view
.format
=
2501 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2503 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2504 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2505 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2506 params
.dst
.view
.format
= params
.src
.view
.format
;
2508 params
.dst
.view
.format
=
2509 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2512 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2513 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2516 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2517 /* It's safe to do a blorp_copy between things which are sRGB with CCS_E
2518 * enabled even though CCS_E doesn't technically do sRGB on SKL because
2519 * we stomp everything to UINT anyway. The one thing we have to be
2520 * careful of is clear colors. Because fast clear colors for sRGB on
2521 * gen9 are encoded as the float values between format conversion and
2522 * sRGB curve application, a given clear color float will convert to the
2523 * same bits regardless of whether the format is UNORM or sRGB.
2524 * Therefore, we can handle sRGB without any special cases.
2526 UNUSED
enum isl_format linear_src_format
=
2527 isl_format_srgb_to_linear(src_surf
->surf
->format
);
2528 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2530 params
.src
.view
.format
));
2531 params
.src
.clear_color
=
2532 bitcast_color_value_to_uint(params
.src
.clear_color
, src_fmtl
);
2535 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2536 /* See above where we handle linear_src_format */
2537 UNUSED
enum isl_format linear_dst_format
=
2538 isl_format_srgb_to_linear(dst_surf
->surf
->format
);
2539 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2541 params
.dst
.view
.format
));
2542 params
.dst
.clear_color
=
2543 bitcast_color_value_to_uint(params
.dst
.clear_color
, dst_fmtl
);
2546 wm_prog_key
.src_bpc
=
2547 isl_format_get_layout(params
.src
.view
.format
)->channels
.r
.bits
;
2548 wm_prog_key
.dst_bpc
=
2549 isl_format_get_layout(params
.dst
.view
.format
)->channels
.r
.bits
;
2551 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2552 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2554 &src_width
, &src_height
);
2555 wm_prog_key
.need_src_offset
= true;
2558 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2559 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2560 &dst_x
, &dst_y
, NULL
, NULL
);
2561 wm_prog_key
.need_dst_offset
= true;
2564 /* Once both surfaces are stompped to uncompressed as needed, the
2565 * destination size is the same as the source size.
2567 uint32_t dst_width
= src_width
;
2568 uint32_t dst_height
= src_height
;
2570 struct blt_coords coords
= {
2573 .src1
= src_x
+ src_width
,
2575 .dst1
= dst_x
+ dst_width
,
2580 .src1
= src_y
+ src_height
,
2582 .dst1
= dst_y
+ dst_height
,
2587 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2590 static enum isl_format
2591 isl_format_for_size(unsigned size_B
)
2594 case 1: return ISL_FORMAT_R8_UINT
;
2595 case 2: return ISL_FORMAT_R8G8_UINT
;
2596 case 4: return ISL_FORMAT_R8G8B8A8_UINT
;
2597 case 8: return ISL_FORMAT_R16G16B16A16_UINT
;
2598 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
2600 unreachable("Not a power-of-two format size");
2605 * Returns the greatest common divisor of a and b that is a power of two.
2608 gcd_pow2_u64(uint64_t a
, uint64_t b
)
2610 assert(a
> 0 || b
> 0);
2612 unsigned a_log2
= ffsll(a
) - 1;
2613 unsigned b_log2
= ffsll(b
) - 1;
2615 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
2616 * case, the MIN2() will take the other one. If both are 0 then we will
2617 * hit the assert above.
2619 return 1 << MIN2(a_log2
, b_log2
);
2623 do_buffer_copy(struct blorp_batch
*batch
,
2624 struct blorp_address
*src
,
2625 struct blorp_address
*dst
,
2626 int width
, int height
, int block_size
)
2628 /* The actual format we pick doesn't matter as blorp will throw it away.
2629 * The only thing that actually matters is the size.
2631 enum isl_format format
= isl_format_for_size(block_size
);
2634 struct isl_surf surf
;
2635 ok
= isl_surf_init(batch
->blorp
->isl_dev
, &surf
,
2636 .dim
= ISL_SURF_DIM_2D
,
2644 .row_pitch
= width
* block_size
,
2645 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
2646 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
2647 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
2650 struct blorp_surf src_blorp_surf
= {
2655 struct blorp_surf dst_blorp_surf
= {
2660 blorp_copy(batch
, &src_blorp_surf
, 0, 0, &dst_blorp_surf
, 0, 0,
2661 0, 0, 0, 0, width
, height
);
2665 blorp_buffer_copy(struct blorp_batch
*batch
,
2666 struct blorp_address src
,
2667 struct blorp_address dst
,
2670 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
2671 uint64_t copy_size
= size
;
2673 /* This is maximum possible width/height our HW can handle */
2674 uint64_t max_surface_dim
= 1 << (devinfo
->gen
>= 7 ? 14 : 13);
2676 /* First, we compute the biggest format that can be used with the
2677 * given offsets and size.
2680 bs
= gcd_pow2_u64(bs
, src
.offset
);
2681 bs
= gcd_pow2_u64(bs
, dst
.offset
);
2682 bs
= gcd_pow2_u64(bs
, size
);
2684 /* First, we make a bunch of max-sized copies */
2685 uint64_t max_copy_size
= max_surface_dim
* max_surface_dim
* bs
;
2686 while (copy_size
>= max_copy_size
) {
2687 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, max_surface_dim
, bs
);
2688 copy_size
-= max_copy_size
;
2689 src
.offset
+= max_copy_size
;
2690 dst
.offset
+= max_copy_size
;
2693 /* Now make a max-width copy */
2694 uint64_t height
= copy_size
/ (max_surface_dim
* bs
);
2695 assert(height
< max_surface_dim
);
2697 uint64_t rect_copy_size
= height
* max_surface_dim
* bs
;
2698 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, height
, bs
);
2699 copy_size
-= rect_copy_size
;
2700 src
.offset
+= rect_copy_size
;
2701 dst
.offset
+= rect_copy_size
;
2704 /* Finally, make a small copy to finish it off */
2705 if (copy_size
!= 0) {
2706 do_buffer_copy(batch
, &src
, &dst
, copy_size
/ bs
, 1, bs
);