2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/nir/nir_builder.h"
26 #include "blorp_priv.h"
28 /* header-only include needed for _mesa_unorm_to_float and friends. */
29 #include "mesa/main/format_utils.h"
31 #define FILE_DEBUG_FLAG DEBUG_BLORP
33 static const bool split_blorp_blit_debug
= false;
36 * Enum to specify the order of arguments in a sampler message
38 enum sampler_message_arg
40 SAMPLER_MESSAGE_ARG_U_FLOAT
,
41 SAMPLER_MESSAGE_ARG_V_FLOAT
,
42 SAMPLER_MESSAGE_ARG_U_INT
,
43 SAMPLER_MESSAGE_ARG_V_INT
,
44 SAMPLER_MESSAGE_ARG_R_INT
,
45 SAMPLER_MESSAGE_ARG_SI_INT
,
46 SAMPLER_MESSAGE_ARG_MCS_INT
,
47 SAMPLER_MESSAGE_ARG_ZERO_INT
,
50 struct brw_blorp_blit_vars
{
51 /* Input values from brw_blorp_wm_inputs */
52 nir_variable
*v_discard_rect
;
53 nir_variable
*v_rect_grid
;
54 nir_variable
*v_coord_transform
;
55 nir_variable
*v_src_z
;
56 nir_variable
*v_src_offset
;
57 nir_variable
*v_dst_offset
;
58 nir_variable
*v_src_inv_size
;
61 nir_variable
*frag_coord
;
64 nir_variable
*color_out
;
68 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
69 const struct brw_blorp_blit_prog_key
*key
)
71 /* Blended and scaled blits never use pixel discard. */
72 assert(!key
->use_kill
|| !(key
->blend
&& key
->blit_scaled
));
74 #define LOAD_INPUT(name, type)\
75 v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
77 LOAD_INPUT(discard_rect
, glsl_vec4_type())
78 LOAD_INPUT(rect_grid
, glsl_vec4_type())
79 LOAD_INPUT(coord_transform
, glsl_vec4_type())
80 LOAD_INPUT(src_z
, glsl_uint_type())
81 LOAD_INPUT(src_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
82 LOAD_INPUT(dst_offset
, glsl_vector_type(GLSL_TYPE_UINT
, 2))
83 LOAD_INPUT(src_inv_size
, glsl_vector_type(GLSL_TYPE_FLOAT
, 2))
87 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
88 glsl_vec4_type(), "gl_FragCoord");
89 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
90 v
->frag_coord
->data
.origin_upper_left
= true;
92 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
93 glsl_vec4_type(), "gl_FragColor");
94 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
98 blorp_blit_get_frag_coords(nir_builder
*b
,
99 const struct brw_blorp_blit_prog_key
*key
,
100 struct brw_blorp_blit_vars
*v
)
102 nir_ssa_def
*coord
= nir_f2i32(b
, nir_load_var(b
, v
->frag_coord
));
104 /* Account for destination surface intratile offset
106 * Transformation parameters giving translation from destination to source
107 * coordinates don't take into account possible intra-tile destination
108 * offset. Therefore it has to be first subtracted from the incoming
109 * coordinates. Vertices are set up based on coordinates containing the
112 if (key
->need_dst_offset
)
113 coord
= nir_isub(b
, coord
, nir_load_var(b
, v
->v_dst_offset
));
115 if (key
->persample_msaa_dispatch
) {
116 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
117 nir_load_sample_id(b
));
119 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
124 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
128 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
129 struct brw_blorp_blit_vars
*v
)
131 nir_ssa_def
*coord_transform
= nir_load_var(b
, v
->v_coord_transform
);
133 nir_ssa_def
*offset
= nir_vec2(b
, nir_channel(b
, coord_transform
, 1),
134 nir_channel(b
, coord_transform
, 3));
135 nir_ssa_def
*mul
= nir_vec2(b
, nir_channel(b
, coord_transform
, 0),
136 nir_channel(b
, coord_transform
, 2));
138 return nir_fadd(b
, nir_fmul(b
, src_pos
, mul
), offset
);
142 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
143 struct brw_blorp_blit_vars
*v
)
145 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
146 nir_ssa_def
*discard_rect
= nir_load_var(b
, v
->v_discard_rect
);
147 nir_ssa_def
*dst_x0
= nir_channel(b
, discard_rect
, 0);
148 nir_ssa_def
*dst_x1
= nir_channel(b
, discard_rect
, 1);
149 nir_ssa_def
*dst_y0
= nir_channel(b
, discard_rect
, 2);
150 nir_ssa_def
*dst_y1
= nir_channel(b
, discard_rect
, 3);
152 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), dst_x0
);
153 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), dst_x1
);
154 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), dst_y0
);
155 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), dst_y1
);
157 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
159 nir_intrinsic_instr
*discard
=
160 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
161 discard
->src
[0] = nir_src_for_ssa(oob
);
162 nir_builder_instr_insert(b
, &discard
->instr
);
165 static nir_tex_instr
*
166 blorp_create_nir_tex_instr(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
167 nir_texop op
, nir_ssa_def
*pos
, unsigned num_srcs
,
168 nir_alu_type dst_type
)
170 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, num_srcs
);
174 tex
->dest_type
= dst_type
;
175 tex
->is_array
= false;
176 tex
->is_shadow
= false;
178 /* Blorp only has one texture and it's bound at unit 0 */
181 tex
->texture_index
= 0;
182 tex
->sampler_index
= 0;
184 /* To properly handle 3-D and 2-D array textures, we pull the Z component
185 * from an input. TODO: This is a bit magic; we should probably make this
186 * more explicit in the future.
188 assert(pos
->num_components
>= 2);
189 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
190 nir_load_var(b
, v
->v_src_z
));
192 tex
->src
[0].src_type
= nir_tex_src_coord
;
193 tex
->src
[0].src
= nir_src_for_ssa(pos
);
194 tex
->coord_components
= 3;
196 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
202 blorp_nir_tex(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
203 const struct brw_blorp_blit_prog_key
*key
, nir_ssa_def
*pos
)
205 if (key
->need_src_offset
)
206 pos
= nir_fadd(b
, pos
, nir_i2f32(b
, nir_load_var(b
, v
->v_src_offset
)));
208 /* If the sampler requires normalized coordinates, we need to compensate. */
209 if (key
->src_coords_normalized
)
210 pos
= nir_fmul(b
, pos
, nir_load_var(b
, v
->v_src_inv_size
));
213 blorp_create_nir_tex_instr(b
, v
, nir_texop_tex
, pos
, 2,
214 key
->texture_data_type
);
216 assert(pos
->num_components
== 2);
217 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
218 tex
->src
[1].src_type
= nir_tex_src_lod
;
219 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
221 nir_builder_instr_insert(b
, &tex
->instr
);
223 return &tex
->dest
.ssa
;
227 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
228 nir_ssa_def
*pos
, nir_alu_type dst_type
)
231 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf
, pos
, 2, dst_type
);
233 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
234 tex
->src
[1].src_type
= nir_tex_src_lod
;
235 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
237 nir_builder_instr_insert(b
, &tex
->instr
);
239 return &tex
->dest
.ssa
;
243 blorp_nir_txf_ms(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
244 nir_ssa_def
*pos
, nir_ssa_def
*mcs
, nir_alu_type dst_type
)
247 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms
, pos
,
248 mcs
!= NULL
? 3 : 2, dst_type
);
250 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
252 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
253 if (pos
->num_components
== 2) {
254 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
256 assert(pos
->num_components
== 3);
257 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
261 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
262 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
265 nir_builder_instr_insert(b
, &tex
->instr
);
267 return &tex
->dest
.ssa
;
271 blorp_blit_txf_ms_mcs(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
275 blorp_create_nir_tex_instr(b
, v
, nir_texop_txf_ms_mcs
,
276 pos
, 1, nir_type_int
);
278 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
280 nir_builder_instr_insert(b
, &tex
->instr
);
282 return &tex
->dest
.ssa
;
286 nir_mask_shift_or(struct nir_builder
*b
, nir_ssa_def
*dst
, nir_ssa_def
*src
,
287 uint32_t src_mask
, int src_left_shift
)
289 nir_ssa_def
*masked
= nir_iand(b
, src
, nir_imm_int(b
, src_mask
));
291 nir_ssa_def
*shifted
;
292 if (src_left_shift
> 0) {
293 shifted
= nir_ishl(b
, masked
, nir_imm_int(b
, src_left_shift
));
294 } else if (src_left_shift
< 0) {
295 shifted
= nir_ushr(b
, masked
, nir_imm_int(b
, -src_left_shift
));
297 assert(src_left_shift
== 0);
301 return nir_ior(b
, dst
, shifted
);
305 * Emit code to compensate for the difference between Y and W tiling.
307 * This code modifies the X and Y coordinates according to the formula:
309 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
311 * (See brw_blorp_build_nir_shader).
313 static inline nir_ssa_def
*
314 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
316 assert(pos
->num_components
== 2);
317 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
318 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
320 /* Given X and Y coordinates that describe an address using Y tiling,
321 * translate to the X and Y coordinates that describe the same address
324 * If we break down the low order bits of X and Y, using a
325 * single letter to represent each low-order bit:
327 * X = A << 7 | 0bBCDEFGH
328 * Y = J << 5 | 0bKLMNP (1)
330 * Then we can apply the Y tiling formula to see the memory offset being
333 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
335 * If we apply the W detiling formula to this memory location, that the
336 * corresponding X' and Y' coordinates are:
338 * X' = A << 6 | 0bBCDPFH (3)
339 * Y' = J << 6 | 0bKLMNEG
341 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
342 * we need to make the following computation:
344 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
345 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
347 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
348 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
349 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
350 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
352 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
353 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
354 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
355 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
357 return nir_vec2(b
, x_W
, y_W
);
361 * Emit code to compensate for the difference between Y and W tiling.
363 * This code modifies the X and Y coordinates according to the formula:
365 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
367 * (See brw_blorp_build_nir_shader).
369 static inline nir_ssa_def
*
370 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
372 assert(pos
->num_components
== 2);
373 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
374 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
376 /* Applying the same logic as above, but in reverse, we obtain the
379 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
380 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
382 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
383 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
384 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
385 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
386 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
388 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
389 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
390 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
392 return nir_vec2(b
, x_Y
, y_Y
);
396 * Emit code to compensate for the difference between MSAA and non-MSAA
399 * This code modifies the X and Y coordinates according to the formula:
401 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
403 * (See brw_blorp_blit_program).
405 static inline nir_ssa_def
*
406 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
407 unsigned num_samples
, enum isl_msaa_layout layout
)
409 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
412 case ISL_MSAA_LAYOUT_NONE
:
413 assert(pos
->num_components
== 2);
415 case ISL_MSAA_LAYOUT_ARRAY
:
416 /* No translation needed */
418 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
419 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
420 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
421 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
422 nir_channel(b
, pos
, 2);
424 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
425 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
426 switch (num_samples
) {
429 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
430 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
433 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
434 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
435 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
437 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
438 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
439 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
440 if (num_samples
== 2) {
443 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
444 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
445 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
450 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
451 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
453 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
455 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
456 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
457 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
458 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
459 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
460 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
461 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
465 /* encode_msaa(16, IMS, X, Y, S) = (X', Y', 0)
466 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
468 * Y' = (Y & ~0b1) << 2 | (S & 0b1000) >> 1 (S & 0b10)
471 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
472 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
473 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
474 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
475 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 2);
476 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x8, -1);
477 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
478 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
482 unreachable("Invalid number of samples for IMS layout");
485 return nir_vec2(b
, x_out
, y_out
);
489 unreachable("Invalid MSAA layout");
494 * Emit code to compensate for the difference between MSAA and non-MSAA
497 * This code modifies the X and Y coordinates according to the formula:
499 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
501 * (See brw_blorp_blit_program).
503 static inline nir_ssa_def
*
504 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
505 unsigned num_samples
, enum isl_msaa_layout layout
)
507 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
510 case ISL_MSAA_LAYOUT_NONE
:
511 /* No translation necessary, and S should already be zero. */
512 assert(pos
->num_components
== 2);
514 case ISL_MSAA_LAYOUT_ARRAY
:
515 /* No translation necessary. */
517 case ISL_MSAA_LAYOUT_INTERLEAVED
: {
518 assert(pos
->num_components
== 2);
520 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
521 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
523 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
524 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
525 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
526 switch (num_samples
) {
529 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
530 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
531 * S = (X & 0b10) >> 1
533 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
534 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
535 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
536 * S = (Y & 0b10) | (X & 0b10) >> 1
538 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
539 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
540 if (num_samples
== 2) {
542 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
544 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
545 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
546 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
547 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
552 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
553 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
554 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
555 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
557 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
558 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
559 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
560 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
561 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
562 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
563 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
567 /* decode_msaa(16, IMS, X, Y, 0) = (X', Y', S)
568 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
569 * Y' = (Y & ~0b111) >> 2 | (Y & 0b1)
570 * S = (Y & 0b100) << 1 | (X & 0b100) |
571 * (Y & 0b10) | (X & 0b10) >> 1
573 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
574 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
575 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffff8, -2);
576 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
577 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x4, 1);
578 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
579 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
580 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
584 unreachable("Invalid number of samples for IMS layout");
587 return nir_vec3(b
, x_out
, y_out
, s_out
);
591 unreachable("Invalid MSAA layout");
596 * Count the number of trailing 1 bits in the given value. For example:
598 * count_trailing_one_bits(0) == 0
599 * count_trailing_one_bits(7) == 3
600 * count_trailing_one_bits(11) == 2
602 static inline int count_trailing_one_bits(unsigned value
)
604 #ifdef HAVE___BUILTIN_CTZ
605 return __builtin_ctz(~value
);
607 return _mesa_bitcount(value
& ~(value
+ 1));
612 blorp_nir_manual_blend_average(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
613 nir_ssa_def
*pos
, unsigned tex_samples
,
614 enum isl_aux_usage tex_aux_usage
,
615 nir_alu_type dst_type
)
617 /* If non-null, this is the outer-most if statement */
618 nir_if
*outer_if
= NULL
;
620 nir_variable
*color
=
621 nir_local_variable_create(b
->impl
, glsl_vec4_type(), "color");
623 nir_ssa_def
*mcs
= NULL
;
624 if (tex_aux_usage
== ISL_AUX_USAGE_MCS
)
625 mcs
= blorp_blit_txf_ms_mcs(b
, v
, pos
);
627 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
629 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
631 * This ensures that when all samples have the same value, no numerical
632 * precision is lost, since each addition operation always adds two equal
633 * values, and summing two equal floating point values does not lose
636 * We perform this computation by treating the texture_data array as a
637 * stack and performing the following operations:
639 * - push sample 0 onto stack
640 * - push sample 1 onto stack
641 * - add top two stack entries
642 * - push sample 2 onto stack
643 * - push sample 3 onto stack
644 * - add top two stack entries
645 * - add top two stack entries
646 * - divide top stack entry by 4
648 * Note that after pushing sample i onto the stack, the number of add
649 * operations we do is equal to the number of trailing 1 bits in i. This
650 * works provided the total number of samples is a power of two, which it
651 * always is for i965.
653 * For integer formats, we replace the add operations with average
654 * operations and skip the final division.
656 nir_ssa_def
*texture_data
[5];
657 unsigned stack_depth
= 0;
658 for (unsigned i
= 0; i
< tex_samples
; ++i
) {
659 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
661 /* Push sample i onto the stack */
662 assert(stack_depth
< ARRAY_SIZE(texture_data
));
664 nir_ssa_def
*ms_pos
= nir_vec3(b
, nir_channel(b
, pos
, 0),
665 nir_channel(b
, pos
, 1),
667 texture_data
[stack_depth
++] = blorp_nir_txf_ms(b
, v
, ms_pos
, mcs
, dst_type
);
669 if (i
== 0 && tex_aux_usage
== ISL_AUX_USAGE_MCS
) {
670 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
671 * suggests an optimization:
673 * "A simple optimization with probable large return in
674 * performance is to compare the MCS value to zero (indicating
675 * all samples are on sample slice 0), and sample only from
676 * sample slice 0 using ld2dss if MCS is zero."
678 * Note that in the case where the MCS value is zero, sampling from
679 * sample slice 0 using ld2dss and sampling from sample 0 using
680 * ld2dms are equivalent (since all samples are on sample slice 0).
681 * Since we have already sampled from sample 0, all we need to do is
682 * skip the remaining fetches and averaging if MCS is zero.
684 nir_ssa_def
*mcs_zero
=
685 nir_ieq(b
, nir_channel(b
, mcs
, 0), nir_imm_int(b
, 0));
686 if (tex_samples
== 16) {
687 mcs_zero
= nir_iand(b
, mcs_zero
,
688 nir_ieq(b
, nir_channel(b
, mcs
, 1), nir_imm_int(b
, 0)));
691 nir_if
*if_stmt
= nir_if_create(b
->shader
);
692 if_stmt
->condition
= nir_src_for_ssa(mcs_zero
);
693 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
695 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
696 nir_store_var(b
, color
, texture_data
[0], 0xf);
698 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
702 for (int j
= 0; j
< count_trailing_one_bits(i
); j
++) {
703 assert(stack_depth
>= 2);
706 assert(dst_type
== nir_type_float
);
707 texture_data
[stack_depth
- 1] =
708 nir_fadd(b
, texture_data
[stack_depth
- 1],
709 texture_data
[stack_depth
]);
713 /* We should have just 1 sample on the stack now. */
714 assert(stack_depth
== 1);
716 texture_data
[0] = nir_fmul(b
, texture_data
[0],
717 nir_imm_float(b
, 1.0 / tex_samples
));
719 nir_store_var(b
, color
, texture_data
[0], 0xf);
722 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
724 return nir_load_var(b
, color
);
727 static inline nir_ssa_def
*
728 nir_imm_vec2(nir_builder
*build
, float x
, float y
)
732 memset(&v
, 0, sizeof(v
));
736 return nir_build_imm(build
, 4, 32, v
);
740 blorp_nir_manual_blend_bilinear(nir_builder
*b
, nir_ssa_def
*pos
,
741 unsigned tex_samples
,
742 const struct brw_blorp_blit_prog_key
*key
,
743 struct brw_blorp_blit_vars
*v
)
745 nir_ssa_def
*pos_xy
= nir_channels(b
, pos
, 0x3);
746 nir_ssa_def
*rect_grid
= nir_load_var(b
, v
->v_rect_grid
);
747 nir_ssa_def
*scale
= nir_imm_vec2(b
, key
->x_scale
, key
->y_scale
);
749 /* Translate coordinates to lay out the samples in a rectangular grid
750 * roughly corresponding to sample locations.
752 pos_xy
= nir_fmul(b
, pos_xy
, scale
);
753 /* Adjust coordinates so that integers represent pixel centers rather
756 pos_xy
= nir_fadd(b
, pos_xy
, nir_imm_float(b
, -0.5));
757 /* Clamp the X, Y texture coordinates to properly handle the sampling of
758 * texels on texture edges.
760 pos_xy
= nir_fmin(b
, nir_fmax(b
, pos_xy
, nir_imm_float(b
, 0.0)),
761 nir_vec2(b
, nir_channel(b
, rect_grid
, 0),
762 nir_channel(b
, rect_grid
, 1)));
764 /* Store the fractional parts to be used as bilinear interpolation
767 nir_ssa_def
*frac_xy
= nir_ffract(b
, pos_xy
);
768 /* Round the float coordinates down to nearest integer */
769 pos_xy
= nir_fdiv(b
, nir_ftrunc(b
, pos_xy
), scale
);
771 nir_ssa_def
*tex_data
[4];
772 for (unsigned i
= 0; i
< 4; ++i
) {
773 float sample_off_x
= (float)(i
& 0x1) / key
->x_scale
;
774 float sample_off_y
= (float)((i
>> 1) & 0x1) / key
->y_scale
;
775 nir_ssa_def
*sample_off
= nir_imm_vec2(b
, sample_off_x
, sample_off_y
);
777 nir_ssa_def
*sample_coords
= nir_fadd(b
, pos_xy
, sample_off
);
778 nir_ssa_def
*sample_coords_int
= nir_f2i32(b
, sample_coords
);
780 /* The MCS value we fetch has to match up with the pixel that we're
781 * sampling from. Since we sample from different pixels in each
782 * iteration of this "for" loop, the call to mcs_fetch() should be
783 * here inside the loop after computing the pixel coordinates.
785 nir_ssa_def
*mcs
= NULL
;
786 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
787 mcs
= blorp_blit_txf_ms_mcs(b
, v
, sample_coords_int
);
789 /* Compute sample index and map the sample index to a sample number.
790 * Sample index layout shows the numbering of slots in a rectangular
791 * grid of samples with in a pixel. Sample number layout shows the
792 * rectangular grid of samples roughly corresponding to the real sample
793 * locations with in a pixel.
794 * In case of 4x MSAA, layout of sample indices matches the layout of
802 * In case of 8x MSAA the two layouts don't match.
803 * sample index layout : --------- sample number layout : ---------
804 * | 0 | 1 | | 3 | 7 |
805 * --------- ---------
806 * | 2 | 3 | | 5 | 0 |
807 * --------- ---------
808 * | 4 | 5 | | 1 | 2 |
809 * --------- ---------
810 * | 6 | 7 | | 4 | 6 |
811 * --------- ---------
813 * Fortunately, this can be done fairly easily as:
814 * S' = (0x17306425 >> (S * 4)) & 0xf
816 * In the case of 16x MSAA the two layouts don't match.
817 * Sample index layout: Sample number layout:
818 * --------------------- ---------------------
819 * | 0 | 1 | 2 | 3 | | 15 | 10 | 9 | 7 |
820 * --------------------- ---------------------
821 * | 4 | 5 | 6 | 7 | | 4 | 1 | 3 | 13 |
822 * --------------------- ---------------------
823 * | 8 | 9 | 10 | 11 | | 12 | 2 | 0 | 6 |
824 * --------------------- ---------------------
825 * | 12 | 13 | 14 | 15 | | 11 | 8 | 5 | 14 |
826 * --------------------- ---------------------
828 * This is equivalent to
829 * S' = (0xe58b602cd31479af >> (S * 4)) & 0xf
831 nir_ssa_def
*frac
= nir_ffract(b
, sample_coords
);
832 nir_ssa_def
*sample
=
833 nir_fdot2(b
, frac
, nir_imm_vec2(b
, key
->x_scale
,
834 key
->x_scale
* key
->y_scale
));
835 sample
= nir_f2i32(b
, sample
);
837 if (tex_samples
== 8) {
838 sample
= nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0x64210573),
839 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
840 nir_imm_int(b
, 0xf));
841 } else if (tex_samples
== 16) {
842 nir_ssa_def
*sample_low
=
843 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xd31479af),
844 nir_ishl(b
, sample
, nir_imm_int(b
, 2))),
845 nir_imm_int(b
, 0xf));
846 nir_ssa_def
*sample_high
=
847 nir_iand(b
, nir_ishr(b
, nir_imm_int(b
, 0xe58b602c),
848 nir_ishl(b
, nir_iadd(b
, sample
,
851 nir_imm_int(b
, 0xf));
853 sample
= nir_bcsel(b
, nir_ilt(b
, sample
, nir_imm_int(b
, 8)),
854 sample_low
, sample_high
);
856 nir_ssa_def
*pos_ms
= nir_vec3(b
, nir_channel(b
, sample_coords_int
, 0),
857 nir_channel(b
, sample_coords_int
, 1),
859 tex_data
[i
] = blorp_nir_txf_ms(b
, v
, pos_ms
, mcs
, key
->texture_data_type
);
862 nir_ssa_def
*frac_x
= nir_channel(b
, frac_xy
, 0);
863 nir_ssa_def
*frac_y
= nir_channel(b
, frac_xy
, 1);
864 return nir_flrp(b
, nir_flrp(b
, tex_data
[0], tex_data
[1], frac_x
),
865 nir_flrp(b
, tex_data
[2], tex_data
[3], frac_x
),
869 /** Perform a color bit-cast operation
871 * For copy operations involving CCS, we may need to use different formats for
872 * the source and destination surfaces. The two formats must both be UINT
873 * formats and must have the same size but may have different bit layouts.
874 * For instance, we may be copying from R8G8B8A8_UINT to R32_UINT or R32_UINT
875 * to R16G16_UINT. This function generates code to shuffle bits around to get
876 * us from one to the other.
879 bit_cast_color(struct nir_builder
*b
, nir_ssa_def
*color
,
880 const struct brw_blorp_blit_prog_key
*key
)
882 assert(key
->texture_data_type
== nir_type_uint
);
884 if (key
->dst_bpc
> key
->src_bpc
) {
885 nir_ssa_def
*u
= nir_ssa_undef(b
, 1, 32);
886 nir_ssa_def
*dst_chan
[2] = { u
, u
};
888 unsigned dst_idx
= 0;
889 for (unsigned i
= 0; i
< 4; i
++) {
890 nir_ssa_def
*shifted
= nir_ishl(b
, nir_channel(b
, color
, i
),
891 nir_imm_int(b
, shift
));
893 dst_chan
[dst_idx
] = shifted
;
895 dst_chan
[dst_idx
] = nir_ior(b
, dst_chan
[dst_idx
], shifted
);
898 shift
+= key
->src_bpc
;
899 if (shift
>= key
->dst_bpc
) {
905 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], u
, u
);
907 assert(key
->dst_bpc
< key
->src_bpc
);
909 nir_ssa_def
*mask
= nir_imm_int(b
, ~0u >> (32 - key
->dst_bpc
));
911 nir_ssa_def
*dst_chan
[4];
912 unsigned src_idx
= 0;
914 for (unsigned i
= 0; i
< 4; i
++) {
915 dst_chan
[i
] = nir_iand(b
, nir_ushr(b
, nir_channel(b
, color
, src_idx
),
916 nir_imm_int(b
, shift
)),
918 shift
+= key
->dst_bpc
;
919 if (shift
>= key
->src_bpc
) {
925 return nir_vec4(b
, dst_chan
[0], dst_chan
[1], dst_chan
[2], dst_chan
[3]);
930 * Generator for WM programs used in BLORP blits.
932 * The bulk of the work done by the WM program is to wrap and unwrap the
933 * coordinate transformations used by the hardware to store surfaces in
934 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
935 * sample index for a multisampled surface) to a memory offset by the
936 * following formulas:
938 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
939 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
941 * For a single-sampled surface, or for a multisampled surface using
942 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
945 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
946 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
947 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
948 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
950 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
951 * embeds the sample number into bit 1 of the X and Y coordinates:
953 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
954 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
955 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
956 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
957 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
958 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
959 * S = (Y & 0b10) | (X & 0b10) >> 1
961 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
962 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
965 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
966 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
967 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
968 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
969 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
970 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
971 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
973 * For X tiling, tile() combines together the low-order bits of the X and Y
974 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
975 * bytes wide and 8 rows high:
977 * tile(x_tiled, X, Y, S) = A
978 * where A = tile_num << 12 | offset
979 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
980 * offset = (Y' & 0b111) << 9
981 * | (X & 0b111111111)
983 * Y' = Y + S * qpitch
984 * detile(x_tiled, A) = (X, Y, S)
988 * Y' = (tile_num / tile_pitch) << 3
989 * | (A & 0b111000000000) >> 9
990 * X' = (tile_num % tile_pitch) << 9
991 * | (A & 0b111111111)
993 * (In all tiling formulas, cpp is the number of bytes occupied by a single
994 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
995 * to fill the width of the surface, and qpitch is the spacing (in rows)
996 * between array slices).
998 * For Y tiling, tile() combines together the low-order bits of the X and Y
999 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
1000 * bytes wide and 32 rows high:
1002 * tile(y_tiled, X, Y, S) = A
1003 * where A = tile_num << 12 | offset
1004 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
1005 * offset = (X' & 0b1110000) << 5
1006 * | (Y' & 0b11111) << 4
1009 * Y' = Y + S * qpitch
1010 * detile(y_tiled, A) = (X, Y, S)
1011 * where X = X' / cpp
1014 * Y' = (tile_num / tile_pitch) << 5
1015 * | (A & 0b111110000) >> 4
1016 * X' = (tile_num % tile_pitch) << 7
1017 * | (A & 0b111000000000) >> 5
1020 * For W tiling, tile() combines together the low-order bits of the X and Y
1021 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
1022 * bytes wide and 64 rows high (note that W tiling is only used for stencil
1023 * buffers, which always have cpp = 1 and S=0):
1025 * tile(w_tiled, X, Y, S) = A
1026 * where A = tile_num << 12 | offset
1027 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
1028 * offset = (X' & 0b111000) << 6
1029 * | (Y' & 0b111100) << 3
1030 * | (X' & 0b100) << 2
1031 * | (Y' & 0b10) << 2
1032 * | (X' & 0b10) << 1
1036 * Y' = Y + S * qpitch
1037 * detile(w_tiled, A) = (X, Y, S)
1038 * where X = X' / cpp = X'
1039 * Y = Y' % qpitch = Y'
1040 * S = Y / qpitch = 0
1041 * Y' = (tile_num / tile_pitch) << 6
1042 * | (A & 0b111100000) >> 3
1043 * | (A & 0b1000) >> 2
1045 * X' = (tile_num % tile_pitch) << 6
1046 * | (A & 0b111000000000) >> 6
1047 * | (A & 0b10000) >> 2
1048 * | (A & 0b100) >> 1
1051 * Finally, for a non-tiled surface, tile() simply combines together the X and
1052 * Y coordinates in the natural way:
1054 * tile(untiled, X, Y, S) = A
1055 * where A = Y * pitch + X'
1057 * Y' = Y + S * qpitch
1058 * detile(untiled, A) = (X, Y, S)
1059 * where X = X' / cpp
1065 * (In these formulas, pitch is the number of bytes occupied by a single row
1069 brw_blorp_build_nir_shader(struct blorp_context
*blorp
, void *mem_ctx
,
1070 const struct brw_blorp_blit_prog_key
*key
)
1072 const struct gen_device_info
*devinfo
= blorp
->isl_dev
->info
;
1073 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1076 if (key
->dst_tiled_w
&& key
->rt_samples
> 1) {
1077 /* If the destination image is W tiled and multisampled, then the thread
1078 * must be dispatched once per sample, not once per pixel. This is
1079 * necessary because after conversion between W and Y tiling, there's no
1080 * guarantee that all samples corresponding to a single pixel will still
1083 assert(key
->persample_msaa_dispatch
);
1087 /* We are blending, which means we won't have an opportunity to
1088 * translate the tiling and sample count for the texture surface. So
1089 * the surface state for the texture must be configured with the correct
1090 * tiling and sample count.
1092 assert(!key
->src_tiled_w
);
1093 assert(key
->tex_samples
== key
->src_samples
);
1094 assert(key
->tex_layout
== key
->src_layout
);
1095 assert(key
->tex_samples
> 0);
1098 if (key
->persample_msaa_dispatch
) {
1099 /* It only makes sense to do persample dispatch if the render target is
1100 * configured as multisampled.
1102 assert(key
->rt_samples
> 0);
1105 /* Make sure layout is consistent with sample count */
1106 assert((key
->tex_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1107 (key
->tex_samples
<= 1));
1108 assert((key
->rt_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1109 (key
->rt_samples
<= 1));
1110 assert((key
->src_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1111 (key
->src_samples
<= 1));
1112 assert((key
->dst_layout
== ISL_MSAA_LAYOUT_NONE
) ==
1113 (key
->dst_samples
<= 1));
1116 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
1118 struct brw_blorp_blit_vars v
;
1119 brw_blorp_blit_vars_init(&b
, &v
, key
);
1121 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1123 /* Render target and texture hardware don't support W tiling until Gen8. */
1124 const bool rt_tiled_w
= false;
1125 const bool tex_tiled_w
= devinfo
->gen
>= 8 && key
->src_tiled_w
;
1127 /* The address that data will be written to is determined by the
1128 * coordinates supplied to the WM thread and the tiling and sample count of
1129 * the render target, according to the formula:
1131 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1133 * If the actual tiling and sample count of the destination surface are not
1134 * the same as the configuration of the render target, then these
1135 * coordinates are wrong and we have to adjust them to compensate for the
1138 if (rt_tiled_w
!= key
->dst_tiled_w
||
1139 key
->rt_samples
!= key
->dst_samples
||
1140 key
->rt_layout
!= key
->dst_layout
) {
1141 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1143 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1144 if (rt_tiled_w
!= key
->dst_tiled_w
)
1145 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1146 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1147 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1151 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1153 * That is: X, Y and S now contain the true coordinates and sample index of
1154 * the data that the WM thread should output.
1156 * If we need to kill pixels that are outside the destination rectangle,
1157 * now is the time to do it.
1159 if (key
->use_kill
) {
1160 assert(!(key
->blend
&& key
->blit_scaled
));
1161 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1164 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f32(&b
, dst_pos
), &v
);
1165 if (dst_pos
->num_components
== 3) {
1166 /* The sample coordinate is an integer that we want left alone but
1167 * blorp_blit_apply_transform() blindly applies the transform to all
1168 * three coordinates. Grab the original sample index.
1170 src_pos
= nir_vec3(&b
, nir_channel(&b
, src_pos
, 0),
1171 nir_channel(&b
, src_pos
, 1),
1172 nir_channel(&b
, dst_pos
, 2));
1175 /* If the source image is not multisampled, then we want to fetch sample
1176 * number 0, because that's the only sample there is.
1178 if (key
->src_samples
== 1)
1179 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1181 /* X, Y, and S are now the coordinates of the pixel in the source image
1182 * that we want to texture from. Exception: if we are blending, then S is
1183 * irrelevant, because we are going to fetch all samples.
1185 if (key
->blend
&& !key
->blit_scaled
) {
1186 /* Resolves (effecively) use texelFetch, so we need integers and we
1187 * don't care about the sample index if we got one.
1189 src_pos
= nir_f2i32(&b
, nir_channels(&b
, src_pos
, 0x3));
1191 if (devinfo
->gen
== 6) {
1192 /* Because gen6 only supports 4x interleved MSAA, we can do all the
1193 * blending we need with a single linear-interpolated texture lookup
1194 * at the center of the sample. The texture coordinates to be odd
1195 * integers so that they correspond to the center of a 2x2 block
1196 * representing the four samples that maxe up a pixel. So we need
1197 * to multiply our X and Y coordinates each by 2 and then add 1.
1199 assert(key
->src_coords_normalized
);
1200 src_pos
= nir_fadd(&b
,
1201 nir_i2f32(&b
, src_pos
),
1202 nir_imm_float(&b
, 0.5f
));
1203 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1205 /* Gen7+ hardware doesn't automaticaly blend. */
1206 color
= blorp_nir_manual_blend_average(&b
, &v
, src_pos
, key
->src_samples
,
1208 key
->texture_data_type
);
1210 } else if (key
->blend
&& key
->blit_scaled
) {
1211 assert(!key
->use_kill
);
1212 color
= blorp_nir_manual_blend_bilinear(&b
, src_pos
, key
->src_samples
, key
, &v
);
1214 if (key
->bilinear_filter
) {
1215 color
= blorp_nir_tex(&b
, &v
, key
, src_pos
);
1217 /* We're going to use texelFetch, so we need integers */
1218 if (src_pos
->num_components
== 2) {
1219 src_pos
= nir_f2i32(&b
, src_pos
);
1221 assert(src_pos
->num_components
== 3);
1222 src_pos
= nir_vec3(&b
, nir_channel(&b
, nir_f2i32(&b
, src_pos
), 0),
1223 nir_channel(&b
, nir_f2i32(&b
, src_pos
), 1),
1224 nir_channel(&b
, src_pos
, 2));
1227 /* We aren't blending, which means we just want to fetch a single
1228 * sample from the source surface. The address that we want to fetch
1229 * from is related to the X, Y and S values according to the formula:
1231 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1233 * If the actual tiling and sample count of the source surface are
1234 * not the same as the configuration of the texture, then we need to
1235 * adjust the coordinates to compensate for the difference.
1237 if (tex_tiled_w
!= key
->src_tiled_w
||
1238 key
->tex_samples
!= key
->src_samples
||
1239 key
->tex_layout
!= key
->src_layout
) {
1240 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1242 /* Now (X, Y, S) = detile(src_tiling, offset) */
1243 if (tex_tiled_w
!= key
->src_tiled_w
)
1244 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1245 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1246 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1250 if (key
->need_src_offset
)
1251 src_pos
= nir_iadd(&b
, src_pos
, nir_load_var(&b
, v
.v_src_offset
));
1253 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1255 * In other words: X, Y, and S now contain values which, when passed to
1256 * the texturing unit, will cause data to be read from the correct
1257 * memory location. So we can fetch the texel now.
1259 if (key
->src_samples
== 1) {
1260 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1262 nir_ssa_def
*mcs
= NULL
;
1263 if (key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
)
1264 mcs
= blorp_blit_txf_ms_mcs(&b
, &v
, src_pos
);
1266 color
= blorp_nir_txf_ms(&b
, &v
, src_pos
, mcs
, key
->texture_data_type
);
1271 if (key
->dst_bpc
!= key
->src_bpc
)
1272 color
= bit_cast_color(&b
, color
, key
);
1275 /* The destination image is bound as a red texture three times as wide
1276 * as the actual image. Our shader is effectively running one color
1277 * component at a time. We need to pick off the appropriate component
1278 * from the source color and write that to destination red.
1280 assert(dst_pos
->num_components
== 2);
1282 nir_umod(&b
, nir_channel(&b
, dst_pos
, 0), nir_imm_int(&b
, 3));
1284 nir_ssa_def
*color_component
=
1285 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
1286 nir_channel(&b
, color
, 0),
1287 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
1288 nir_channel(&b
, color
, 1),
1289 nir_channel(&b
, color
, 2)));
1291 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
1292 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
1295 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1301 brw_blorp_get_blit_kernel(struct blorp_context
*blorp
,
1302 struct blorp_params
*params
,
1303 const struct brw_blorp_blit_prog_key
*prog_key
)
1305 if (blorp
->lookup_shader(blorp
, prog_key
, sizeof(*prog_key
),
1306 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1309 void *mem_ctx
= ralloc_context(NULL
);
1311 const unsigned *program
;
1312 struct brw_wm_prog_data prog_data
;
1314 nir_shader
*nir
= brw_blorp_build_nir_shader(blorp
, mem_ctx
, prog_key
);
1315 nir
->info
.name
= ralloc_strdup(nir
, "BLORP-blit");
1317 struct brw_wm_prog_key wm_key
;
1318 brw_blorp_init_wm_prog_key(&wm_key
);
1319 wm_key
.tex
.compressed_multisample_layout_mask
=
1320 prog_key
->tex_aux_usage
== ISL_AUX_USAGE_MCS
;
1321 wm_key
.tex
.msaa_16
= prog_key
->tex_samples
== 16;
1322 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
1324 program
= blorp_compile_fs(blorp
, mem_ctx
, nir
, &wm_key
, false,
1328 blorp
->upload_shader(blorp
, prog_key
, sizeof(*prog_key
),
1329 program
, prog_data
.base
.program_size
,
1330 &prog_data
.base
, sizeof(prog_data
),
1331 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1333 ralloc_free(mem_ctx
);
1338 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
1339 GLfloat src0
, GLfloat src1
,
1340 GLfloat dst0
, GLfloat dst1
,
1343 double scale
= (double)(src1
- src0
) / (double)(dst1
- dst0
);
1345 /* When not mirroring a coordinate (say, X), we need:
1346 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1348 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1350 * blorp program uses "round toward zero" to convert the
1351 * transformed floating point coordinates to integer coordinates,
1352 * whereas the behaviour we actually want is "round to nearest",
1353 * so 0.5 provides the necessary correction.
1355 xform
->multiplier
= scale
;
1356 xform
->offset
= src0
+ (-(double)dst0
+ 0.5) * scale
;
1358 /* When mirroring X we need:
1359 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1361 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1363 xform
->multiplier
= -scale
;
1364 xform
->offset
= src0
+ ((double)dst1
- 0.5) * scale
;
1369 surf_get_intratile_offset_px(struct brw_blorp_surface_info
*info
,
1370 uint32_t *tile_x_px
, uint32_t *tile_y_px
)
1372 if (info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1373 struct isl_extent2d px_size_sa
=
1374 isl_get_interleaved_msaa_px_size_sa(info
->surf
.samples
);
1375 assert(info
->tile_x_sa
% px_size_sa
.width
== 0);
1376 assert(info
->tile_y_sa
% px_size_sa
.height
== 0);
1377 *tile_x_px
= info
->tile_x_sa
/ px_size_sa
.width
;
1378 *tile_y_px
= info
->tile_y_sa
/ px_size_sa
.height
;
1380 *tile_x_px
= info
->tile_x_sa
;
1381 *tile_y_px
= info
->tile_y_sa
;
1386 blorp_surf_convert_to_single_slice(const struct isl_device
*isl_dev
,
1387 struct brw_blorp_surface_info
*info
)
1391 /* Just bail if we have nothing to do. */
1392 if (info
->surf
.dim
== ISL_SURF_DIM_2D
&&
1393 info
->view
.base_level
== 0 && info
->view
.base_array_layer
== 0 &&
1394 info
->surf
.levels
== 1 && info
->surf
.logical_level0_px
.array_len
== 1)
1397 /* If this gets triggered then we've gotten here twice which. This
1398 * shouldn't happen thanks to the above early return.
1400 assert(info
->tile_x_sa
== 0 && info
->tile_y_sa
== 0);
1402 uint32_t layer
= 0, z
= 0;
1403 if (info
->surf
.dim
== ISL_SURF_DIM_3D
)
1404 z
= info
->view
.base_array_layer
+ info
->z_offset
;
1406 layer
= info
->view
.base_array_layer
;
1408 uint32_t byte_offset
;
1409 isl_surf_get_image_surf(isl_dev
, &info
->surf
,
1410 info
->view
.base_level
, layer
, z
,
1412 &byte_offset
, &info
->tile_x_sa
, &info
->tile_y_sa
);
1413 info
->addr
.offset
+= byte_offset
;
1415 uint32_t tile_x_px
, tile_y_px
;
1416 surf_get_intratile_offset_px(info
, &tile_x_px
, &tile_y_px
);
1418 /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we place
1419 * the image at the tile boundary and offset our sampling or rendering.
1420 * For this reason, we need to grow the image by the offset to ensure that
1421 * the hardware doesn't think we've gone past the edge.
1423 info
->surf
.logical_level0_px
.w
+= tile_x_px
;
1424 info
->surf
.logical_level0_px
.h
+= tile_y_px
;
1425 info
->surf
.phys_level0_sa
.w
+= info
->tile_x_sa
;
1426 info
->surf
.phys_level0_sa
.h
+= info
->tile_y_sa
;
1428 /* The view is also different now. */
1429 info
->view
.base_level
= 0;
1430 info
->view
.levels
= 1;
1431 info
->view
.base_array_layer
= 0;
1432 info
->view
.array_len
= 1;
1437 surf_fake_interleaved_msaa(const struct isl_device
*isl_dev
,
1438 struct brw_blorp_surface_info
*info
)
1440 assert(info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1442 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1443 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1445 info
->surf
.logical_level0_px
= info
->surf
.phys_level0_sa
;
1446 info
->surf
.samples
= 1;
1447 info
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
1451 surf_retile_w_to_y(const struct isl_device
*isl_dev
,
1452 struct brw_blorp_surface_info
*info
)
1454 assert(info
->surf
.tiling
== ISL_TILING_W
);
1456 /* First, we need to convert it to a simple 1-level 1-layer 2-D surface */
1457 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1459 /* On gen7+, we don't have interleaved multisampling for color render
1460 * targets so we have to fake it.
1462 * TODO: Are we sure we don't also need to fake it on gen6?
1464 if (isl_dev
->info
->gen
> 6 &&
1465 info
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1466 surf_fake_interleaved_msaa(isl_dev
, info
);
1469 if (isl_dev
->info
->gen
== 6) {
1470 /* Gen6 stencil buffers have a very large alignment coming in from the
1471 * miptree. It's out-of-bounds for what the surface state can handle.
1472 * Since we have a single layer and level, it doesn't really matter as
1473 * long as we don't pass a bogus value into isl_surf_fill_state().
1475 info
->surf
.image_alignment_el
= isl_extent3d(4, 2, 1);
1478 /* Now that we've converted everything to a simple 2-D surface with only
1479 * one miplevel, we can go about retiling it.
1481 const unsigned x_align
= 8, y_align
= info
->surf
.samples
!= 0 ? 8 : 4;
1482 info
->surf
.tiling
= ISL_TILING_Y0
;
1483 info
->surf
.logical_level0_px
.width
=
1484 ALIGN(info
->surf
.logical_level0_px
.width
, x_align
) * 2;
1485 info
->surf
.logical_level0_px
.height
=
1486 ALIGN(info
->surf
.logical_level0_px
.height
, y_align
) / 2;
1487 info
->tile_x_sa
*= 2;
1488 info
->tile_y_sa
/= 2;
1492 can_shrink_surface(const struct brw_blorp_surface_info
*surf
)
1494 /* The current code doesn't support offsets into the aux buffers. This
1495 * should be possible, but we need to make sure the offset is page
1496 * aligned for both the surface and the aux buffer surface. Generally
1497 * this mean using the page aligned offset for the aux buffer.
1499 * Currently the cases where we must split the blit are limited to cases
1500 * where we don't have a aux buffer.
1502 if (surf
->aux_addr
.buffer
!= NULL
)
1505 /* We can't support splitting the blit for gen <= 7, because the qpitch
1506 * size is calculated by the hardware based on the surface height for
1507 * gen <= 7. In gen >= 8, the qpitch is controlled by the driver.
1509 if (surf
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1516 can_shrink_surfaces(const struct blorp_params
*params
)
1519 can_shrink_surface(¶ms
->src
) &&
1520 can_shrink_surface(¶ms
->dst
);
1524 get_max_surface_size(const struct gen_device_info
*devinfo
,
1525 const struct blorp_params
*params
)
1527 const unsigned max
= devinfo
->gen
>= 7 ? 16384 : 8192;
1528 if (split_blorp_blit_debug
&& can_shrink_surfaces(params
))
1529 return max
>> 4; /* A smaller restriction when debug is enabled */
1535 double src0
, src1
, dst0
, dst1
;
1540 struct blt_axis x
, y
;
1544 surf_fake_rgb_with_red(const struct isl_device
*isl_dev
,
1545 struct brw_blorp_surface_info
*info
,
1546 uint32_t *x
, uint32_t *width
)
1548 blorp_surf_convert_to_single_slice(isl_dev
, info
);
1550 info
->surf
.logical_level0_px
.width
*= 3;
1551 info
->surf
.phys_level0_sa
.width
*= 3;
1552 info
->tile_x_sa
*= 3;
1556 enum isl_format red_format
;
1557 switch (info
->view
.format
) {
1558 case ISL_FORMAT_R8G8B8_UNORM
:
1559 red_format
= ISL_FORMAT_R8_UNORM
;
1561 case ISL_FORMAT_R8G8B8_UINT
:
1562 red_format
= ISL_FORMAT_R8_UINT
;
1564 case ISL_FORMAT_R16G16B16_UNORM
:
1565 red_format
= ISL_FORMAT_R16_UNORM
;
1567 case ISL_FORMAT_R16G16B16_UINT
:
1568 red_format
= ISL_FORMAT_R16_UINT
;
1570 case ISL_FORMAT_R32G32B32_UINT
:
1571 red_format
= ISL_FORMAT_R32_UINT
;
1574 unreachable("Invalid RGB copy destination format");
1576 assert(isl_format_get_layout(red_format
)->channels
.r
.type
==
1577 isl_format_get_layout(info
->view
.format
)->channels
.r
.type
);
1578 assert(isl_format_get_layout(red_format
)->channels
.r
.bits
==
1579 isl_format_get_layout(info
->view
.format
)->channels
.r
.bits
);
1581 info
->surf
.format
= info
->view
.format
= red_format
;
1585 fake_dest_rgb_with_red(const struct isl_device
*dev
,
1586 struct blorp_params
*params
,
1587 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1588 struct blt_coords
*coords
)
1590 /* Handle RGB destinations for blorp_copy */
1591 const struct isl_format_layout
*dst_fmtl
=
1592 isl_format_get_layout(params
->dst
.surf
.format
);
1594 if (dst_fmtl
->bpb
% 3 == 0) {
1595 uint32_t dst_x
= coords
->x
.dst0
;
1596 uint32_t dst_width
= coords
->x
.dst1
- dst_x
;
1597 surf_fake_rgb_with_red(dev
, ¶ms
->dst
,
1598 &dst_x
, &dst_width
);
1599 coords
->x
.dst0
= dst_x
;
1600 coords
->x
.dst1
= dst_x
+ dst_width
;
1601 wm_prog_key
->dst_rgb
= true;
1602 wm_prog_key
->need_dst_offset
= true;
1606 enum blit_shrink_status
{
1608 BLIT_WIDTH_SHRINK
= 1,
1609 BLIT_HEIGHT_SHRINK
= 2,
1612 /* Try to blit. If the surface parameters exceed the size allowed by hardware,
1613 * then enum blit_shrink_status will be returned. If BLIT_NO_SHRINK is
1614 * returned, then the blit was successful.
1616 static enum blit_shrink_status
1617 try_blorp_blit(struct blorp_batch
*batch
,
1618 struct blorp_params
*params
,
1619 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1620 struct blt_coords
*coords
)
1622 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
1624 fake_dest_rgb_with_red(batch
->blorp
->isl_dev
, params
, wm_prog_key
, coords
);
1626 if (isl_format_has_sint_channel(params
->src
.view
.format
)) {
1627 wm_prog_key
->texture_data_type
= nir_type_int
;
1628 } else if (isl_format_has_uint_channel(params
->src
.view
.format
)) {
1629 wm_prog_key
->texture_data_type
= nir_type_uint
;
1631 wm_prog_key
->texture_data_type
= nir_type_float
;
1634 /* src_samples and dst_samples are the true sample counts */
1635 wm_prog_key
->src_samples
= params
->src
.surf
.samples
;
1636 wm_prog_key
->dst_samples
= params
->dst
.surf
.samples
;
1638 wm_prog_key
->tex_aux_usage
= params
->src
.aux_usage
;
1640 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1643 wm_prog_key
->src_layout
= params
->src
.surf
.msaa_layout
;
1644 wm_prog_key
->dst_layout
= params
->dst
.surf
.msaa_layout
;
1646 /* Round floating point values to nearest integer to avoid "off by one texel"
1647 * kind of errors when blitting.
1649 params
->x0
= params
->wm_inputs
.discard_rect
.x0
= round(coords
->x
.dst0
);
1650 params
->y0
= params
->wm_inputs
.discard_rect
.y0
= round(coords
->y
.dst0
);
1651 params
->x1
= params
->wm_inputs
.discard_rect
.x1
= round(coords
->x
.dst1
);
1652 params
->y1
= params
->wm_inputs
.discard_rect
.y1
= round(coords
->y
.dst1
);
1654 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[0],
1655 coords
->x
.src0
, coords
->x
.src1
,
1656 coords
->x
.dst0
, coords
->x
.dst1
,
1658 brw_blorp_setup_coord_transform(¶ms
->wm_inputs
.coord_transform
[1],
1659 coords
->y
.src0
, coords
->y
.src1
,
1660 coords
->y
.dst0
, coords
->y
.dst1
,
1664 if (devinfo
->gen
== 4) {
1665 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
1666 * Convert them to a single slice on gen4.
1668 if (params
->dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1669 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1670 wm_prog_key
->need_dst_offset
= true;
1673 if (params
->src
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
) {
1674 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
->src
);
1675 wm_prog_key
->need_src_offset
= true;
1679 if (devinfo
->gen
> 6 &&
1680 params
->dst
.surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
1681 assert(params
->dst
.surf
.samples
> 1);
1683 /* We must expand the rectangle we send through the rendering pipeline,
1684 * to account for the fact that we are mapping the destination region as
1685 * single-sampled when it is in fact multisampled. We must also align
1686 * it to a multiple of the multisampling pattern, because the
1687 * differences between multisampled and single-sampled surface formats
1688 * will mean that pixels are scrambled within the multisampling pattern.
1689 * TODO: what if this makes the coordinates too large?
1691 * Note: this only works if the destination surface uses the IMS layout.
1692 * If it's UMS, then we have no choice but to set up the rendering
1693 * pipeline as multisampled.
1695 struct isl_extent2d px_size_sa
=
1696 isl_get_interleaved_msaa_px_size_sa(params
->dst
.surf
.samples
);
1697 params
->x0
= ROUND_DOWN_TO(params
->x0
, 2) * px_size_sa
.width
;
1698 params
->y0
= ROUND_DOWN_TO(params
->y0
, 2) * px_size_sa
.height
;
1699 params
->x1
= ALIGN(params
->x1
, 2) * px_size_sa
.width
;
1700 params
->y1
= ALIGN(params
->y1
, 2) * px_size_sa
.height
;
1702 surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1704 wm_prog_key
->use_kill
= true;
1705 wm_prog_key
->need_dst_offset
= true;
1708 if (params
->dst
.surf
.tiling
== ISL_TILING_W
) {
1709 /* We must modify the rectangle we send through the rendering pipeline
1710 * (and the size and x/y offset of the destination surface), to account
1711 * for the fact that we are mapping it as Y-tiled when it is in fact
1714 * Both Y tiling and W tiling can be understood as organizations of
1715 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1716 * is different, but the layout of the 32-byte sub-tiles within the 4k
1717 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1718 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1719 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1721 * Therefore, to account for the layout differences within the 32-byte
1722 * sub-tiles, we must expand the rectangle so the X coordinates of its
1723 * edges are multiples of 8 (the W sub-tile width), and its Y
1724 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1725 * Then we need to scale the X and Y coordinates of the rectangle to
1726 * account for the differences in aspect ratio between the Y and W
1727 * sub-tiles. We need to modify the layer width and height similarly.
1729 * A correction needs to be applied when MSAA is in use: since
1730 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1731 * we need to align the Y coordinates to multiples of 8, so that when
1732 * they are divided by two they are still multiples of 4.
1734 * Note: Since the x/y offset of the surface will be applied using the
1735 * SURFACE_STATE command packet, it will be invisible to the swizzling
1736 * code in the shader; therefore it needs to be in a multiple of the
1737 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1738 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1739 * buffer), and the miplevel alignment used for stencil buffers is 8
1740 * pixels horizontally and either 4 or 8 pixels vertically (see
1741 * intel_horizontal_texture_alignment_unit() and
1742 * intel_vertical_texture_alignment_unit()).
1744 * Note: Also, since the SURFACE_STATE command packet can only apply
1745 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1746 * vertically, it is important that the offsets will be multiples of
1747 * these sizes after they are converted into Y-tiled coordinates.
1748 * Fortunately they will be, since we know from above that the offsets
1749 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1750 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1752 * TODO: what if this makes the coordinates (or the texture size) too
1755 const unsigned x_align
= 8;
1756 const unsigned y_align
= params
->dst
.surf
.samples
!= 0 ? 8 : 4;
1757 params
->x0
= ROUND_DOWN_TO(params
->x0
, x_align
) * 2;
1758 params
->y0
= ROUND_DOWN_TO(params
->y0
, y_align
) / 2;
1759 params
->x1
= ALIGN(params
->x1
, x_align
) * 2;
1760 params
->y1
= ALIGN(params
->y1
, y_align
) / 2;
1762 /* Retile the surface to Y-tiled */
1763 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->dst
);
1765 wm_prog_key
->dst_tiled_w
= true;
1766 wm_prog_key
->use_kill
= true;
1767 wm_prog_key
->need_dst_offset
= true;
1769 if (params
->dst
.surf
.samples
> 1) {
1770 /* If the destination surface is a W-tiled multisampled stencil
1771 * buffer that we're mapping as Y tiled, then we need to arrange for
1772 * the WM program to run once per sample rather than once per pixel,
1773 * because the memory layout of related samples doesn't match between
1776 wm_prog_key
->persample_msaa_dispatch
= true;
1780 if (devinfo
->gen
< 8 && params
->src
.surf
.tiling
== ISL_TILING_W
) {
1781 /* On Haswell and earlier, we have to fake W-tiled sources as Y-tiled.
1782 * Broadwell adds support for sampling from stencil.
1784 * See the comments above concerning x/y offset alignment for the
1785 * destination surface.
1787 * TODO: what if this makes the texture size too large?
1789 surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
->src
);
1791 wm_prog_key
->src_tiled_w
= true;
1792 wm_prog_key
->need_src_offset
= true;
1795 /* tex_samples and rt_samples are the sample counts that are set up in
1798 wm_prog_key
->tex_samples
= params
->src
.surf
.samples
;
1799 wm_prog_key
->rt_samples
= params
->dst
.surf
.samples
;
1801 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1802 * use to access the source and destination surfaces.
1804 wm_prog_key
->tex_layout
= params
->src
.surf
.msaa_layout
;
1805 wm_prog_key
->rt_layout
= params
->dst
.surf
.msaa_layout
;
1807 if (params
->src
.surf
.samples
> 0 && params
->dst
.surf
.samples
> 1) {
1808 /* We are blitting from a multisample buffer to a multisample buffer, so
1809 * we must preserve samples within a pixel. This means we have to
1810 * arrange for the WM program to run once per sample rather than once
1813 wm_prog_key
->persample_msaa_dispatch
= true;
1816 params
->num_samples
= params
->dst
.surf
.samples
;
1818 if ((wm_prog_key
->bilinear_filter
||
1819 (wm_prog_key
->blend
&& !wm_prog_key
->blit_scaled
)) &&
1820 batch
->blorp
->isl_dev
->info
->gen
<= 6) {
1821 /* Gen4-5 don't support non-normalized texture coordinates */
1822 wm_prog_key
->src_coords_normalized
= true;
1823 params
->wm_inputs
.src_inv_size
[0] =
1824 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.width
,
1825 params
->src
.view
.base_level
);
1826 params
->wm_inputs
.src_inv_size
[1] =
1827 1.0f
/ minify(params
->src
.surf
.logical_level0_px
.height
,
1828 params
->src
.view
.base_level
);
1831 if (params
->src
.tile_x_sa
|| params
->src
.tile_y_sa
) {
1832 assert(wm_prog_key
->need_src_offset
);
1833 surf_get_intratile_offset_px(¶ms
->src
,
1834 ¶ms
->wm_inputs
.src_offset
.x
,
1835 ¶ms
->wm_inputs
.src_offset
.y
);
1838 if (params
->dst
.tile_x_sa
|| params
->dst
.tile_y_sa
) {
1839 assert(wm_prog_key
->need_dst_offset
);
1840 surf_get_intratile_offset_px(¶ms
->dst
,
1841 ¶ms
->wm_inputs
.dst_offset
.x
,
1842 ¶ms
->wm_inputs
.dst_offset
.y
);
1843 params
->x0
+= params
->wm_inputs
.dst_offset
.x
;
1844 params
->y0
+= params
->wm_inputs
.dst_offset
.y
;
1845 params
->x1
+= params
->wm_inputs
.dst_offset
.x
;
1846 params
->y1
+= params
->wm_inputs
.dst_offset
.y
;
1849 /* For some texture types, we need to pass the layer through the sampler. */
1850 params
->wm_inputs
.src_z
= params
->src
.z_offset
;
1852 if (!brw_blorp_get_blit_kernel(batch
->blorp
, params
, wm_prog_key
))
1855 if (!blorp_ensure_sf_program(batch
->blorp
, params
))
1858 unsigned result
= 0;
1859 unsigned max_surface_size
= get_max_surface_size(devinfo
, params
);
1860 if (params
->src
.surf
.logical_level0_px
.width
> max_surface_size
||
1861 params
->dst
.surf
.logical_level0_px
.width
> max_surface_size
)
1862 result
|= BLIT_WIDTH_SHRINK
;
1863 if (params
->src
.surf
.logical_level0_px
.height
> max_surface_size
||
1864 params
->dst
.surf
.logical_level0_px
.height
> max_surface_size
)
1865 result
|= BLIT_HEIGHT_SHRINK
;
1868 batch
->blorp
->exec(batch
, params
);
1874 /* Adjust split blit source coordinates for the current destination
1878 adjust_split_source_coords(const struct blt_axis
*orig
,
1879 struct blt_axis
*split_coords
,
1882 /* When scale is greater than 0, then we are growing from the start, so
1883 * src0 uses delta0, and src1 uses delta1. When scale is less than 0, the
1884 * source range shrinks from the end. In that case src0 is adjusted by
1885 * delta1, and src1 is adjusted by delta0.
1887 double delta0
= scale
* (split_coords
->dst0
- orig
->dst0
);
1888 double delta1
= scale
* (split_coords
->dst1
- orig
->dst1
);
1889 split_coords
->src0
= orig
->src0
+ (scale
>= 0.0 ? delta0
: delta1
);
1890 split_coords
->src1
= orig
->src1
+ (scale
>= 0.0 ? delta1
: delta0
);
1893 static struct isl_extent2d
1894 get_px_size_sa(const struct isl_surf
*surf
)
1896 static const struct isl_extent2d one_to_one
= { .w
= 1, .h
= 1 };
1898 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
)
1901 return isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
1905 shrink_surface_params(const struct isl_device
*dev
,
1906 struct brw_blorp_surface_info
*info
,
1907 double *x0
, double *x1
, double *y0
, double *y1
)
1909 uint32_t byte_offset
, x_offset_sa
, y_offset_sa
, size
;
1910 struct isl_extent2d px_size_sa
;
1913 blorp_surf_convert_to_single_slice(dev
, info
);
1915 px_size_sa
= get_px_size_sa(&info
->surf
);
1917 /* Because this gets called after we lower compressed images, the tile
1918 * offsets may be non-zero and we need to incorporate them in our
1921 x_offset_sa
= (uint32_t)*x0
* px_size_sa
.w
+ info
->tile_x_sa
;
1922 y_offset_sa
= (uint32_t)*y0
* px_size_sa
.h
+ info
->tile_y_sa
;
1923 isl_tiling_get_intratile_offset_sa(info
->surf
.tiling
,
1924 info
->surf
.format
, info
->surf
.row_pitch
,
1925 x_offset_sa
, y_offset_sa
,
1927 &info
->tile_x_sa
, &info
->tile_y_sa
);
1929 info
->addr
.offset
+= byte_offset
;
1931 adjust
= (int)info
->tile_x_sa
/ px_size_sa
.w
- (int)*x0
;
1934 info
->tile_x_sa
= 0;
1936 adjust
= (int)info
->tile_y_sa
/ px_size_sa
.h
- (int)*y0
;
1939 info
->tile_y_sa
= 0;
1941 size
= MIN2((uint32_t)ceil(*x1
), info
->surf
.logical_level0_px
.width
);
1942 info
->surf
.logical_level0_px
.width
= size
;
1943 info
->surf
.phys_level0_sa
.width
= size
* px_size_sa
.w
;
1945 size
= MIN2((uint32_t)ceil(*y1
), info
->surf
.logical_level0_px
.height
);
1946 info
->surf
.logical_level0_px
.height
= size
;
1947 info
->surf
.phys_level0_sa
.height
= size
* px_size_sa
.h
;
1951 shrink_surfaces(const struct isl_device
*dev
,
1952 struct blorp_params
*params
,
1953 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1954 struct blt_coords
*coords
)
1956 /* Shrink source surface */
1957 shrink_surface_params(dev
, ¶ms
->src
, &coords
->x
.src0
, &coords
->x
.src1
,
1958 &coords
->y
.src0
, &coords
->y
.src1
);
1959 wm_prog_key
->need_src_offset
= false;
1961 /* Shrink destination surface */
1962 shrink_surface_params(dev
, ¶ms
->dst
, &coords
->x
.dst0
, &coords
->x
.dst1
,
1963 &coords
->y
.dst0
, &coords
->y
.dst1
);
1964 wm_prog_key
->need_dst_offset
= false;
1968 do_blorp_blit(struct blorp_batch
*batch
,
1969 const struct blorp_params
*orig_params
,
1970 struct brw_blorp_blit_prog_key
*wm_prog_key
,
1971 const struct blt_coords
*orig
)
1973 struct blorp_params params
;
1974 struct blt_coords blit_coords
;
1975 struct blt_coords split_coords
= *orig
;
1976 double w
= orig
->x
.dst1
- orig
->x
.dst0
;
1977 double h
= orig
->y
.dst1
- orig
->y
.dst0
;
1978 double x_scale
= (orig
->x
.src1
- orig
->x
.src0
) / w
;
1979 double y_scale
= (orig
->y
.src1
- orig
->y
.src0
) / h
;
1985 bool x_done
, y_done
;
1986 bool shrink
= split_blorp_blit_debug
&& can_shrink_surfaces(orig_params
);
1988 params
= *orig_params
;
1989 blit_coords
= split_coords
;
1991 shrink_surfaces(batch
->blorp
->isl_dev
, ¶ms
, wm_prog_key
,
1993 enum blit_shrink_status result
=
1994 try_blorp_blit(batch
, ¶ms
, wm_prog_key
, &blit_coords
);
1996 if (result
& BLIT_WIDTH_SHRINK
) {
1999 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2000 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2002 if (result
& BLIT_HEIGHT_SHRINK
) {
2005 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2006 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2010 assert(can_shrink_surfaces(orig_params
));
2015 y_done
= (orig
->y
.dst1
- split_coords
.y
.dst1
< 0.5);
2016 x_done
= y_done
&& (orig
->x
.dst1
- split_coords
.x
.dst1
< 0.5);
2019 } else if (y_done
) {
2020 split_coords
.x
.dst0
+= w
;
2021 split_coords
.x
.dst1
= MIN2(split_coords
.x
.dst0
+ w
, orig
->x
.dst1
);
2022 split_coords
.y
.dst0
= orig
->y
.dst0
;
2023 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2024 adjust_split_source_coords(&orig
->x
, &split_coords
.x
, x_scale
);
2026 split_coords
.y
.dst0
+= h
;
2027 split_coords
.y
.dst1
= MIN2(split_coords
.y
.dst0
+ h
, orig
->y
.dst1
);
2028 adjust_split_source_coords(&orig
->y
, &split_coords
.y
, y_scale
);
2034 blorp_blit(struct blorp_batch
*batch
,
2035 const struct blorp_surf
*src_surf
,
2036 unsigned src_level
, unsigned src_layer
,
2037 enum isl_format src_format
, struct isl_swizzle src_swizzle
,
2038 const struct blorp_surf
*dst_surf
,
2039 unsigned dst_level
, unsigned dst_layer
,
2040 enum isl_format dst_format
, struct isl_swizzle dst_swizzle
,
2041 float src_x0
, float src_y0
,
2042 float src_x1
, float src_y1
,
2043 float dst_x0
, float dst_y0
,
2044 float dst_x1
, float dst_y1
,
2045 GLenum filter
, bool mirror_x
, bool mirror_y
)
2047 struct blorp_params params
;
2048 blorp_params_init(¶ms
);
2050 /* We cannot handle combined depth and stencil. */
2051 if (src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2052 assert(src_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2053 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
2054 assert(dst_surf
->surf
->format
== ISL_FORMAT_R8_UINT
);
2056 if (dst_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) {
2057 assert(src_surf
->surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
);
2058 /* Prior to Broadwell, we can't render to R8_UINT */
2059 if (batch
->blorp
->isl_dev
->info
->gen
< 8) {
2060 src_format
= ISL_FORMAT_R8_UNORM
;
2061 dst_format
= ISL_FORMAT_R8_UNORM
;
2065 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2066 src_layer
, src_format
, false);
2067 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2068 dst_layer
, dst_format
, true);
2070 params
.src
.view
.swizzle
= src_swizzle
;
2071 params
.dst
.view
.swizzle
= dst_swizzle
;
2073 struct brw_blorp_blit_prog_key wm_prog_key
= {
2074 .shader_type
= BLORP_SHADER_TYPE_BLIT
2077 /* Scaled blitting or not. */
2078 wm_prog_key
.blit_scaled
=
2079 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2080 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2082 /* Scaling factors used for bilinear filtering in multisample scaled
2085 if (params
.src
.surf
.samples
== 16)
2086 wm_prog_key
.x_scale
= 4.0f
;
2088 wm_prog_key
.x_scale
= 2.0f
;
2089 wm_prog_key
.y_scale
= params
.src
.surf
.samples
/ wm_prog_key
.x_scale
;
2091 if (filter
== GL_LINEAR
&&
2092 params
.src
.surf
.samples
<= 1 && params
.dst
.surf
.samples
<= 1) {
2093 wm_prog_key
.bilinear_filter
= true;
2096 if ((params
.src
.surf
.usage
& ISL_SURF_USAGE_DEPTH_BIT
) == 0 &&
2097 (params
.src
.surf
.usage
& ISL_SURF_USAGE_STENCIL_BIT
) == 0 &&
2098 !isl_format_has_int_channel(params
.src
.surf
.format
) &&
2099 params
.src
.surf
.samples
> 1 && params
.dst
.surf
.samples
<= 1) {
2100 /* We are downsampling a non-integer color buffer, so blend.
2102 * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
2104 * "If the source formats are integer types or stencil values, a
2105 * single sample's value is selected for each pixel."
2107 * This implies we should not blend in that case.
2109 wm_prog_key
.blend
= true;
2112 params
.wm_inputs
.rect_grid
.x1
=
2113 minify(params
.src
.surf
.logical_level0_px
.width
, src_level
) *
2114 wm_prog_key
.x_scale
- 1.0f
;
2115 params
.wm_inputs
.rect_grid
.y1
=
2116 minify(params
.src
.surf
.logical_level0_px
.height
, src_level
) *
2117 wm_prog_key
.y_scale
- 1.0f
;
2119 struct blt_coords coords
= {
2136 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2139 static enum isl_format
2140 get_copy_format_for_bpb(const struct isl_device
*isl_dev
, unsigned bpb
)
2142 /* The choice of UNORM and UINT formats is very intentional here. Most
2143 * of the time, we want to use a UINT format to avoid any rounding error
2144 * in the blit. For stencil blits, R8_UINT is required by the hardware.
2145 * (It's the only format allowed in conjunction with W-tiling.) Also we
2146 * intentionally use the 4-channel formats whenever we can. This is so
2147 * that, when we do a RGB <-> RGBX copy, the two formats will line up
2148 * even though one of them is 3/4 the size of the other. The choice of
2149 * UNORM vs. UINT is also very intentional because we don't have 8 or
2150 * 16-bit RGB UINT formats until Sky Lake so we have to use UNORM there.
2151 * Fortunately, the only time we should ever use two different formats in
2152 * the table below is for RGB -> RGBA blits and so we will never have any
2153 * UNORM/UINT mismatch.
2155 if (ISL_DEV_GEN(isl_dev
) >= 9) {
2157 case 8: return ISL_FORMAT_R8_UINT
;
2158 case 16: return ISL_FORMAT_R8G8_UINT
;
2159 case 24: return ISL_FORMAT_R8G8B8_UINT
;
2160 case 32: return ISL_FORMAT_R8G8B8A8_UINT
;
2161 case 48: return ISL_FORMAT_R16G16B16_UINT
;
2162 case 64: return ISL_FORMAT_R16G16B16A16_UINT
;
2163 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2164 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2166 unreachable("Unknown format bpb");
2170 case 8: return ISL_FORMAT_R8_UINT
;
2171 case 16: return ISL_FORMAT_R8G8_UINT
;
2172 case 24: return ISL_FORMAT_R8G8B8_UNORM
;
2173 case 32: return ISL_FORMAT_R8G8B8A8_UNORM
;
2174 case 48: return ISL_FORMAT_R16G16B16_UNORM
;
2175 case 64: return ISL_FORMAT_R16G16B16A16_UNORM
;
2176 case 96: return ISL_FORMAT_R32G32B32_UINT
;
2177 case 128:return ISL_FORMAT_R32G32B32A32_UINT
;
2179 unreachable("Unknown format bpb");
2184 /** Returns a UINT format that is CCS-compatible with the given format
2186 * The PRM's say absolutely nothing about how render compression works. The
2187 * only thing they provide is a list of formats on which it is and is not
2188 * supported. Empirical testing indicates that the compression is only based
2189 * on the bit-layout of the format and the channel encoding doesn't matter.
2190 * So, while texture views don't work in general, you can create a view as
2191 * long as the bit-layout of the formats are the same.
2193 * Fortunately, for every render compression capable format, the UINT format
2194 * with the same bit layout also supports render compression. This means that
2195 * we only need to handle UINT formats for copy operations. In order to do
2196 * copies between formats with different bit layouts, we attach both with a
2197 * UINT format and use bit_cast_color() to generate code to do the bit-cast
2198 * operation between the two bit layouts.
2200 static enum isl_format
2201 get_ccs_compatible_uint_format(const struct isl_format_layout
*fmtl
)
2203 switch (fmtl
->format
) {
2204 case ISL_FORMAT_R32G32B32A32_FLOAT
:
2205 case ISL_FORMAT_R32G32B32A32_SINT
:
2206 case ISL_FORMAT_R32G32B32A32_UINT
:
2207 case ISL_FORMAT_R32G32B32A32_UNORM
:
2208 case ISL_FORMAT_R32G32B32A32_SNORM
:
2209 case ISL_FORMAT_R32G32B32X32_FLOAT
:
2210 return ISL_FORMAT_R32G32B32A32_UINT
;
2212 case ISL_FORMAT_R16G16B16A16_UNORM
:
2213 case ISL_FORMAT_R16G16B16A16_SNORM
:
2214 case ISL_FORMAT_R16G16B16A16_SINT
:
2215 case ISL_FORMAT_R16G16B16A16_UINT
:
2216 case ISL_FORMAT_R16G16B16A16_FLOAT
:
2217 case ISL_FORMAT_R16G16B16X16_UNORM
:
2218 case ISL_FORMAT_R16G16B16X16_FLOAT
:
2219 return ISL_FORMAT_R16G16B16A16_UINT
;
2221 case ISL_FORMAT_R32G32_FLOAT
:
2222 case ISL_FORMAT_R32G32_SINT
:
2223 case ISL_FORMAT_R32G32_UINT
:
2224 case ISL_FORMAT_R32G32_UNORM
:
2225 case ISL_FORMAT_R32G32_SNORM
:
2226 return ISL_FORMAT_R32G32_UINT
;
2228 case ISL_FORMAT_B8G8R8A8_UNORM
:
2229 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2230 case ISL_FORMAT_R8G8B8A8_UNORM
:
2231 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
:
2232 case ISL_FORMAT_R8G8B8A8_SNORM
:
2233 case ISL_FORMAT_R8G8B8A8_SINT
:
2234 case ISL_FORMAT_R8G8B8A8_UINT
:
2235 case ISL_FORMAT_B8G8R8X8_UNORM
:
2236 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
:
2237 case ISL_FORMAT_R8G8B8X8_UNORM
:
2238 case ISL_FORMAT_R8G8B8X8_UNORM_SRGB
:
2239 return ISL_FORMAT_R8G8B8A8_UINT
;
2241 case ISL_FORMAT_R16G16_UNORM
:
2242 case ISL_FORMAT_R16G16_SNORM
:
2243 case ISL_FORMAT_R16G16_SINT
:
2244 case ISL_FORMAT_R16G16_UINT
:
2245 case ISL_FORMAT_R16G16_FLOAT
:
2246 return ISL_FORMAT_R16G16_UINT
;
2248 case ISL_FORMAT_R32_SINT
:
2249 case ISL_FORMAT_R32_UINT
:
2250 case ISL_FORMAT_R32_FLOAT
:
2251 case ISL_FORMAT_R32_UNORM
:
2252 case ISL_FORMAT_R32_SNORM
:
2253 return ISL_FORMAT_R32_UINT
;
2256 unreachable("Not a compressible format");
2260 /* Takes an isl_color_value and returns a color value that is the original
2261 * color value only bit-casted to a UINT format. This value, together with
2262 * the format from get_ccs_compatible_uint_format, will yield the same bit
2263 * value as the original color and format.
2265 static union isl_color_value
2266 bitcast_color_value_to_uint(union isl_color_value color
,
2267 const struct isl_format_layout
*fmtl
)
2269 /* All CCS formats have the same number of bits in each channel */
2270 const struct isl_channel_layout
*chan
= &fmtl
->channels
.r
;
2272 union isl_color_value bits
;
2273 switch (chan
->type
) {
2276 /* Hardware will ignore the high bits so there's no need to cast */
2281 for (unsigned i
= 0; i
< 4; i
++)
2282 bits
.u32
[i
] = _mesa_float_to_unorm(color
.f32
[i
], chan
->bits
);
2286 for (unsigned i
= 0; i
< 4; i
++)
2287 bits
.i32
[i
] = _mesa_float_to_snorm(color
.f32
[i
], chan
->bits
);
2291 switch (chan
->bits
) {
2293 for (unsigned i
= 0; i
< 4; i
++)
2294 bits
.u32
[i
] = _mesa_float_to_half(color
.f32
[i
]);
2302 unreachable("Invalid float format size");
2307 unreachable("Invalid channel type");
2310 switch (fmtl
->format
) {
2311 case ISL_FORMAT_B8G8R8A8_UNORM
:
2312 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
:
2313 case ISL_FORMAT_B8G8R8X8_UNORM
:
2314 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
: {
2315 /* If it's a BGRA format, we need to swap blue and red */
2316 uint32_t tmp
= bits
.u32
[0];
2317 bits
.u32
[0] = bits
.u32
[2];
2323 break; /* Nothing to do */
2330 blorp_surf_convert_to_uncompressed(const struct isl_device
*isl_dev
,
2331 struct brw_blorp_surface_info
*info
,
2332 uint32_t *x
, uint32_t *y
,
2333 uint32_t *width
, uint32_t *height
)
2335 const struct isl_format_layout
*fmtl
=
2336 isl_format_get_layout(info
->surf
.format
);
2338 assert(fmtl
->bw
> 1 || fmtl
->bh
> 1);
2340 /* This is a compressed surface. We need to convert it to a single
2341 * slice (because compressed layouts don't perfectly match uncompressed
2342 * ones with the same bpb) and divide x, y, width, and height by the
2345 blorp_surf_convert_to_single_slice(isl_dev
, info
);
2347 if (width
|| height
) {
2349 uint32_t right_edge_px
= info
->tile_x_sa
+ *x
+ *width
;
2350 uint32_t bottom_edge_px
= info
->tile_y_sa
+ *y
+ *height
;
2351 assert(*width
% fmtl
->bw
== 0 ||
2352 right_edge_px
== info
->surf
.logical_level0_px
.width
);
2353 assert(*height
% fmtl
->bh
== 0 ||
2354 bottom_edge_px
== info
->surf
.logical_level0_px
.height
);
2356 *width
= DIV_ROUND_UP(*width
, fmtl
->bw
);
2357 *height
= DIV_ROUND_UP(*height
, fmtl
->bh
);
2361 assert(*x
% fmtl
->bw
== 0);
2362 assert(*y
% fmtl
->bh
== 0);
2367 info
->surf
.logical_level0_px
.width
=
2368 DIV_ROUND_UP(info
->surf
.logical_level0_px
.width
, fmtl
->bw
);
2369 info
->surf
.logical_level0_px
.height
=
2370 DIV_ROUND_UP(info
->surf
.logical_level0_px
.height
, fmtl
->bh
);
2372 assert(info
->surf
.phys_level0_sa
.width
% fmtl
->bw
== 0);
2373 assert(info
->surf
.phys_level0_sa
.height
% fmtl
->bh
== 0);
2374 info
->surf
.phys_level0_sa
.width
/= fmtl
->bw
;
2375 info
->surf
.phys_level0_sa
.height
/= fmtl
->bh
;
2377 assert(info
->tile_x_sa
% fmtl
->bw
== 0);
2378 assert(info
->tile_y_sa
% fmtl
->bh
== 0);
2379 info
->tile_x_sa
/= fmtl
->bw
;
2380 info
->tile_y_sa
/= fmtl
->bh
;
2382 /* It's now an uncompressed surface so we need an uncompressed format */
2383 info
->surf
.format
= get_copy_format_for_bpb(isl_dev
, fmtl
->bpb
);
2387 blorp_copy(struct blorp_batch
*batch
,
2388 const struct blorp_surf
*src_surf
,
2389 unsigned src_level
, unsigned src_layer
,
2390 const struct blorp_surf
*dst_surf
,
2391 unsigned dst_level
, unsigned dst_layer
,
2392 uint32_t src_x
, uint32_t src_y
,
2393 uint32_t dst_x
, uint32_t dst_y
,
2394 uint32_t src_width
, uint32_t src_height
)
2396 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
2397 struct blorp_params params
;
2399 if (src_width
== 0 || src_height
== 0)
2402 blorp_params_init(¶ms
);
2403 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, src_surf
, src_level
,
2404 src_layer
, ISL_FORMAT_UNSUPPORTED
, false);
2405 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, dst_surf
, dst_level
,
2406 dst_layer
, ISL_FORMAT_UNSUPPORTED
, true);
2408 struct brw_blorp_blit_prog_key wm_prog_key
= {
2409 .shader_type
= BLORP_SHADER_TYPE_BLIT
2412 const struct isl_format_layout
*src_fmtl
=
2413 isl_format_get_layout(params
.src
.surf
.format
);
2414 const struct isl_format_layout
*dst_fmtl
=
2415 isl_format_get_layout(params
.dst
.surf
.format
);
2417 assert(params
.src
.aux_usage
== ISL_AUX_USAGE_NONE
||
2418 params
.src
.aux_usage
== ISL_AUX_USAGE_MCS
||
2419 params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2420 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
||
2421 params
.dst
.aux_usage
== ISL_AUX_USAGE_MCS
||
2422 params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
2424 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2425 params
.dst
.view
.format
= get_ccs_compatible_uint_format(dst_fmtl
);
2426 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2427 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2428 } else if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2429 params
.src
.view
.format
= params
.dst
.view
.format
;
2431 params
.src
.view
.format
=
2432 get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2434 } else if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2435 params
.src
.view
.format
= get_ccs_compatible_uint_format(src_fmtl
);
2436 if (src_fmtl
->bpb
== dst_fmtl
->bpb
) {
2437 params
.dst
.view
.format
= params
.src
.view
.format
;
2439 params
.dst
.view
.format
=
2440 get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2443 params
.dst
.view
.format
= get_copy_format_for_bpb(isl_dev
, dst_fmtl
->bpb
);
2444 params
.src
.view
.format
= get_copy_format_for_bpb(isl_dev
, src_fmtl
->bpb
);
2447 if (params
.src
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2448 /* It's safe to do a blorp_copy between things which are sRGB with CCS_E
2449 * enabled even though CCS_E doesn't technically do sRGB on SKL because
2450 * we stomp everything to UINT anyway. The one thing we have to be
2451 * careful of is clear colors. Because fast clear colors for sRGB on
2452 * gen9 are encoded as the float values between format conversion and
2453 * sRGB curve application, a given clear color float will convert to the
2454 * same bits regardless of whether the format is UNORM or sRGB.
2455 * Therefore, we can handle sRGB without any special cases.
2457 UNUSED
enum isl_format linear_src_format
=
2458 isl_format_srgb_to_linear(src_surf
->surf
->format
);
2459 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2461 params
.src
.view
.format
));
2462 params
.src
.clear_color
=
2463 bitcast_color_value_to_uint(params
.src
.clear_color
, src_fmtl
);
2466 if (params
.dst
.aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2467 /* See above where we handle linear_src_format */
2468 UNUSED
enum isl_format linear_dst_format
=
2469 isl_format_srgb_to_linear(dst_surf
->surf
->format
);
2470 assert(isl_formats_are_ccs_e_compatible(batch
->blorp
->isl_dev
->info
,
2472 params
.dst
.view
.format
));
2473 params
.dst
.clear_color
=
2474 bitcast_color_value_to_uint(params
.dst
.clear_color
, dst_fmtl
);
2477 wm_prog_key
.src_bpc
=
2478 isl_format_get_layout(params
.src
.view
.format
)->channels
.r
.bits
;
2479 wm_prog_key
.dst_bpc
=
2480 isl_format_get_layout(params
.dst
.view
.format
)->channels
.r
.bits
;
2482 if (src_fmtl
->bw
> 1 || src_fmtl
->bh
> 1) {
2483 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.src
,
2485 &src_width
, &src_height
);
2486 wm_prog_key
.need_src_offset
= true;
2489 if (dst_fmtl
->bw
> 1 || dst_fmtl
->bh
> 1) {
2490 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
2491 &dst_x
, &dst_y
, NULL
, NULL
);
2492 wm_prog_key
.need_dst_offset
= true;
2495 /* Once both surfaces are stompped to uncompressed as needed, the
2496 * destination size is the same as the source size.
2498 uint32_t dst_width
= src_width
;
2499 uint32_t dst_height
= src_height
;
2501 struct blt_coords coords
= {
2504 .src1
= src_x
+ src_width
,
2506 .dst1
= dst_x
+ dst_width
,
2511 .src1
= src_y
+ src_height
,
2513 .dst1
= dst_y
+ dst_height
,
2518 do_blorp_blit(batch
, ¶ms
, &wm_prog_key
, &coords
);
2521 static enum isl_format
2522 isl_format_for_size(unsigned size_B
)
2525 case 1: return ISL_FORMAT_R8_UINT
;
2526 case 2: return ISL_FORMAT_R8G8_UINT
;
2527 case 4: return ISL_FORMAT_R8G8B8A8_UINT
;
2528 case 8: return ISL_FORMAT_R16G16B16A16_UINT
;
2529 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
2531 unreachable("Not a power-of-two format size");
2536 * Returns the greatest common divisor of a and b that is a power of two.
2539 gcd_pow2_u64(uint64_t a
, uint64_t b
)
2541 assert(a
> 0 || b
> 0);
2543 unsigned a_log2
= ffsll(a
) - 1;
2544 unsigned b_log2
= ffsll(b
) - 1;
2546 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
2547 * case, the MIN2() will take the other one. If both are 0 then we will
2548 * hit the assert above.
2550 return 1 << MIN2(a_log2
, b_log2
);
2554 do_buffer_copy(struct blorp_batch
*batch
,
2555 struct blorp_address
*src
,
2556 struct blorp_address
*dst
,
2557 int width
, int height
, int block_size
)
2559 /* The actual format we pick doesn't matter as blorp will throw it away.
2560 * The only thing that actually matters is the size.
2562 enum isl_format format
= isl_format_for_size(block_size
);
2565 struct isl_surf surf
;
2566 ok
= isl_surf_init(batch
->blorp
->isl_dev
, &surf
,
2567 .dim
= ISL_SURF_DIM_2D
,
2575 .row_pitch
= width
* block_size
,
2576 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
2577 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
2578 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
2581 struct blorp_surf src_blorp_surf
= {
2586 struct blorp_surf dst_blorp_surf
= {
2591 blorp_copy(batch
, &src_blorp_surf
, 0, 0, &dst_blorp_surf
, 0, 0,
2592 0, 0, 0, 0, width
, height
);
2596 blorp_buffer_copy(struct blorp_batch
*batch
,
2597 struct blorp_address src
,
2598 struct blorp_address dst
,
2601 const struct gen_device_info
*devinfo
= batch
->blorp
->isl_dev
->info
;
2602 uint64_t copy_size
= size
;
2604 /* This is maximum possible width/height our HW can handle */
2605 uint64_t max_surface_dim
= 1 << (devinfo
->gen
>= 7 ? 14 : 13);
2607 /* First, we compute the biggest format that can be used with the
2608 * given offsets and size.
2611 bs
= gcd_pow2_u64(bs
, src
.offset
);
2612 bs
= gcd_pow2_u64(bs
, dst
.offset
);
2613 bs
= gcd_pow2_u64(bs
, size
);
2615 /* First, we make a bunch of max-sized copies */
2616 uint64_t max_copy_size
= max_surface_dim
* max_surface_dim
* bs
;
2617 while (copy_size
>= max_copy_size
) {
2618 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, max_surface_dim
, bs
);
2619 copy_size
-= max_copy_size
;
2620 src
.offset
+= max_copy_size
;
2621 dst
.offset
+= max_copy_size
;
2624 /* Now make a max-width copy */
2625 uint64_t height
= copy_size
/ (max_surface_dim
* bs
);
2626 assert(height
< max_surface_dim
);
2628 uint64_t rect_copy_size
= height
* max_surface_dim
* bs
;
2629 do_buffer_copy(batch
, &src
, &dst
, max_surface_dim
, height
, bs
);
2630 copy_size
-= rect_copy_size
;
2631 src
.offset
+= rect_copy_size
;
2632 dst
.offset
+= rect_copy_size
;
2635 /* Finally, make a small copy to finish it off */
2636 if (copy_size
!= 0) {
2637 do_buffer_copy(batch
, &src
, &dst
, copy_size
/ bs
, 1, bs
);