2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/ralloc.h"
26 #include "main/macros.h" /* Needed for MAX3 and MAX2 for format_rgb9e5 */
27 #include "util/format_rgb9e5.h"
28 #include "util/format_srgb.h"
30 #include "blorp_priv.h"
31 #include "compiler/brw_eu_defines.h"
33 #include "blorp_nir_builder.h"
35 #define FILE_DEBUG_FLAG DEBUG_BLORP
37 struct brw_blorp_const_color_prog_key
39 enum blorp_shader_type shader_type
; /* Must be BLORP_SHADER_TYPE_CLEAR */
40 bool use_simd16_replicated_data
;
45 blorp_params_get_clear_kernel(struct blorp_context
*blorp
,
46 struct blorp_params
*params
,
47 bool use_replicated_data
)
49 const struct brw_blorp_const_color_prog_key blorp_key
= {
50 .shader_type
= BLORP_SHADER_TYPE_CLEAR
,
51 .use_simd16_replicated_data
= use_replicated_data
,
54 if (blorp
->lookup_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
55 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
58 void *mem_ctx
= ralloc_context(NULL
);
61 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
62 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "BLORP-clear");
64 nir_variable
*v_color
=
65 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
67 nir_variable
*frag_color
= nir_variable_create(b
.shader
, nir_var_shader_out
,
70 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
72 nir_copy_var(&b
, frag_color
, v_color
);
74 struct brw_wm_prog_key wm_key
;
75 brw_blorp_init_wm_prog_key(&wm_key
);
77 struct brw_wm_prog_data prog_data
;
78 const unsigned *program
=
79 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, use_replicated_data
,
83 blorp
->upload_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
84 program
, prog_data
.base
.program_size
,
85 &prog_data
.base
, sizeof(prog_data
),
86 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
92 struct layer_offset_vs_key
{
93 enum blorp_shader_type shader_type
;
97 /* In the case of doing attachment clears, we are using a surface state that
98 * is handed to us so we can't set (and don't even know) the base array layer.
99 * In order to do a layered clear in this scenario, we need some way of adding
100 * the base array layer to the instance id. Unfortunately, our hardware has
101 * no real concept of "base instance", so we have to do it manually in a
105 blorp_params_get_layer_offset_vs(struct blorp_context
*blorp
,
106 struct blorp_params
*params
)
108 struct layer_offset_vs_key blorp_key
= {
109 .shader_type
= BLORP_SHADER_TYPE_LAYER_OFFSET_VS
,
112 if (params
->wm_prog_data
)
113 blorp_key
.num_inputs
= params
->wm_prog_data
->num_varying_inputs
;
115 if (blorp
->lookup_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
116 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
))
119 void *mem_ctx
= ralloc_context(NULL
);
122 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_VERTEX
, NULL
);
123 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "BLORP-layer-offset-vs");
125 const struct glsl_type
*uvec4_type
= glsl_vector_type(GLSL_TYPE_UINT
, 4);
127 /* First we deal with the header which has instance and base instance */
128 nir_variable
*a_header
= nir_variable_create(b
.shader
, nir_var_shader_in
,
129 uvec4_type
, "header");
130 a_header
->data
.location
= VERT_ATTRIB_GENERIC0
;
132 nir_variable
*v_layer
= nir_variable_create(b
.shader
, nir_var_shader_out
,
133 glsl_int_type(), "layer_id");
134 v_layer
->data
.location
= VARYING_SLOT_LAYER
;
136 /* Compute the layer id */
137 nir_ssa_def
*header
= nir_load_var(&b
, a_header
);
138 nir_ssa_def
*base_layer
= nir_channel(&b
, header
, 0);
139 nir_ssa_def
*instance
= nir_channel(&b
, header
, 1);
140 nir_store_var(&b
, v_layer
, nir_iadd(&b
, instance
, base_layer
), 0x1);
142 /* Then we copy the vertex from the next slot to VARYING_SLOT_POS */
143 nir_variable
*a_vertex
= nir_variable_create(b
.shader
, nir_var_shader_in
,
144 glsl_vec4_type(), "a_vertex");
145 a_vertex
->data
.location
= VERT_ATTRIB_GENERIC1
;
147 nir_variable
*v_pos
= nir_variable_create(b
.shader
, nir_var_shader_out
,
148 glsl_vec4_type(), "v_pos");
149 v_pos
->data
.location
= VARYING_SLOT_POS
;
151 nir_copy_var(&b
, v_pos
, a_vertex
);
153 /* Then we copy everything else */
154 for (unsigned i
= 0; i
< blorp_key
.num_inputs
; i
++) {
155 nir_variable
*a_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
156 uvec4_type
, "input");
157 a_in
->data
.location
= VERT_ATTRIB_GENERIC2
+ i
;
159 nir_variable
*v_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
160 uvec4_type
, "output");
161 v_out
->data
.location
= VARYING_SLOT_VAR0
+ i
;
163 nir_copy_var(&b
, v_out
, a_in
);
166 struct brw_vs_prog_data vs_prog_data
;
167 memset(&vs_prog_data
, 0, sizeof(vs_prog_data
));
169 const unsigned *program
=
170 blorp_compile_vs(blorp
, mem_ctx
, b
.shader
, &vs_prog_data
);
173 blorp
->upload_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
174 program
, vs_prog_data
.base
.base
.program_size
,
175 &vs_prog_data
.base
.base
, sizeof(vs_prog_data
),
176 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
);
178 ralloc_free(mem_ctx
);
182 /* The x0, y0, x1, and y1 parameters must already be populated with the render
183 * area of the framebuffer to be cleared.
186 get_fast_clear_rect(const struct isl_device
*dev
,
187 const struct isl_surf
*aux_surf
,
188 unsigned *x0
, unsigned *y0
,
189 unsigned *x1
, unsigned *y1
)
191 unsigned int x_align
, y_align
;
192 unsigned int x_scaledown
, y_scaledown
;
194 /* Only single sampled surfaces need to (and actually can) be resolved. */
195 if (aux_surf
->usage
== ISL_SURF_USAGE_CCS_BIT
) {
196 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
197 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
199 * Clear pass must have a clear rectangle that must follow
200 * alignment rules in terms of pixels and lines as shown in the
201 * table below. Further, the clear-rectangle height and width
202 * must be multiple of the following dimensions. If the height
203 * and width of the render target being cleared do not meet these
204 * requirements, an MCS buffer can be created such that it
205 * follows the requirement and covers the RT.
207 * The alignment size in the table that follows is related to the
208 * alignment size that is baked into the CCS surface format but with X
209 * alignment multiplied by 16 and Y alignment multiplied by 32.
211 x_align
= isl_format_get_layout(aux_surf
->format
)->bw
;
212 y_align
= isl_format_get_layout(aux_surf
->format
)->bh
;
216 /* SKL+ line alignment requirement for Y-tiled are half those of the prior
219 if (dev
->info
->gen
>= 9)
224 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
225 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
227 * In order to optimize the performance MCS buffer (when bound to
228 * 1X RT) clear similarly to MCS buffer clear for MSRT case,
229 * clear rect is required to be scaled by the following factors
230 * in the horizontal and vertical directions:
232 * The X and Y scale down factors in the table that follows are each
233 * equal to half the alignment value computed above.
235 x_scaledown
= x_align
/ 2;
236 y_scaledown
= y_align
/ 2;
238 /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
239 * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
240 * Clear of Non-MultiSampled Render Target Restrictions":
242 * Clear rectangle must be aligned to two times the number of
243 * pixels in the table shown below due to 16x16 hashing across the
249 assert(aux_surf
->usage
== ISL_SURF_USAGE_MCS_BIT
);
251 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
252 * Target(s)", beneath the "MSAA Compression" bullet (p326):
254 * Clear pass for this case requires that scaled down primitive
255 * is sent down with upper left co-ordinate to coincide with
256 * actual rectangle being cleared. For MSAA, clear rectangle’s
257 * height and width need to as show in the following table in
258 * terms of (width,height) of the RT.
260 * MSAA Width of Clear Rect Height of Clear Rect
261 * 2X Ceil(1/8*width) Ceil(1/2*height)
262 * 4X Ceil(1/8*width) Ceil(1/2*height)
263 * 8X Ceil(1/2*width) Ceil(1/2*height)
264 * 16X width Ceil(1/2*height)
266 * The text "with upper left co-ordinate to coincide with actual
267 * rectangle being cleared" is a little confusing--it seems to imply
268 * that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
269 * feed the pipeline using the rectangle (x,y) to
270 * (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
271 * the number of samples. Experiments indicate that this is not
272 * quite correct; actually, what the hardware appears to do is to
273 * align whatever rectangle is sent down the pipeline to the nearest
274 * multiple of 2x2 blocks, and then scale it up by a factor of N
275 * horizontally and 2 vertically. So the resulting alignment is 4
276 * vertically and either 4 or 16 horizontally, and the scaledown
277 * factor is 2 vertically and either 2 or 8 horizontally.
279 switch (aux_surf
->format
) {
280 case ISL_FORMAT_MCS_2X
:
281 case ISL_FORMAT_MCS_4X
:
284 case ISL_FORMAT_MCS_8X
:
287 case ISL_FORMAT_MCS_16X
:
291 unreachable("Unexpected MCS format for fast clear");
294 x_align
= x_scaledown
* 2;
295 y_align
= y_scaledown
* 2;
298 *x0
= ROUND_DOWN_TO(*x0
, x_align
) / x_scaledown
;
299 *y0
= ROUND_DOWN_TO(*y0
, y_align
) / y_scaledown
;
300 *x1
= ALIGN(*x1
, x_align
) / x_scaledown
;
301 *y1
= ALIGN(*y1
, y_align
) / y_scaledown
;
305 blorp_fast_clear(struct blorp_batch
*batch
,
306 const struct blorp_surf
*surf
, enum isl_format format
,
307 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
308 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
310 /* Ensure that all layers undergoing the clear have an auxiliary buffer. */
311 assert(start_layer
+ num_layers
<=
312 MAX2(surf
->aux_surf
->logical_level0_px
.depth
>> level
,
313 surf
->aux_surf
->logical_level0_px
.array_len
));
315 struct blorp_params params
;
316 blorp_params_init(¶ms
);
317 params
.num_layers
= num_layers
;
324 memset(¶ms
.wm_inputs
.clear_color
, 0xff, 4*sizeof(float));
325 params
.fast_clear_op
= BLORP_FAST_CLEAR_OP_CLEAR
;
327 get_fast_clear_rect(batch
->blorp
->isl_dev
, surf
->aux_surf
,
328 ¶ms
.x0
, ¶ms
.y0
, ¶ms
.x1
, ¶ms
.y1
);
330 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, true))
333 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
334 start_layer
, format
, true);
335 params
.num_samples
= params
.dst
.surf
.samples
;
337 batch
->blorp
->exec(batch
, ¶ms
);
340 static union isl_color_value
341 swizzle_color_value(union isl_color_value src
, struct isl_swizzle swizzle
)
343 union isl_color_value dst
= { .u32
= { 0, } };
345 /* We assign colors in ABGR order so that the first one will be taken in
346 * RGBA precedence order. According to the PRM docs for shader channel
347 * select, this matches Haswell hardware behavior.
349 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
350 dst
.u32
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[3];
351 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
352 dst
.u32
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[2];
353 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
354 dst
.u32
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[1];
355 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
356 dst
.u32
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[0];
362 blorp_clear(struct blorp_batch
*batch
,
363 const struct blorp_surf
*surf
,
364 enum isl_format format
, struct isl_swizzle swizzle
,
365 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
366 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
367 union isl_color_value clear_color
,
368 const bool color_write_disable
[4])
370 struct blorp_params params
;
371 blorp_params_init(¶ms
);
373 /* Manually apply the clear destination swizzle. This way swizzled clears
374 * will work for swizzles which we can't normally use for rendering and it
375 * also ensures that they work on pre-Haswell hardware which can't swizlle
378 clear_color
= swizzle_color_value(clear_color
, swizzle
);
379 swizzle
= ISL_SWIZZLE_IDENTITY
;
381 if (format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
382 clear_color
.u32
[0] = float3_to_rgb9e5(clear_color
.f32
);
383 format
= ISL_FORMAT_R32_UINT
;
384 } else if (format
== ISL_FORMAT_L8_UNORM_SRGB
) {
385 clear_color
.f32
[0] = util_format_linear_to_srgb_float(clear_color
.f32
[0]);
386 format
= ISL_FORMAT_R8_UNORM
;
387 } else if (format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
388 /* Broadwell and earlier cannot render to this format so we need to work
389 * around it by swapping the colors around and using B4G4R4A4 instead.
391 const struct isl_swizzle ARGB
= ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
);
392 clear_color
= swizzle_color_value(clear_color
, ARGB
);
393 format
= ISL_FORMAT_B4G4R4A4_UNORM
;
396 memcpy(¶ms
.wm_inputs
.clear_color
, clear_color
.f32
, sizeof(float) * 4);
398 bool use_simd16_replicated_data
= true;
400 /* From the SNB PRM (Vol4_Part1):
402 * "Replicated data (Message Type = 111) is only supported when
403 * accessing tiled memory. Using this Message Type to access linear
404 * (untiled) memory is UNDEFINED."
406 if (surf
->surf
->tiling
== ISL_TILING_LINEAR
)
407 use_simd16_replicated_data
= false;
409 /* Replicated clears don't work yet before gen6 */
410 if (batch
->blorp
->isl_dev
->info
->gen
< 6)
411 use_simd16_replicated_data
= false;
413 /* Constant color writes ignore everyting in blend and color calculator
414 * state. This is not documented.
416 if (color_write_disable
) {
417 for (unsigned i
= 0; i
< 4; i
++) {
418 params
.color_write_disable
[i
] = color_write_disable
[i
];
419 if (color_write_disable
[i
])
420 use_simd16_replicated_data
= false;
424 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
,
425 use_simd16_replicated_data
))
428 if (!blorp_ensure_sf_program(batch
->blorp
, ¶ms
))
431 while (num_layers
> 0) {
432 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
433 start_layer
, format
, true);
434 params
.dst
.view
.swizzle
= swizzle
;
441 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
442 * Convert them to a single slice on gen4.
444 if (batch
->blorp
->isl_dev
->info
->gen
== 4 &&
445 (params
.dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
)) {
446 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
.dst
);
449 if (isl_format_is_compressed(params
.dst
.surf
.format
)) {
450 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
451 NULL
, NULL
, NULL
, NULL
);
452 //&dst_x, &dst_y, &dst_w, &dst_h);
455 if (params
.dst
.tile_x_sa
|| params
.dst
.tile_y_sa
) {
456 /* Either we're on gen4 where there is no multisampling or the
457 * surface is compressed which also implies no multisampling.
458 * Therefore, sa == px and we don't need to do a conversion.
460 assert(params
.dst
.surf
.samples
== 1);
461 params
.x0
+= params
.dst
.tile_x_sa
;
462 params
.y0
+= params
.dst
.tile_y_sa
;
463 params
.x1
+= params
.dst
.tile_x_sa
;
464 params
.y1
+= params
.dst
.tile_y_sa
;
467 params
.num_samples
= params
.dst
.surf
.samples
;
469 /* We may be restricted on the number of layers we can bind at any one
470 * time. In particular, Sandy Bridge has a maximum number of layers of
471 * 512 but a maximum 3D texture size is much larger.
473 params
.num_layers
= MIN2(params
.dst
.view
.array_len
, num_layers
);
474 batch
->blorp
->exec(batch
, ¶ms
);
476 start_layer
+= params
.num_layers
;
477 num_layers
-= params
.num_layers
;
482 blorp_clear_depth_stencil(struct blorp_batch
*batch
,
483 const struct blorp_surf
*depth
,
484 const struct blorp_surf
*stencil
,
485 uint32_t level
, uint32_t start_layer
,
487 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
488 bool clear_depth
, float depth_value
,
489 uint8_t stencil_mask
, uint8_t stencil_value
)
491 struct blorp_params params
;
492 blorp_params_init(¶ms
);
499 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) == 6) {
500 /* For some reason, Sandy Bridge gets occlusion queries wrong if we
501 * don't have a shader. In particular, it records samples even though
502 * we disable statistics in 3DSTATE_WM. Give it the usual clear shader
503 * to work around the issue.
505 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, false))
509 while (num_layers
> 0) {
510 params
.num_layers
= num_layers
;
513 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
515 ISL_FORMAT_UNSUPPORTED
, true);
516 params
.stencil_mask
= stencil_mask
;
517 params
.stencil_ref
= stencil_value
;
519 params
.dst
.surf
.samples
= params
.stencil
.surf
.samples
;
520 params
.dst
.surf
.logical_level0_px
=
521 params
.stencil
.surf
.logical_level0_px
;
522 params
.dst
.view
= params
.depth
.view
;
524 params
.num_samples
= params
.stencil
.surf
.samples
;
526 /* We may be restricted on the number of layers we can bind at any
527 * one time. In particular, Sandy Bridge has a maximum number of
528 * layers of 512 but a maximum 3D texture size is much larger.
530 if (params
.stencil
.view
.array_len
< params
.num_layers
)
531 params
.num_layers
= params
.stencil
.view
.array_len
;
535 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
537 ISL_FORMAT_UNSUPPORTED
, true);
538 params
.z
= depth_value
;
539 params
.depth_format
=
540 isl_format_get_depth_format(depth
->surf
->format
, false);
542 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
543 params
.dst
.surf
.logical_level0_px
=
544 params
.depth
.surf
.logical_level0_px
;
545 params
.dst
.view
= params
.depth
.view
;
547 params
.num_samples
= params
.depth
.surf
.samples
;
549 /* We may be restricted on the number of layers we can bind at any
550 * one time. In particular, Sandy Bridge has a maximum number of
551 * layers of 512 but a maximum 3D texture size is much larger.
553 if (params
.depth
.view
.array_len
< params
.num_layers
)
554 params
.num_layers
= params
.depth
.view
.array_len
;
557 batch
->blorp
->exec(batch
, ¶ms
);
559 start_layer
+= params
.num_layers
;
560 num_layers
-= params
.num_layers
;
565 blorp_can_hiz_clear_depth(uint8_t gen
, enum isl_format format
,
566 uint32_t num_samples
,
567 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
569 /* This function currently doesn't support any gen prior to gen8 */
572 if (gen
== 8 && format
== ISL_FORMAT_R16_UNORM
) {
573 /* Apply the D16 alignment restrictions. On BDW, HiZ has an 8x4 sample
574 * block with the following property: as the number of samples increases,
575 * the number of pixels representable by this block decreases by a factor
576 * of the sample dimensions. Sample dimensions scale following the MSAA
577 * interleaved pattern.
579 * Sample|Sample|Pixel
581 * ===================
588 * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
590 const struct isl_extent2d sa_block_dim
=
591 isl_get_interleaved_msaa_px_size_sa(num_samples
);
592 const uint8_t align_px_w
= 8 / sa_block_dim
.w
;
593 const uint8_t align_px_h
= 4 / sa_block_dim
.h
;
595 /* Fast depth clears clear an entire sample block at a time. As a result,
596 * the rectangle must be aligned to the dimensions of the encompassing
597 * pixel block for a successful operation.
599 * Fast clears can still work if the upper-left corner is aligned and the
600 * bottom-rigtht corner touches the edge of a depth buffer whose extent
601 * is unaligned. This is because each miplevel in the depth buffer is
602 * padded by the Pixel Dim (similar to a standard compressed texture).
603 * In this case, the clear rectangle could be padded by to match the full
604 * depth buffer extent but to support multiple clearing techniques, we
605 * chose to be unaware of the depth buffer's extent and thus don't handle
608 if (x0
% align_px_w
|| y0
% align_px_h
||
609 x1
% align_px_w
|| y1
% align_px_h
)
615 /* Given a depth stencil attachment, this function performs a fast depth clear
616 * on a depth portion and a regular clear on the stencil portion. When
617 * performing a fast depth clear on the depth portion, the HiZ buffer is simply
618 * tagged as cleared so the depth clear value is not actually needed.
621 blorp_gen8_hiz_clear_attachments(struct blorp_batch
*batch
,
622 uint32_t num_samples
,
623 uint32_t x0
, uint32_t y0
,
624 uint32_t x1
, uint32_t y1
,
625 bool clear_depth
, bool clear_stencil
,
626 uint8_t stencil_value
)
628 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
630 struct blorp_params params
;
631 blorp_params_init(¶ms
);
632 params
.num_layers
= 1;
633 params
.hiz_op
= BLORP_HIZ_OP_DEPTH_CLEAR
;
638 params
.num_samples
= num_samples
;
639 params
.depth
.enabled
= clear_depth
;
640 params
.stencil
.enabled
= clear_stencil
;
641 params
.stencil_ref
= stencil_value
;
642 batch
->blorp
->exec(batch
, ¶ms
);
645 /** Clear active color/depth/stencili attachments
647 * This function performs a clear operation on the currently bound
648 * color/depth/stencil attachments. It is assumed that any information passed
649 * in here is valid, consistent, and in-bounds relative to the currently
650 * attached depth/stencil. The binding_table_offset parameter is the 32-bit
651 * offset relative to surface state base address where pre-baked binding table
652 * that we are to use lives. If clear_color is false, binding_table_offset
653 * must point to a binding table with one entry which is a valid null surface
654 * that matches the currently bound depth and stencil.
657 blorp_clear_attachments(struct blorp_batch
*batch
,
658 uint32_t binding_table_offset
,
659 enum isl_format depth_format
,
660 uint32_t num_samples
,
661 uint32_t start_layer
, uint32_t num_layers
,
662 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
663 bool clear_color
, union isl_color_value color_value
,
664 bool clear_depth
, float depth_value
,
665 uint8_t stencil_mask
, uint8_t stencil_value
)
667 struct blorp_params params
;
668 blorp_params_init(¶ms
);
670 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
677 params
.use_pre_baked_binding_table
= true;
678 params
.pre_baked_binding_table_offset
= binding_table_offset
;
680 params
.num_layers
= num_layers
;
681 params
.num_samples
= num_samples
;
684 params
.dst
.enabled
= true;
686 memcpy(¶ms
.wm_inputs
.clear_color
, color_value
.f32
, sizeof(float) * 4);
688 /* Unfortunately, without knowing whether or not our destination surface
689 * is tiled or not, we have to assume it may be linear. This means no
690 * SIMD16_REPDATA for us. :-(
692 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, false))
697 params
.depth
.enabled
= true;
699 params
.z
= depth_value
;
700 params
.depth_format
= isl_format_get_depth_format(depth_format
, false);
704 params
.stencil
.enabled
= true;
706 params
.stencil_mask
= stencil_mask
;
707 params
.stencil_ref
= stencil_value
;
710 if (!blorp_params_get_layer_offset_vs(batch
->blorp
, ¶ms
))
713 params
.vs_inputs
.base_layer
= start_layer
;
715 batch
->blorp
->exec(batch
, ¶ms
);
719 blorp_ccs_resolve(struct blorp_batch
*batch
,
720 struct blorp_surf
*surf
, uint32_t level
,
721 uint32_t start_layer
, uint32_t num_layers
,
722 enum isl_format format
,
723 enum blorp_fast_clear_op resolve_op
)
725 struct blorp_params params
;
727 blorp_params_init(¶ms
);
728 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
,
729 level
, start_layer
, format
, true);
731 /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
733 * A rectangle primitive must be scaled down by the following factors
734 * with respect to render target being resolved.
736 * The scaledown factors in the table that follows are related to the block
737 * size of the CCS format. For IVB and HSW, we divide by two, for BDW we
738 * multiply by 8 and 16. On Sky Lake, we multiply by 8.
740 const struct isl_format_layout
*aux_fmtl
=
741 isl_format_get_layout(params
.dst
.aux_surf
.format
);
742 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
744 unsigned x_scaledown
, y_scaledown
;
745 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 9) {
746 x_scaledown
= aux_fmtl
->bw
* 8;
747 y_scaledown
= aux_fmtl
->bh
* 8;
748 } else if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
749 x_scaledown
= aux_fmtl
->bw
* 8;
750 y_scaledown
= aux_fmtl
->bh
* 16;
752 x_scaledown
= aux_fmtl
->bw
/ 2;
753 y_scaledown
= aux_fmtl
->bh
/ 2;
755 params
.x0
= params
.y0
= 0;
756 params
.x1
= minify(params
.dst
.aux_surf
.logical_level0_px
.width
, level
);
757 params
.y1
= minify(params
.dst
.aux_surf
.logical_level0_px
.height
, level
);
758 params
.x1
= ALIGN(params
.x1
, x_scaledown
) / x_scaledown
;
759 params
.y1
= ALIGN(params
.y1
, y_scaledown
) / y_scaledown
;
761 if (batch
->blorp
->isl_dev
->info
->gen
>= 9) {
762 assert(resolve_op
== BLORP_FAST_CLEAR_OP_RESOLVE_FULL
||
763 resolve_op
== BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
);
765 /* Broadwell and earlier do not have a partial resolve */
766 assert(resolve_op
== BLORP_FAST_CLEAR_OP_RESOLVE_FULL
);
768 params
.fast_clear_op
= resolve_op
;
769 params
.num_layers
= num_layers
;
771 /* Note: there is no need to initialize push constants because it doesn't
772 * matter what data gets dispatched to the render target. However, we must
773 * ensure that the fragment shader delivers the data using the "replicated
777 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, true))
780 batch
->blorp
->exec(batch
, ¶ms
);
783 struct blorp_mcs_partial_resolve_key
785 enum blorp_shader_type shader_type
;
786 uint32_t num_samples
;
790 blorp_params_get_mcs_partial_resolve_kernel(struct blorp_context
*blorp
,
791 struct blorp_params
*params
)
793 const struct blorp_mcs_partial_resolve_key blorp_key
= {
794 .shader_type
= BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE
,
795 .num_samples
= params
->num_samples
,
798 if (blorp
->lookup_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
799 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
802 void *mem_ctx
= ralloc_context(NULL
);
805 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, NULL
);
806 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "BLORP-mcs-partial-resolve");
808 nir_variable
*v_color
=
809 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
811 nir_variable
*frag_color
=
812 nir_variable_create(b
.shader
, nir_var_shader_out
,
813 glsl_vec4_type(), "gl_FragColor");
814 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
816 /* Do an MCS fetch and check if it is equal to the magic clear value */
818 blorp_nir_txf_ms_mcs(&b
, nir_f2i32(&b
, blorp_nir_frag_coord(&b
)),
819 nir_load_layer_id(&b
));
820 nir_ssa_def
*is_clear
=
821 blorp_nir_mcs_is_clear_color(&b
, mcs
, blorp_key
.num_samples
);
823 /* If we aren't the clear value, discard. */
824 nir_intrinsic_instr
*discard
=
825 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_discard_if
);
826 discard
->src
[0] = nir_src_for_ssa(nir_inot(&b
, is_clear
));
827 nir_builder_instr_insert(&b
, &discard
->instr
);
829 nir_copy_var(&b
, frag_color
, v_color
);
831 struct brw_wm_prog_key wm_key
;
832 brw_blorp_init_wm_prog_key(&wm_key
);
833 wm_key
.tex
.compressed_multisample_layout_mask
= 1;
834 wm_key
.tex
.msaa_16
= blorp_key
.num_samples
== 16;
835 wm_key
.multisample_fbo
= true;
837 struct brw_wm_prog_data prog_data
;
838 const unsigned *program
=
839 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, false,
843 blorp
->upload_shader(blorp
, &blorp_key
, sizeof(blorp_key
),
844 program
, prog_data
.base
.program_size
,
845 &prog_data
.base
, sizeof(prog_data
),
846 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
848 ralloc_free(mem_ctx
);
853 blorp_mcs_partial_resolve(struct blorp_batch
*batch
,
854 struct blorp_surf
*surf
,
855 enum isl_format format
,
856 uint32_t start_layer
, uint32_t num_layers
)
858 struct blorp_params params
;
859 blorp_params_init(¶ms
);
861 assert(batch
->blorp
->isl_dev
->info
->gen
>= 7);
865 params
.x1
= surf
->surf
->logical_level0_px
.width
;
866 params
.y1
= surf
->surf
->logical_level0_px
.height
;
868 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, surf
, 0,
869 start_layer
, format
, false);
870 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, 0,
871 start_layer
, format
, true);
873 params
.num_samples
= params
.dst
.surf
.samples
;
874 params
.num_layers
= num_layers
;
876 memcpy(¶ms
.wm_inputs
.clear_color
,
877 surf
->clear_color
.f32
, sizeof(float) * 4);
879 if (!blorp_params_get_mcs_partial_resolve_kernel(batch
->blorp
, ¶ms
))
882 batch
->blorp
->exec(batch
, ¶ms
);
885 /** Clear a CCS to the "uncompressed" state
887 * This pass is the CCS equivalent of a "HiZ resolve". It sets the CCS values
888 * for a given layer/level of a surface to 0x0 which is the "uncompressed"
889 * state which tells the sampler to go look at the main surface.
892 blorp_ccs_ambiguate(struct blorp_batch
*batch
,
893 struct blorp_surf
*surf
,
894 uint32_t level
, uint32_t layer
)
896 struct blorp_params params
;
897 blorp_params_init(¶ms
);
899 assert(ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 7);
901 const struct isl_format_layout
*aux_fmtl
=
902 isl_format_get_layout(surf
->aux_surf
->format
);
903 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
905 params
.dst
= (struct brw_blorp_surface_info
) {
907 .addr
= surf
->aux_addr
,
909 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
910 .format
= ISL_FORMAT_R32G32B32A32_UINT
,
912 .base_array_layer
= 0,
915 .swizzle
= ISL_SWIZZLE_IDENTITY
,
920 if (surf
->surf
->dim
== ISL_SURF_DIM_3D
) {
925 uint32_t offset_B
, x_offset_el
, y_offset_el
;
926 isl_surf_get_image_offset_el(surf
->aux_surf
, level
, layer
, z
,
927 &x_offset_el
, &y_offset_el
);
928 isl_tiling_get_intratile_offset_el(surf
->aux_surf
->tiling
, aux_fmtl
->bpb
,
929 surf
->aux_surf
->row_pitch
,
930 x_offset_el
, y_offset_el
,
931 &offset_B
, &x_offset_el
, &y_offset_el
);
932 params
.dst
.addr
.offset
+= offset_B
;
934 const uint32_t width_px
=
935 minify(surf
->aux_surf
->logical_level0_px
.width
, level
);
936 const uint32_t height_px
=
937 minify(surf
->aux_surf
->logical_level0_px
.height
, level
);
938 const uint32_t width_el
= DIV_ROUND_UP(width_px
, aux_fmtl
->bw
);
939 const uint32_t height_el
= DIV_ROUND_UP(height_px
, aux_fmtl
->bh
);
941 struct isl_tile_info ccs_tile_info
;
942 isl_surf_get_tile_info(surf
->aux_surf
, &ccs_tile_info
);
944 /* We're going to map it as a regular RGBA32_UINT surface. We need to
945 * downscale a good deal. We start by computing the area on the CCS to
946 * clear in units of Y-tiled cache lines.
948 uint32_t x_offset_cl
, y_offset_cl
, width_cl
, height_cl
;
949 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
950 /* From the Sky Lake PRM Vol. 12 in the section on planes:
952 * "The Color Control Surface (CCS) contains the compression status
953 * of the cache-line pairs. The compression state of the cache-line
954 * pair is specified by 2 bits in the CCS. Each CCS cache-line
955 * represents an area on the main surface of 16x16 sets of 128 byte
956 * Y-tiled cache-line-pairs. CCS is always Y tiled."
958 * Each 2-bit surface element in the CCS corresponds to a single
959 * cache-line pair in the main surface. This means that 16x16 el block
960 * in the CCS maps to a Y-tiled cache line. Fortunately, CCS layouts
961 * are calculated with a very large alignment so we can round up to a
962 * whole cache line without worrying about overdraw.
965 /* On Broadwell and above, a CCS tile is the same as a Y tile when
966 * viewed at the cache-line granularity. Fortunately, the horizontal
967 * and vertical alignment requirements of the CCS are such that we can
968 * align to an entire cache line without worrying about crossing over
969 * from one LOD to another.
971 const uint32_t x_el_per_cl
= ccs_tile_info
.logical_extent_el
.w
/ 8;
972 const uint32_t y_el_per_cl
= ccs_tile_info
.logical_extent_el
.h
/ 8;
973 assert(surf
->aux_surf
->image_alignment_el
.w
% x_el_per_cl
== 0);
974 assert(surf
->aux_surf
->image_alignment_el
.h
% y_el_per_cl
== 0);
976 assert(x_offset_el
% x_el_per_cl
== 0);
977 assert(y_offset_el
% y_el_per_cl
== 0);
978 x_offset_cl
= x_offset_el
/ x_el_per_cl
;
979 y_offset_cl
= y_offset_el
/ y_el_per_cl
;
980 width_cl
= DIV_ROUND_UP(width_el
, x_el_per_cl
);
981 height_cl
= DIV_ROUND_UP(height_el
, y_el_per_cl
);
983 /* On gen7, the CCS tiling is not so nice. However, there we are
984 * guaranteed that we only have a single level and slice so we don't
985 * have to worry about it and can just align to a whole tile.
987 assert(surf
->aux_surf
->logical_level0_px
.depth
== 1);
988 assert(surf
->aux_surf
->logical_level0_px
.array_len
== 1);
989 assert(x_offset_el
== 0 && y_offset_el
== 0);
990 const uint32_t width_tl
=
991 DIV_ROUND_UP(width_el
, ccs_tile_info
.logical_extent_el
.w
);
992 const uint32_t height_tl
=
993 DIV_ROUND_UP(height_el
, ccs_tile_info
.logical_extent_el
.h
);
996 width_cl
= width_tl
* 8;
997 height_cl
= height_tl
* 8;
1000 /* We're going to use a RGBA32 format so as to write data as quickly as
1001 * possible. A y-tiled cache line will then be 1x4 px.
1003 const uint32_t x_offset_rgba_px
= x_offset_cl
;
1004 const uint32_t y_offset_rgba_px
= y_offset_cl
* 4;
1005 const uint32_t width_rgba_px
= width_cl
;
1006 const uint32_t height_rgba_px
= height_cl
* 4;
1008 MAYBE_UNUSED
bool ok
=
1009 isl_surf_init(batch
->blorp
->isl_dev
, ¶ms
.dst
.surf
,
1010 .dim
= ISL_SURF_DIM_2D
,
1011 .format
= ISL_FORMAT_R32G32B32A32_UINT
,
1012 .width
= width_rgba_px
+ x_offset_rgba_px
,
1013 .height
= height_rgba_px
+ y_offset_rgba_px
,
1018 .row_pitch
= surf
->aux_surf
->row_pitch
,
1019 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1020 .tiling_flags
= ISL_TILING_Y0_BIT
);
1023 params
.x0
= x_offset_rgba_px
;
1024 params
.y0
= y_offset_rgba_px
;
1025 params
.x1
= x_offset_rgba_px
+ width_rgba_px
;
1026 params
.y1
= y_offset_rgba_px
+ height_rgba_px
;
1028 /* A CCS value of 0 means "uncompressed." */
1029 memset(¶ms
.wm_inputs
.clear_color
, 0,
1030 sizeof(params
.wm_inputs
.clear_color
));
1032 if (!blorp_params_get_clear_kernel(batch
->blorp
, ¶ms
, true))
1035 batch
->blorp
->exec(batch
, ¶ms
);