2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/ralloc.h"
26 #include "main/macros.h" /* Needed for MAX3 and MAX2 for format_rgb9e5 */
27 #include "util/format_rgb9e5.h"
28 #include "util/format_srgb.h"
30 #include "blorp_priv.h"
31 #include "compiler/brw_eu_defines.h"
33 #include "blorp_nir_builder.h"
35 #define FILE_DEBUG_FLAG DEBUG_BLORP
37 struct brw_blorp_const_color_prog_key
39 enum blorp_shader_type shader_type
; /* Must be BLORP_SHADER_TYPE_CLEAR */
40 bool use_simd16_replicated_data
;
41 bool clear_rgb_as_red
;
46 blorp_params_get_clear_kernel(struct blorp_batch
*batch
,
47 struct blorp_params
*params
,
48 bool use_replicated_data
,
49 bool clear_rgb_as_red
)
51 struct blorp_context
*blorp
= batch
->blorp
;
53 const struct brw_blorp_const_color_prog_key blorp_key
= {
54 .shader_type
= BLORP_SHADER_TYPE_CLEAR
,
55 .use_simd16_replicated_data
= use_replicated_data
,
56 .clear_rgb_as_red
= clear_rgb_as_red
,
59 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
60 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
63 void *mem_ctx
= ralloc_context(NULL
);
66 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
, "BLORP-clear");
68 nir_variable
*v_color
=
69 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
70 nir_ssa_def
*color
= nir_load_var(&b
, v_color
);
72 if (clear_rgb_as_red
) {
73 nir_ssa_def
*pos
= nir_f2i32(&b
, nir_load_frag_coord(&b
));
74 nir_ssa_def
*comp
= nir_umod(&b
, nir_channel(&b
, pos
, 0),
76 nir_ssa_def
*color_component
=
77 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 0)),
78 nir_channel(&b
, color
, 0),
79 nir_bcsel(&b
, nir_ieq(&b
, comp
, nir_imm_int(&b
, 1)),
80 nir_channel(&b
, color
, 1),
81 nir_channel(&b
, color
, 2)));
83 nir_ssa_def
*u
= nir_ssa_undef(&b
, 1, 32);
84 color
= nir_vec4(&b
, color_component
, u
, u
, u
);
87 nir_variable
*frag_color
= nir_variable_create(b
.shader
, nir_var_shader_out
,
90 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
91 nir_store_var(&b
, frag_color
, color
, 0xf);
93 struct brw_wm_prog_key wm_key
;
94 brw_blorp_init_wm_prog_key(&wm_key
);
96 struct brw_wm_prog_data prog_data
;
97 const unsigned *program
=
98 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, use_replicated_data
,
102 blorp
->upload_shader(batch
, &blorp_key
, sizeof(blorp_key
),
103 program
, prog_data
.base
.program_size
,
104 &prog_data
.base
, sizeof(prog_data
),
105 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
107 ralloc_free(mem_ctx
);
111 struct layer_offset_vs_key
{
112 enum blorp_shader_type shader_type
;
116 /* In the case of doing attachment clears, we are using a surface state that
117 * is handed to us so we can't set (and don't even know) the base array layer.
118 * In order to do a layered clear in this scenario, we need some way of adding
119 * the base array layer to the instance id. Unfortunately, our hardware has
120 * no real concept of "base instance", so we have to do it manually in a
124 blorp_params_get_layer_offset_vs(struct blorp_batch
*batch
,
125 struct blorp_params
*params
)
127 struct blorp_context
*blorp
= batch
->blorp
;
128 struct layer_offset_vs_key blorp_key
= {
129 .shader_type
= BLORP_SHADER_TYPE_LAYER_OFFSET_VS
,
132 if (params
->wm_prog_data
)
133 blorp_key
.num_inputs
= params
->wm_prog_data
->num_varying_inputs
;
135 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
136 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
))
139 void *mem_ctx
= ralloc_context(NULL
);
142 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_VERTEX
, "BLORP-layer-offset-vs");
144 const struct glsl_type
*uvec4_type
= glsl_vector_type(GLSL_TYPE_UINT
, 4);
146 /* First we deal with the header which has instance and base instance */
147 nir_variable
*a_header
= nir_variable_create(b
.shader
, nir_var_shader_in
,
148 uvec4_type
, "header");
149 a_header
->data
.location
= VERT_ATTRIB_GENERIC0
;
151 nir_variable
*v_layer
= nir_variable_create(b
.shader
, nir_var_shader_out
,
152 glsl_int_type(), "layer_id");
153 v_layer
->data
.location
= VARYING_SLOT_LAYER
;
155 /* Compute the layer id */
156 nir_ssa_def
*header
= nir_load_var(&b
, a_header
);
157 nir_ssa_def
*base_layer
= nir_channel(&b
, header
, 0);
158 nir_ssa_def
*instance
= nir_channel(&b
, header
, 1);
159 nir_store_var(&b
, v_layer
, nir_iadd(&b
, instance
, base_layer
), 0x1);
161 /* Then we copy the vertex from the next slot to VARYING_SLOT_POS */
162 nir_variable
*a_vertex
= nir_variable_create(b
.shader
, nir_var_shader_in
,
163 glsl_vec4_type(), "a_vertex");
164 a_vertex
->data
.location
= VERT_ATTRIB_GENERIC1
;
166 nir_variable
*v_pos
= nir_variable_create(b
.shader
, nir_var_shader_out
,
167 glsl_vec4_type(), "v_pos");
168 v_pos
->data
.location
= VARYING_SLOT_POS
;
170 nir_copy_var(&b
, v_pos
, a_vertex
);
172 /* Then we copy everything else */
173 for (unsigned i
= 0; i
< blorp_key
.num_inputs
; i
++) {
174 nir_variable
*a_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
175 uvec4_type
, "input");
176 a_in
->data
.location
= VERT_ATTRIB_GENERIC2
+ i
;
178 nir_variable
*v_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
179 uvec4_type
, "output");
180 v_out
->data
.location
= VARYING_SLOT_VAR0
+ i
;
182 nir_copy_var(&b
, v_out
, a_in
);
185 struct brw_vs_prog_data vs_prog_data
;
186 memset(&vs_prog_data
, 0, sizeof(vs_prog_data
));
188 const unsigned *program
=
189 blorp_compile_vs(blorp
, mem_ctx
, b
.shader
, &vs_prog_data
);
192 blorp
->upload_shader(batch
, &blorp_key
, sizeof(blorp_key
),
193 program
, vs_prog_data
.base
.base
.program_size
,
194 &vs_prog_data
.base
.base
, sizeof(vs_prog_data
),
195 ¶ms
->vs_prog_kernel
, ¶ms
->vs_prog_data
);
197 ralloc_free(mem_ctx
);
201 /* The x0, y0, x1, and y1 parameters must already be populated with the render
202 * area of the framebuffer to be cleared.
205 get_fast_clear_rect(const struct isl_device
*dev
,
206 const struct isl_surf
*aux_surf
,
207 unsigned *x0
, unsigned *y0
,
208 unsigned *x1
, unsigned *y1
)
210 unsigned int x_align
, y_align
;
211 unsigned int x_scaledown
, y_scaledown
;
213 /* Only single sampled surfaces need to (and actually can) be resolved. */
214 if (aux_surf
->usage
== ISL_SURF_USAGE_CCS_BIT
) {
215 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
216 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
218 * Clear pass must have a clear rectangle that must follow
219 * alignment rules in terms of pixels and lines as shown in the
220 * table below. Further, the clear-rectangle height and width
221 * must be multiple of the following dimensions. If the height
222 * and width of the render target being cleared do not meet these
223 * requirements, an MCS buffer can be created such that it
224 * follows the requirement and covers the RT.
226 * The alignment size in the table that follows is related to the
227 * alignment size that is baked into the CCS surface format but with X
228 * alignment multiplied by 16 and Y alignment multiplied by 32.
230 x_align
= isl_format_get_layout(aux_surf
->format
)->bw
;
231 y_align
= isl_format_get_layout(aux_surf
->format
)->bh
;
235 /* The line alignment requirement for Y-tiled is halved at SKL and again
238 if (dev
->info
->gen
>= 12)
240 else if (dev
->info
->gen
>= 9)
245 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
246 * Target(s)", beneath the "Fast Color Clear" bullet (p327):
248 * In order to optimize the performance MCS buffer (when bound to
249 * 1X RT) clear similarly to MCS buffer clear for MSRT case,
250 * clear rect is required to be scaled by the following factors
251 * in the horizontal and vertical directions:
253 * The X and Y scale down factors in the table that follows are each
254 * equal to half the alignment value computed above.
256 x_scaledown
= x_align
/ 2;
257 y_scaledown
= y_align
/ 2;
259 if (ISL_DEV_IS_HASWELL(dev
)) {
260 /* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
261 * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
262 * Clear of Non-MultiSampled Render Target Restrictions":
264 * Clear rectangle must be aligned to two times the number of
265 * pixels in the table shown below due to 16x16 hashing across the
268 * This restriction is only documented to exist on HSW GT3 but
269 * empirical evidence suggests that it's also needed GT2.
275 assert(aux_surf
->usage
== ISL_SURF_USAGE_MCS_BIT
);
277 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
278 * Target(s)", beneath the "MSAA Compression" bullet (p326):
280 * Clear pass for this case requires that scaled down primitive
281 * is sent down with upper left co-ordinate to coincide with
282 * actual rectangle being cleared. For MSAA, clear rectangle’s
283 * height and width need to as show in the following table in
284 * terms of (width,height) of the RT.
286 * MSAA Width of Clear Rect Height of Clear Rect
287 * 2X Ceil(1/8*width) Ceil(1/2*height)
288 * 4X Ceil(1/8*width) Ceil(1/2*height)
289 * 8X Ceil(1/2*width) Ceil(1/2*height)
290 * 16X width Ceil(1/2*height)
292 * The text "with upper left co-ordinate to coincide with actual
293 * rectangle being cleared" is a little confusing--it seems to imply
294 * that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
295 * feed the pipeline using the rectangle (x,y) to
296 * (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
297 * the number of samples. Experiments indicate that this is not
298 * quite correct; actually, what the hardware appears to do is to
299 * align whatever rectangle is sent down the pipeline to the nearest
300 * multiple of 2x2 blocks, and then scale it up by a factor of N
301 * horizontally and 2 vertically. So the resulting alignment is 4
302 * vertically and either 4 or 16 horizontally, and the scaledown
303 * factor is 2 vertically and either 2 or 8 horizontally.
305 switch (aux_surf
->format
) {
306 case ISL_FORMAT_MCS_2X
:
307 case ISL_FORMAT_MCS_4X
:
310 case ISL_FORMAT_MCS_8X
:
313 case ISL_FORMAT_MCS_16X
:
317 unreachable("Unexpected MCS format for fast clear");
320 x_align
= x_scaledown
* 2;
321 y_align
= y_scaledown
* 2;
324 *x0
= ROUND_DOWN_TO(*x0
, x_align
) / x_scaledown
;
325 *y0
= ROUND_DOWN_TO(*y0
, y_align
) / y_scaledown
;
326 *x1
= ALIGN(*x1
, x_align
) / x_scaledown
;
327 *y1
= ALIGN(*y1
, y_align
) / y_scaledown
;
331 blorp_fast_clear(struct blorp_batch
*batch
,
332 const struct blorp_surf
*surf
, enum isl_format format
,
333 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
334 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
336 struct blorp_params params
;
337 blorp_params_init(¶ms
);
338 params
.num_layers
= num_layers
;
345 memset(¶ms
.wm_inputs
.clear_color
, 0xff, 4*sizeof(float));
346 params
.fast_clear_op
= ISL_AUX_OP_FAST_CLEAR
;
348 get_fast_clear_rect(batch
->blorp
->isl_dev
, surf
->aux_surf
,
349 ¶ms
.x0
, ¶ms
.y0
, ¶ms
.x1
, ¶ms
.y1
);
351 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
354 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
355 start_layer
, format
, true);
356 params
.num_samples
= params
.dst
.surf
.samples
;
358 batch
->blorp
->exec(batch
, ¶ms
);
361 union isl_color_value
362 swizzle_color_value(union isl_color_value src
, struct isl_swizzle swizzle
)
364 union isl_color_value dst
= { .u32
= { 0, } };
366 /* We assign colors in ABGR order so that the first one will be taken in
367 * RGBA precedence order. According to the PRM docs for shader channel
368 * select, this matches Haswell hardware behavior.
370 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
371 dst
.u32
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[3];
372 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
373 dst
.u32
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[2];
374 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
375 dst
.u32
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[1];
376 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
377 dst
.u32
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[0];
383 blorp_clear(struct blorp_batch
*batch
,
384 const struct blorp_surf
*surf
,
385 enum isl_format format
, struct isl_swizzle swizzle
,
386 uint32_t level
, uint32_t start_layer
, uint32_t num_layers
,
387 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
388 union isl_color_value clear_color
,
389 const bool color_write_disable
[4])
391 struct blorp_params params
;
392 blorp_params_init(¶ms
);
394 /* Manually apply the clear destination swizzle. This way swizzled clears
395 * will work for swizzles which we can't normally use for rendering and it
396 * also ensures that they work on pre-Haswell hardware which can't swizlle
399 clear_color
= swizzle_color_value(clear_color
, swizzle
);
400 swizzle
= ISL_SWIZZLE_IDENTITY
;
402 bool clear_rgb_as_red
= false;
403 if (format
== ISL_FORMAT_R9G9B9E5_SHAREDEXP
) {
404 clear_color
.u32
[0] = float3_to_rgb9e5(clear_color
.f32
);
405 format
= ISL_FORMAT_R32_UINT
;
406 } else if (format
== ISL_FORMAT_L8_UNORM_SRGB
) {
407 clear_color
.f32
[0] = util_format_linear_to_srgb_float(clear_color
.f32
[0]);
408 format
= ISL_FORMAT_R8_UNORM
;
409 } else if (format
== ISL_FORMAT_A4B4G4R4_UNORM
) {
410 /* Broadwell and earlier cannot render to this format so we need to work
411 * around it by swapping the colors around and using B4G4R4A4 instead.
413 const struct isl_swizzle ARGB
= ISL_SWIZZLE(ALPHA
, RED
, GREEN
, BLUE
);
414 clear_color
= swizzle_color_value(clear_color
, ARGB
);
415 format
= ISL_FORMAT_B4G4R4A4_UNORM
;
416 } else if (isl_format_get_layout(format
)->bpb
% 3 == 0) {
417 clear_rgb_as_red
= true;
418 if (format
== ISL_FORMAT_R8G8B8_UNORM_SRGB
) {
419 clear_color
.f32
[0] = util_format_linear_to_srgb_float(clear_color
.f32
[0]);
420 clear_color
.f32
[1] = util_format_linear_to_srgb_float(clear_color
.f32
[1]);
421 clear_color
.f32
[2] = util_format_linear_to_srgb_float(clear_color
.f32
[2]);
425 memcpy(¶ms
.wm_inputs
.clear_color
, clear_color
.f32
, sizeof(float) * 4);
427 bool use_simd16_replicated_data
= true;
429 /* From the SNB PRM (Vol4_Part1):
431 * "Replicated data (Message Type = 111) is only supported when
432 * accessing tiled memory. Using this Message Type to access linear
433 * (untiled) memory is UNDEFINED."
435 if (surf
->surf
->tiling
== ISL_TILING_LINEAR
)
436 use_simd16_replicated_data
= false;
438 /* Replicated clears don't work yet before gen6 */
439 if (batch
->blorp
->isl_dev
->info
->gen
< 6)
440 use_simd16_replicated_data
= false;
442 /* Constant color writes ignore everyting in blend and color calculator
443 * state. This is not documented.
445 if (color_write_disable
) {
446 for (unsigned i
= 0; i
< 4; i
++) {
447 params
.color_write_disable
[i
] = color_write_disable
[i
];
448 if (color_write_disable
[i
])
449 use_simd16_replicated_data
= false;
453 if (!blorp_params_get_clear_kernel(batch
, ¶ms
,
454 use_simd16_replicated_data
,
458 if (!blorp_ensure_sf_program(batch
, ¶ms
))
461 while (num_layers
> 0) {
462 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
463 start_layer
, format
, true);
464 params
.dst
.view
.swizzle
= swizzle
;
471 if (params
.dst
.tile_x_sa
|| params
.dst
.tile_y_sa
) {
472 assert(params
.dst
.surf
.samples
== 1);
473 assert(num_layers
== 1);
474 params
.x0
+= params
.dst
.tile_x_sa
;
475 params
.y0
+= params
.dst
.tile_y_sa
;
476 params
.x1
+= params
.dst
.tile_x_sa
;
477 params
.y1
+= params
.dst
.tile_y_sa
;
480 /* The MinLOD and MinimumArrayElement don't work properly for cube maps.
481 * Convert them to a single slice on gen4.
483 if (batch
->blorp
->isl_dev
->info
->gen
== 4 &&
484 (params
.dst
.surf
.usage
& ISL_SURF_USAGE_CUBE_BIT
)) {
485 blorp_surf_convert_to_single_slice(batch
->blorp
->isl_dev
, ¶ms
.dst
);
488 if (clear_rgb_as_red
) {
489 surf_fake_rgb_with_red(batch
->blorp
->isl_dev
, ¶ms
.dst
);
494 if (isl_format_is_compressed(params
.dst
.surf
.format
)) {
495 blorp_surf_convert_to_uncompressed(batch
->blorp
->isl_dev
, ¶ms
.dst
,
496 NULL
, NULL
, NULL
, NULL
);
497 //&dst_x, &dst_y, &dst_w, &dst_h);
500 if (params
.dst
.tile_x_sa
|| params
.dst
.tile_y_sa
) {
501 /* Either we're on gen4 where there is no multisampling or the
502 * surface is compressed which also implies no multisampling.
503 * Therefore, sa == px and we don't need to do a conversion.
505 assert(params
.dst
.surf
.samples
== 1);
506 params
.x0
+= params
.dst
.tile_x_sa
;
507 params
.y0
+= params
.dst
.tile_y_sa
;
508 params
.x1
+= params
.dst
.tile_x_sa
;
509 params
.y1
+= params
.dst
.tile_y_sa
;
512 params
.num_samples
= params
.dst
.surf
.samples
;
514 /* We may be restricted on the number of layers we can bind at any one
515 * time. In particular, Sandy Bridge has a maximum number of layers of
516 * 512 but a maximum 3D texture size is much larger.
518 params
.num_layers
= MIN2(params
.dst
.view
.array_len
, num_layers
);
520 const unsigned max_image_width
= 16 * 1024;
521 if (params
.dst
.surf
.logical_level0_px
.width
> max_image_width
) {
522 /* Clearing an RGB image as red multiplies the surface width by 3
523 * so it may now be too wide for the hardware surface limits. We
524 * have to break the clear up into pieces in order to clear wide
527 assert(clear_rgb_as_red
);
528 assert(params
.dst
.surf
.dim
== ISL_SURF_DIM_2D
);
529 assert(params
.dst
.surf
.tiling
== ISL_TILING_LINEAR
);
530 assert(params
.dst
.surf
.logical_level0_px
.depth
== 1);
531 assert(params
.dst
.surf
.logical_level0_px
.array_len
== 1);
532 assert(params
.dst
.surf
.levels
== 1);
533 assert(params
.dst
.surf
.samples
== 1);
534 assert(params
.dst
.tile_x_sa
== 0 || params
.dst
.tile_y_sa
== 0);
535 assert(params
.dst
.aux_usage
== ISL_AUX_USAGE_NONE
);
537 /* max_image_width rounded down to a multiple of 3 */
538 const unsigned max_fake_rgb_width
= (max_image_width
/ 3) * 3;
540 isl_format_get_layout(params
.dst
.surf
.format
)->bpb
/ 8;
542 params
.dst
.surf
.logical_level0_px
.width
= max_fake_rgb_width
;
543 params
.dst
.surf
.phys_level0_sa
.width
= max_fake_rgb_width
;
545 uint32_t orig_x0
= params
.x0
, orig_x1
= params
.x1
;
546 uint64_t orig_offset
= params
.dst
.addr
.offset
;
547 for (uint32_t x
= orig_x0
; x
< orig_x1
; x
+= max_fake_rgb_width
) {
548 /* Offset to the surface. It's easy because we're linear */
549 params
.dst
.addr
.offset
= orig_offset
+ x
* cpp
;
552 params
.x1
= MIN2(orig_x1
- x
, max_image_width
);
554 batch
->blorp
->exec(batch
, ¶ms
);
557 batch
->blorp
->exec(batch
, ¶ms
);
560 start_layer
+= params
.num_layers
;
561 num_layers
-= params
.num_layers
;
566 blorp_clear_stencil_as_rgba(struct blorp_batch
*batch
,
567 const struct blorp_surf
*surf
,
568 uint32_t level
, uint32_t start_layer
,
570 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
571 uint8_t stencil_mask
, uint8_t stencil_value
)
573 /* We only support separate W-tiled stencil for now */
574 if (surf
->surf
->format
!= ISL_FORMAT_R8_UINT
||
575 surf
->surf
->tiling
!= ISL_TILING_W
)
578 /* Stencil mask support would require piles of shader magic */
579 if (stencil_mask
!= 0xff)
582 if (surf
->surf
->samples
> 1) {
583 /* Adjust x0, y0, x1, and y1 to be in units of samples */
584 assert(surf
->surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
585 struct isl_extent2d msaa_px_size_sa
=
586 isl_get_interleaved_msaa_px_size_sa(surf
->surf
->samples
);
588 x0
*= msaa_px_size_sa
.w
;
589 y0
*= msaa_px_size_sa
.h
;
590 x1
*= msaa_px_size_sa
.w
;
591 y1
*= msaa_px_size_sa
.h
;
594 /* W-tiles and Y-tiles have the same layout as far as cache lines are
595 * concerned: both are 8x8 cache lines laid out Y-major. The difference is
596 * entirely in how the data is arranged withing the cache line. W-tiling
597 * is 8x8 pixels in a swizzled pattern while Y-tiling is 16B by 4 rows
598 * regardless of image format size. As long as everything is aligned to 8,
599 * we can just treat the W-tiled image as Y-tiled, ignore the layout
600 * difference within a cache line, and blast out data.
602 if (x0
% 8 != 0 || y0
% 8 != 0 || x1
% 8 != 0 || y1
% 8 != 0)
605 struct blorp_params params
;
606 blorp_params_init(¶ms
);
608 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
611 memset(¶ms
.wm_inputs
.clear_color
, stencil_value
,
612 sizeof(params
.wm_inputs
.clear_color
));
614 /* The Sandy Bridge PRM Vol. 4 Pt. 2, section 2.11.2.1.1 has the
615 * following footnote to the format table:
617 * 128 BPE Formats cannot be Tiled Y when used as render targets
619 * We have to use RGBA16_UINT on SNB.
621 enum isl_format wide_format
;
622 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) <= 6) {
623 wide_format
= ISL_FORMAT_R16G16B16A16_UINT
;
625 /* For RGBA16_UINT, we need to mask the stencil value otherwise, we risk
626 * clamping giving us the wrong values
628 for (unsigned i
= 0; i
< 4; i
++)
629 params
.wm_inputs
.clear_color
[i
] &= 0xffff;
631 wide_format
= ISL_FORMAT_R32G32B32A32_UINT
;
634 for (uint32_t a
= 0; a
< num_layers
; a
++) {
635 uint32_t layer
= start_layer
+ a
;
637 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, level
,
638 layer
, ISL_FORMAT_UNSUPPORTED
, true);
640 if (surf
->surf
->samples
> 1)
641 blorp_surf_fake_interleaved_msaa(batch
->blorp
->isl_dev
, ¶ms
.dst
);
643 /* Make it Y-tiled */
644 blorp_surf_retile_w_to_y(batch
->blorp
->isl_dev
, ¶ms
.dst
);
647 isl_format_get_layout(wide_format
)->bpb
/ 8;
649 params
.dst
.view
.format
= params
.dst
.surf
.format
= wide_format
;
650 assert(params
.dst
.surf
.logical_level0_px
.width
% wide_Bpp
== 0);
651 params
.dst
.surf
.logical_level0_px
.width
/= wide_Bpp
;
652 assert(params
.dst
.tile_x_sa
% wide_Bpp
== 0);
653 params
.dst
.tile_x_sa
/= wide_Bpp
;
655 params
.x0
= params
.dst
.tile_x_sa
+ x0
/ (wide_Bpp
/ 2);
656 params
.y0
= params
.dst
.tile_y_sa
+ y0
/ 2;
657 params
.x1
= params
.dst
.tile_x_sa
+ x1
/ (wide_Bpp
/ 2);
658 params
.y1
= params
.dst
.tile_y_sa
+ y1
/ 2;
660 batch
->blorp
->exec(batch
, ¶ms
);
667 blorp_clear_depth_stencil(struct blorp_batch
*batch
,
668 const struct blorp_surf
*depth
,
669 const struct blorp_surf
*stencil
,
670 uint32_t level
, uint32_t start_layer
,
672 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
673 bool clear_depth
, float depth_value
,
674 uint8_t stencil_mask
, uint8_t stencil_value
)
676 if (!clear_depth
&& blorp_clear_stencil_as_rgba(batch
, stencil
, level
,
677 start_layer
, num_layers
,
683 struct blorp_params params
;
684 blorp_params_init(¶ms
);
691 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) == 6) {
692 /* For some reason, Sandy Bridge gets occlusion queries wrong if we
693 * don't have a shader. In particular, it records samples even though
694 * we disable statistics in 3DSTATE_WM. Give it the usual clear shader
695 * to work around the issue.
697 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, false, false))
701 while (num_layers
> 0) {
702 params
.num_layers
= num_layers
;
705 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
707 ISL_FORMAT_UNSUPPORTED
, true);
708 params
.stencil_mask
= stencil_mask
;
709 params
.stencil_ref
= stencil_value
;
711 params
.dst
.surf
.samples
= params
.stencil
.surf
.samples
;
712 params
.dst
.surf
.logical_level0_px
=
713 params
.stencil
.surf
.logical_level0_px
;
714 params
.dst
.view
= params
.stencil
.view
;
716 params
.num_samples
= params
.stencil
.surf
.samples
;
718 /* We may be restricted on the number of layers we can bind at any
719 * one time. In particular, Sandy Bridge has a maximum number of
720 * layers of 512 but a maximum 3D texture size is much larger.
722 if (params
.stencil
.view
.array_len
< params
.num_layers
)
723 params
.num_layers
= params
.stencil
.view
.array_len
;
727 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
729 ISL_FORMAT_UNSUPPORTED
, true);
730 params
.z
= depth_value
;
731 params
.depth_format
=
732 isl_format_get_depth_format(depth
->surf
->format
, false);
734 params
.dst
.surf
.samples
= params
.depth
.surf
.samples
;
735 params
.dst
.surf
.logical_level0_px
=
736 params
.depth
.surf
.logical_level0_px
;
737 params
.dst
.view
= params
.depth
.view
;
739 params
.num_samples
= params
.depth
.surf
.samples
;
741 /* We may be restricted on the number of layers we can bind at any
742 * one time. In particular, Sandy Bridge has a maximum number of
743 * layers of 512 but a maximum 3D texture size is much larger.
745 if (params
.depth
.view
.array_len
< params
.num_layers
)
746 params
.num_layers
= params
.depth
.view
.array_len
;
749 batch
->blorp
->exec(batch
, ¶ms
);
751 start_layer
+= params
.num_layers
;
752 num_layers
-= params
.num_layers
;
757 blorp_can_hiz_clear_depth(const struct gen_device_info
*devinfo
,
758 const struct isl_surf
*surf
,
759 enum isl_aux_usage aux_usage
,
760 uint32_t level
, uint32_t layer
,
761 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
)
763 /* This function currently doesn't support any gen prior to gen8 */
764 assert(devinfo
->gen
>= 8);
766 if (devinfo
->gen
== 8 && surf
->format
== ISL_FORMAT_R16_UNORM
) {
767 /* Apply the D16 alignment restrictions. On BDW, HiZ has an 8x4 sample
768 * block with the following property: as the number of samples increases,
769 * the number of pixels representable by this block decreases by a factor
770 * of the sample dimensions. Sample dimensions scale following the MSAA
771 * interleaved pattern.
773 * Sample|Sample|Pixel
775 * ===================
782 * Table: Pixel Dimensions in a HiZ Sample Block Pre-SKL
784 const struct isl_extent2d sa_block_dim
=
785 isl_get_interleaved_msaa_px_size_sa(surf
->samples
);
786 const uint8_t align_px_w
= 8 / sa_block_dim
.w
;
787 const uint8_t align_px_h
= 4 / sa_block_dim
.h
;
789 /* Fast depth clears clear an entire sample block at a time. As a result,
790 * the rectangle must be aligned to the dimensions of the encompassing
791 * pixel block for a successful operation.
793 * Fast clears can still work if the upper-left corner is aligned and the
794 * bottom-rigtht corner touches the edge of a depth buffer whose extent
795 * is unaligned. This is because each miplevel in the depth buffer is
796 * padded by the Pixel Dim (similar to a standard compressed texture).
797 * In this case, the clear rectangle could be padded by to match the full
798 * depth buffer extent but to support multiple clearing techniques, we
799 * chose to be unaware of the depth buffer's extent and thus don't handle
802 if (x0
% align_px_w
|| y0
% align_px_h
||
803 x1
% align_px_w
|| y1
% align_px_h
)
805 } else if (isl_surf_supports_hiz_ccs_wt(devinfo
, surf
, aux_usage
)) {
806 /* We have to set the WM_HZ_OP::FullSurfaceDepthandStencilClear bit
807 * whenever we clear an uninitialized HIZ buffer (as some drivers
808 * currently do). However, this bit seems liable to clear 16x8 pixels in
809 * the ZCS on Gen12 - greater than the slice alignments for depth
812 assert(surf
->image_alignment_el
.w
% 16 != 0 ||
813 surf
->image_alignment_el
.h
% 8 != 0);
815 /* This is the hypothesis behind some corruption that was seen with the
816 * amd_vertex_shader_layer-layered-depth-texture-render piglit test.
818 * From the Compressed Depth Buffers section of the Bspec, under the
819 * Gen12 texture performant and ZCS columns:
821 * Update with clear at either 16x8 or 8x4 granularity, based on
822 * fs_clr or otherwise.
824 * There are a number of ways to avoid full surface CCS clears that
825 * overlap other slices, but for now we choose to disable fast-clears
826 * when an initializing clear could hit another miplevel.
828 * NOTE: Because the CCS compresses the depth buffer and not a version
829 * of it that has been rearranged with different alignments (like Gen8+
830 * HIZ), we have to make sure that the x0 and y0 are at least 16x8
831 * aligned in the context of the entire surface.
833 uint32_t slice_x0
, slice_y0
;
834 isl_surf_get_image_offset_el(surf
, level
,
835 surf
->dim
== ISL_SURF_DIM_3D
? 0 : layer
,
836 surf
->dim
== ISL_SURF_DIM_3D
? layer
: 0,
837 &slice_x0
, &slice_y0
);
838 const bool max_x1_y1
=
839 x1
== minify(surf
->logical_level0_px
.width
, level
) &&
840 y1
== minify(surf
->logical_level0_px
.height
, level
);
841 const uint32_t haligned_x1
= ALIGN(x1
, surf
->image_alignment_el
.w
);
842 const uint32_t valigned_y1
= ALIGN(y1
, surf
->image_alignment_el
.h
);
843 const bool unaligned
= (slice_x0
+ x0
) % 16 || (slice_y0
+ y0
) % 8 ||
844 max_x1_y1
? haligned_x1
% 16 || valigned_y1
% 8 :
846 const bool alignment_used
= surf
->levels
> 1 ||
847 surf
->logical_level0_px
.depth
> 1 ||
848 surf
->logical_level0_px
.array_len
> 1;
850 if (unaligned
&& alignment_used
)
854 return isl_aux_usage_has_hiz(aux_usage
);
858 blorp_hiz_clear_depth_stencil(struct blorp_batch
*batch
,
859 const struct blorp_surf
*depth
,
860 const struct blorp_surf
*stencil
,
862 uint32_t start_layer
, uint32_t num_layers
,
863 uint32_t x0
, uint32_t y0
,
864 uint32_t x1
, uint32_t y1
,
865 bool clear_depth
, float depth_value
,
866 bool clear_stencil
, uint8_t stencil_value
)
868 struct blorp_params params
;
869 blorp_params_init(¶ms
);
871 /* This requires WM_HZ_OP which only exists on gen8+ */
872 assert(ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8);
874 params
.hiz_op
= ISL_AUX_OP_FAST_CLEAR
;
875 params
.num_layers
= 1;
882 for (uint32_t l
= 0; l
< num_layers
; l
++) {
883 const uint32_t layer
= start_layer
+ l
;
885 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.stencil
, stencil
,
887 ISL_FORMAT_UNSUPPORTED
, true);
888 params
.stencil_mask
= 0xff;
889 params
.stencil_ref
= stencil_value
;
890 params
.num_samples
= params
.stencil
.surf
.samples
;
894 /* If we're clearing depth, we must have HiZ */
895 assert(depth
&& depth
->aux_usage
== ISL_AUX_USAGE_HIZ
);
897 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.depth
, depth
,
899 ISL_FORMAT_UNSUPPORTED
, true);
900 params
.depth
.clear_color
.f32
[0] = depth_value
;
901 params
.depth_format
=
902 isl_format_get_depth_format(depth
->surf
->format
, false);
903 params
.num_samples
= params
.depth
.surf
.samples
;
906 batch
->blorp
->exec(batch
, ¶ms
);
910 /* Given a depth stencil attachment, this function performs a fast depth clear
911 * on a depth portion and a regular clear on the stencil portion. When
912 * performing a fast depth clear on the depth portion, the HiZ buffer is simply
913 * tagged as cleared so the depth clear value is not actually needed.
916 blorp_gen8_hiz_clear_attachments(struct blorp_batch
*batch
,
917 uint32_t num_samples
,
918 uint32_t x0
, uint32_t y0
,
919 uint32_t x1
, uint32_t y1
,
920 bool clear_depth
, bool clear_stencil
,
921 uint8_t stencil_value
)
923 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
925 struct blorp_params params
;
926 blorp_params_init(¶ms
);
927 params
.num_layers
= 1;
928 params
.hiz_op
= ISL_AUX_OP_FAST_CLEAR
;
933 params
.num_samples
= num_samples
;
934 params
.depth
.enabled
= clear_depth
;
935 params
.stencil
.enabled
= clear_stencil
;
936 params
.stencil_ref
= stencil_value
;
937 batch
->blorp
->exec(batch
, ¶ms
);
940 /** Clear active color/depth/stencili attachments
942 * This function performs a clear operation on the currently bound
943 * color/depth/stencil attachments. It is assumed that any information passed
944 * in here is valid, consistent, and in-bounds relative to the currently
945 * attached depth/stencil. The binding_table_offset parameter is the 32-bit
946 * offset relative to surface state base address where pre-baked binding table
947 * that we are to use lives. If clear_color is false, binding_table_offset
948 * must point to a binding table with one entry which is a valid null surface
949 * that matches the currently bound depth and stencil.
952 blorp_clear_attachments(struct blorp_batch
*batch
,
953 uint32_t binding_table_offset
,
954 enum isl_format depth_format
,
955 uint32_t num_samples
,
956 uint32_t start_layer
, uint32_t num_layers
,
957 uint32_t x0
, uint32_t y0
, uint32_t x1
, uint32_t y1
,
958 bool clear_color
, union isl_color_value color_value
,
959 bool clear_depth
, float depth_value
,
960 uint8_t stencil_mask
, uint8_t stencil_value
)
962 struct blorp_params params
;
963 blorp_params_init(¶ms
);
965 assert(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
972 params
.use_pre_baked_binding_table
= true;
973 params
.pre_baked_binding_table_offset
= binding_table_offset
;
975 params
.num_layers
= num_layers
;
976 params
.num_samples
= num_samples
;
979 params
.dst
.enabled
= true;
981 memcpy(¶ms
.wm_inputs
.clear_color
, color_value
.f32
, sizeof(float) * 4);
983 /* Unfortunately, without knowing whether or not our destination surface
984 * is tiled or not, we have to assume it may be linear. This means no
985 * SIMD16_REPDATA for us. :-(
987 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, false, false))
992 params
.depth
.enabled
= true;
994 params
.z
= depth_value
;
995 params
.depth_format
= isl_format_get_depth_format(depth_format
, false);
999 params
.stencil
.enabled
= true;
1001 params
.stencil_mask
= stencil_mask
;
1002 params
.stencil_ref
= stencil_value
;
1005 if (!blorp_params_get_layer_offset_vs(batch
, ¶ms
))
1008 params
.vs_inputs
.base_layer
= start_layer
;
1010 batch
->blorp
->exec(batch
, ¶ms
);
1014 blorp_ccs_resolve(struct blorp_batch
*batch
,
1015 struct blorp_surf
*surf
, uint32_t level
,
1016 uint32_t start_layer
, uint32_t num_layers
,
1017 enum isl_format format
,
1018 enum isl_aux_op resolve_op
)
1020 struct blorp_params params
;
1022 blorp_params_init(¶ms
);
1023 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
,
1024 level
, start_layer
, format
, true);
1026 /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
1028 * A rectangle primitive must be scaled down by the following factors
1029 * with respect to render target being resolved.
1031 * The scaledown factors in the table that follows are related to the block
1032 * size of the CCS format. For IVB and HSW, we divide by two, for BDW we
1033 * multiply by 8 and 16. On Sky Lake, we multiply by 8.
1035 const struct isl_format_layout
*aux_fmtl
=
1036 isl_format_get_layout(params
.dst
.aux_surf
.format
);
1037 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
1039 unsigned x_scaledown
, y_scaledown
;
1040 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 12) {
1041 x_scaledown
= aux_fmtl
->bw
* 8;
1042 y_scaledown
= aux_fmtl
->bh
* 4;
1043 } else if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 9) {
1044 x_scaledown
= aux_fmtl
->bw
* 8;
1045 y_scaledown
= aux_fmtl
->bh
* 8;
1046 } else if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
1047 x_scaledown
= aux_fmtl
->bw
* 8;
1048 y_scaledown
= aux_fmtl
->bh
* 16;
1050 x_scaledown
= aux_fmtl
->bw
/ 2;
1051 y_scaledown
= aux_fmtl
->bh
/ 2;
1053 params
.x0
= params
.y0
= 0;
1054 params
.x1
= minify(params
.dst
.surf
.logical_level0_px
.width
, level
);
1055 params
.y1
= minify(params
.dst
.surf
.logical_level0_px
.height
, level
);
1056 params
.x1
= ALIGN(params
.x1
, x_scaledown
) / x_scaledown
;
1057 params
.y1
= ALIGN(params
.y1
, y_scaledown
) / y_scaledown
;
1059 if (batch
->blorp
->isl_dev
->info
->gen
>= 10) {
1060 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
||
1061 resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
||
1062 resolve_op
== ISL_AUX_OP_AMBIGUATE
);
1063 } else if (batch
->blorp
->isl_dev
->info
->gen
>= 9) {
1064 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
||
1065 resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
1067 /* Broadwell and earlier do not have a partial resolve */
1068 assert(resolve_op
== ISL_AUX_OP_FULL_RESOLVE
);
1070 params
.fast_clear_op
= resolve_op
;
1071 params
.num_layers
= num_layers
;
1073 /* Note: there is no need to initialize push constants because it doesn't
1074 * matter what data gets dispatched to the render target. However, we must
1075 * ensure that the fragment shader delivers the data using the "replicated
1079 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
1082 batch
->blorp
->exec(batch
, ¶ms
);
1085 static nir_ssa_def
*
1086 blorp_nir_bit(nir_builder
*b
, nir_ssa_def
*src
, unsigned bit
)
1088 return nir_iand(b
, nir_ushr(b
, src
, nir_imm_int(b
, bit
)),
1092 struct blorp_mcs_partial_resolve_key
1094 enum blorp_shader_type shader_type
;
1095 bool indirect_clear_color
;
1097 uint32_t num_samples
;
1101 blorp_params_get_mcs_partial_resolve_kernel(struct blorp_batch
*batch
,
1102 struct blorp_params
*params
)
1104 struct blorp_context
*blorp
= batch
->blorp
;
1105 const struct blorp_mcs_partial_resolve_key blorp_key
= {
1106 .shader_type
= BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE
,
1107 .indirect_clear_color
= params
->dst
.clear_color_addr
.buffer
!= NULL
,
1108 .int_format
= isl_format_has_int_channel(params
->dst
.view
.format
),
1109 .num_samples
= params
->num_samples
,
1112 if (blorp
->lookup_shader(batch
, &blorp_key
, sizeof(blorp_key
),
1113 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
1116 void *mem_ctx
= ralloc_context(NULL
);
1119 blorp_nir_init_shader(&b
, mem_ctx
, MESA_SHADER_FRAGMENT
,
1120 "BLORP-mcs-partial-resolve");
1122 nir_variable
*v_color
=
1123 BLORP_CREATE_NIR_INPUT(b
.shader
, clear_color
, glsl_vec4_type());
1125 nir_variable
*frag_color
=
1126 nir_variable_create(b
.shader
, nir_var_shader_out
,
1127 glsl_vec4_type(), "gl_FragColor");
1128 frag_color
->data
.location
= FRAG_RESULT_COLOR
;
1130 /* Do an MCS fetch and check if it is equal to the magic clear value */
1132 blorp_nir_txf_ms_mcs(&b
, nir_f2i32(&b
, nir_load_frag_coord(&b
)),
1133 nir_load_layer_id(&b
));
1134 nir_ssa_def
*is_clear
=
1135 blorp_nir_mcs_is_clear_color(&b
, mcs
, blorp_key
.num_samples
);
1137 /* If we aren't the clear value, discard. */
1138 nir_intrinsic_instr
*discard
=
1139 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_discard_if
);
1140 discard
->src
[0] = nir_src_for_ssa(nir_inot(&b
, is_clear
));
1141 nir_builder_instr_insert(&b
, &discard
->instr
);
1143 nir_ssa_def
*clear_color
= nir_load_var(&b
, v_color
);
1144 if (blorp_key
.indirect_clear_color
&& blorp
->isl_dev
->info
->gen
<= 8) {
1145 /* Gen7-8 clear colors are stored as single 0/1 bits */
1146 clear_color
= nir_vec4(&b
, blorp_nir_bit(&b
, clear_color
, 31),
1147 blorp_nir_bit(&b
, clear_color
, 30),
1148 blorp_nir_bit(&b
, clear_color
, 29),
1149 blorp_nir_bit(&b
, clear_color
, 28));
1151 if (!blorp_key
.int_format
)
1152 clear_color
= nir_i2f32(&b
, clear_color
);
1154 nir_store_var(&b
, frag_color
, clear_color
, 0xf);
1156 struct brw_wm_prog_key wm_key
;
1157 brw_blorp_init_wm_prog_key(&wm_key
);
1158 wm_key
.base
.tex
.compressed_multisample_layout_mask
= 1;
1159 wm_key
.base
.tex
.msaa_16
= blorp_key
.num_samples
== 16;
1160 wm_key
.multisample_fbo
= true;
1162 struct brw_wm_prog_data prog_data
;
1163 const unsigned *program
=
1164 blorp_compile_fs(blorp
, mem_ctx
, b
.shader
, &wm_key
, false,
1168 blorp
->upload_shader(batch
, &blorp_key
, sizeof(blorp_key
),
1169 program
, prog_data
.base
.program_size
,
1170 &prog_data
.base
, sizeof(prog_data
),
1171 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
1173 ralloc_free(mem_ctx
);
1178 blorp_mcs_partial_resolve(struct blorp_batch
*batch
,
1179 struct blorp_surf
*surf
,
1180 enum isl_format format
,
1181 uint32_t start_layer
, uint32_t num_layers
)
1183 struct blorp_params params
;
1184 blorp_params_init(¶ms
);
1186 assert(batch
->blorp
->isl_dev
->info
->gen
>= 7);
1190 params
.x1
= surf
->surf
->logical_level0_px
.width
;
1191 params
.y1
= surf
->surf
->logical_level0_px
.height
;
1193 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.src
, surf
, 0,
1194 start_layer
, format
, false);
1195 brw_blorp_surface_info_init(batch
->blorp
, ¶ms
.dst
, surf
, 0,
1196 start_layer
, format
, true);
1198 params
.num_samples
= params
.dst
.surf
.samples
;
1199 params
.num_layers
= num_layers
;
1200 params
.dst_clear_color_as_input
= surf
->clear_color_addr
.buffer
!= NULL
;
1202 memcpy(¶ms
.wm_inputs
.clear_color
,
1203 surf
->clear_color
.f32
, sizeof(float) * 4);
1205 if (!blorp_params_get_mcs_partial_resolve_kernel(batch
, ¶ms
))
1208 batch
->blorp
->exec(batch
, ¶ms
);
1211 /** Clear a CCS to the "uncompressed" state
1213 * This pass is the CCS equivalent of a "HiZ resolve". It sets the CCS values
1214 * for a given layer/level of a surface to 0x0 which is the "uncompressed"
1215 * state which tells the sampler to go look at the main surface.
1218 blorp_ccs_ambiguate(struct blorp_batch
*batch
,
1219 struct blorp_surf
*surf
,
1220 uint32_t level
, uint32_t layer
)
1222 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 10) {
1223 /* On gen10 and above, we have a hardware resolve op for this */
1224 return blorp_ccs_resolve(batch
, surf
, level
, layer
, 1,
1225 surf
->surf
->format
, ISL_AUX_OP_AMBIGUATE
);
1228 struct blorp_params params
;
1229 blorp_params_init(¶ms
);
1231 assert(ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 7);
1233 const struct isl_format_layout
*aux_fmtl
=
1234 isl_format_get_layout(surf
->aux_surf
->format
);
1235 assert(aux_fmtl
->txc
== ISL_TXC_CCS
);
1237 params
.dst
= (struct brw_blorp_surface_info
) {
1239 .addr
= surf
->aux_addr
,
1241 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1242 .format
= ISL_FORMAT_R32G32B32A32_UINT
,
1244 .base_array_layer
= 0,
1247 .swizzle
= ISL_SWIZZLE_IDENTITY
,
1252 if (surf
->surf
->dim
== ISL_SURF_DIM_3D
) {
1257 uint32_t offset_B
, x_offset_el
, y_offset_el
;
1258 isl_surf_get_image_offset_el(surf
->aux_surf
, level
, layer
, z
,
1259 &x_offset_el
, &y_offset_el
);
1260 isl_tiling_get_intratile_offset_el(surf
->aux_surf
->tiling
, aux_fmtl
->bpb
,
1261 surf
->aux_surf
->row_pitch_B
,
1262 x_offset_el
, y_offset_el
,
1263 &offset_B
, &x_offset_el
, &y_offset_el
);
1264 params
.dst
.addr
.offset
+= offset_B
;
1266 const uint32_t width_px
=
1267 minify(surf
->aux_surf
->logical_level0_px
.width
, level
);
1268 const uint32_t height_px
=
1269 minify(surf
->aux_surf
->logical_level0_px
.height
, level
);
1270 const uint32_t width_el
= DIV_ROUND_UP(width_px
, aux_fmtl
->bw
);
1271 const uint32_t height_el
= DIV_ROUND_UP(height_px
, aux_fmtl
->bh
);
1273 struct isl_tile_info ccs_tile_info
;
1274 isl_surf_get_tile_info(surf
->aux_surf
, &ccs_tile_info
);
1276 /* We're going to map it as a regular RGBA32_UINT surface. We need to
1277 * downscale a good deal. We start by computing the area on the CCS to
1278 * clear in units of Y-tiled cache lines.
1280 uint32_t x_offset_cl
, y_offset_cl
, width_cl
, height_cl
;
1281 if (ISL_DEV_GEN(batch
->blorp
->isl_dev
) >= 8) {
1282 /* From the Sky Lake PRM Vol. 12 in the section on planes:
1284 * "The Color Control Surface (CCS) contains the compression status
1285 * of the cache-line pairs. The compression state of the cache-line
1286 * pair is specified by 2 bits in the CCS. Each CCS cache-line
1287 * represents an area on the main surface of 16x16 sets of 128 byte
1288 * Y-tiled cache-line-pairs. CCS is always Y tiled."
1290 * Each 2-bit surface element in the CCS corresponds to a single
1291 * cache-line pair in the main surface. This means that 16x16 el block
1292 * in the CCS maps to a Y-tiled cache line. Fortunately, CCS layouts
1293 * are calculated with a very large alignment so we can round up to a
1294 * whole cache line without worrying about overdraw.
1297 /* On Broadwell and above, a CCS tile is the same as a Y tile when
1298 * viewed at the cache-line granularity. Fortunately, the horizontal
1299 * and vertical alignment requirements of the CCS are such that we can
1300 * align to an entire cache line without worrying about crossing over
1301 * from one LOD to another.
1303 const uint32_t x_el_per_cl
= ccs_tile_info
.logical_extent_el
.w
/ 8;
1304 const uint32_t y_el_per_cl
= ccs_tile_info
.logical_extent_el
.h
/ 8;
1305 assert(surf
->aux_surf
->image_alignment_el
.w
% x_el_per_cl
== 0);
1306 assert(surf
->aux_surf
->image_alignment_el
.h
% y_el_per_cl
== 0);
1308 assert(x_offset_el
% x_el_per_cl
== 0);
1309 assert(y_offset_el
% y_el_per_cl
== 0);
1310 x_offset_cl
= x_offset_el
/ x_el_per_cl
;
1311 y_offset_cl
= y_offset_el
/ y_el_per_cl
;
1312 width_cl
= DIV_ROUND_UP(width_el
, x_el_per_cl
);
1313 height_cl
= DIV_ROUND_UP(height_el
, y_el_per_cl
);
1315 /* On gen7, the CCS tiling is not so nice. However, there we are
1316 * guaranteed that we only have a single level and slice so we don't
1317 * have to worry about it and can just align to a whole tile.
1319 assert(surf
->aux_surf
->logical_level0_px
.depth
== 1);
1320 assert(surf
->aux_surf
->logical_level0_px
.array_len
== 1);
1321 assert(x_offset_el
== 0 && y_offset_el
== 0);
1322 const uint32_t width_tl
=
1323 DIV_ROUND_UP(width_el
, ccs_tile_info
.logical_extent_el
.w
);
1324 const uint32_t height_tl
=
1325 DIV_ROUND_UP(height_el
, ccs_tile_info
.logical_extent_el
.h
);
1328 width_cl
= width_tl
* 8;
1329 height_cl
= height_tl
* 8;
1332 /* We're going to use a RGBA32 format so as to write data as quickly as
1333 * possible. A y-tiled cache line will then be 1x4 px.
1335 const uint32_t x_offset_rgba_px
= x_offset_cl
;
1336 const uint32_t y_offset_rgba_px
= y_offset_cl
* 4;
1337 const uint32_t width_rgba_px
= width_cl
;
1338 const uint32_t height_rgba_px
= height_cl
* 4;
1341 isl_surf_init(batch
->blorp
->isl_dev
, ¶ms
.dst
.surf
,
1342 .dim
= ISL_SURF_DIM_2D
,
1343 .format
= ISL_FORMAT_R32G32B32A32_UINT
,
1344 .width
= width_rgba_px
+ x_offset_rgba_px
,
1345 .height
= height_rgba_px
+ y_offset_rgba_px
,
1350 .row_pitch_B
= surf
->aux_surf
->row_pitch_B
,
1351 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1352 .tiling_flags
= ISL_TILING_Y0_BIT
);
1355 params
.x0
= x_offset_rgba_px
;
1356 params
.y0
= y_offset_rgba_px
;
1357 params
.x1
= x_offset_rgba_px
+ width_rgba_px
;
1358 params
.y1
= y_offset_rgba_px
+ height_rgba_px
;
1360 /* A CCS value of 0 means "uncompressed." */
1361 memset(¶ms
.wm_inputs
.clear_color
, 0,
1362 sizeof(params
.wm_inputs
.clear_color
));
1364 if (!blorp_params_get_clear_kernel(batch
, ¶ms
, true, false))
1367 batch
->blorp
->exec(batch
, ¶ms
);