src/intel/common/gen_device_info.h

   1  /*
   2   * Copyright © 2013 Intel Corporation
   3   *
   4   * Permission is hereby granted, free of charge, to any person obtaining a
   5   * copy of this software and associated documentation files (the "Software"),
   6   * to deal in the Software without restriction, including without limitation
   7   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8   * and/or sell copies of the Software, and to permit persons to whom the
   9   * Software is furnished to do so, subject to the following conditions:
  10   *
  11   * The above copyright notice and this permission notice (including the next
  12   * paragraph) shall be included in all copies or substantial portions of the
  13   * Software.
  14   *
  15   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20   * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21   * IN THE SOFTWARE.
  22   *
  23   */
  24
  25 #ifndef GEN_DEVICE_INFO_H
  26 #define GEN_DEVICE_INFO_H
  27
  28 #include <stdbool.h>
  29 #include <stdint.h>
  30
  31 /**
  32  * Intel hardware information and quirks
  33  */
  34 struct gen_device_info
  35 {
  36    int gen; /**< Generation number: 4, 5, 6, 7, ... */
  37    int gt;
  38
  39    bool is_g4x;
  40    bool is_ivybridge;
  41    bool is_baytrail;
  42    bool is_haswell;
  43    bool is_broadwell;
  44    bool is_cherryview;
  45    bool is_skylake;
  46    bool is_broxton;
  47    bool is_kabylake;
  48    bool is_geminilake;
  49    bool is_coffeelake;
  50    bool is_cannonlake;
  51
  52    bool has_hiz_and_separate_stencil;
  53    bool must_use_separate_stencil;
  54
  55    bool has_llc;
  56
  57    bool has_pln;
  58    bool has_compr4;
  59    bool has_surface_tile_offset;
  60    bool supports_simd16_3src;
  61    bool has_resource_streamer;
  62
  63    /**
  64     * \name Intel hardware quirks
  65     *  @{
  66     */
  67    bool has_negative_rhw_bug;
  68
  69    /**
  70     * Some versions of Gen hardware don't do centroid interpolation correctly
  71     * on unlit pixels, causing incorrect values for derivatives near triangle
  72     * edges.  Enabling this flag causes the fragment shader to use
  73     * non-centroid interpolation for unlit pixels, at the expense of two extra
  74     * fragment shader instructions.
  75     */
  76    bool needs_unlit_centroid_workaround;
  77    /** @} */
  78
  79    /**
  80     * \name GPU hardware limits
  81     *
  82     * In general, you can find shader thread maximums by looking at the "Maximum
  83     * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
  84     * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
  85     * limits come from the "Number of URB Entries" field in the
  86     * 3DSTATE_URB_VS command and friends.
  87     *
  88     * These fields are used to calculate the scratch space to allocate.  The
  89     * amount of scratch space can be larger without being harmful on modern
  90     * GPUs, however, prior to Haswell, programming the maximum number of threads
  91     * to greater than the hardware maximum would cause GPU performance to tank.
  92     *
  93     *  @{
  94     */
  95    /**
  96     * Total number of slices present on the device whether or not they've been
  97     * fused off.
  98     *
  99     * XXX: CS thread counts are limited by the inability to do cross subslice
 100     * communication. It is the effectively the number of logical threads which
 101     * can be executed in a subslice. Fuse configurations may cause this number
 102     * to change, so we program @max_cs_threads as the lower maximum.
 103     */
 104    unsigned num_slices;
 105
 106    /**
 107     * Number of subslices for each slice (used to be uniform until CNL).
 108     */
 109    unsigned num_subslices[3];
 110
 111    /**
 112     * Number of threads per eu, varies between 4 and 8 between generations.
 113     */
 114    unsigned num_thread_per_eu;
 115
 116    unsigned l3_banks;
 117    unsigned max_vs_threads;   /**< Maximum Vertex Shader threads */
 118    unsigned max_tcs_threads;  /**< Maximum Hull Shader threads */
 119    unsigned max_tes_threads;  /**< Maximum Domain Shader threads */
 120    unsigned max_gs_threads;   /**< Maximum Geometry Shader threads. */
 121    /**
 122     * Theoretical maximum number of Pixel Shader threads.
 123     *
 124     * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will
 125     * automatically scale pixel shader thread count, based on a single value
 126     * programmed into 3DSTATE_PS.
 127     *
 128     * To calculate the maximum number of threads for Gen8 beyond (which have
 129     * multiple Pixel Shader Dispatchers):
 130     *
 131     * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD"
 132     * - Usually there's only one PSD per subslice, so use the number of
 133     *   subslices for number of PSDs.
 134     * - For max_wm_threads, the total should be PSD threads * #PSDs.
 135     */
 136    unsigned max_wm_threads;
 137
 138    /**
 139     * Maximum Compute Shader threads.
 140     *
 141     * Thread count * number of EUs per subslice
 142     */
 143    unsigned max_cs_threads;
 144
 145    struct {
 146       /**
 147        * Hardware default URB size.
 148        *
 149        * The units this is expressed in are somewhat inconsistent: 512b units
 150        * on Gen4-5, KB on Gen6-7, and KB times the slice count on Gen8+.
 151        *
 152        * Look up "URB Size" in the "Device Attributes" page, and take the
 153        * maximum.  Look up the slice count for each GT SKU on the same page.
 154        * urb.size = URB Size (kbytes) / slice count
 155        */
 156       unsigned size;
 157
 158       /**
 159        * The minimum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
 160        */
 161       unsigned min_entries[4];
 162
 163       /**
 164        * The maximum number of URB entries.  See the 3DSTATE_URB_<XS> docs.
 165        */
 166       unsigned max_entries[4];
 167    } urb;
 168
 169    /**
 170     * For the longest time the timestamp frequency for Gen's timestamp counter
 171     * could be assumed to be 12.5MHz, where the least significant bit neatly
 172     * corresponded to 80 nanoseconds.
 173     *
 174     * Since Gen9 the numbers aren't so round, with a a frequency of 12MHz for
 175     * SKL (or scale factor of 83.33333333) and a frequency of 19200000Hz for
 176     * BXT.
 177     *
 178     * For simplicty to fit with the current code scaling by a single constant
 179     * to map from raw timestamps to nanoseconds we now do the conversion in
 180     * floating point instead of integer arithmetic.
 181     *
 182     * In general it's probably worth noting that the documented constants we
 183     * have for the per-platform timestamp frequencies aren't perfect and
 184     * shouldn't be trusted for scaling and comparing timestamps with a large
 185     * delta.
 186     *
 187     * E.g. with crude testing on my system using the 'correct' scale factor I'm
 188     * seeing a drift of ~2 milliseconds per second.
 189     */
 190    uint64_t timestamp_frequency;
 191
 192    /** @} */
 193 };
 194
 195 #define gen_device_info_is_9lp(devinfo) \
 196    ((devinfo)->is_broxton || (devinfo)->is_geminilake)
 197
 198 bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
 199 const char *gen_get_device_name(int devid);
 200
 201 #endif /* GEN_DEVICE_INFO_H */