src/intel/common/gen_l3_config.c

   1 /*
   2  * Copyright (c) 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdlib.h>
  25 #include <math.h>
  26
  27 #include "util/macros.h"
  28 #include "main/macros.h"
  29
  30 #include "gen_l3_config.h"
  31
  32 struct gen_l3_list {
  33    const struct gen_l3_config *configs;
  34    int length;
  35 };
  36
  37 #define DECLARE_L3_LIST(hw) \
  38    struct gen_l3_list hw##_l3_list = \
  39    { .configs = hw##_l3_configs, .length = ARRAY_SIZE(hw##_l3_configs) }
  40
  41 /**
  42  * IVB/HSW validated L3 configurations.  The first entry will be used as
  43  * default by gen7_restore_default_l3_config(), otherwise the ordering is
  44  * unimportant.
  45  */
  46 static const struct gen_l3_config ivb_l3_configs[] = {
  47    /* SLM URB ALL DC  RO  IS   C   T */
  48    {{  0, 32,  0,  0, 32,  0,  0,  0 }},
  49    {{  0, 32,  0, 16, 16,  0,  0,  0 }},
  50    {{  0, 32,  0,  4,  0,  8,  4, 16 }},
  51    {{  0, 28,  0,  8,  0,  8,  4, 16 }},
  52    {{  0, 28,  0, 16,  0,  8,  4,  8 }},
  53    {{  0, 28,  0,  8,  0, 16,  4,  8 }},
  54    {{  0, 28,  0,  0,  0, 16,  4, 16 }},
  55    {{  0, 32,  0,  0,  0, 16,  0, 16 }},
  56    {{  0, 28,  0,  4, 32,  0,  0,  0 }},
  57    {{ 16, 16,  0, 16, 16,  0,  0,  0 }},
  58    {{ 16, 16,  0,  8,  0,  8,  8,  8 }},
  59    {{ 16, 16,  0,  4,  0,  8,  4, 16 }},
  60    {{ 16, 16,  0,  4,  0, 16,  4,  8 }},
  61    {{ 16, 16,  0,  0, 32,  0,  0,  0 }},
  62 };
  63 DECLARE_L3_LIST(ivb);
  64
  65 /**
  66  * VLV validated L3 configurations.  \sa ivb_l3_configs.
  67  */
  68 static const struct gen_l3_config vlv_l3_configs[] = {
  69    /* SLM URB ALL DC  RO  IS   C   T */
  70    {{  0, 64,  0,  0, 32,  0,  0,  0 }},
  71    {{  0, 80,  0,  0, 16,  0,  0,  0 }},
  72    {{  0, 80,  0,  8,  8,  0,  0,  0 }},
  73    {{  0, 64,  0, 16, 16,  0,  0,  0 }},
  74    {{  0, 60,  0,  4, 32,  0,  0,  0 }},
  75    {{ 32, 32,  0, 16, 16,  0,  0,  0 }},
  76    {{ 32, 40,  0,  8, 16,  0,  0,  0 }},
  77    {{ 32, 40,  0, 16,  8,  0,  0,  0 }},
  78 };
  79 DECLARE_L3_LIST(vlv);
  80
  81 /**
  82  * BDW validated L3 configurations.  \sa ivb_l3_configs.
  83  */
  84 static const struct gen_l3_config bdw_l3_configs[] = {
  85    /* SLM URB ALL DC  RO  IS   C   T */
  86    {{  0, 48, 48,  0,  0,  0,  0,  0 }},
  87    {{  0, 48,  0, 16, 32,  0,  0,  0 }},
  88    {{  0, 32,  0, 16, 48,  0,  0,  0 }},
  89    {{  0, 32,  0,  0, 64,  0,  0,  0 }},
  90    {{  0, 32, 64,  0,  0,  0,  0,  0 }},
  91    {{ 24, 16, 48,  0,  0,  0,  0,  0 }},
  92    {{ 24, 16,  0, 16, 32,  0,  0,  0 }},
  93    {{ 24, 16,  0, 32, 16,  0,  0,  0 }},
  94 };
  95 DECLARE_L3_LIST(bdw);
  96
  97 /**
  98  * CHV/SKL validated L3 configurations.  \sa ivb_l3_configs.
  99  */
 100 static const struct gen_l3_config chv_l3_configs[] = {
 101    /* SLM URB ALL DC  RO  IS   C   T */
 102    {{  0, 48, 48,  0,  0,  0,  0,  0 }},
 103    {{  0, 48,  0, 16, 32,  0,  0,  0 }},
 104    {{  0, 32,  0, 16, 48,  0,  0,  0 }},
 105    {{  0, 32,  0,  0, 64,  0,  0,  0 }},
 106    {{  0, 32, 64,  0,  0,  0,  0,  0 }},
 107    {{ 32, 16, 48,  0,  0,  0,  0,  0 }},
 108    {{ 32, 16,  0, 16, 32,  0,  0,  0 }},
 109    {{ 32, 16,  0, 32, 16,  0,  0,  0 }},
 110 };
 111 DECLARE_L3_LIST(chv);
 112
 113 /**
 114  * BXT 2x6 validated L3 configurations.  \sa ivb_l3_configs.
 115  */
 116 static const struct gen_l3_config bxt_2x6_l3_configs[] = {
 117    /* SLM URB ALL DC  RO  IS   C   T */
 118    {{  0, 32, 48,  0,  0,  0,  0,  0 }},
 119    {{  0, 32,  0,  8, 40,  0,  0,  0 }},
 120    {{  0, 32,  0, 32, 16,  0,  0,  0 }},
 121    {{ 16, 16, 48,  0,  0,  0,  0,  0 }},
 122    {{ 16, 16,  0, 40,  8,  0,  0,  0 }},
 123    {{ 16, 16,  0, 16, 32,  0,  0,  0 }},
 124 };
 125 DECLARE_L3_LIST(bxt_2x6);
 126
 127 /**
 128  * CNL validated L3 configurations.  \sa ivb_l3_configs.
 129  */
 130 static const struct gen_l3_config cnl_l3_configs[] = {
 131    /* SLM URB ALL DC  RO  IS   C   T */
 132    {{  0, 64, 64,  0,  0,  0,  0,  0 }},
 133    {{  0, 64,  0, 16, 48,  0,  0,  0 }},
 134    {{  0, 48,  0, 16, 64,  0,  0,  0 }},
 135    {{  0, 32,  0,  0, 96,  0,  0,  0 }},
 136    {{  0, 32, 96,  0,  0,  0,  0,  0 }},
 137    {{  0, 32,  0, 16, 80,  0,  0,  0 }},
 138    {{ 32, 16, 80,  0,  0,  0,  0,  0 }},
 139    {{ 32, 16,  0, 64, 16,  0,  0,  0 }},
 140    {{ 32,  0, 96,  0,  0,  0,  0,  0 }},
 141 };
 142 DECLARE_L3_LIST(cnl);
 143
 144 /**
 145  * ICL validated L3 configurations.  \sa icl_l3_configs.
 146  * Zeroth entry in below table has been commented out intentionally
 147  * due to known issues with this configuration. Many other entries
 148  * suggested by h/w specification aren't added here because they
 149  * do under allocation of L3 cache with below partitioning.
 150  */
 151 static const struct gen_l3_config icl_l3_configs[] = {
 152    /* SLM URB ALL DC  RO  IS   C   T */
 153    /*{{  0, 16, 80,  0,  0,  0,  0,  0 }},*/
 154    {{  0, 32, 64,  0,  0,  0,  0,  0 }},
 155 };
 156 DECLARE_L3_LIST(icl);
 157
 158 /**
 159  * TGL validated L3 configurations.  \sa tgl_l3_configs.
 160  */
 161 static const struct gen_l3_config tgl_l3_configs[] = {
 162    /* SLM URB ALL DC  RO  IS   C   T */
 163    {{  0, 32,  88,  0,  0,  0,  0,  0 }},
 164    {{  0, 16, 104,  0,  0,  0,  0,  0 }},
 165 };
 166 DECLARE_L3_LIST(tgl);
 167
 168 /**
 169  * DG1 validated L3 configurations.  \sa dg1_l3_configs.
 170  */
 171 static const struct gen_l3_config dg1_l3_configs[] = {
 172    /* No configurations. L3FullWayAllocationEnable is always set. */
 173 };
 174 DECLARE_L3_LIST(dg1);
 175
 176 /**
 177  * Return a zero-terminated array of validated L3 configurations for the
 178  * specified device.
 179  */
 180 static const struct gen_l3_list *
 181 get_l3_list(const struct gen_device_info *devinfo)
 182 {
 183    switch (devinfo->gen) {
 184    case 7:
 185       return (devinfo->is_baytrail ? &vlv_l3_list : &ivb_l3_list);
 186
 187    case 8:
 188       return (devinfo->is_cherryview ? &chv_l3_list : &bdw_l3_list);
 189
 190    case 9:
 191       if (devinfo->l3_banks == 1)
 192          return &bxt_2x6_l3_list;
 193       return &chv_l3_list;
 194
 195    case 10:
 196       return &cnl_l3_list;
 197
 198    case 11:
 199       return &icl_l3_list;
 200
 201    case 12:
 202       if (devinfo->is_dg1)
 203          return &dg1_l3_list;
 204       else
 205          return &tgl_l3_list;
 206
 207    default:
 208       unreachable("Not implemented");
 209    }
 210 }
 211
 212 /**
 213  * L1-normalize a vector of L3 partition weights.
 214  */
 215 static struct gen_l3_weights
 216 norm_l3_weights(struct gen_l3_weights w)
 217 {
 218    float sz = 0;
 219
 220    for (unsigned i = 0; i < GEN_NUM_L3P; i++)
 221       sz += w.w[i];
 222
 223    for (unsigned i = 0; i < GEN_NUM_L3P; i++)
 224       w.w[i] /= sz;
 225
 226    return w;
 227 }
 228
 229 /**
 230  * Get the relative partition weights of the specified L3 configuration.
 231  */
 232 struct gen_l3_weights
 233 gen_get_l3_config_weights(const struct gen_l3_config *cfg)
 234 {
 235    if (cfg) {
 236       struct gen_l3_weights w;
 237
 238       for (unsigned i = 0; i < GEN_NUM_L3P; i++)
 239          w.w[i] = cfg->n[i];
 240
 241       return norm_l3_weights(w);
 242    } else {
 243       const struct gen_l3_weights w = { { 0 } };
 244       return w;
 245    }
 246 }
 247
 248 /**
 249  * Distance between two L3 configurations represented as vectors of weights.
 250  * Usually just the L1 metric except when the two configurations are
 251  * considered incompatible in which case the distance will be infinite.  Note
 252  * that the compatibility condition is asymmetric -- They will be considered
 253  * incompatible whenever the reference configuration \p w0 requires SLM, DC,
 254  * or URB but \p w1 doesn't provide it.
 255  */
 256 float
 257 gen_diff_l3_weights(struct gen_l3_weights w0, struct gen_l3_weights w1)
 258 {
 259    if ((w0.w[GEN_L3P_SLM] && !w1.w[GEN_L3P_SLM]) ||
 260        (w0.w[GEN_L3P_DC] && !w1.w[GEN_L3P_DC] && !w1.w[GEN_L3P_ALL]) ||
 261        (w0.w[GEN_L3P_URB] && !w1.w[GEN_L3P_URB])) {
 262       return HUGE_VALF;
 263
 264    } else {
 265       float dw = 0;
 266
 267       for (unsigned i = 0; i < GEN_NUM_L3P; i++)
 268          dw += fabsf(w0.w[i] - w1.w[i]);
 269
 270       return dw;
 271    }
 272 }
 273
 274 /**
 275  * Return a reasonable default L3 configuration for the specified device based
 276  * on whether SLM and DC are required.  In the non-SLM non-DC case the result
 277  * is intended to approximately resemble the hardware defaults.
 278  */
 279 struct gen_l3_weights
 280 gen_get_default_l3_weights(const struct gen_device_info *devinfo,
 281                            bool needs_dc, bool needs_slm)
 282 {
 283    struct gen_l3_weights w = {{ 0 }};
 284
 285    w.w[GEN_L3P_SLM] = devinfo->gen < 11 && needs_slm;
 286    w.w[GEN_L3P_URB] = 1.0;
 287
 288    if (devinfo->gen >= 8) {
 289       w.w[GEN_L3P_ALL] = 1.0;
 290    } else {
 291       w.w[GEN_L3P_DC] = needs_dc ? 0.1 : 0;
 292       w.w[GEN_L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0;
 293    }
 294
 295    return norm_l3_weights(w);
 296 }
 297
 298 /**
 299  * Get the default L3 configuration
 300  */
 301 const struct gen_l3_config *
 302 gen_get_default_l3_config(const struct gen_device_info *devinfo)
 303 {
 304    /* For efficiency assume that the first entry of the array matches the
 305     * default configuration.
 306     */
 307    const struct gen_l3_list *const list = get_l3_list(devinfo);
 308    assert(list->length > 0 || devinfo->gen >= 12);
 309    if (list->length > 0) {
 310       const struct gen_l3_config *const cfg = &list->configs[0];
 311       assert(cfg == gen_get_l3_config(devinfo,
 312                        gen_get_default_l3_weights(devinfo, false, false)));
 313       return cfg;
 314    } else {
 315       return NULL;
 316    }
 317 }
 318
 319 /**
 320  * Return the closest validated L3 configuration for the specified device and
 321  * weight vector.
 322  */
 323 const struct gen_l3_config *
 324 gen_get_l3_config(const struct gen_device_info *devinfo,
 325                   struct gen_l3_weights w0)
 326 {
 327    const struct gen_l3_list *const list = get_l3_list(devinfo);
 328    const struct gen_l3_config *const cfgs = list->configs;
 329    const struct gen_l3_config *cfg_best = NULL;
 330    float dw_best = HUGE_VALF;
 331
 332    for (int i = 0; i < list->length; i++) {
 333       const struct gen_l3_config *cfg = &cfgs[i];
 334       const float dw = gen_diff_l3_weights(w0, gen_get_l3_config_weights(cfg));
 335
 336       if (dw < dw_best) {
 337          cfg_best = cfg;
 338          dw_best = dw;
 339       }
 340    }
 341
 342    assert(cfg_best || devinfo->gen >= 12);
 343    return cfg_best;
 344 }
 345
 346 /**
 347  * Return the size of an L3 way in KB.
 348  */
 349 static unsigned
 350 get_l3_way_size(const struct gen_device_info *devinfo)
 351 {
 352    const unsigned way_size_per_bank =
 353       (devinfo->gen >= 9 && devinfo->l3_banks == 1) || devinfo->gen >= 11 ?
 354       4 : 2;
 355
 356    assert(devinfo->l3_banks);
 357    return way_size_per_bank * devinfo->l3_banks;
 358 }
 359
 360 /**
 361  * Return the unit brw_context::urb::size is expressed in, in KB.  \sa
 362  * gen_device_info::urb::size.
 363  */
 364 static unsigned
 365 get_urb_size_scale(const struct gen_device_info *devinfo)
 366 {
 367    return (devinfo->gen >= 8 ? devinfo->num_slices : 1);
 368 }
 369
 370 unsigned
 371 gen_get_l3_config_urb_size(const struct gen_device_info *devinfo,
 372                            const struct gen_l3_config *cfg)
 373 {
 374    /* From the SKL "L3 Allocation and Programming" documentation:
 375     *
 376     * "URB is limited to 1008KB due to programming restrictions.  This is not
 377     * a restriction of the L3 implementation, but of the FF and other clients.
 378     * Therefore, in a GT4 implementation it is possible for the programmed
 379     * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
 380     * only 1008KB of this will be used."
 381     */
 382    const unsigned max = (devinfo->gen == 9 ? 1008 : ~0);
 383    return MIN2(max, cfg->n[GEN_L3P_URB] * get_l3_way_size(devinfo)) /
 384           get_urb_size_scale(devinfo);
 385 }
 386
 387 /**
 388  * Print out the specified L3 configuration.
 389  */
 390 void
 391 gen_dump_l3_config(const struct gen_l3_config *cfg, FILE *fp)
 392 {
 393    fprintf(stderr, "SLM=%d URB=%d ALL=%d DC=%d RO=%d IS=%d C=%d T=%d\n",
 394            cfg->n[GEN_L3P_SLM], cfg->n[GEN_L3P_URB], cfg->n[GEN_L3P_ALL],
 395            cfg->n[GEN_L3P_DC], cfg->n[GEN_L3P_RO],
 396            cfg->n[GEN_L3P_IS], cfg->n[GEN_L3P_C], cfg->n[GEN_L3P_T]);
 397 }