src/intel/compiler/brw_compiler.c

   1 /*
   2  * Copyright © 2015-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_compiler.h"
  25 #include "brw_shader.h"
  26 #include "brw_eu.h"
  27 #include "dev/gen_debug.h"
  28 #include "compiler/nir/nir.h"
  29 #include "main/errors.h"
  30 #include "util/debug.h"
  31
  32 #define COMMON_OPTIONS                                                        \
  33    .lower_sub = true,                                                         \
  34    .lower_fdiv = true,                                                        \
  35    .lower_scmp = true,                                                        \
  36    .lower_flrp16 = true,                                                      \
  37    .lower_fmod = true,                                                        \
  38    .lower_bitfield_extract = true,                                            \
  39    .lower_bitfield_insert = true,                                             \
  40    .lower_uadd_carry = true,                                                  \
  41    .lower_usub_borrow = true,                                                 \
  42    .lower_fdiv = true,                                                        \
  43    .lower_flrp64 = true,                                                      \
  44    .lower_isign = true,                                                       \
  45    .lower_ldexp = true,                                                       \
  46    .lower_device_index_to_zero = true,                                        \
  47    .vectorize_io = true,                                                      \
  48    .use_interpolated_input_intrinsics = true,                                 \
  49    .vertex_id_zero_based = true,                                              \
  50    .lower_base_vertex = true,                                                 \
  51    .use_scoped_memory_barrier = true,                                         \
  52    .support_8bit_alu = true,                                                  \
  53    .support_16bit_alu = true
  54
  55 #define COMMON_SCALAR_OPTIONS                                                 \
  56    .lower_to_scalar = true,                                                   \
  57    .lower_pack_half_2x16 = true,                                              \
  58    .lower_pack_snorm_2x16 = true,                                             \
  59    .lower_pack_snorm_4x8 = true,                                              \
  60    .lower_pack_unorm_2x16 = true,                                             \
  61    .lower_pack_unorm_4x8 = true,                                              \
  62    .lower_unpack_half_2x16 = true,                                            \
  63    .lower_unpack_snorm_2x16 = true,                                           \
  64    .lower_unpack_snorm_4x8 = true,                                            \
  65    .lower_unpack_unorm_2x16 = true,                                           \
  66    .lower_unpack_unorm_4x8 = true,                                            \
  67    .lower_usub_sat64 = true,                                                  \
  68    .lower_hadd64 = true,                                                      \
  69    .max_unroll_iterations = 32
  70
  71 static const struct nir_shader_compiler_options scalar_nir_options = {
  72    COMMON_OPTIONS,
  73    COMMON_SCALAR_OPTIONS,
  74 };
  75
  76 static const struct nir_shader_compiler_options vector_nir_options = {
  77    COMMON_OPTIONS,
  78
  79    /* In the vec4 backend, our dpN instruction replicates its result to all the
  80     * components of a vec4.  We would like NIR to give us replicated fdot
  81     * instructions because it can optimize better for us.
  82     */
  83    .fdot_replicates = true,
  84
  85    .lower_pack_snorm_2x16 = true,
  86    .lower_pack_unorm_2x16 = true,
  87    .lower_unpack_snorm_2x16 = true,
  88    .lower_unpack_unorm_2x16 = true,
  89    .lower_extract_byte = true,
  90    .lower_extract_word = true,
  91    .intel_vec4 = true,
  92    .max_unroll_iterations = 32,
  93 };
  94
  95 struct brw_compiler *
  96 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
  97 {
  98    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  99
 100    compiler->devinfo = devinfo;
 101
 102    brw_fs_alloc_reg_sets(compiler);
 103    brw_vec4_alloc_reg_set(compiler);
 104    brw_init_compaction_tables(devinfo);
 105
 106    compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 107
 108    compiler->use_tcs_8_patch =
 109       devinfo->gen >= 12 ||
 110       (devinfo->gen >= 9 && (INTEL_DEBUG & DEBUG_TCS_EIGHT_PATCH));
 111
 112    if (devinfo->gen >= 10) {
 113       /* We don't support vec4 mode on Cannonlake. */
 114       for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++)
 115          compiler->scalar_stage[i] = true;
 116    } else {
 117       compiler->scalar_stage[MESA_SHADER_VERTEX] =
 118          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_VS", true);
 119       compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
 120          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
 121       compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
 122          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
 123       compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
 124          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
 125       compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
 126       compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
 127    }
 128
 129    nir_lower_int64_options int64_options =
 130       nir_lower_imul64 |
 131       nir_lower_isign64 |
 132       nir_lower_divmod64 |
 133       nir_lower_imul_high64;
 134    nir_lower_doubles_options fp64_options =
 135       nir_lower_drcp |
 136       nir_lower_dsqrt |
 137       nir_lower_drsq |
 138       nir_lower_dtrunc |
 139       nir_lower_dfloor |
 140       nir_lower_dceil |
 141       nir_lower_dfract |
 142       nir_lower_dround_even |
 143       nir_lower_dmod |
 144       nir_lower_dsub |
 145       nir_lower_ddiv;
 146
 147    if (!devinfo->has_64bit_float || (INTEL_DEBUG & DEBUG_SOFT64)) {
 148       int64_options |= nir_lower_mov64 |
 149                        nir_lower_icmp64 |
 150                        nir_lower_iadd64 |
 151                        nir_lower_iabs64 |
 152                        nir_lower_ineg64 |
 153                        nir_lower_logic64 |
 154                        nir_lower_minmax64 |
 155                        nir_lower_shift64 |
 156                        nir_lower_extract64;
 157       fp64_options |= nir_lower_fp64_full_software;
 158    }
 159
 160    /* The Bspec's section tittled "Instruction_multiply[DevBDW+]" claims that
 161     * destination type can be Quadword and source type Doubleword for Gen8 and
 162     * Gen9. So, lower 64 bit multiply instruction on rest of the platforms.
 163     */
 164    if (devinfo->gen < 8 || devinfo->gen > 9)
 165       int64_options |= nir_lower_imul_2x32_64;
 166
 167    /* We want the GLSL compiler to emit code that uses condition codes */
 168    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 169       compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
 170       compiler->glsl_compiler_options[i].MaxIfDepth =
 171          devinfo->gen < 6 ? 16 : UINT_MAX;
 172
 173       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 174       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 175
 176       bool is_scalar = compiler->scalar_stage[i];
 177
 178       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 179       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 180       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 181
 182       struct nir_shader_compiler_options *nir_options =
 183          rzalloc(compiler, struct nir_shader_compiler_options);
 184       if (is_scalar) {
 185          *nir_options = scalar_nir_options;
 186       } else {
 187          *nir_options = vector_nir_options;
 188       }
 189
 190       /* Prior to Gen6, there are no three source operations, and Gen11 loses
 191        * LRP.
 192        */
 193       nir_options->lower_ffma = devinfo->gen < 6;
 194       nir_options->lower_flrp32 = devinfo->gen < 6 || devinfo->gen >= 11;
 195       nir_options->lower_fpow = devinfo->gen >= 12;
 196
 197       nir_options->lower_rotate = devinfo->gen < 11;
 198       nir_options->lower_bitfield_reverse = devinfo->gen < 7;
 199
 200       nir_options->lower_int64_options = int64_options;
 201       nir_options->lower_doubles_options = fp64_options;
 202
 203       nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
 204
 205       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 206
 207       compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
 208    }
 209
 210    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 211    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 212    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false;
 213
 214    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 215       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 216
 217    return compiler;
 218 }
 219
 220 static void
 221 insert_u64_bit(uint64_t *val, bool add)
 222 {
 223    *val = (*val << 1) | !!add;
 224 }
 225
 226 uint64_t
 227 brw_get_compiler_config_value(const struct brw_compiler *compiler)
 228 {
 229    uint64_t config = 0;
 230    insert_u64_bit(&config, compiler->precise_trig);
 231    if (compiler->devinfo->gen >= 8 && compiler->devinfo->gen < 10) {
 232       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_VERTEX]);
 233       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
 234       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
 235       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
 236    }
 237    uint64_t debug_bits = INTEL_DEBUG;
 238    uint64_t mask = DEBUG_DISK_CACHE_MASK;
 239    while (mask != 0) {
 240       const uint64_t bit = 1ULL << (ffsll(mask) - 1);
 241       insert_u64_bit(&config, (debug_bits & bit) != 0);
 242       mask &= ~bit;
 243    }
 244    return config;
 245 }
 246
 247 unsigned
 248 brw_prog_data_size(gl_shader_stage stage)
 249 {
 250    STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
 251    STATIC_ASSERT(MESA_SHADER_TESS_CTRL == 1);
 252    STATIC_ASSERT(MESA_SHADER_TESS_EVAL == 2);
 253    STATIC_ASSERT(MESA_SHADER_GEOMETRY == 3);
 254    STATIC_ASSERT(MESA_SHADER_FRAGMENT == 4);
 255    STATIC_ASSERT(MESA_SHADER_COMPUTE == 5);
 256    static const size_t stage_sizes[] = {
 257       sizeof(struct brw_vs_prog_data),
 258       sizeof(struct brw_tcs_prog_data),
 259       sizeof(struct brw_tes_prog_data),
 260       sizeof(struct brw_gs_prog_data),
 261       sizeof(struct brw_wm_prog_data),
 262       sizeof(struct brw_cs_prog_data),
 263    };
 264    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 265    return stage_sizes[stage];
 266 }
 267
 268 unsigned
 269 brw_prog_key_size(gl_shader_stage stage)
 270 {
 271    static const size_t stage_sizes[] = {
 272       sizeof(struct brw_vs_prog_key),
 273       sizeof(struct brw_tcs_prog_key),
 274       sizeof(struct brw_tes_prog_key),
 275       sizeof(struct brw_gs_prog_key),
 276       sizeof(struct brw_wm_prog_key),
 277       sizeof(struct brw_cs_prog_key),
 278    };
 279    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 280    return stage_sizes[stage];
 281 }