src/intel/compiler/brw_compiler.c

   1 /*
   2  * Copyright © 2015-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_compiler.h"
  25 #include "brw_shader.h"
  26 #include "brw_eu.h"
  27 #include "common/gen_debug.h"
  28 #include "compiler/nir/nir.h"
  29 #include "main/errors.h"
  30 #include "util/debug.h"
  31
  32 #define COMMON_OPTIONS                                                        \
  33    .lower_sub = true,                                                         \
  34    .lower_fdiv = true,                                                        \
  35    .lower_scmp = true,                                                        \
  36    .lower_fmod16 = true,                                                      \
  37    .lower_fmod32 = true,                                                      \
  38    .lower_fmod64 = false,                                                     \
  39    .lower_bitfield_extract = true,                                            \
  40    .lower_bitfield_insert = true,                                             \
  41    .lower_uadd_carry = true,                                                  \
  42    .lower_usub_borrow = true,                                                 \
  43    .lower_fdiv = true,                                                        \
  44    .lower_flrp64 = true,                                                      \
  45    .lower_isign = true,                                                       \
  46    .lower_ldexp = true,                                                       \
  47    .lower_cs_local_id_from_index = true,                                      \
  48    .lower_device_index_to_zero = true,                                        \
  49    .native_integers = true,                                                   \
  50    .use_interpolated_input_intrinsics = true,                                 \
  51    .vertex_id_zero_based = true,                                              \
  52    .lower_base_vertex = true
  53
  54 #define COMMON_SCALAR_OPTIONS                                                 \
  55    .lower_pack_half_2x16 = true,                                              \
  56    .lower_pack_snorm_2x16 = true,                                             \
  57    .lower_pack_snorm_4x8 = true,                                              \
  58    .lower_pack_unorm_2x16 = true,                                             \
  59    .lower_pack_unorm_4x8 = true,                                              \
  60    .lower_unpack_half_2x16 = true,                                            \
  61    .lower_unpack_snorm_2x16 = true,                                           \
  62    .lower_unpack_snorm_4x8 = true,                                            \
  63    .lower_unpack_unorm_2x16 = true,                                           \
  64    .lower_unpack_unorm_4x8 = true,                                            \
  65    .max_unroll_iterations = 32
  66
  67 static const struct nir_shader_compiler_options scalar_nir_options = {
  68    COMMON_OPTIONS,
  69    COMMON_SCALAR_OPTIONS,
  70 };
  71
  72 static const struct nir_shader_compiler_options scalar_nir_options_gen11 = {
  73    COMMON_OPTIONS,
  74    COMMON_SCALAR_OPTIONS,
  75    .lower_flrp32 = true,
  76 };
  77
  78 static const struct nir_shader_compiler_options vector_nir_options = {
  79    COMMON_OPTIONS,
  80
  81    /* In the vec4 backend, our dpN instruction replicates its result to all the
  82     * components of a vec4.  We would like NIR to give us replicated fdot
  83     * instructions because it can optimize better for us.
  84     */
  85    .fdot_replicates = true,
  86
  87    /* Prior to Gen6, there are no three source operations for SIMD4x2. */
  88    .lower_flrp32 = true,
  89
  90    .lower_pack_snorm_2x16 = true,
  91    .lower_pack_unorm_2x16 = true,
  92    .lower_unpack_snorm_2x16 = true,
  93    .lower_unpack_unorm_2x16 = true,
  94    .lower_extract_byte = true,
  95    .lower_extract_word = true,
  96    .max_unroll_iterations = 32,
  97 };
  98
  99 static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
 100    COMMON_OPTIONS,
 101
 102    /* In the vec4 backend, our dpN instruction replicates its result to all the
 103     * components of a vec4.  We would like NIR to give us replicated fdot
 104     * instructions because it can optimize better for us.
 105     */
 106    .fdot_replicates = true,
 107
 108    .lower_pack_snorm_2x16 = true,
 109    .lower_pack_unorm_2x16 = true,
 110    .lower_unpack_snorm_2x16 = true,
 111    .lower_unpack_unorm_2x16 = true,
 112    .lower_extract_byte = true,
 113    .lower_extract_word = true,
 114    .max_unroll_iterations = 32,
 115 };
 116
 117 struct brw_compiler *
 118 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
 119 {
 120    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
 121
 122    compiler->devinfo = devinfo;
 123
 124    brw_fs_alloc_reg_sets(compiler);
 125    brw_vec4_alloc_reg_set(compiler);
 126    brw_init_compaction_tables(devinfo);
 127
 128    compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 129
 130    if (devinfo->gen >= 10) {
 131       /* We don't support vec4 mode on Cannonlake. */
 132       for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++)
 133          compiler->scalar_stage[i] = true;
 134    } else {
 135       compiler->scalar_stage[MESA_SHADER_VERTEX] =
 136          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_VS", true);
 137       compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
 138          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
 139       compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
 140          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
 141       compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
 142          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
 143       compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
 144       compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
 145    }
 146
 147    nir_lower_int64_options int64_options =
 148       nir_lower_imul64 |
 149       nir_lower_isign64 |
 150       nir_lower_divmod64 |
 151       nir_lower_imul_high64;
 152    nir_lower_doubles_options fp64_options =
 153       nir_lower_drcp |
 154       nir_lower_dsqrt |
 155       nir_lower_drsq |
 156       nir_lower_dtrunc |
 157       nir_lower_dfloor |
 158       nir_lower_dceil |
 159       nir_lower_dfract |
 160       nir_lower_dround_even |
 161       nir_lower_dmod;
 162
 163    if (!devinfo->has_64bit_types || (INTEL_DEBUG & DEBUG_SOFT64)) {
 164       int64_options |= nir_lower_mov64 |
 165                        nir_lower_icmp64 |
 166                        nir_lower_iadd64 |
 167                        nir_lower_iabs64 |
 168                        nir_lower_ineg64 |
 169                        nir_lower_logic64 |
 170                        nir_lower_minmax64 |
 171                        nir_lower_shift64;
 172       fp64_options |= nir_lower_fp64_full_software;
 173    }
 174
 175    /* The Bspec's section tittled "Instruction_multiply[DevBDW+]" claims that
 176     * destination type can be Quadword and source type Doubleword for Gen8 and
 177     * Gen9. So, lower 64 bit multiply instruction on rest of the platforms.
 178     */
 179    if (devinfo->gen < 8 || devinfo->gen > 9)
 180       int64_options |= nir_lower_imul_2x32_64;
 181
 182    /* We want the GLSL compiler to emit code that uses condition codes */
 183    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 184       compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
 185       compiler->glsl_compiler_options[i].MaxIfDepth =
 186          devinfo->gen < 6 ? 16 : UINT_MAX;
 187
 188       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 189       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 190
 191       bool is_scalar = compiler->scalar_stage[i];
 192
 193       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 194       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 195       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 196
 197       struct nir_shader_compiler_options *nir_options =
 198          rzalloc(compiler, struct nir_shader_compiler_options);
 199       if (is_scalar) {
 200          *nir_options =
 201             devinfo->gen < 11 ? scalar_nir_options : scalar_nir_options_gen11;
 202       } else {
 203          *nir_options =
 204             devinfo->gen < 6 ? vector_nir_options : vector_nir_options_gen6;
 205       }
 206       nir_options->lower_int64_options = int64_options;
 207       nir_options->lower_doubles_options = fp64_options;
 208       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 209
 210       compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
 211    }
 212
 213    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 214    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 215    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false;
 216
 217    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 218       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 219
 220    return compiler;
 221 }
 222
 223 static void
 224 insert_u64_bit(uint64_t *val, bool add)
 225 {
 226    *val = (*val << 1) | !!add;
 227 }
 228
 229 uint64_t
 230 brw_get_compiler_config_value(const struct brw_compiler *compiler)
 231 {
 232    uint64_t config = 0;
 233    insert_u64_bit(&config, compiler->precise_trig);
 234    if (compiler->devinfo->gen >= 8 && compiler->devinfo->gen < 10) {
 235       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_VERTEX]);
 236       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
 237       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
 238       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
 239    }
 240    uint64_t debug_bits = INTEL_DEBUG;
 241    uint64_t mask = DEBUG_DISK_CACHE_MASK;
 242    while (mask != 0) {
 243       const uint64_t bit = 1ULL << (ffsll(mask) - 1);
 244       insert_u64_bit(&config, (debug_bits & bit) != 0);
 245       mask &= ~bit;
 246    }
 247    return config;
 248 }
 249
 250 unsigned
 251 brw_prog_data_size(gl_shader_stage stage)
 252 {
 253    STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
 254    STATIC_ASSERT(MESA_SHADER_TESS_CTRL == 1);
 255    STATIC_ASSERT(MESA_SHADER_TESS_EVAL == 2);
 256    STATIC_ASSERT(MESA_SHADER_GEOMETRY == 3);
 257    STATIC_ASSERT(MESA_SHADER_FRAGMENT == 4);
 258    STATIC_ASSERT(MESA_SHADER_COMPUTE == 5);
 259    static const size_t stage_sizes[] = {
 260       sizeof(struct brw_vs_prog_data),
 261       sizeof(struct brw_tcs_prog_data),
 262       sizeof(struct brw_tes_prog_data),
 263       sizeof(struct brw_gs_prog_data),
 264       sizeof(struct brw_wm_prog_data),
 265       sizeof(struct brw_cs_prog_data),
 266    };
 267    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 268    return stage_sizes[stage];
 269 }
 270
 271 unsigned
 272 brw_prog_key_size(gl_shader_stage stage)
 273 {
 274    static const size_t stage_sizes[] = {
 275       sizeof(struct brw_vs_prog_key),
 276       sizeof(struct brw_tcs_prog_key),
 277       sizeof(struct brw_tes_prog_key),
 278       sizeof(struct brw_gs_prog_key),
 279       sizeof(struct brw_wm_prog_key),
 280       sizeof(struct brw_cs_prog_key),
 281    };
 282    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 283    return stage_sizes[stage];
 284 }