2 * Copyright © 2010 - 2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
96 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
99 * Apply workarounds for SIN and COS output range problems.
100 * This can negatively impact performance.
105 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
106 * Base Address? (If not, it's a normal GPU address.)
108 bool constant_buffer_0_is_relative
;
111 * Whether or not the driver supports pull constants. If not, the compiler
112 * will attempt to push everything.
114 bool supports_pull_constants
;
118 * We use a constant subgroup size of 32. It really only needs to be a
119 * maximum and, since we do SIMD32 for compute shaders in some cases, it
120 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
121 * subgroup size of 32 but will act as if 16 or 24 of those channels are
124 #define BRW_SUBGROUP_SIZE 32
127 * Program key structures.
129 * When drawing, we look for the currently bound shaders in the program
130 * cache. This is essentially a hash table lookup, and these are the keys.
132 * Sometimes OpenGL features specified as state need to be simulated via
133 * shader code, due to a mismatch between the API and the hardware. This
134 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
135 * in the program key so it's considered when searching for a program. If
136 * we haven't seen a particular combination before, we have to recompile a
137 * new specialized version.
139 * Shader compilation should not look up state in gl_context directly, but
140 * instead use the copy in the program key. This guarantees recompiles will
146 enum PACKED gen6_gather_sampler_wa
{
147 WA_SIGN
= 1, /* whether we need to sign extend */
148 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
149 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
153 * Sampler information needed by VS, WM, and GS program cache keys.
155 struct brw_sampler_prog_key_data
{
157 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
159 uint16_t swizzles
[MAX_SAMPLERS
];
161 uint32_t gl_clamp_mask
[3];
164 * For RG32F, gather4's channel select is broken.
166 uint32_t gather_channel_quirk_mask
;
169 * Whether this sampler uses the compressed multisample surface layout.
171 uint32_t compressed_multisample_layout_mask
;
174 * Whether this sampler is using 16x multisampling. If so fetching from
175 * this sampler will be handled with a different instruction, ld2dms_w
181 * For Sandybridge, which shader w/a we need for gather quirks.
183 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
186 * Texture units that have a YUV image bound.
188 uint32_t y_u_v_image_mask
;
189 uint32_t y_uv_image_mask
;
190 uint32_t yx_xuxv_image_mask
;
191 uint32_t xy_uxvx_image_mask
;
195 * The VF can't natively handle certain types of attributes, such as GL_FIXED
196 * or most 10_10_10_2 types. These flags enable various VS workarounds to
197 * "fix" attributes at the beginning of shaders.
199 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
200 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
201 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
202 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
203 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
206 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
207 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
208 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
209 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
211 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
212 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
214 /** The program key for Vertex Shaders. */
215 struct brw_vs_prog_key
{
216 unsigned program_string_id
;
219 * Per-attribute workaround flags
221 * For each attribute, a combination of BRW_ATTRIB_WA_*.
223 * For OpenGL, where we expose a maximum of 16 user input atttributes
224 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
225 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
226 * expose up to 28 user input vertex attributes that are mapped to slots
227 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
228 * enough to hold this many slots.
230 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
232 bool copy_edgeflag
:1;
234 bool clamp_vertex_color
:1;
237 * How many user clipping planes are being uploaded to the vertex shader as
240 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
243 unsigned nr_userclip_plane_consts
:4;
246 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
247 * are going to be replaced with point coordinates (as a consequence of a
248 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
249 * our SF thread requires exact matching between VS outputs and FS inputs,
250 * these texture coordinates will need to be unconditionally included in
251 * the VUE, even if they aren't written by the vertex shader.
253 uint8_t point_coord_replace
;
255 struct brw_sampler_prog_key_data tex
;
258 /** The program key for Tessellation Control Shaders. */
259 struct brw_tcs_prog_key
261 unsigned program_string_id
;
263 GLenum tes_primitive_mode
;
265 unsigned input_vertices
;
267 /** A bitfield of per-patch outputs written. */
268 uint32_t patch_outputs_written
;
270 /** A bitfield of per-vertex outputs written. */
271 uint64_t outputs_written
;
273 bool quads_workaround
;
275 struct brw_sampler_prog_key_data tex
;
278 /** The program key for Tessellation Evaluation Shaders. */
279 struct brw_tes_prog_key
281 unsigned program_string_id
;
283 /** A bitfield of per-patch inputs read. */
284 uint32_t patch_inputs_read
;
286 /** A bitfield of per-vertex inputs read. */
287 uint64_t inputs_read
;
289 struct brw_sampler_prog_key_data tex
;
292 /** The program key for Geometry Shaders. */
293 struct brw_gs_prog_key
295 unsigned program_string_id
;
297 struct brw_sampler_prog_key_data tex
;
300 enum brw_sf_primitive
{
301 BRW_SF_PRIM_POINTS
= 0,
302 BRW_SF_PRIM_LINES
= 1,
303 BRW_SF_PRIM_TRIANGLES
= 2,
304 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
307 struct brw_sf_prog_key
{
309 bool contains_flat_varying
;
310 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
311 uint8_t point_sprite_coord_replace
;
312 enum brw_sf_primitive primitive
:2;
313 bool do_twoside_color
:1;
314 bool frontface_ccw
:1;
315 bool do_point_sprite
:1;
316 bool do_point_coord
:1;
317 bool sprite_origin_lower_left
:1;
318 bool userclip_active
:1;
322 BRW_CLIP_MODE_NORMAL
= 0,
323 BRW_CLIP_MODE_CLIP_ALL
= 1,
324 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
325 BRW_CLIP_MODE_REJECT_ALL
= 3,
326 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
327 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
330 enum brw_clip_fill_mode
{
331 BRW_CLIP_FILL_MODE_LINE
= 0,
332 BRW_CLIP_FILL_MODE_POINT
= 1,
333 BRW_CLIP_FILL_MODE_FILL
= 2,
334 BRW_CLIP_FILL_MODE_CULL
= 3,
337 /* Note that if unfilled primitives are being emitted, we have to fix
338 * up polygon offset and flatshading at this point:
340 struct brw_clip_prog_key
{
342 bool contains_flat_varying
;
343 bool contains_noperspective_varying
;
344 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
345 unsigned primitive
:4;
346 unsigned nr_userclip
:4;
349 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
350 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
355 enum brw_clip_mode clip_mode
:3;
362 /* A big lookup table is used to figure out which and how many
363 * additional regs will inserted before the main payload in the WM
364 * program execution. These mainly relate to depth and stencil
365 * processing and the early-depth-test optimization.
367 enum brw_wm_iz_bits
{
368 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
369 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
370 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
371 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
372 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
373 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
374 BRW_WM_IZ_BIT_MAX
= 0x40
377 enum brw_wm_aa_enable
{
383 /** The program key for Fragment/Pixel Shaders. */
384 struct brw_wm_prog_key
{
385 /* Some collection of BRW_WM_IZ_* */
389 unsigned nr_color_regions
:5;
390 bool replicate_alpha
:1;
391 bool clamp_fragment_color
:1;
392 bool persample_interp
:1;
393 bool multisample_fbo
:1;
394 bool frag_coord_adds_sample_pos
:1;
395 enum brw_wm_aa_enable line_aa
:2;
396 bool high_quality_derivatives
:1;
397 bool force_dual_color_blend
:1;
398 bool coherent_fb_fetch
:1;
400 uint64_t input_slots_valid
;
401 unsigned program_string_id
;
402 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
403 float alpha_test_ref
;
405 struct brw_sampler_prog_key_data tex
;
408 struct brw_cs_prog_key
{
409 uint32_t program_string_id
;
410 struct brw_sampler_prog_key_data tex
;
413 /* brw_any_prog_key is any of the keys that map to an API stage */
414 union brw_any_prog_key
{
415 struct brw_vs_prog_key vs
;
416 struct brw_tcs_prog_key tcs
;
417 struct brw_tes_prog_key tes
;
418 struct brw_gs_prog_key gs
;
419 struct brw_wm_prog_key wm
;
420 struct brw_cs_prog_key cs
;
424 * Image metadata structure as laid out in the shader parameter
425 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
426 * able to use them. That's okay because the padding and any unused
427 * entries [most of them except when we're doing untyped surface
428 * access] will be removed by the uniform packing pass.
430 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
431 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
432 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
433 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
434 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
435 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
436 #define BRW_IMAGE_PARAM_SIZE 24
438 struct brw_image_param
{
439 /** Surface binding table index. */
440 uint32_t surface_idx
;
442 /** Offset applied to the X and Y surface coordinates. */
445 /** Surface X, Y and Z dimensions. */
448 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
449 * pixels, vertical slice stride in pixels.
453 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
457 * Right shift to apply for bit 6 address swizzling. Two different
458 * swizzles can be specified and will be applied one after the other. The
459 * resulting address will be:
461 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
462 * (addr >> swizzling[1])))
464 * Use \c 0xff if any of the swizzles is not required.
466 uint32_t swizzling
[2];
469 /** Max number of render targets in a shader */
470 #define BRW_MAX_DRAW_BUFFERS 8
473 * Max number of binding table entries used for stream output.
475 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
476 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
478 * On Gen6, the size of transform feedback data is limited not by the number
479 * of components but by the number of binding table entries we set aside. We
480 * use one binding table entry for a float, one entry for a vector, and one
481 * entry per matrix column. Since the only way we can communicate our
482 * transform feedback capabilities to the client is via
483 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
484 * worst case, in which all the varyings are floats, so we use up one binding
485 * table entry per component. Therefore we need to set aside at least 64
486 * binding table entries for use by transform feedback.
488 * Note: since we don't currently pack varyings, it is currently impossible
489 * for the client to actually use up all of these binding table entries--if
490 * all of their varyings were floats, they would run out of varying slots and
491 * fail to link. But that's a bug, so it seems prudent to go ahead and
492 * allocate the number of binding table entries we will need once the bug is
495 #define BRW_MAX_SOL_BINDINGS 64
498 * Binding table index for the first gen6 SOL binding.
500 #define BRW_GEN6_SOL_BINDING_START 0
503 * Stride in bytes between shader_time entries.
505 * We separate entries by a cacheline to reduce traffic between EUs writing to
508 #define BRW_SHADER_TIME_STRIDE 64
517 /* We reserve the first 2^16 values for builtins */
518 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
520 enum brw_param_builtin
{
521 BRW_PARAM_BUILTIN_ZERO
,
523 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
524 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
525 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
526 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
527 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
528 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
529 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
530 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
531 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
532 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
533 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
534 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
535 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
536 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
537 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
538 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
539 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
540 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
541 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
542 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
543 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
544 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
545 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
546 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
547 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
548 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
549 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
550 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
551 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
552 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
553 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
554 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
556 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
557 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
558 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
559 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
560 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
561 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
563 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X
,
564 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y
,
565 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z
,
566 BRW_PARAM_BUILTIN_SUBGROUP_ID
,
569 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
570 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
572 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
573 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
574 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
576 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
577 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
579 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
580 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
582 struct brw_stage_prog_data
{
584 /** size of our binding table. */
588 * surface indices for the various groups of surfaces
590 uint32_t pull_constants_start
;
591 uint32_t texture_start
;
592 uint32_t gather_texture_start
;
595 uint32_t image_start
;
596 uint32_t shader_time_start
;
597 uint32_t plane_start
[3];
601 struct brw_ubo_range ubo_ranges
[4];
603 GLuint nr_params
; /**< number of float params/constants */
604 GLuint nr_pull_params
;
606 unsigned curb_read_length
;
607 unsigned total_scratch
;
608 unsigned total_shared
;
610 unsigned program_size
;
613 * Register where the thread expects to find input data from the URB
614 * (typically uniforms, followed by vertex or fragment attributes).
616 unsigned dispatch_grf_start_reg
;
618 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
620 /* 32-bit identifiers for all push/pull parameters. These can be anything
621 * the driver wishes them to be; the core of the back-end compiler simply
622 * re-arranges them. The one restriction is that the bottom 2^16 values
623 * are reserved for builtins defined in the brw_param_builtin enum defined
627 uint32_t *pull_param
;
630 static inline uint32_t *
631 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
632 unsigned nr_new_params
)
634 unsigned old_nr_params
= prog_data
->nr_params
;
635 prog_data
->nr_params
+= nr_new_params
;
636 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
637 prog_data
->param
, uint32_t,
638 prog_data
->nr_params
);
639 return prog_data
->param
+ old_nr_params
;
643 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
646 /* A binding table index is 8 bits and the top 3 values are reserved for
647 * special things (stateless and SLM).
649 assert(surf_index
<= 252);
651 prog_data
->binding_table
.size_bytes
=
652 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
655 enum brw_barycentric_mode
{
656 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
657 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
658 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
659 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
660 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
661 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
662 BRW_BARYCENTRIC_MODE_COUNT
= 6
664 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
665 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
666 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
667 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
669 enum brw_pixel_shader_computed_depth_mode
{
670 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
671 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
672 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
673 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
676 /* Data about a particular attempt to compile a program. Note that
677 * there can be many of these, each in a different GL state
678 * corresponding to a different brw_wm_prog_key struct, with different
681 struct brw_wm_prog_data
{
682 struct brw_stage_prog_data base
;
684 GLuint num_varying_inputs
;
686 uint8_t reg_blocks_8
;
687 uint8_t reg_blocks_16
;
689 uint8_t dispatch_grf_start_reg_16
;
690 uint32_t prog_offset_16
;
694 * surface indices the WM-specific surfaces
696 uint32_t render_target_read_start
;
700 uint8_t computed_depth_mode
;
701 bool computed_stencil
;
703 bool early_fragment_tests
;
704 bool post_depth_coverage
;
709 bool persample_dispatch
;
710 bool uses_pos_offset
;
715 bool uses_sample_mask
;
716 bool has_render_target_reads
;
717 bool has_side_effects
;
720 bool contains_flat_varying
;
721 bool contains_noperspective_varying
;
724 * Mask of which interpolation modes are required by the fragment shader.
725 * Used in hardware setup on gen6+.
727 uint32_t barycentric_interp_modes
;
730 * Mask of which FS inputs are marked flat by the shader source. This is
731 * needed for setting up 3DSTATE_SF/SBE.
733 uint32_t flat_inputs
;
735 /* Mapping of VUE slots to interpolation modes.
736 * Used by the Gen4-5 clip/sf/wm stages.
738 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
741 * Map from gl_varying_slot to the position within the FS setup data
742 * payload where the varying's attribute vertex deltas should be delivered.
743 * For varying slots that are not used by the FS, the value is -1.
745 int urb_setup
[VARYING_SLOT_MAX
];
748 /** Returns the SIMD width corresponding to a given KSP index
750 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
751 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
752 * kernel start pointer (KSP) indices that is based on what dispatch widths
753 * are enabled. This function provides, effectively, the reverse mapping.
755 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
756 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
758 static inline unsigned
759 brw_fs_simd_width_for_ksp(unsigned ksp_idx
, bool simd8_enabled
,
760 bool simd16_enabled
, bool simd32_enabled
)
762 /* This function strictly ignores contiguous dispatch */
765 return simd8_enabled
? 8 :
766 (simd16_enabled
&& !simd32_enabled
) ? 16 :
767 (simd32_enabled
&& !simd16_enabled
) ? 32 : 0;
769 return (simd32_enabled
&& (simd16_enabled
|| simd8_enabled
)) ? 32 : 0;
771 return (simd16_enabled
&& (simd32_enabled
|| simd8_enabled
)) ? 16 : 0;
773 unreachable("Invalid KSP index");
777 #define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
778 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
779 (wm_state)._16PixelDispatchEnable, \
780 (wm_state)._32PixelDispatchEnable)
782 #define brw_wm_state_has_ksp(wm_state, ksp_idx) \
783 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
785 static inline uint32_t
786 _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data
*prog_data
,
789 switch (simd_width
) {
791 case 16: return prog_data
->prog_offset_16
;
796 #define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
797 _brw_wm_prog_data_prog_offset(prog_data, \
798 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
800 static inline uint8_t
801 _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data
*prog_data
,
804 switch (simd_width
) {
805 case 8: return prog_data
->base
.dispatch_grf_start_reg
;
806 case 16: return prog_data
->dispatch_grf_start_reg_16
;
811 #define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
812 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
813 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
815 static inline uint8_t
816 _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data
*prog_data
,
819 switch (simd_width
) {
820 case 8: return prog_data
->reg_blocks_8
;
821 case 16: return prog_data
->reg_blocks_16
;
826 #define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
827 _brw_wm_prog_data_reg_blocks(prog_data, \
828 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
830 struct brw_push_const_block
{
831 unsigned dwords
; /* Dword count, not reg aligned */
833 unsigned size
; /* Bytes, register aligned */
836 struct brw_cs_prog_data
{
837 struct brw_stage_prog_data base
;
839 unsigned local_size
[3];
843 bool uses_num_work_groups
;
846 struct brw_push_const_block cross_thread
;
847 struct brw_push_const_block per_thread
;
848 struct brw_push_const_block total
;
853 * surface indices the CS-specific surfaces
855 uint32_t work_groups_start
;
861 * Enum representing the i965-specific vertex results that don't correspond
862 * exactly to any element of gl_varying_slot. The values of this enum are
863 * assigned such that they don't conflict with gl_varying_slot.
867 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
868 BRW_VARYING_SLOT_PAD
,
870 * Technically this is not a varying but just a placeholder that
871 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
872 * builtin variable to be compiled correctly. see compile_sf_prog() for
875 BRW_VARYING_SLOT_PNTC
,
876 BRW_VARYING_SLOT_COUNT
880 * We always program SF to start reading at an offset of 1 (2 varying slots)
881 * from the start of the vertex URB entry. This causes it to skip:
882 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
883 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
885 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
888 * Bitmask indicating which fragment shader inputs represent varyings (and
889 * hence have to be delivered to the fragment shader by the SF/SBE stage).
891 #define BRW_FS_VARYING_INPUT_MASK \
892 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
893 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
896 * Data structure recording the relationship between the gl_varying_slot enum
897 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
898 * single octaword within the VUE (128 bits).
900 * Note that each BRW register contains 256 bits (2 octawords), so when
901 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
902 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
903 * in a vertex shader), each register corresponds to a single VUE slot, since
904 * it contains data for two separate vertices.
908 * Bitfield representing all varying slots that are (a) stored in this VUE
909 * map, and (b) actually written by the shader. Does not include any of
910 * the additional varying slots defined in brw_varying_slot.
912 uint64_t slots_valid
;
915 * Is this VUE map for a separate shader pipeline?
917 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
918 * without the linker having a chance to dead code eliminate unused varyings.
920 * This means that we have to use a fixed slot layout, based on the output's
921 * location field, rather than assigning slots in a compact contiguous block.
926 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
927 * not stored in a slot (because they are not written, or because
928 * additional processing is applied before storing them in the VUE), the
931 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
934 * Map from VUE slot to gl_varying_slot value. For slots that do not
935 * directly correspond to a gl_varying_slot, the value comes from
938 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
940 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
943 * Total number of VUE slots in use
948 * Number of per-patch VUE slots. Only valid for tessellation control
949 * shader outputs and tessellation evaluation shader inputs.
951 int num_per_patch_slots
;
954 * Number of per-vertex VUE slots. Only valid for tessellation control
955 * shader outputs and tessellation evaluation shader inputs.
957 int num_per_vertex_slots
;
960 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
963 * Convert a VUE slot number into a byte offset within the VUE.
965 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
971 * Convert a vertex output (brw_varying_slot) into a byte offset within the
975 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
977 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
980 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
981 struct brw_vue_map
*vue_map
,
982 uint64_t slots_valid
,
983 bool separate_shader
);
985 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
986 uint64_t slots_valid
,
989 /* brw_interpolation_map.c */
990 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
991 struct nir_shader
*nir
,
992 struct brw_wm_prog_data
*prog_data
,
993 const struct gen_device_info
*devinfo
);
995 enum shader_dispatch_mode
{
996 DISPATCH_MODE_4X1_SINGLE
= 0,
997 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
998 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
999 DISPATCH_MODE_SIMD8
= 3,
1003 * @defgroup Tessellator parameter enumerations.
1005 * These correspond to the hardware values in 3DSTATE_TE, and are provided
1006 * as part of the tessellation evaluation shader.
1010 enum brw_tess_partitioning
{
1011 BRW_TESS_PARTITIONING_INTEGER
= 0,
1012 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
1013 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
1016 enum brw_tess_output_topology
{
1017 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
1018 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
1019 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
1020 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
1023 enum brw_tess_domain
{
1024 BRW_TESS_DOMAIN_QUAD
= 0,
1025 BRW_TESS_DOMAIN_TRI
= 1,
1026 BRW_TESS_DOMAIN_ISOLINE
= 2,
1030 struct brw_vue_prog_data
{
1031 struct brw_stage_prog_data base
;
1032 struct brw_vue_map vue_map
;
1034 /** Should the hardware deliver input VUE handles for URB pull loads? */
1035 bool include_vue_handles
;
1037 GLuint urb_read_length
;
1040 uint32_t clip_distance_mask
;
1041 uint32_t cull_distance_mask
;
1043 /* Used for calculating urb partitions. In the VS, this is the size of the
1044 * URB entry used for both input and output to the thread. In the GS, this
1045 * is the size of the URB entry used for output.
1047 GLuint urb_entry_size
;
1049 enum shader_dispatch_mode dispatch_mode
;
1052 struct brw_vs_prog_data
{
1053 struct brw_vue_prog_data base
;
1055 GLbitfield64 inputs_read
;
1056 GLbitfield64 double_inputs_read
;
1058 unsigned nr_attribute_slots
;
1061 bool uses_instanceid
;
1062 bool uses_is_indexed_draw
;
1063 bool uses_firstvertex
;
1064 bool uses_baseinstance
;
1068 struct brw_tcs_prog_data
1070 struct brw_vue_prog_data base
;
1072 /** Number vertices in output patch */
1077 struct brw_tes_prog_data
1079 struct brw_vue_prog_data base
;
1081 enum brw_tess_partitioning partitioning
;
1082 enum brw_tess_output_topology output_topology
;
1083 enum brw_tess_domain domain
;
1086 struct brw_gs_prog_data
1088 struct brw_vue_prog_data base
;
1090 unsigned vertices_in
;
1093 * Size of an output vertex, measured in HWORDS (32 bytes).
1095 unsigned output_vertex_size_hwords
;
1097 unsigned output_topology
;
1100 * Size of the control data (cut bits or StreamID bits), in hwords (32
1101 * bytes). 0 if there is no control data.
1103 unsigned control_data_header_size_hwords
;
1106 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1107 * if the control data is StreamID bits, or
1108 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1109 * Ignored if control_data_header_size is 0.
1111 unsigned control_data_format
;
1113 bool include_primitive_id
;
1116 * The number of vertices emitted, if constant - otherwise -1.
1118 int static_vertex_count
;
1123 * Gen6: Provoking vertex convention for odd-numbered triangles
1129 * Gen6: Number of varyings that are output to transform feedback.
1131 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1134 * Gen6: Map from the index of a transform feedback binding table entry to the
1135 * gl_varying_slot that should be streamed out through that binding table
1138 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1141 * Gen6: Map from the index of a transform feedback binding table entry to the
1142 * swizzles that should be used when streaming out data through that
1143 * binding table entry.
1145 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1148 struct brw_sf_prog_data
{
1149 uint32_t urb_read_length
;
1152 /* Each vertex may have upto 12 attributes, 4 components each,
1153 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1156 * Actually we use 4 for each, so call it 12 rows.
1158 unsigned urb_entry_size
;
1161 struct brw_clip_prog_data
{
1162 uint32_t curb_read_length
; /* user planes? */
1164 uint32_t urb_read_length
;
1168 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1169 union brw_any_prog_data
{
1170 struct brw_stage_prog_data base
;
1171 struct brw_vue_prog_data vue
;
1172 struct brw_vs_prog_data vs
;
1173 struct brw_tcs_prog_data tcs
;
1174 struct brw_tes_prog_data tes
;
1175 struct brw_gs_prog_data gs
;
1176 struct brw_wm_prog_data wm
;
1177 struct brw_cs_prog_data cs
;
1180 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1181 static inline struct brw_##stage##_prog_data * \
1182 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1184 return (struct brw_##stage##_prog_data *) prog_data; \
1186 DEFINE_PROG_DATA_DOWNCAST(vue
)
1187 DEFINE_PROG_DATA_DOWNCAST(vs
)
1188 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1189 DEFINE_PROG_DATA_DOWNCAST(tes
)
1190 DEFINE_PROG_DATA_DOWNCAST(gs
)
1191 DEFINE_PROG_DATA_DOWNCAST(wm
)
1192 DEFINE_PROG_DATA_DOWNCAST(cs
)
1193 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1194 DEFINE_PROG_DATA_DOWNCAST(clip
)
1195 DEFINE_PROG_DATA_DOWNCAST(sf
)
1196 #undef DEFINE_PROG_DATA_DOWNCAST
1200 struct brw_compiler
*
1201 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1204 brw_prog_data_size(gl_shader_stage stage
);
1207 brw_prog_key_size(gl_shader_stage stage
);
1210 * Compile a vertex shader.
1212 * Returns the final assembly and the program's size.
1215 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1217 const struct brw_vs_prog_key
*key
,
1218 struct brw_vs_prog_data
*prog_data
,
1219 const struct nir_shader
*shader
,
1220 int shader_time_index
,
1224 * Compile a tessellation control shader.
1226 * Returns the final assembly and the program's size.
1229 brw_compile_tcs(const struct brw_compiler
*compiler
,
1232 const struct brw_tcs_prog_key
*key
,
1233 struct brw_tcs_prog_data
*prog_data
,
1234 const struct nir_shader
*nir
,
1235 int shader_time_index
,
1239 * Compile a tessellation evaluation shader.
1241 * Returns the final assembly and the program's size.
1244 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1246 const struct brw_tes_prog_key
*key
,
1247 const struct brw_vue_map
*input_vue_map
,
1248 struct brw_tes_prog_data
*prog_data
,
1249 const struct nir_shader
*shader
,
1250 struct gl_program
*prog
,
1251 int shader_time_index
,
1255 * Compile a vertex shader.
1257 * Returns the final assembly and the program's size.
1260 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1262 const struct brw_gs_prog_key
*key
,
1263 struct brw_gs_prog_data
*prog_data
,
1264 const struct nir_shader
*shader
,
1265 struct gl_program
*prog
,
1266 int shader_time_index
,
1270 * Compile a strips and fans shader.
1272 * This is a fixed-function shader determined entirely by the shader key and
1275 * Returns the final assembly and the program's size.
1278 brw_compile_sf(const struct brw_compiler
*compiler
,
1280 const struct brw_sf_prog_key
*key
,
1281 struct brw_sf_prog_data
*prog_data
,
1282 struct brw_vue_map
*vue_map
,
1283 unsigned *final_assembly_size
);
1286 * Compile a clipper shader.
1288 * This is a fixed-function shader determined entirely by the shader key and
1291 * Returns the final assembly and the program's size.
1294 brw_compile_clip(const struct brw_compiler
*compiler
,
1296 const struct brw_clip_prog_key
*key
,
1297 struct brw_clip_prog_data
*prog_data
,
1298 struct brw_vue_map
*vue_map
,
1299 unsigned *final_assembly_size
);
1302 * Compile a fragment shader.
1304 * Returns the final assembly and the program's size.
1307 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1309 const struct brw_wm_prog_key
*key
,
1310 struct brw_wm_prog_data
*prog_data
,
1311 const struct nir_shader
*shader
,
1312 struct gl_program
*prog
,
1313 int shader_time_index8
,
1314 int shader_time_index16
,
1315 int shader_time_index32
,
1316 bool allow_spilling
,
1317 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1321 * Compile a compute shader.
1323 * Returns the final assembly and the program's size.
1326 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1328 const struct brw_cs_prog_key
*key
,
1329 struct brw_cs_prog_data
*prog_data
,
1330 const struct nir_shader
*shader
,
1331 int shader_time_index
,
1334 static inline uint32_t
1335 encode_slm_size(unsigned gen
, uint32_t bytes
)
1337 uint32_t slm_size
= 0;
1339 /* Shared Local Memory is specified as powers of two, and encoded in
1340 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1342 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1343 * -------------------------------------------------------------------
1344 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1345 * -------------------------------------------------------------------
1346 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1348 assert(bytes
<= 64 * 1024);
1351 /* Shared Local Memory Size is specified as powers of two. */
1352 slm_size
= util_next_power_of_two(bytes
);
1355 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1356 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1358 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1359 slm_size
= MAX2(slm_size
, 4096) / 4096;
1367 * Return true if the given shader stage is dispatched contiguously by the
1368 * relevant fixed function starting from channel 0 of the SIMD thread, which
1369 * implies that the dispatch mask of a thread can be assumed to have the form
1370 * '2^n - 1' for some n.
1373 brw_stage_has_packed_dispatch(MAYBE_UNUSED
const struct gen_device_info
*devinfo
,
1374 gl_shader_stage stage
,
1375 const struct brw_stage_prog_data
*prog_data
)
1377 /* The code below makes assumptions about the hardware's thread dispatch
1378 * behavior that could be proven wrong in future generations -- Make sure
1379 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1380 * the NIR front-end before changing this assertion.
1382 assert(devinfo
->gen
<= 11);
1385 case MESA_SHADER_FRAGMENT
: {
1386 /* The PSD discards subspans coming in with no lit samples, which in the
1387 * per-pixel shading case implies that each subspan will either be fully
1388 * lit (due to the VMask being used to allow derivative computations),
1389 * or not dispatched at all. In per-sample dispatch mode individual
1390 * samples from the same subspan have a fixed relative location within
1391 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1392 * general and we should return false.
1394 const struct brw_wm_prog_data
*wm_prog_data
=
1395 (const struct brw_wm_prog_data
*)prog_data
;
1396 return !wm_prog_data
->persample_dispatch
;
1398 case MESA_SHADER_COMPUTE
:
1399 /* Compute shaders will be spawned with either a fully enabled dispatch
1400 * mask or with whatever bottom/right execution mask was given to the
1401 * GPGPU walker command to be used along the workgroup edges -- In both
1402 * cases the dispatch mask is required to be tightly packed for our
1403 * invocation index calculations to work.
1407 /* Most remaining fixed functions are limited to use a packed dispatch
1408 * mask due to the hardware representation of the dispatch mask as a
1409 * single counter representing the number of enabled channels.
1416 * Computes the first varying slot in the URB produced by the previous stage
1417 * that is used in the next stage. We do this by testing the varying slots in
1418 * the previous stage's vue map against the inputs read in the next stage.
1422 * - Each URB offset contains two varying slots and we can only skip a
1423 * full offset if both slots are unused, so the value we return here is always
1424 * rounded down to the closest multiple of two.
1426 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1427 * part of the vue header, so if these are read we can't skip anything.
1430 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1431 const struct brw_vue_map
*prev_stage_vue_map
)
1433 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1434 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1435 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1436 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1437 return ROUND_DOWN_TO(i
, 2);
1448 #endif /* BRW_COMPILER_H */