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24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "common/gen_device_info.h"
29 #include "main/mtypes.h"
30 #include "main/macros.h"
39 union gl_constant_value
;
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
96 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
99 * Apply workarounds for SIN and COS output range problems.
100 * This can negatively impact performance.
105 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
106 * Base Address? (If not, it's a normal GPU address.)
108 bool constant_buffer_0_is_relative
;
113 * Program key structures.
115 * When drawing, we look for the currently bound shaders in the program
116 * cache. This is essentially a hash table lookup, and these are the keys.
118 * Sometimes OpenGL features specified as state need to be simulated via
119 * shader code, due to a mismatch between the API and the hardware. This
120 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
121 * in the program key so it's considered when searching for a program. If
122 * we haven't seen a particular combination before, we have to recompile a
123 * new specialized version.
125 * Shader compilation should not look up state in gl_context directly, but
126 * instead use the copy in the program key. This guarantees recompiles will
132 enum PACKED gen6_gather_sampler_wa
{
133 WA_SIGN
= 1, /* whether we need to sign extend */
134 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
135 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
139 * Sampler information needed by VS, WM, and GS program cache keys.
141 struct brw_sampler_prog_key_data
{
143 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
145 uint16_t swizzles
[MAX_SAMPLERS
];
147 uint32_t gl_clamp_mask
[3];
150 * For RG32F, gather4's channel select is broken.
152 uint32_t gather_channel_quirk_mask
;
155 * Whether this sampler uses the compressed multisample surface layout.
157 uint32_t compressed_multisample_layout_mask
;
160 * Whether this sampler is using 16x multisampling. If so fetching from
161 * this sampler will be handled with a different instruction, ld2dms_w
167 * For Sandybridge, which shader w/a we need for gather quirks.
169 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
172 * Texture units that have a YUV image bound.
174 uint32_t y_u_v_image_mask
;
175 uint32_t y_uv_image_mask
;
176 uint32_t yx_xuxv_image_mask
;
177 uint32_t xy_uxvx_image_mask
;
181 * The VF can't natively handle certain types of attributes, such as GL_FIXED
182 * or most 10_10_10_2 types. These flags enable various VS workarounds to
183 * "fix" attributes at the beginning of shaders.
185 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
186 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
187 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
188 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
189 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
191 /** The program key for Vertex Shaders. */
192 struct brw_vs_prog_key
{
193 unsigned program_string_id
;
196 * Per-attribute workaround flags
198 * For each attribute, a combination of BRW_ATTRIB_WA_*.
200 uint8_t gl_attrib_wa_flags
[VERT_ATTRIB_MAX
];
202 bool copy_edgeflag
:1;
204 bool clamp_vertex_color
:1;
207 * How many user clipping planes are being uploaded to the vertex shader as
210 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
213 unsigned nr_userclip_plane_consts
:4;
216 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
217 * are going to be replaced with point coordinates (as a consequence of a
218 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
219 * our SF thread requires exact matching between VS outputs and FS inputs,
220 * these texture coordinates will need to be unconditionally included in
221 * the VUE, even if they aren't written by the vertex shader.
223 uint8_t point_coord_replace
;
225 struct brw_sampler_prog_key_data tex
;
228 /** The program key for Tessellation Control Shaders. */
229 struct brw_tcs_prog_key
231 unsigned program_string_id
;
233 GLenum tes_primitive_mode
;
235 unsigned input_vertices
;
237 /** A bitfield of per-patch outputs written. */
238 uint32_t patch_outputs_written
;
240 /** A bitfield of per-vertex outputs written. */
241 uint64_t outputs_written
;
243 bool quads_workaround
;
245 struct brw_sampler_prog_key_data tex
;
248 /** The program key for Tessellation Evaluation Shaders. */
249 struct brw_tes_prog_key
251 unsigned program_string_id
;
253 /** A bitfield of per-patch inputs read. */
254 uint32_t patch_inputs_read
;
256 /** A bitfield of per-vertex inputs read. */
257 uint64_t inputs_read
;
259 struct brw_sampler_prog_key_data tex
;
262 /** The program key for Geometry Shaders. */
263 struct brw_gs_prog_key
265 unsigned program_string_id
;
267 struct brw_sampler_prog_key_data tex
;
270 enum brw_sf_primitive
{
271 BRW_SF_PRIM_POINTS
= 0,
272 BRW_SF_PRIM_LINES
= 1,
273 BRW_SF_PRIM_TRIANGLES
= 2,
274 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
277 struct brw_sf_prog_key
{
279 bool contains_flat_varying
;
280 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
281 uint8_t point_sprite_coord_replace
;
282 enum brw_sf_primitive primitive
:2;
283 bool do_twoside_color
:1;
284 bool frontface_ccw
:1;
285 bool do_point_sprite
:1;
286 bool do_point_coord
:1;
287 bool sprite_origin_lower_left
:1;
288 bool userclip_active
:1;
292 BRW_CLIP_MODE_NORMAL
= 0,
293 BRW_CLIP_MODE_CLIP_ALL
= 1,
294 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
295 BRW_CLIP_MODE_REJECT_ALL
= 3,
296 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
297 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
300 enum brw_clip_fill_mode
{
301 BRW_CLIP_FILL_MODE_LINE
= 0,
302 BRW_CLIP_FILL_MODE_POINT
= 1,
303 BRW_CLIP_FILL_MODE_FILL
= 2,
304 BRW_CLIP_FILL_MODE_CULL
= 3,
307 /* Note that if unfilled primitives are being emitted, we have to fix
308 * up polygon offset and flatshading at this point:
310 struct brw_clip_prog_key
{
312 bool contains_flat_varying
;
313 bool contains_noperspective_varying
;
314 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
315 unsigned primitive
:4;
316 unsigned nr_userclip
:4;
319 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
320 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
325 enum brw_clip_mode clip_mode
:3;
332 /* A big lookup table is used to figure out which and how many
333 * additional regs will inserted before the main payload in the WM
334 * program execution. These mainly relate to depth and stencil
335 * processing and the early-depth-test optimization.
337 enum brw_wm_iz_bits
{
338 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
339 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
340 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
341 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
342 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
343 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
344 BRW_WM_IZ_BIT_MAX
= 0x40
347 enum brw_wm_aa_enable
{
353 /** The program key for Fragment/Pixel Shaders. */
354 struct brw_wm_prog_key
{
355 /* Some collection of BRW_WM_IZ_* */
359 unsigned nr_color_regions
:5;
360 bool replicate_alpha
:1;
361 bool clamp_fragment_color
:1;
362 bool persample_interp
:1;
363 bool multisample_fbo
:1;
364 bool frag_coord_adds_sample_pos
:1;
365 enum brw_wm_aa_enable line_aa
:2;
366 bool high_quality_derivatives
:1;
367 bool force_dual_color_blend
:1;
368 bool coherent_fb_fetch
:1;
370 uint16_t drawable_height
;
371 uint64_t input_slots_valid
;
372 unsigned program_string_id
;
373 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
374 float alpha_test_ref
;
376 struct brw_sampler_prog_key_data tex
;
379 struct brw_cs_prog_key
{
380 uint32_t program_string_id
;
381 struct brw_sampler_prog_key_data tex
;
385 * Image metadata structure as laid out in the shader parameter
386 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
387 * able to use them. That's okay because the padding and any unused
388 * entries [most of them except when we're doing untyped surface
389 * access] will be removed by the uniform packing pass.
391 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
392 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
393 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
394 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
395 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
396 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
397 #define BRW_IMAGE_PARAM_SIZE 24
399 struct brw_image_param
{
400 /** Surface binding table index. */
401 uint32_t surface_idx
;
403 /** Offset applied to the X and Y surface coordinates. */
406 /** Surface X, Y and Z dimensions. */
409 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
410 * pixels, vertical slice stride in pixels.
414 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
418 * Right shift to apply for bit 6 address swizzling. Two different
419 * swizzles can be specified and will be applied one after the other. The
420 * resulting address will be:
422 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
423 * (addr >> swizzling[1])))
425 * Use \c 0xff if any of the swizzles is not required.
427 uint32_t swizzling
[2];
430 /** Max number of render targets in a shader */
431 #define BRW_MAX_DRAW_BUFFERS 8
434 * Max number of binding table entries used for stream output.
436 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
437 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
439 * On Gen6, the size of transform feedback data is limited not by the number
440 * of components but by the number of binding table entries we set aside. We
441 * use one binding table entry for a float, one entry for a vector, and one
442 * entry per matrix column. Since the only way we can communicate our
443 * transform feedback capabilities to the client is via
444 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
445 * worst case, in which all the varyings are floats, so we use up one binding
446 * table entry per component. Therefore we need to set aside at least 64
447 * binding table entries for use by transform feedback.
449 * Note: since we don't currently pack varyings, it is currently impossible
450 * for the client to actually use up all of these binding table entries--if
451 * all of their varyings were floats, they would run out of varying slots and
452 * fail to link. But that's a bug, so it seems prudent to go ahead and
453 * allocate the number of binding table entries we will need once the bug is
456 #define BRW_MAX_SOL_BINDINGS 64
459 * Binding table index for the first gen6 SOL binding.
461 #define BRW_GEN6_SOL_BINDING_START 0
464 * Stride in bytes between shader_time entries.
466 * We separate entries by a cacheline to reduce traffic between EUs writing to
469 #define BRW_SHADER_TIME_STRIDE 64
478 struct brw_stage_prog_data
{
480 /** size of our binding table. */
484 * surface indices for the various groups of surfaces
486 uint32_t pull_constants_start
;
487 uint32_t texture_start
;
488 uint32_t gather_texture_start
;
492 uint32_t image_start
;
493 uint32_t shader_time_start
;
494 uint32_t plane_start
[3];
498 struct brw_ubo_range ubo_ranges
[4];
500 GLuint nr_params
; /**< number of float params/constants */
501 GLuint nr_pull_params
;
502 unsigned nr_image_params
;
504 unsigned curb_read_length
;
505 unsigned total_scratch
;
506 unsigned total_shared
;
509 * Register where the thread expects to find input data from the URB
510 * (typically uniforms, followed by vertex or fragment attributes).
512 unsigned dispatch_grf_start_reg
;
514 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
516 /* Pointers to tracked values (only valid once
517 * _mesa_load_state_parameters has been called at runtime).
519 const union gl_constant_value
**param
;
520 const union gl_constant_value
**pull_param
;
522 /** Image metadata passed to the shader as uniforms. */
523 struct brw_image_param
*image_param
;
527 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
530 /* A binding table index is 8 bits and the top 3 values are reserved for
531 * special things (stateless and SLM).
533 assert(surf_index
<= 252);
535 prog_data
->binding_table
.size_bytes
=
536 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
539 enum brw_barycentric_mode
{
540 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
541 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
542 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
543 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
544 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
545 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
546 BRW_BARYCENTRIC_MODE_COUNT
= 6
548 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
549 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
550 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
551 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
553 enum brw_pixel_shader_computed_depth_mode
{
554 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
555 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
556 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
557 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
560 /* Data about a particular attempt to compile a program. Note that
561 * there can be many of these, each in a different GL state
562 * corresponding to a different brw_wm_prog_key struct, with different
565 struct brw_wm_prog_data
{
566 struct brw_stage_prog_data base
;
568 GLuint num_varying_inputs
;
570 uint8_t reg_blocks_0
;
571 uint8_t reg_blocks_2
;
573 uint8_t dispatch_grf_start_reg_2
;
574 uint32_t prog_offset_2
;
578 * surface indices the WM-specific surfaces
580 uint32_t render_target_start
;
581 uint32_t render_target_read_start
;
585 uint8_t computed_depth_mode
;
586 bool computed_stencil
;
588 bool early_fragment_tests
;
589 bool post_depth_coverage
;
594 bool persample_dispatch
;
595 bool uses_pos_offset
;
600 bool uses_sample_mask
;
601 bool has_side_effects
;
604 bool contains_flat_varying
;
605 bool contains_noperspective_varying
;
608 * Mask of which interpolation modes are required by the fragment shader.
609 * Used in hardware setup on gen6+.
611 uint32_t barycentric_interp_modes
;
614 * Mask of which FS inputs are marked flat by the shader source. This is
615 * needed for setting up 3DSTATE_SF/SBE.
617 uint32_t flat_inputs
;
619 /* Mapping of VUE slots to interpolation modes.
620 * Used by the Gen4-5 clip/sf/wm stages.
622 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
625 * Map from gl_varying_slot to the position within the FS setup data
626 * payload where the varying's attribute vertex deltas should be delivered.
627 * For varying slots that are not used by the FS, the value is -1.
629 int urb_setup
[VARYING_SLOT_MAX
];
632 struct brw_push_const_block
{
633 unsigned dwords
; /* Dword count, not reg aligned */
635 unsigned size
; /* Bytes, register aligned */
638 struct brw_cs_prog_data
{
639 struct brw_stage_prog_data base
;
641 GLuint dispatch_grf_start_reg_16
;
642 unsigned local_size
[3];
646 bool uses_num_work_groups
;
647 int thread_local_id_index
;
650 struct brw_push_const_block cross_thread
;
651 struct brw_push_const_block per_thread
;
652 struct brw_push_const_block total
;
657 * surface indices the CS-specific surfaces
659 uint32_t work_groups_start
;
665 * Enum representing the i965-specific vertex results that don't correspond
666 * exactly to any element of gl_varying_slot. The values of this enum are
667 * assigned such that they don't conflict with gl_varying_slot.
671 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
672 BRW_VARYING_SLOT_PAD
,
674 * Technically this is not a varying but just a placeholder that
675 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
676 * builtin variable to be compiled correctly. see compile_sf_prog() for
679 BRW_VARYING_SLOT_PNTC
,
680 BRW_VARYING_SLOT_COUNT
684 * We always program SF to start reading at an offset of 1 (2 varying slots)
685 * from the start of the vertex URB entry. This causes it to skip:
686 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
687 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
689 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
692 * Bitmask indicating which fragment shader inputs represent varyings (and
693 * hence have to be delivered to the fragment shader by the SF/SBE stage).
695 #define BRW_FS_VARYING_INPUT_MASK \
696 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
697 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
700 * Data structure recording the relationship between the gl_varying_slot enum
701 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
702 * single octaword within the VUE (128 bits).
704 * Note that each BRW register contains 256 bits (2 octawords), so when
705 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
706 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
707 * in a vertex shader), each register corresponds to a single VUE slot, since
708 * it contains data for two separate vertices.
712 * Bitfield representing all varying slots that are (a) stored in this VUE
713 * map, and (b) actually written by the shader. Does not include any of
714 * the additional varying slots defined in brw_varying_slot.
716 uint64_t slots_valid
;
719 * Is this VUE map for a separate shader pipeline?
721 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
722 * without the linker having a chance to dead code eliminate unused varyings.
724 * This means that we have to use a fixed slot layout, based on the output's
725 * location field, rather than assigning slots in a compact contiguous block.
730 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
731 * not stored in a slot (because they are not written, or because
732 * additional processing is applied before storing them in the VUE), the
735 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
738 * Map from VUE slot to gl_varying_slot value. For slots that do not
739 * directly correspond to a gl_varying_slot, the value comes from
742 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
744 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
747 * Total number of VUE slots in use
752 * Number of per-patch VUE slots. Only valid for tessellation control
753 * shader outputs and tessellation evaluation shader inputs.
755 int num_per_patch_slots
;
758 * Number of per-vertex VUE slots. Only valid for tessellation control
759 * shader outputs and tessellation evaluation shader inputs.
761 int num_per_vertex_slots
;
764 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
767 * Convert a VUE slot number into a byte offset within the VUE.
769 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
775 * Convert a vertex output (brw_varying_slot) into a byte offset within the
779 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
781 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
784 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
785 struct brw_vue_map
*vue_map
,
786 uint64_t slots_valid
,
787 bool separate_shader
);
789 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
790 uint64_t slots_valid
,
793 /* brw_interpolation_map.c */
794 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
795 struct nir_shader
*nir
,
796 struct brw_wm_prog_data
*prog_data
,
797 const struct gen_device_info
*devinfo
);
799 enum shader_dispatch_mode
{
800 DISPATCH_MODE_4X1_SINGLE
= 0,
801 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
802 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
803 DISPATCH_MODE_SIMD8
= 3,
807 * @defgroup Tessellator parameter enumerations.
809 * These correspond to the hardware values in 3DSTATE_TE, and are provided
810 * as part of the tessellation evaluation shader.
814 enum brw_tess_partitioning
{
815 BRW_TESS_PARTITIONING_INTEGER
= 0,
816 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
817 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
820 enum brw_tess_output_topology
{
821 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
822 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
823 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
824 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
827 enum brw_tess_domain
{
828 BRW_TESS_DOMAIN_QUAD
= 0,
829 BRW_TESS_DOMAIN_TRI
= 1,
830 BRW_TESS_DOMAIN_ISOLINE
= 2,
834 struct brw_vue_prog_data
{
835 struct brw_stage_prog_data base
;
836 struct brw_vue_map vue_map
;
838 /** Should the hardware deliver input VUE handles for URB pull loads? */
839 bool include_vue_handles
;
841 GLuint urb_read_length
;
844 uint32_t clip_distance_mask
;
845 uint32_t cull_distance_mask
;
847 /* Used for calculating urb partitions. In the VS, this is the size of the
848 * URB entry used for both input and output to the thread. In the GS, this
849 * is the size of the URB entry used for output.
851 GLuint urb_entry_size
;
853 enum shader_dispatch_mode dispatch_mode
;
856 struct brw_vs_prog_data
{
857 struct brw_vue_prog_data base
;
859 GLbitfield64 inputs_read
;
860 GLbitfield64 double_inputs_read
;
862 unsigned nr_attributes
;
863 unsigned nr_attribute_slots
;
866 bool uses_instanceid
;
867 bool uses_basevertex
;
868 bool uses_baseinstance
;
872 struct brw_tcs_prog_data
874 struct brw_vue_prog_data base
;
876 /** Number vertices in output patch */
881 struct brw_tes_prog_data
883 struct brw_vue_prog_data base
;
885 enum brw_tess_partitioning partitioning
;
886 enum brw_tess_output_topology output_topology
;
887 enum brw_tess_domain domain
;
890 struct brw_gs_prog_data
892 struct brw_vue_prog_data base
;
894 unsigned vertices_in
;
897 * Size of an output vertex, measured in HWORDS (32 bytes).
899 unsigned output_vertex_size_hwords
;
901 unsigned output_topology
;
904 * Size of the control data (cut bits or StreamID bits), in hwords (32
905 * bytes). 0 if there is no control data.
907 unsigned control_data_header_size_hwords
;
910 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
911 * if the control data is StreamID bits, or
912 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
913 * Ignored if control_data_header_size is 0.
915 unsigned control_data_format
;
917 bool include_primitive_id
;
920 * The number of vertices emitted, if constant - otherwise -1.
922 int static_vertex_count
;
927 * Gen6: Provoking vertex convention for odd-numbered triangles
933 * Gen6: Number of varyings that are output to transform feedback.
935 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
938 * Gen6: Map from the index of a transform feedback binding table entry to the
939 * gl_varying_slot that should be streamed out through that binding table
942 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
945 * Gen6: Map from the index of a transform feedback binding table entry to the
946 * swizzles that should be used when streaming out data through that
947 * binding table entry.
949 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
952 struct brw_sf_prog_data
{
953 uint32_t urb_read_length
;
956 /* Each vertex may have upto 12 attributes, 4 components each,
957 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
960 * Actually we use 4 for each, so call it 12 rows.
962 unsigned urb_entry_size
;
965 struct brw_clip_prog_data
{
966 uint32_t curb_read_length
; /* user planes? */
968 uint32_t urb_read_length
;
972 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
973 static inline struct brw_##stage##_prog_data * \
974 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
976 return (struct brw_##stage##_prog_data *) prog_data; \
978 DEFINE_PROG_DATA_DOWNCAST(vue
)
979 DEFINE_PROG_DATA_DOWNCAST(vs
)
980 DEFINE_PROG_DATA_DOWNCAST(tcs
)
981 DEFINE_PROG_DATA_DOWNCAST(tes
)
982 DEFINE_PROG_DATA_DOWNCAST(gs
)
983 DEFINE_PROG_DATA_DOWNCAST(wm
)
984 DEFINE_PROG_DATA_DOWNCAST(cs
)
985 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
986 DEFINE_PROG_DATA_DOWNCAST(clip
)
987 DEFINE_PROG_DATA_DOWNCAST(sf
)
988 #undef DEFINE_PROG_DATA_DOWNCAST
992 struct brw_compiler
*
993 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
996 * Compile a vertex shader.
998 * Returns the final assembly and the program's size.
1001 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1003 const struct brw_vs_prog_key
*key
,
1004 struct brw_vs_prog_data
*prog_data
,
1005 const struct nir_shader
*shader
,
1006 gl_clip_plane
*clip_planes
,
1007 bool use_legacy_snorm_formula
,
1008 int shader_time_index
,
1009 unsigned *final_assembly_size
,
1013 * Compile a tessellation control shader.
1015 * Returns the final assembly and the program's size.
1018 brw_compile_tcs(const struct brw_compiler
*compiler
,
1021 const struct brw_tcs_prog_key
*key
,
1022 struct brw_tcs_prog_data
*prog_data
,
1023 const struct nir_shader
*nir
,
1024 int shader_time_index
,
1025 unsigned *final_assembly_size
,
1029 * Compile a tessellation evaluation shader.
1031 * Returns the final assembly and the program's size.
1034 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1036 const struct brw_tes_prog_key
*key
,
1037 const struct brw_vue_map
*input_vue_map
,
1038 struct brw_tes_prog_data
*prog_data
,
1039 const struct nir_shader
*shader
,
1040 struct gl_program
*prog
,
1041 int shader_time_index
,
1042 unsigned *final_assembly_size
,
1046 * Compile a vertex shader.
1048 * Returns the final assembly and the program's size.
1051 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1053 const struct brw_gs_prog_key
*key
,
1054 struct brw_gs_prog_data
*prog_data
,
1055 const struct nir_shader
*shader
,
1056 struct gl_program
*prog
,
1057 int shader_time_index
,
1058 unsigned *final_assembly_size
,
1062 * Compile a strips and fans shader.
1064 * This is a fixed-function shader determined entirely by the shader key and
1067 * Returns the final assembly and the program's size.
1070 brw_compile_sf(const struct brw_compiler
*compiler
,
1072 const struct brw_sf_prog_key
*key
,
1073 struct brw_sf_prog_data
*prog_data
,
1074 struct brw_vue_map
*vue_map
,
1075 unsigned *final_assembly_size
);
1078 * Compile a clipper shader.
1080 * This is a fixed-function shader determined entirely by the shader key and
1083 * Returns the final assembly and the program's size.
1086 brw_compile_clip(const struct brw_compiler
*compiler
,
1088 const struct brw_clip_prog_key
*key
,
1089 struct brw_clip_prog_data
*prog_data
,
1090 struct brw_vue_map
*vue_map
,
1091 unsigned *final_assembly_size
);
1094 * Compile a fragment shader.
1096 * Returns the final assembly and the program's size.
1099 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1101 const struct brw_wm_prog_key
*key
,
1102 struct brw_wm_prog_data
*prog_data
,
1103 const struct nir_shader
*shader
,
1104 struct gl_program
*prog
,
1105 int shader_time_index8
,
1106 int shader_time_index16
,
1107 bool allow_spilling
,
1108 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1109 unsigned *final_assembly_size
,
1113 * Compile a compute shader.
1115 * Returns the final assembly and the program's size.
1118 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1120 const struct brw_cs_prog_key
*key
,
1121 struct brw_cs_prog_data
*prog_data
,
1122 const struct nir_shader
*shader
,
1123 int shader_time_index
,
1124 unsigned *final_assembly_size
,
1127 static inline uint32_t
1128 encode_slm_size(unsigned gen
, uint32_t bytes
)
1130 uint32_t slm_size
= 0;
1132 /* Shared Local Memory is specified as powers of two, and encoded in
1133 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1135 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1136 * -------------------------------------------------------------------
1137 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1138 * -------------------------------------------------------------------
1139 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1141 assert(bytes
<= 64 * 1024);
1144 /* Shared Local Memory Size is specified as powers of two. */
1145 slm_size
= util_next_power_of_two(bytes
);
1148 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1149 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1151 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1152 slm_size
= MAX2(slm_size
, 4096) / 4096;
1160 * Return true if the given shader stage is dispatched contiguously by the
1161 * relevant fixed function starting from channel 0 of the SIMD thread, which
1162 * implies that the dispatch mask of a thread can be assumed to have the form
1163 * '2^n - 1' for some n.
1166 brw_stage_has_packed_dispatch(const struct gen_device_info
*devinfo
,
1167 gl_shader_stage stage
,
1168 const struct brw_stage_prog_data
*prog_data
)
1170 /* The code below makes assumptions about the hardware's thread dispatch
1171 * behavior that could be proven wrong in future generations -- Make sure
1172 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1173 * the NIR front-end before changing this assertion.
1175 assert(devinfo
->gen
<= 10);
1178 case MESA_SHADER_FRAGMENT
: {
1179 /* The PSD discards subspans coming in with no lit samples, which in the
1180 * per-pixel shading case implies that each subspan will either be fully
1181 * lit (due to the VMask being used to allow derivative computations),
1182 * or not dispatched at all. In per-sample dispatch mode individual
1183 * samples from the same subspan have a fixed relative location within
1184 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1185 * general and we should return false.
1187 const struct brw_wm_prog_data
*wm_prog_data
=
1188 (const struct brw_wm_prog_data
*)prog_data
;
1189 return !wm_prog_data
->persample_dispatch
;
1191 case MESA_SHADER_COMPUTE
:
1192 /* Compute shaders will be spawned with either a fully enabled dispatch
1193 * mask or with whatever bottom/right execution mask was given to the
1194 * GPGPU walker command to be used along the workgroup edges -- In both
1195 * cases the dispatch mask is required to be tightly packed for our
1196 * invocation index calculations to work.
1200 /* Most remaining fixed functions are limited to use a packed dispatch
1201 * mask due to the hardware representation of the dispatch mask as a
1202 * single counter representing the number of enabled channels.
1212 #endif /* BRW_COMPILER_H */