2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
39 #include "brw_eu_defines.h"
41 #include "brw_disasm_info.h"
47 #define BRW_EU_MAX_INSN_STACK 5
49 struct brw_insn_state
{
50 /* One of BRW_EXECUTE_* */
53 /* Group in units of channels */
56 /* Compression control on gen4-5 */
59 /* One of BRW_MASK_* */
60 unsigned mask_control
:1;
62 /* Scheduling info for Gen12+ */
67 /* One of BRW_ALIGN_* */
68 unsigned access_mode
:1;
70 /* One of BRW_PREDICATE_* */
71 enum brw_predicate predicate
:4;
75 /* Flag subreg. Bottom bit is subreg, top bit is reg */
76 unsigned flag_subreg
:2;
78 bool acc_wr_control
:1;
82 /* A helper for accessing the last instruction emitted. This makes it easy
83 * to set various bits on an instruction without having to create temporary
84 * variable and assign the emitted instruction to those.
86 #define brw_last_inst (&p->store[p->nr_insn - 1])
92 unsigned int next_insn_offset
;
96 /* Allow clients to push/pop instruction state:
98 struct brw_insn_state stack
[BRW_EU_MAX_INSN_STACK
];
99 struct brw_insn_state
*current
;
101 /** Whether or not the user wants automatic exec sizes
103 * If true, codegen will try to automatically infer the exec size of an
104 * instruction from the width of the destination register. If false, it
105 * will take whatever is set by brw_set_default_exec_size verbatim.
107 * This is set to true by default in brw_init_codegen.
109 bool automatic_exec_sizes
;
111 bool single_program_flow
;
112 const struct gen_device_info
*devinfo
;
114 /* Control flow stacks:
115 * - if_stack contains IF and ELSE instructions which must be patched
116 * (and popped) once the matching ENDIF instruction is encountered.
118 * Just store the instruction pointer(an index).
122 int if_stack_array_size
;
125 * loop_stack contains the instruction pointers of the starts of loops which
126 * must be patched (and popped) once the matching WHILE instruction is
131 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
132 * blocks they were popping out of, to fix up the mask stack. This tracks
133 * the IF/ENDIF nesting in each current nested loop level.
135 int *if_depth_in_loop
;
136 int loop_stack_depth
;
137 int loop_stack_array_size
;
140 void brw_pop_insn_state( struct brw_codegen
*p
);
141 void brw_push_insn_state( struct brw_codegen
*p
);
142 unsigned brw_get_default_exec_size(struct brw_codegen
*p
);
143 unsigned brw_get_default_group(struct brw_codegen
*p
);
144 unsigned brw_get_default_access_mode(struct brw_codegen
*p
);
145 struct tgl_swsb
brw_get_default_swsb(struct brw_codegen
*p
);
146 void brw_set_default_exec_size(struct brw_codegen
*p
, unsigned value
);
147 void brw_set_default_mask_control( struct brw_codegen
*p
, unsigned value
);
148 void brw_set_default_saturate( struct brw_codegen
*p
, bool enable
);
149 void brw_set_default_access_mode( struct brw_codegen
*p
, unsigned access_mode
);
150 void brw_inst_set_compression(const struct gen_device_info
*devinfo
,
151 brw_inst
*inst
, bool on
);
152 void brw_set_default_compression(struct brw_codegen
*p
, bool on
);
153 void brw_inst_set_group(const struct gen_device_info
*devinfo
,
154 brw_inst
*inst
, unsigned group
);
155 void brw_set_default_group(struct brw_codegen
*p
, unsigned group
);
156 void brw_set_default_compression_control(struct brw_codegen
*p
, enum brw_compression c
);
157 void brw_set_default_predicate_control(struct brw_codegen
*p
, enum brw_predicate pc
);
158 void brw_set_default_predicate_inverse(struct brw_codegen
*p
, bool predicate_inverse
);
159 void brw_set_default_flag_reg(struct brw_codegen
*p
, int reg
, int subreg
);
160 void brw_set_default_acc_write_control(struct brw_codegen
*p
, unsigned value
);
161 void brw_set_default_swsb(struct brw_codegen
*p
, struct tgl_swsb value
);
163 void brw_init_codegen(const struct gen_device_info
*, struct brw_codegen
*p
,
165 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
166 const struct brw_inst
*inst
, bool is_compacted
);
167 void brw_disassemble(const struct gen_device_info
*devinfo
,
168 const void *assembly
, int start
, int end
, FILE *out
);
169 const unsigned *brw_get_program( struct brw_codegen
*p
, unsigned *sz
);
171 bool brw_try_override_assembly(struct brw_codegen
*p
, int start_offset
,
172 const char *identifier
);
174 brw_inst
*brw_next_insn(struct brw_codegen
*p
, unsigned opcode
);
175 void brw_set_dest(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg dest
);
176 void brw_set_src0(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
178 void gen6_resolve_implied_move(struct brw_codegen
*p
,
180 unsigned msg_reg_nr
);
182 /* Helpers for regular instructions:
185 brw_inst *brw_##OP(struct brw_codegen *p, \
186 struct brw_reg dest, \
187 struct brw_reg src0);
190 brw_inst *brw_##OP(struct brw_codegen *p, \
191 struct brw_reg dest, \
192 struct brw_reg src0, \
193 struct brw_reg src1);
196 brw_inst *brw_##OP(struct brw_codegen *p, \
197 struct brw_reg dest, \
198 struct brw_reg src0, \
199 struct brw_reg src1, \
200 struct brw_reg src2);
203 void brw_##OP(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0);
256 /* Helpers for SEND instruction:
260 * Construct a message descriptor immediate with the specified common
261 * descriptor controls.
263 static inline uint32_t
264 brw_message_desc(const struct gen_device_info
*devinfo
,
266 unsigned response_length
,
269 if (devinfo
->gen
>= 5) {
270 return (SET_BITS(msg_length
, 28, 25) |
271 SET_BITS(response_length
, 24, 20) |
272 SET_BITS(header_present
, 19, 19));
274 return (SET_BITS(msg_length
, 23, 20) |
275 SET_BITS(response_length
, 19, 16));
279 static inline unsigned
280 brw_message_desc_mlen(const struct gen_device_info
*devinfo
, uint32_t desc
)
282 if (devinfo
->gen
>= 5)
283 return GET_BITS(desc
, 28, 25);
285 return GET_BITS(desc
, 23, 20);
288 static inline unsigned
289 brw_message_desc_rlen(const struct gen_device_info
*devinfo
, uint32_t desc
)
291 if (devinfo
->gen
>= 5)
292 return GET_BITS(desc
, 24, 20);
294 return GET_BITS(desc
, 19, 16);
298 brw_message_desc_header_present(ASSERTED
const struct gen_device_info
*devinfo
,
301 assert(devinfo
->gen
>= 5);
302 return GET_BITS(desc
, 19, 19);
305 static inline unsigned
306 brw_message_ex_desc(UNUSED
const struct gen_device_info
*devinfo
,
307 unsigned ex_msg_length
)
309 return SET_BITS(ex_msg_length
, 9, 6);
312 static inline unsigned
313 brw_message_ex_desc_ex_mlen(UNUSED
const struct gen_device_info
*devinfo
,
316 return GET_BITS(ex_desc
, 9, 6);
320 * Construct a message descriptor immediate with the specified sampler
323 static inline uint32_t
324 brw_sampler_desc(const struct gen_device_info
*devinfo
,
325 unsigned binding_table_index
,
329 unsigned return_format
)
331 const unsigned desc
= (SET_BITS(binding_table_index
, 7, 0) |
332 SET_BITS(sampler
, 11, 8));
333 if (devinfo
->gen
>= 7)
334 return (desc
| SET_BITS(msg_type
, 16, 12) |
335 SET_BITS(simd_mode
, 18, 17));
336 else if (devinfo
->gen
>= 5)
337 return (desc
| SET_BITS(msg_type
, 15, 12) |
338 SET_BITS(simd_mode
, 17, 16));
339 else if (devinfo
->is_g4x
)
340 return desc
| SET_BITS(msg_type
, 15, 12);
342 return (desc
| SET_BITS(return_format
, 13, 12) |
343 SET_BITS(msg_type
, 15, 14));
346 static inline unsigned
347 brw_sampler_desc_binding_table_index(UNUSED
const struct gen_device_info
*devinfo
,
350 return GET_BITS(desc
, 7, 0);
353 static inline unsigned
354 brw_sampler_desc_sampler(UNUSED
const struct gen_device_info
*devinfo
, uint32_t desc
)
356 return GET_BITS(desc
, 11, 8);
359 static inline unsigned
360 brw_sampler_desc_msg_type(const struct gen_device_info
*devinfo
, uint32_t desc
)
362 if (devinfo
->gen
>= 7)
363 return GET_BITS(desc
, 16, 12);
364 else if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
365 return GET_BITS(desc
, 15, 12);
367 return GET_BITS(desc
, 15, 14);
370 static inline unsigned
371 brw_sampler_desc_simd_mode(const struct gen_device_info
*devinfo
, uint32_t desc
)
373 assert(devinfo
->gen
>= 5);
374 if (devinfo
->gen
>= 7)
375 return GET_BITS(desc
, 18, 17);
377 return GET_BITS(desc
, 17, 16);
380 static inline unsigned
381 brw_sampler_desc_return_format(ASSERTED
const struct gen_device_info
*devinfo
,
384 assert(devinfo
->gen
== 4 && !devinfo
->is_g4x
);
385 return GET_BITS(desc
, 13, 12);
389 * Construct a message descriptor for the dataport
391 static inline uint32_t
392 brw_dp_desc(const struct gen_device_info
*devinfo
,
393 unsigned binding_table_index
,
395 unsigned msg_control
)
397 /* Prior to gen6, things are too inconsistent; use the dp_read/write_desc
400 assert(devinfo
->gen
>= 6);
401 const unsigned desc
= SET_BITS(binding_table_index
, 7, 0);
402 if (devinfo
->gen
>= 8) {
403 return (desc
| SET_BITS(msg_control
, 13, 8) |
404 SET_BITS(msg_type
, 18, 14));
405 } else if (devinfo
->gen
>= 7) {
406 return (desc
| SET_BITS(msg_control
, 13, 8) |
407 SET_BITS(msg_type
, 17, 14));
409 return (desc
| SET_BITS(msg_control
, 12, 8) |
410 SET_BITS(msg_type
, 16, 13));
414 static inline unsigned
415 brw_dp_desc_binding_table_index(UNUSED
const struct gen_device_info
*devinfo
,
418 return GET_BITS(desc
, 7, 0);
421 static inline unsigned
422 brw_dp_desc_msg_type(const struct gen_device_info
*devinfo
, uint32_t desc
)
424 assert(devinfo
->gen
>= 6);
425 if (devinfo
->gen
>= 8)
426 return GET_BITS(desc
, 18, 14);
427 else if (devinfo
->gen
>= 7)
428 return GET_BITS(desc
, 17, 14);
430 return GET_BITS(desc
, 16, 13);
433 static inline unsigned
434 brw_dp_desc_msg_control(const struct gen_device_info
*devinfo
, uint32_t desc
)
436 assert(devinfo
->gen
>= 6);
437 if (devinfo
->gen
>= 7)
438 return GET_BITS(desc
, 13, 8);
440 return GET_BITS(desc
, 12, 8);
444 * Construct a message descriptor immediate with the specified dataport read
447 static inline uint32_t
448 brw_dp_read_desc(const struct gen_device_info
*devinfo
,
449 unsigned binding_table_index
,
450 unsigned msg_control
,
452 unsigned target_cache
)
454 if (devinfo
->gen
>= 6)
455 return brw_dp_desc(devinfo
, binding_table_index
, msg_type
, msg_control
);
456 else if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
457 return (SET_BITS(binding_table_index
, 7, 0) |
458 SET_BITS(msg_control
, 10, 8) |
459 SET_BITS(msg_type
, 13, 11) |
460 SET_BITS(target_cache
, 15, 14));
462 return (SET_BITS(binding_table_index
, 7, 0) |
463 SET_BITS(msg_control
, 11, 8) |
464 SET_BITS(msg_type
, 13, 12) |
465 SET_BITS(target_cache
, 15, 14));
468 static inline unsigned
469 brw_dp_read_desc_msg_type(const struct gen_device_info
*devinfo
, uint32_t desc
)
471 if (devinfo
->gen
>= 6)
472 return brw_dp_desc_msg_type(devinfo
, desc
);
473 else if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
474 return GET_BITS(desc
, 13, 11);
476 return GET_BITS(desc
, 13, 12);
479 static inline unsigned
480 brw_dp_read_desc_msg_control(const struct gen_device_info
*devinfo
,
483 if (devinfo
->gen
>= 6)
484 return brw_dp_desc_msg_control(devinfo
, desc
);
485 else if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
486 return GET_BITS(desc
, 10, 8);
488 return GET_BITS(desc
, 11, 8);
492 * Construct a message descriptor immediate with the specified dataport write
495 static inline uint32_t
496 brw_dp_write_desc(const struct gen_device_info
*devinfo
,
497 unsigned binding_table_index
,
498 unsigned msg_control
,
500 unsigned last_render_target
,
501 unsigned send_commit_msg
)
503 assert(devinfo
->gen
<= 6 || !send_commit_msg
);
504 if (devinfo
->gen
>= 6)
505 return brw_dp_desc(devinfo
, binding_table_index
, msg_type
, msg_control
) |
506 SET_BITS(last_render_target
, 12, 12) |
507 SET_BITS(send_commit_msg
, 17, 17);
509 return (SET_BITS(binding_table_index
, 7, 0) |
510 SET_BITS(msg_control
, 11, 8) |
511 SET_BITS(last_render_target
, 11, 11) |
512 SET_BITS(msg_type
, 14, 12) |
513 SET_BITS(send_commit_msg
, 15, 15));
516 static inline unsigned
517 brw_dp_write_desc_msg_type(const struct gen_device_info
*devinfo
,
520 if (devinfo
->gen
>= 6)
521 return brw_dp_desc_msg_type(devinfo
, desc
);
523 return GET_BITS(desc
, 14, 12);
526 static inline unsigned
527 brw_dp_write_desc_msg_control(const struct gen_device_info
*devinfo
,
530 if (devinfo
->gen
>= 6)
531 return brw_dp_desc_msg_control(devinfo
, desc
);
533 return GET_BITS(desc
, 11, 8);
537 brw_dp_write_desc_last_render_target(const struct gen_device_info
*devinfo
,
540 if (devinfo
->gen
>= 6)
541 return GET_BITS(desc
, 12, 12);
543 return GET_BITS(desc
, 11, 11);
547 brw_dp_write_desc_write_commit(const struct gen_device_info
*devinfo
,
550 assert(devinfo
->gen
<= 6);
551 if (devinfo
->gen
>= 6)
552 return GET_BITS(desc
, 17, 17);
554 return GET_BITS(desc
, 15, 15);
558 * Construct a message descriptor immediate with the specified dataport
559 * surface function controls.
561 static inline uint32_t
562 brw_dp_surface_desc(const struct gen_device_info
*devinfo
,
564 unsigned msg_control
)
566 assert(devinfo
->gen
>= 7);
567 /* We'll OR in the binding table index later */
568 return brw_dp_desc(devinfo
, 0, msg_type
, msg_control
);
571 static inline uint32_t
572 brw_dp_untyped_atomic_desc(const struct gen_device_info
*devinfo
,
573 unsigned exec_size
, /**< 0 for SIMD4x2 */
575 bool response_expected
)
577 assert(exec_size
<= 8 || exec_size
== 16);
580 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
582 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP
;
584 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2
;
587 msg_type
= GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP
;
590 const unsigned msg_control
=
591 SET_BITS(atomic_op
, 3, 0) |
592 SET_BITS(0 < exec_size
&& exec_size
<= 8, 4, 4) |
593 SET_BITS(response_expected
, 5, 5);
595 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
598 static inline uint32_t
599 brw_dp_untyped_atomic_float_desc(const struct gen_device_info
*devinfo
,
602 bool response_expected
)
604 assert(exec_size
<= 8 || exec_size
== 16);
605 assert(devinfo
->gen
>= 9);
607 assert(exec_size
> 0);
608 const unsigned msg_type
= GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP
;
610 const unsigned msg_control
=
611 SET_BITS(atomic_op
, 1, 0) |
612 SET_BITS(exec_size
<= 8, 4, 4) |
613 SET_BITS(response_expected
, 5, 5);
615 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
618 static inline unsigned
619 brw_mdc_cmask(unsigned num_channels
)
621 /* See also MDC_CMASK in the SKL PRM Vol 2d. */
622 return 0xf & (0xf << num_channels
);
625 static inline uint32_t
626 brw_dp_untyped_surface_rw_desc(const struct gen_device_info
*devinfo
,
627 unsigned exec_size
, /**< 0 for SIMD4x2 */
628 unsigned num_channels
,
631 assert(exec_size
<= 8 || exec_size
== 16);
635 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
636 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE
;
638 msg_type
= GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE
;
642 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
643 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ
;
645 msg_type
= GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ
;
649 /* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
650 if (write
&& devinfo
->gen
== 7 && !devinfo
->is_haswell
&& exec_size
== 0)
653 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
654 const unsigned simd_mode
= exec_size
== 0 ? 0 : /* SIMD4x2 */
655 exec_size
<= 8 ? 2 : 1;
657 const unsigned msg_control
=
658 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
659 SET_BITS(simd_mode
, 5, 4);
661 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
664 static inline unsigned
665 brw_mdc_ds(unsigned bit_size
)
669 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE
;
671 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD
;
673 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD
;
675 unreachable("Unsupported bit_size for byte scattered messages");
679 static inline uint32_t
680 brw_dp_byte_scattered_rw_desc(const struct gen_device_info
*devinfo
,
685 assert(exec_size
<= 8 || exec_size
== 16);
687 assert(devinfo
->gen
> 7 || devinfo
->is_haswell
);
688 const unsigned msg_type
=
689 write
? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE
:
690 HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ
;
692 assert(exec_size
> 0);
693 const unsigned msg_control
=
694 SET_BITS(exec_size
== 16, 0, 0) |
695 SET_BITS(brw_mdc_ds(bit_size
), 3, 2);
697 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
700 static inline uint32_t
701 brw_dp_dword_scattered_rw_desc(const struct gen_device_info
*devinfo
,
705 assert(exec_size
== 8 || exec_size
== 16);
709 if (devinfo
->gen
>= 6) {
710 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE
;
712 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE
;
715 if (devinfo
->gen
>= 7) {
716 msg_type
= GEN7_DATAPORT_DC_DWORD_SCATTERED_READ
;
717 } else if (devinfo
->gen
> 4 || devinfo
->is_g4x
) {
718 msg_type
= G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
;
720 msg_type
= BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
;
724 const unsigned msg_control
=
725 SET_BITS(1, 1, 1) | /* Legacy SIMD Mode */
726 SET_BITS(exec_size
== 16, 0, 0);
728 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
731 static inline uint32_t
732 brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info
*devinfo
,
733 unsigned exec_size
, /**< 0 for SIMD4x2 */
734 unsigned num_channels
,
737 assert(exec_size
<= 8 || exec_size
== 16);
738 assert(devinfo
->gen
>= 8);
741 write
? GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE
:
742 GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ
;
744 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
745 const unsigned simd_mode
= exec_size
== 0 ? 0 : /* SIMD4x2 */
746 exec_size
<= 8 ? 2 : 1;
748 const unsigned msg_control
=
749 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
750 SET_BITS(simd_mode
, 5, 4);
752 return brw_dp_desc(devinfo
, BRW_BTI_STATELESS
, msg_type
, msg_control
);
756 * Calculate the data size (see MDC_A64_DS in the "Structures" volume of the
759 static inline uint32_t
760 brw_mdc_a64_ds(unsigned elems
)
768 unreachable("Unsupported elmeent count for A64 scattered message");
772 static inline uint32_t
773 brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info
*devinfo
,
774 unsigned exec_size
, /**< 0 for SIMD4x2 */
778 assert(exec_size
<= 8 || exec_size
== 16);
779 assert(devinfo
->gen
>= 8);
782 write
? GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE
:
783 GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ
;
785 const unsigned msg_control
=
786 SET_BITS(GEN8_A64_SCATTERED_SUBTYPE_BYTE
, 1, 0) |
787 SET_BITS(brw_mdc_a64_ds(bit_size
/ 8), 3, 2) |
788 SET_BITS(exec_size
== 16, 4, 4);
790 return brw_dp_desc(devinfo
, BRW_BTI_STATELESS
, msg_type
, msg_control
);
793 static inline uint32_t
794 brw_dp_a64_untyped_atomic_desc(const struct gen_device_info
*devinfo
,
795 ASSERTED
unsigned exec_size
, /**< 0 for SIMD4x2 */
798 bool response_expected
)
800 assert(exec_size
== 8);
801 assert(devinfo
->gen
>= 8);
802 assert(bit_size
== 32 || bit_size
== 64);
804 const unsigned msg_type
= GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP
;
806 const unsigned msg_control
=
807 SET_BITS(atomic_op
, 3, 0) |
808 SET_BITS(bit_size
== 64, 4, 4) |
809 SET_BITS(response_expected
, 5, 5);
811 return brw_dp_desc(devinfo
, BRW_BTI_STATELESS
, msg_type
, msg_control
);
814 static inline uint32_t
815 brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info
*devinfo
,
816 ASSERTED
unsigned exec_size
,
818 bool response_expected
)
820 assert(exec_size
== 8);
821 assert(devinfo
->gen
>= 9);
823 assert(exec_size
> 0);
824 const unsigned msg_type
= GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP
;
826 const unsigned msg_control
=
827 SET_BITS(atomic_op
, 1, 0) |
828 SET_BITS(response_expected
, 5, 5);
830 return brw_dp_desc(devinfo
, BRW_BTI_STATELESS
, msg_type
, msg_control
);
833 static inline uint32_t
834 brw_dp_typed_atomic_desc(const struct gen_device_info
*devinfo
,
838 bool response_expected
)
840 assert(exec_size
> 0 || exec_group
== 0);
841 assert(exec_group
% 8 == 0);
844 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
845 if (exec_size
== 0) {
846 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2
;
848 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP
;
851 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
852 assert(exec_size
> 0);
853 msg_type
= GEN7_DATAPORT_RC_TYPED_ATOMIC_OP
;
856 const bool high_sample_mask
= (exec_group
/ 8) % 2 == 1;
858 const unsigned msg_control
=
859 SET_BITS(atomic_op
, 3, 0) |
860 SET_BITS(high_sample_mask
, 4, 4) |
861 SET_BITS(response_expected
, 5, 5);
863 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
866 static inline uint32_t
867 brw_dp_typed_surface_rw_desc(const struct gen_device_info
*devinfo
,
870 unsigned num_channels
,
873 assert(exec_size
> 0 || exec_group
== 0);
874 assert(exec_group
% 8 == 0);
876 /* Typed surface reads and writes don't support SIMD16 */
877 assert(exec_size
<= 8);
881 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
882 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE
;
884 msg_type
= GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE
;
887 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
888 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ
;
890 msg_type
= GEN7_DATAPORT_RC_TYPED_SURFACE_READ
;
894 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
895 unsigned msg_control
;
896 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
897 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
898 const unsigned slot_group
= exec_size
== 0 ? 0 : /* SIMD4x2 */
899 1 + ((exec_group
/ 8) % 2);
902 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
903 SET_BITS(slot_group
, 5, 4);
905 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
906 assert(exec_size
> 0);
907 const unsigned slot_group
= ((exec_group
/ 8) % 2);
910 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
911 SET_BITS(slot_group
, 5, 5);
914 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
918 * Construct a message descriptor immediate with the specified pixel
919 * interpolator function controls.
921 static inline uint32_t
922 brw_pixel_interp_desc(UNUSED
const struct gen_device_info
*devinfo
,
928 return (SET_BITS(slot_group
, 11, 11) |
929 SET_BITS(msg_type
, 13, 12) |
930 SET_BITS(!!noperspective
, 14, 14) |
931 SET_BITS(simd_mode
, 16, 16));
934 void brw_urb_WRITE(struct brw_codegen
*p
,
938 enum brw_urb_write_flags flags
,
940 unsigned response_length
,
945 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
946 * desc. If \p desc is not an immediate it will be transparently loaded to an
947 * address register using an OR instruction.
950 brw_send_indirect_message(struct brw_codegen
*p
,
953 struct brw_reg payload
,
959 brw_send_indirect_split_message(struct brw_codegen
*p
,
962 struct brw_reg payload0
,
963 struct brw_reg payload1
,
966 struct brw_reg ex_desc
,
967 unsigned ex_desc_imm
,
970 void brw_ff_sync(struct brw_codegen
*p
,
975 unsigned response_length
,
978 void brw_svb_write(struct brw_codegen
*p
,
982 unsigned binding_table_index
,
983 bool send_commit_msg
);
985 brw_inst
*brw_fb_WRITE(struct brw_codegen
*p
,
986 struct brw_reg payload
,
987 struct brw_reg implied_header
,
988 unsigned msg_control
,
989 unsigned binding_table_index
,
991 unsigned response_length
,
993 bool last_render_target
,
994 bool header_present
);
996 brw_inst
*gen9_fb_READ(struct brw_codegen
*p
,
998 struct brw_reg payload
,
999 unsigned binding_table_index
,
1000 unsigned msg_length
,
1001 unsigned response_length
,
1004 void brw_SAMPLE(struct brw_codegen
*p
,
1005 struct brw_reg dest
,
1006 unsigned msg_reg_nr
,
1007 struct brw_reg src0
,
1008 unsigned binding_table_index
,
1011 unsigned response_length
,
1012 unsigned msg_length
,
1013 unsigned header_present
,
1015 unsigned return_format
);
1017 void brw_adjust_sampler_state_pointer(struct brw_codegen
*p
,
1018 struct brw_reg header
,
1019 struct brw_reg sampler_index
);
1021 void gen4_math(struct brw_codegen
*p
,
1022 struct brw_reg dest
,
1024 unsigned msg_reg_nr
,
1026 unsigned precision
);
1028 void gen6_math(struct brw_codegen
*p
,
1029 struct brw_reg dest
,
1031 struct brw_reg src0
,
1032 struct brw_reg src1
);
1034 void brw_oword_block_read(struct brw_codegen
*p
,
1035 struct brw_reg dest
,
1038 uint32_t bind_table_index
);
1040 unsigned brw_scratch_surface_idx(const struct brw_codegen
*p
);
1042 void brw_oword_block_read_scratch(struct brw_codegen
*p
,
1043 struct brw_reg dest
,
1048 void brw_oword_block_write_scratch(struct brw_codegen
*p
,
1053 void gen7_block_read_scratch(struct brw_codegen
*p
,
1054 struct brw_reg dest
,
1058 void brw_shader_time_add(struct brw_codegen
*p
,
1059 struct brw_reg payload
,
1060 uint32_t surf_index
);
1063 * Return the generation-specific jump distance scaling factor.
1065 * Given the number of instructions to jump, we need to scale by
1066 * some number to obtain the actual jump distance to program in an
1069 static inline unsigned
1070 brw_jump_scale(const struct gen_device_info
*devinfo
)
1072 /* Broadwell measures jump targets in bytes. */
1073 if (devinfo
->gen
>= 8)
1076 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
1077 * (to support compaction), so each 128-bit instruction requires 2 chunks.
1079 if (devinfo
->gen
>= 5)
1082 /* Gen4 simply uses the number of 128-bit instructions. */
1086 void brw_barrier(struct brw_codegen
*p
, struct brw_reg src
);
1088 /* If/else/endif. Works by manipulating the execution flags on each
1091 brw_inst
*brw_IF(struct brw_codegen
*p
, unsigned execute_size
);
1092 brw_inst
*gen6_IF(struct brw_codegen
*p
, enum brw_conditional_mod conditional
,
1093 struct brw_reg src0
, struct brw_reg src1
);
1095 void brw_ELSE(struct brw_codegen
*p
);
1096 void brw_ENDIF(struct brw_codegen
*p
);
1100 brw_inst
*brw_DO(struct brw_codegen
*p
, unsigned execute_size
);
1102 brw_inst
*brw_WHILE(struct brw_codegen
*p
);
1104 brw_inst
*brw_BREAK(struct brw_codegen
*p
);
1105 brw_inst
*brw_CONT(struct brw_codegen
*p
);
1106 brw_inst
*gen6_HALT(struct brw_codegen
*p
);
1110 void brw_land_fwd_jump(struct brw_codegen
*p
, int jmp_insn_idx
);
1112 brw_inst
*brw_JMPI(struct brw_codegen
*p
, struct brw_reg index
,
1113 unsigned predicate_control
);
1115 void brw_NOP(struct brw_codegen
*p
);
1117 void brw_WAIT(struct brw_codegen
*p
);
1119 void brw_SYNC(struct brw_codegen
*p
, enum tgl_sync_function func
);
1121 /* Special case: there is never a destination, execution size will be
1124 void brw_CMP(struct brw_codegen
*p
,
1125 struct brw_reg dest
,
1126 unsigned conditional
,
1127 struct brw_reg src0
,
1128 struct brw_reg src1
);
1131 brw_untyped_atomic(struct brw_codegen
*p
,
1133 struct brw_reg payload
,
1134 struct brw_reg surface
,
1136 unsigned msg_length
,
1137 bool response_expected
,
1138 bool header_present
);
1141 brw_untyped_surface_read(struct brw_codegen
*p
,
1143 struct brw_reg payload
,
1144 struct brw_reg surface
,
1145 unsigned msg_length
,
1146 unsigned num_channels
);
1149 brw_untyped_surface_write(struct brw_codegen
*p
,
1150 struct brw_reg payload
,
1151 struct brw_reg surface
,
1152 unsigned msg_length
,
1153 unsigned num_channels
,
1154 bool header_present
);
1157 brw_memory_fence(struct brw_codegen
*p
,
1160 enum opcode send_op
,
1165 brw_pixel_interpolator_query(struct brw_codegen
*p
,
1166 struct brw_reg dest
,
1170 struct brw_reg data
,
1171 unsigned msg_length
,
1172 unsigned response_length
);
1175 brw_find_live_channel(struct brw_codegen
*p
,
1177 struct brw_reg mask
);
1180 brw_broadcast(struct brw_codegen
*p
,
1183 struct brw_reg idx
);
1186 brw_float_controls_mode(struct brw_codegen
*p
,
1187 unsigned mode
, unsigned mask
);
1189 /***********************************************************************
1193 void brw_copy_indirect_to_indirect(struct brw_codegen
*p
,
1194 struct brw_indirect dst_ptr
,
1195 struct brw_indirect src_ptr
,
1198 void brw_copy_from_indirect(struct brw_codegen
*p
,
1200 struct brw_indirect ptr
,
1203 void brw_copy4(struct brw_codegen
*p
,
1208 void brw_copy8(struct brw_codegen
*p
,
1213 void brw_math_invert( struct brw_codegen
*p
,
1215 struct brw_reg src
);
1217 void brw_set_src1(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
1219 void brw_set_desc_ex(struct brw_codegen
*p
, brw_inst
*insn
,
1220 unsigned desc
, unsigned ex_desc
);
1223 brw_set_desc(struct brw_codegen
*p
, brw_inst
*insn
, unsigned desc
)
1225 brw_set_desc_ex(p
, insn
, desc
, 0);
1228 void brw_set_uip_jip(struct brw_codegen
*p
, int start_offset
);
1230 enum brw_conditional_mod
brw_negate_cmod(enum brw_conditional_mod cmod
);
1231 enum brw_conditional_mod
brw_swap_cmod(enum brw_conditional_mod cmod
);
1233 /* brw_eu_compact.c */
1234 void brw_init_compaction_tables(const struct gen_device_info
*devinfo
);
1235 void brw_compact_instructions(struct brw_codegen
*p
, int start_offset
,
1236 struct disasm_info
*disasm
);
1237 void brw_uncompact_instruction(const struct gen_device_info
*devinfo
,
1238 brw_inst
*dst
, brw_compact_inst
*src
);
1239 bool brw_try_compact_instruction(const struct gen_device_info
*devinfo
,
1240 brw_compact_inst
*dst
, const brw_inst
*src
);
1242 void brw_debug_compact_uncompact(const struct gen_device_info
*devinfo
,
1243 brw_inst
*orig
, brw_inst
*uncompacted
);
1245 /* brw_eu_validate.c */
1246 bool brw_validate_instruction(const struct gen_device_info
*devinfo
,
1247 const brw_inst
*inst
, int offset
,
1248 struct disasm_info
*disasm
);
1249 bool brw_validate_instructions(const struct gen_device_info
*devinfo
,
1250 const void *assembly
, int start_offset
, int end_offset
,
1251 struct disasm_info
*disasm
);
1254 next_offset(const struct gen_device_info
*devinfo
, void *store
, int offset
)
1256 brw_inst
*insn
= (brw_inst
*)((char *)store
+ offset
);
1258 if (brw_inst_cmpt_control(devinfo
, insn
))
1264 struct opcode_desc
{
1273 const struct opcode_desc
*
1274 brw_opcode_desc(const struct gen_device_info
*devinfo
, enum opcode opcode
);
1276 const struct opcode_desc
*
1277 brw_opcode_desc_from_hw(const struct gen_device_info
*devinfo
, unsigned hw
);
1279 static inline unsigned
1280 brw_opcode_encode(const struct gen_device_info
*devinfo
, enum opcode opcode
)
1282 return brw_opcode_desc(devinfo
, opcode
)->hw
;
1285 static inline enum opcode
1286 brw_opcode_decode(const struct gen_device_info
*devinfo
, unsigned hw
)
1288 const struct opcode_desc
*desc
= brw_opcode_desc_from_hw(devinfo
, hw
);
1289 return desc
? (enum opcode
)desc
->ir
: BRW_OPCODE_ILLEGAL
;
1293 brw_inst_set_opcode(const struct gen_device_info
*devinfo
,
1294 brw_inst
*inst
, enum opcode opcode
)
1296 brw_inst_set_hw_opcode(devinfo
, inst
, brw_opcode_encode(devinfo
, opcode
));
1299 static inline enum opcode
1300 brw_inst_opcode(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
1302 return brw_opcode_decode(devinfo
, brw_inst_hw_opcode(devinfo
, inst
));
1306 is_3src(const struct gen_device_info
*devinfo
, enum opcode opcode
)
1308 const struct opcode_desc
*desc
= brw_opcode_desc(devinfo
, opcode
);
1309 return desc
&& desc
->nsrc
== 3;
1312 /** Maximum SEND message length */
1313 #define BRW_MAX_MSG_LENGTH 15
1315 /** First MRF register used by pull loads */
1316 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
1318 /** First MRF register used by spills */
1319 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)