src/intel/compiler/brw_eu.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #ifndef BRW_EU_H
  34 #define BRW_EU_H
  35
  36 #include <stdbool.h>
  37 #include <stdio.h>
  38 #include "brw_inst.h"
  39 #include "brw_eu_defines.h"
  40 #include "brw_reg.h"
  41 #include "brw_disasm_info.h"
  42
  43 #ifdef __cplusplus
  44 extern "C" {
  45 #endif
  46
  47 #define BRW_EU_MAX_INSN_STACK 5
  48
  49 struct brw_insn_state {
  50    /* One of BRW_EXECUTE_* */
  51    unsigned exec_size:3;
  52
  53    /* Group in units of channels */
  54    unsigned group:5;
  55
  56    /* Compression control on gen4-5 */
  57    bool compressed:1;
  58
  59    /* One of BRW_MASK_* */
  60    unsigned mask_control:1;
  61
  62    /* Scheduling info for Gen12+ */
  63    struct tgl_swsb swsb;
  64
  65    bool saturate:1;
  66
  67    /* One of BRW_ALIGN_* */
  68    unsigned access_mode:1;
  69
  70    /* One of BRW_PREDICATE_* */
  71    enum brw_predicate predicate:4;
  72
  73    bool pred_inv:1;
  74
  75    /* Flag subreg.  Bottom bit is subreg, top bit is reg */
  76    unsigned flag_subreg:2;
  77
  78    bool acc_wr_control:1;
  79 };
  80
  81
  82 /* A helper for accessing the last instruction emitted.  This makes it easy
  83  * to set various bits on an instruction without having to create temporary
  84  * variable and assign the emitted instruction to those.
  85  */
  86 #define brw_last_inst (&p->store[p->nr_insn - 1])
  87
  88 struct brw_codegen {
  89    brw_inst *store;
  90    int store_size;
  91    unsigned nr_insn;
  92    unsigned int next_insn_offset;
  93
  94    void *mem_ctx;
  95
  96    /* Allow clients to push/pop instruction state:
  97     */
  98    struct brw_insn_state stack[BRW_EU_MAX_INSN_STACK];
  99    struct brw_insn_state *current;
 100
 101    /** Whether or not the user wants automatic exec sizes
 102     *
 103     * If true, codegen will try to automatically infer the exec size of an
 104     * instruction from the width of the destination register.  If false, it
 105     * will take whatever is set by brw_set_default_exec_size verbatim.
 106     *
 107     * This is set to true by default in brw_init_codegen.
 108     */
 109    bool automatic_exec_sizes;
 110
 111    bool single_program_flow;
 112    const struct gen_device_info *devinfo;
 113
 114    /* Control flow stacks:
 115     * - if_stack contains IF and ELSE instructions which must be patched
 116     *   (and popped) once the matching ENDIF instruction is encountered.
 117     *
 118     *   Just store the instruction pointer(an index).
 119     */
 120    int *if_stack;
 121    int if_stack_depth;
 122    int if_stack_array_size;
 123
 124    /**
 125     * loop_stack contains the instruction pointers of the starts of loops which
 126     * must be patched (and popped) once the matching WHILE instruction is
 127     * encountered.
 128     */
 129    int *loop_stack;
 130    /**
 131     * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
 132     * blocks they were popping out of, to fix up the mask stack.  This tracks
 133     * the IF/ENDIF nesting in each current nested loop level.
 134     */
 135    int *if_depth_in_loop;
 136    int loop_stack_depth;
 137    int loop_stack_array_size;
 138 };
 139
 140 void brw_pop_insn_state( struct brw_codegen *p );
 141 void brw_push_insn_state( struct brw_codegen *p );
 142 unsigned brw_get_default_exec_size(struct brw_codegen *p);
 143 unsigned brw_get_default_group(struct brw_codegen *p);
 144 unsigned brw_get_default_access_mode(struct brw_codegen *p);
 145 struct tgl_swsb brw_get_default_swsb(struct brw_codegen *p);
 146 void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
 147 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
 148 void brw_set_default_saturate( struct brw_codegen *p, bool enable );
 149 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode );
 150 void brw_inst_set_compression(const struct gen_device_info *devinfo,
 151                               brw_inst *inst, bool on);
 152 void brw_set_default_compression(struct brw_codegen *p, bool on);
 153 void brw_inst_set_group(const struct gen_device_info *devinfo,
 154                         brw_inst *inst, unsigned group);
 155 void brw_set_default_group(struct brw_codegen *p, unsigned group);
 156 void brw_set_default_compression_control(struct brw_codegen *p, enum brw_compression c);
 157 void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc);
 158 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse);
 159 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
 160 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
 161 void brw_set_default_swsb(struct brw_codegen *p, struct tgl_swsb value);
 162
 163 void brw_init_codegen(const struct gen_device_info *, struct brw_codegen *p,
 164                       void *mem_ctx);
 165 int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
 166                          const struct brw_inst *inst, bool is_compacted);
 167 void brw_disassemble(const struct gen_device_info *devinfo,
 168                      const void *assembly, int start, int end, FILE *out);
 169 const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz );
 170
 171 bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
 172                                const char *identifier);
 173
 174 brw_inst *brw_next_insn(struct brw_codegen *p, unsigned opcode);
 175 void brw_set_dest(struct brw_codegen *p, brw_inst *insn, struct brw_reg dest);
 176 void brw_set_src0(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
 177
 178 void gen6_resolve_implied_move(struct brw_codegen *p,
 179                                struct brw_reg *src,
 180                                unsigned msg_reg_nr);
 181
 182 /* Helpers for regular instructions:
 183  */
 184 #define ALU1(OP)                                \
 185 brw_inst *brw_##OP(struct brw_codegen *p,       \
 186               struct brw_reg dest,              \
 187               struct brw_reg src0);
 188
 189 #define ALU2(OP)                                \
 190 brw_inst *brw_##OP(struct brw_codegen *p,       \
 191               struct brw_reg dest,              \
 192               struct brw_reg src0,              \
 193               struct brw_reg src1);
 194
 195 #define ALU3(OP)                                \
 196 brw_inst *brw_##OP(struct brw_codegen *p,       \
 197               struct brw_reg dest,              \
 198               struct brw_reg src0,              \
 199               struct brw_reg src1,              \
 200               struct brw_reg src2);
 201
 202 #define ROUND(OP) \
 203 void brw_##OP(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0);
 204
 205 ALU1(MOV)
 206 ALU2(SEL)
 207 ALU1(NOT)
 208 ALU2(AND)
 209 ALU2(OR)
 210 ALU2(XOR)
 211 ALU2(SHR)
 212 ALU2(SHL)
 213 ALU1(DIM)
 214 ALU2(ASR)
 215 ALU2(ROL)
 216 ALU2(ROR)
 217 ALU3(CSEL)
 218 ALU1(F32TO16)
 219 ALU1(F16TO32)
 220 ALU2(ADD)
 221 ALU2(AVG)
 222 ALU2(MUL)
 223 ALU1(FRC)
 224 ALU1(RNDD)
 225 ALU2(MAC)
 226 ALU2(MACH)
 227 ALU1(LZD)
 228 ALU2(DP4)
 229 ALU2(DPH)
 230 ALU2(DP3)
 231 ALU2(DP2)
 232 ALU2(LINE)
 233 ALU2(PLN)
 234 ALU3(MAD)
 235 ALU3(LRP)
 236 ALU1(BFREV)
 237 ALU3(BFE)
 238 ALU2(BFI1)
 239 ALU3(BFI2)
 240 ALU1(FBH)
 241 ALU1(FBL)
 242 ALU1(CBIT)
 243 ALU2(ADDC)
 244 ALU2(SUBB)
 245 ALU2(MAC)
 246
 247 ROUND(RNDZ)
 248 ROUND(RNDE)
 249
 250 #undef ALU1
 251 #undef ALU2
 252 #undef ALU3
 253 #undef ROUND
 254
 255
 256 /* Helpers for SEND instruction:
 257  */
 258
 259 /**
 260  * Construct a message descriptor immediate with the specified common
 261  * descriptor controls.
 262  */
 263 static inline uint32_t
 264 brw_message_desc(const struct gen_device_info *devinfo,
 265                  unsigned msg_length,
 266                  unsigned response_length,
 267                  bool header_present)
 268 {
 269    if (devinfo->gen >= 5) {
 270       return (SET_BITS(msg_length, 28, 25) |
 271               SET_BITS(response_length, 24, 20) |
 272               SET_BITS(header_present, 19, 19));
 273    } else {
 274       return (SET_BITS(msg_length, 23, 20) |
 275               SET_BITS(response_length, 19, 16));
 276    }
 277 }
 278
 279 static inline unsigned
 280 brw_message_desc_mlen(const struct gen_device_info *devinfo, uint32_t desc)
 281 {
 282    if (devinfo->gen >= 5)
 283       return GET_BITS(desc, 28, 25);
 284    else
 285       return GET_BITS(desc, 23, 20);
 286 }
 287
 288 static inline unsigned
 289 brw_message_desc_rlen(const struct gen_device_info *devinfo, uint32_t desc)
 290 {
 291    if (devinfo->gen >= 5)
 292       return GET_BITS(desc, 24, 20);
 293    else
 294       return GET_BITS(desc, 19, 16);
 295 }
 296
 297 static inline bool
 298 brw_message_desc_header_present(ASSERTED const struct gen_device_info *devinfo,
 299                                 uint32_t desc)
 300 {
 301    assert(devinfo->gen >= 5);
 302    return GET_BITS(desc, 19, 19);
 303 }
 304
 305 static inline unsigned
 306 brw_message_ex_desc(UNUSED const struct gen_device_info *devinfo,
 307                     unsigned ex_msg_length)
 308 {
 309    return SET_BITS(ex_msg_length, 9, 6);
 310 }
 311
 312 static inline unsigned
 313 brw_message_ex_desc_ex_mlen(UNUSED const struct gen_device_info *devinfo,
 314                             uint32_t ex_desc)
 315 {
 316    return GET_BITS(ex_desc, 9, 6);
 317 }
 318
 319 /**
 320  * Construct a message descriptor immediate with the specified sampler
 321  * function controls.
 322  */
 323 static inline uint32_t
 324 brw_sampler_desc(const struct gen_device_info *devinfo,
 325                  unsigned binding_table_index,
 326                  unsigned sampler,
 327                  unsigned msg_type,
 328                  unsigned simd_mode,
 329                  unsigned return_format)
 330 {
 331    const unsigned desc = (SET_BITS(binding_table_index, 7, 0) |
 332                           SET_BITS(sampler, 11, 8));
 333    if (devinfo->gen >= 7)
 334       return (desc | SET_BITS(msg_type, 16, 12) |
 335               SET_BITS(simd_mode, 18, 17));
 336    else if (devinfo->gen >= 5)
 337       return (desc | SET_BITS(msg_type, 15, 12) |
 338               SET_BITS(simd_mode, 17, 16));
 339    else if (devinfo->is_g4x)
 340       return desc | SET_BITS(msg_type, 15, 12);
 341    else
 342       return (desc | SET_BITS(return_format, 13, 12) |
 343               SET_BITS(msg_type, 15, 14));
 344 }
 345
 346 static inline unsigned
 347 brw_sampler_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
 348                                      uint32_t desc)
 349 {
 350    return GET_BITS(desc, 7, 0);
 351 }
 352
 353 static inline unsigned
 354 brw_sampler_desc_sampler(UNUSED const struct gen_device_info *devinfo, uint32_t desc)
 355 {
 356    return GET_BITS(desc, 11, 8);
 357 }
 358
 359 static inline unsigned
 360 brw_sampler_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
 361 {
 362    if (devinfo->gen >= 7)
 363       return GET_BITS(desc, 16, 12);
 364    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 365       return GET_BITS(desc, 15, 12);
 366    else
 367       return GET_BITS(desc, 15, 14);
 368 }
 369
 370 static inline unsigned
 371 brw_sampler_desc_simd_mode(const struct gen_device_info *devinfo, uint32_t desc)
 372 {
 373    assert(devinfo->gen >= 5);
 374    if (devinfo->gen >= 7)
 375       return GET_BITS(desc, 18, 17);
 376    else
 377       return GET_BITS(desc, 17, 16);
 378 }
 379
 380 static  inline unsigned
 381 brw_sampler_desc_return_format(ASSERTED const struct gen_device_info *devinfo,
 382                                uint32_t desc)
 383 {
 384    assert(devinfo->gen == 4 && !devinfo->is_g4x);
 385    return GET_BITS(desc, 13, 12);
 386 }
 387
 388 /**
 389  * Construct a message descriptor for the dataport
 390  */
 391 static inline uint32_t
 392 brw_dp_desc(const struct gen_device_info *devinfo,
 393             unsigned binding_table_index,
 394             unsigned msg_type,
 395             unsigned msg_control)
 396 {
 397    /* Prior to gen6, things are too inconsistent; use the dp_read/write_desc
 398     * helpers instead.
 399     */
 400    assert(devinfo->gen >= 6);
 401    const unsigned desc = SET_BITS(binding_table_index, 7, 0);
 402    if (devinfo->gen >= 8) {
 403       return (desc | SET_BITS(msg_control, 13, 8) |
 404               SET_BITS(msg_type, 18, 14));
 405    } else if (devinfo->gen >= 7) {
 406       return (desc | SET_BITS(msg_control, 13, 8) |
 407               SET_BITS(msg_type, 17, 14));
 408    } else {
 409       return (desc | SET_BITS(msg_control, 12, 8) |
 410               SET_BITS(msg_type, 16, 13));
 411    }
 412 }
 413
 414 static inline unsigned
 415 brw_dp_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
 416                                 uint32_t desc)
 417 {
 418    return GET_BITS(desc, 7, 0);
 419 }
 420
 421 static inline unsigned
 422 brw_dp_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
 423 {
 424    assert(devinfo->gen >= 6);
 425    if (devinfo->gen >= 8)
 426       return GET_BITS(desc, 18, 14);
 427    else if (devinfo->gen >= 7)
 428       return GET_BITS(desc, 17, 14);
 429    else
 430       return GET_BITS(desc, 16, 13);
 431 }
 432
 433 static inline unsigned
 434 brw_dp_desc_msg_control(const struct gen_device_info *devinfo, uint32_t desc)
 435 {
 436    assert(devinfo->gen >= 6);
 437    if (devinfo->gen >= 7)
 438       return GET_BITS(desc, 13, 8);
 439    else
 440       return GET_BITS(desc, 12, 8);
 441 }
 442
 443 /**
 444  * Construct a message descriptor immediate with the specified dataport read
 445  * function controls.
 446  */
 447 static inline uint32_t
 448 brw_dp_read_desc(const struct gen_device_info *devinfo,
 449                  unsigned binding_table_index,
 450                  unsigned msg_control,
 451                  unsigned msg_type,
 452                  unsigned target_cache)
 453 {
 454    if (devinfo->gen >= 6)
 455       return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control);
 456    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 457       return (SET_BITS(binding_table_index, 7, 0) |
 458               SET_BITS(msg_control, 10, 8) |
 459               SET_BITS(msg_type, 13, 11) |
 460               SET_BITS(target_cache, 15, 14));
 461    else
 462       return (SET_BITS(binding_table_index, 7, 0) |
 463               SET_BITS(msg_control, 11, 8) |
 464               SET_BITS(msg_type, 13, 12) |
 465               SET_BITS(target_cache, 15, 14));
 466 }
 467
 468 static inline unsigned
 469 brw_dp_read_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
 470 {
 471    if (devinfo->gen >= 6)
 472       return brw_dp_desc_msg_type(devinfo, desc);
 473    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 474       return GET_BITS(desc, 13, 11);
 475    else
 476       return GET_BITS(desc, 13, 12);
 477 }
 478
 479 static inline unsigned
 480 brw_dp_read_desc_msg_control(const struct gen_device_info *devinfo,
 481                              uint32_t desc)
 482 {
 483    if (devinfo->gen >= 6)
 484       return brw_dp_desc_msg_control(devinfo, desc);
 485    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 486       return GET_BITS(desc, 10, 8);
 487    else
 488       return GET_BITS(desc, 11, 8);
 489 }
 490
 491 /**
 492  * Construct a message descriptor immediate with the specified dataport write
 493  * function controls.
 494  */
 495 static inline uint32_t
 496 brw_dp_write_desc(const struct gen_device_info *devinfo,
 497                   unsigned binding_table_index,
 498                   unsigned msg_control,
 499                   unsigned msg_type,
 500                   unsigned last_render_target,
 501                   unsigned send_commit_msg)
 502 {
 503    assert(devinfo->gen <= 6 || !send_commit_msg);
 504    if (devinfo->gen >= 6)
 505       return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control) |
 506              SET_BITS(last_render_target, 12, 12) |
 507              SET_BITS(send_commit_msg, 17, 17);
 508    else
 509       return (SET_BITS(binding_table_index, 7, 0) |
 510               SET_BITS(msg_control, 11, 8) |
 511               SET_BITS(last_render_target, 11, 11) |
 512               SET_BITS(msg_type, 14, 12) |
 513               SET_BITS(send_commit_msg, 15, 15));
 514 }
 515
 516 static inline unsigned
 517 brw_dp_write_desc_msg_type(const struct gen_device_info *devinfo,
 518                            uint32_t desc)
 519 {
 520    if (devinfo->gen >= 6)
 521       return brw_dp_desc_msg_type(devinfo, desc);
 522    else
 523       return GET_BITS(desc, 14, 12);
 524 }
 525
 526 static inline unsigned
 527 brw_dp_write_desc_msg_control(const struct gen_device_info *devinfo,
 528                               uint32_t desc)
 529 {
 530    if (devinfo->gen >= 6)
 531       return brw_dp_desc_msg_control(devinfo, desc);
 532    else
 533       return GET_BITS(desc, 11, 8);
 534 }
 535
 536 static inline bool
 537 brw_dp_write_desc_last_render_target(const struct gen_device_info *devinfo,
 538                                      uint32_t desc)
 539 {
 540    if (devinfo->gen >= 6)
 541       return GET_BITS(desc, 12, 12);
 542    else
 543       return GET_BITS(desc, 11, 11);
 544 }
 545
 546 static inline bool
 547 brw_dp_write_desc_write_commit(const struct gen_device_info *devinfo,
 548                                uint32_t desc)
 549 {
 550    assert(devinfo->gen <= 6);
 551    if (devinfo->gen >= 6)
 552       return GET_BITS(desc, 17, 17);
 553    else
 554       return GET_BITS(desc, 15, 15);
 555 }
 556
 557 /**
 558  * Construct a message descriptor immediate with the specified dataport
 559  * surface function controls.
 560  */
 561 static inline uint32_t
 562 brw_dp_surface_desc(const struct gen_device_info *devinfo,
 563                     unsigned msg_type,
 564                     unsigned msg_control)
 565 {
 566    assert(devinfo->gen >= 7);
 567    /* We'll OR in the binding table index later */
 568    return brw_dp_desc(devinfo, 0, msg_type, msg_control);
 569 }
 570
 571 static inline uint32_t
 572 brw_dp_untyped_atomic_desc(const struct gen_device_info *devinfo,
 573                            unsigned exec_size, /**< 0 for SIMD4x2 */
 574                            unsigned atomic_op,
 575                            bool response_expected)
 576 {
 577    assert(exec_size <= 8 || exec_size == 16);
 578
 579    unsigned msg_type;
 580    if (devinfo->gen >= 8 || devinfo->is_haswell) {
 581       if (exec_size > 0) {
 582          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
 583       } else {
 584          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2;
 585       }
 586    } else {
 587       msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
 588    }
 589
 590    const unsigned msg_control =
 591       SET_BITS(atomic_op, 3, 0) |
 592       SET_BITS(0 < exec_size && exec_size <= 8, 4, 4) |
 593       SET_BITS(response_expected, 5, 5);
 594
 595    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 596 }
 597
 598 static inline uint32_t
 599 brw_dp_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
 600                                  unsigned exec_size,
 601                                  unsigned atomic_op,
 602                                  bool response_expected)
 603 {
 604    assert(exec_size <= 8 || exec_size == 16);
 605    assert(devinfo->gen >= 9);
 606
 607    assert(exec_size > 0);
 608    const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP;
 609
 610    const unsigned msg_control =
 611       SET_BITS(atomic_op, 1, 0) |
 612       SET_BITS(exec_size <= 8, 4, 4) |
 613       SET_BITS(response_expected, 5, 5);
 614
 615    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 616 }
 617
 618 static inline unsigned
 619 brw_mdc_cmask(unsigned num_channels)
 620 {
 621    /* See also MDC_CMASK in the SKL PRM Vol 2d. */
 622    return 0xf & (0xf << num_channels);
 623 }
 624
 625 static inline uint32_t
 626 brw_dp_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
 627                                unsigned exec_size, /**< 0 for SIMD4x2 */
 628                                unsigned num_channels,
 629                                bool write)
 630 {
 631    assert(exec_size <= 8 || exec_size == 16);
 632
 633    unsigned msg_type;
 634    if (write) {
 635       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 636          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE;
 637       } else {
 638          msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE;
 639       }
 640    } else {
 641       /* Read */
 642       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 643          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
 644       } else {
 645          msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ;
 646       }
 647    }
 648
 649    /* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
 650    if (write && devinfo->gen == 7 && !devinfo->is_haswell && exec_size == 0)
 651       exec_size = 8;
 652
 653    /* See also MDC_SM3 in the SKL PRM Vol 2d. */
 654    const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
 655                               exec_size <= 8 ? 2 : 1;
 656
 657    const unsigned msg_control =
 658       SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 659       SET_BITS(simd_mode, 5, 4);
 660
 661    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 662 }
 663
 664 static inline unsigned
 665 brw_mdc_ds(unsigned bit_size)
 666 {
 667    switch (bit_size) {
 668    case 8:
 669       return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE;
 670    case 16:
 671       return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD;
 672    case 32:
 673       return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD;
 674    default:
 675       unreachable("Unsupported bit_size for byte scattered messages");
 676    }
 677 }
 678
 679 static inline uint32_t
 680 brw_dp_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
 681                               unsigned exec_size,
 682                               unsigned bit_size,
 683                               bool write)
 684 {
 685    assert(exec_size <= 8 || exec_size == 16);
 686
 687    assert(devinfo->gen > 7 || devinfo->is_haswell);
 688    const unsigned msg_type =
 689       write ? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE :
 690               HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ;
 691
 692    assert(exec_size > 0);
 693    const unsigned msg_control =
 694       SET_BITS(exec_size == 16, 0, 0) |
 695       SET_BITS(brw_mdc_ds(bit_size), 3, 2);
 696
 697    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 698 }
 699
 700 static inline uint32_t
 701 brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
 702                                    unsigned exec_size, /**< 0 for SIMD4x2 */
 703                                    unsigned num_channels,
 704                                    bool write)
 705 {
 706    assert(exec_size <= 8 || exec_size == 16);
 707    assert(devinfo->gen >= 8);
 708
 709    unsigned msg_type =
 710       write ? GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE :
 711               GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ;
 712
 713    /* See also MDC_SM3 in the SKL PRM Vol 2d. */
 714    const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
 715                               exec_size <= 8 ? 2 : 1;
 716
 717    const unsigned msg_control =
 718       SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 719       SET_BITS(simd_mode, 5, 4);
 720
 721    return brw_dp_desc(devinfo, BRW_BTI_STATELESS, msg_type, msg_control);
 722 }
 723
 724 /**
 725  * Calculate the data size (see MDC_A64_DS in the "Structures" volume of the
 726  * Skylake PRM).
 727  */
 728 static inline uint32_t
 729 brw_mdc_a64_ds(unsigned elems)
 730 {
 731    switch (elems) {
 732    case 1:  return 0;
 733    case 2:  return 1;
 734    case 4:  return 2;
 735    case 8:  return 3;
 736    default:
 737       unreachable("Unsupported elmeent count for A64 scattered message");
 738    }
 739 }
 740
 741 static inline uint32_t
 742 brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
 743                                   unsigned exec_size, /**< 0 for SIMD4x2 */
 744                                   unsigned bit_size,
 745                                   bool write)
 746 {
 747    assert(exec_size <= 8 || exec_size == 16);
 748    assert(devinfo->gen >= 8);
 749
 750    unsigned msg_type =
 751       write ? GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE :
 752               GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ;
 753
 754    const unsigned msg_control =
 755       SET_BITS(GEN8_A64_SCATTERED_SUBTYPE_BYTE, 1, 0) |
 756       SET_BITS(brw_mdc_a64_ds(bit_size / 8), 3, 2) |
 757       SET_BITS(exec_size == 16, 4, 4);
 758
 759    return brw_dp_desc(devinfo, BRW_BTI_STATELESS, msg_type, msg_control);
 760 }
 761
 762 static inline uint32_t
 763 brw_dp_a64_untyped_atomic_desc(const struct gen_device_info *devinfo,
 764                                ASSERTED unsigned exec_size, /**< 0 for SIMD4x2 */
 765                                unsigned bit_size,
 766                                unsigned atomic_op,
 767                                bool response_expected)
 768 {
 769    assert(exec_size == 8);
 770    assert(devinfo->gen >= 8);
 771    assert(bit_size == 32 || bit_size == 64);
 772
 773    const unsigned msg_type = GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP;
 774
 775    const unsigned msg_control =
 776       SET_BITS(atomic_op, 3, 0) |
 777       SET_BITS(bit_size == 64, 4, 4) |
 778       SET_BITS(response_expected, 5, 5);
 779
 780    return brw_dp_desc(devinfo, BRW_BTI_STATELESS, msg_type, msg_control);
 781 }
 782
 783 static inline uint32_t
 784 brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
 785                                      ASSERTED unsigned exec_size,
 786                                      unsigned atomic_op,
 787                                      bool response_expected)
 788 {
 789    assert(exec_size == 8);
 790    assert(devinfo->gen >= 9);
 791
 792    assert(exec_size > 0);
 793    const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP;
 794
 795    const unsigned msg_control =
 796       SET_BITS(atomic_op, 1, 0) |
 797       SET_BITS(response_expected, 5, 5);
 798
 799    return brw_dp_desc(devinfo, BRW_BTI_STATELESS, msg_type, msg_control);
 800 }
 801
 802 static inline uint32_t
 803 brw_dp_typed_atomic_desc(const struct gen_device_info *devinfo,
 804                          unsigned exec_size,
 805                          unsigned exec_group,
 806                          unsigned atomic_op,
 807                          bool response_expected)
 808 {
 809    assert(exec_size > 0 || exec_group == 0);
 810    assert(exec_group % 8 == 0);
 811
 812    unsigned msg_type;
 813    if (devinfo->gen >= 8 || devinfo->is_haswell) {
 814       if (exec_size == 0) {
 815          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2;
 816       } else {
 817          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP;
 818       }
 819    } else {
 820       /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
 821       assert(exec_size > 0);
 822       msg_type = GEN7_DATAPORT_RC_TYPED_ATOMIC_OP;
 823    }
 824
 825    const bool high_sample_mask = (exec_group / 8) % 2 == 1;
 826
 827    const unsigned msg_control =
 828       SET_BITS(atomic_op, 3, 0) |
 829       SET_BITS(high_sample_mask, 4, 4) |
 830       SET_BITS(response_expected, 5, 5);
 831
 832    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 833 }
 834
 835 static inline uint32_t
 836 brw_dp_typed_surface_rw_desc(const struct gen_device_info *devinfo,
 837                              unsigned exec_size,
 838                              unsigned exec_group,
 839                              unsigned num_channels,
 840                              bool write)
 841 {
 842    assert(exec_size > 0 || exec_group == 0);
 843    assert(exec_group % 8 == 0);
 844
 845    /* Typed surface reads and writes don't support SIMD16 */
 846    assert(exec_size <= 8);
 847
 848    unsigned msg_type;
 849    if (write) {
 850       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 851          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE;
 852       } else {
 853          msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE;
 854       }
 855    } else {
 856       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 857          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ;
 858       } else {
 859          msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_READ;
 860       }
 861    }
 862
 863    /* See also MDC_SG3 in the SKL PRM Vol 2d. */
 864    unsigned msg_control;
 865    if (devinfo->gen >= 8 || devinfo->is_haswell) {
 866       /* See also MDC_SG3 in the SKL PRM Vol 2d. */
 867       const unsigned slot_group = exec_size == 0 ? 0 : /* SIMD4x2 */
 868                                   1 + ((exec_group / 8) % 2);
 869
 870       msg_control =
 871          SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 872          SET_BITS(slot_group, 5, 4);
 873    } else {
 874       /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
 875       assert(exec_size > 0);
 876       const unsigned slot_group = ((exec_group / 8) % 2);
 877
 878       msg_control =
 879          SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 880          SET_BITS(slot_group, 5, 5);
 881    }
 882
 883    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 884 }
 885
 886 /**
 887  * Construct a message descriptor immediate with the specified pixel
 888  * interpolator function controls.
 889  */
 890 static inline uint32_t
 891 brw_pixel_interp_desc(UNUSED const struct gen_device_info *devinfo,
 892                       unsigned msg_type,
 893                       bool noperspective,
 894                       unsigned simd_mode,
 895                       unsigned slot_group)
 896 {
 897    return (SET_BITS(slot_group, 11, 11) |
 898            SET_BITS(msg_type, 13, 12) |
 899            SET_BITS(!!noperspective, 14, 14) |
 900            SET_BITS(simd_mode, 16, 16));
 901 }
 902
 903 void brw_urb_WRITE(struct brw_codegen *p,
 904                    struct brw_reg dest,
 905                    unsigned msg_reg_nr,
 906                    struct brw_reg src0,
 907                    enum brw_urb_write_flags flags,
 908                    unsigned msg_length,
 909                    unsigned response_length,
 910                    unsigned offset,
 911                    unsigned swizzle);
 912
 913 /**
 914  * Send message to shared unit \p sfid with a possibly indirect descriptor \p
 915  * desc.  If \p desc is not an immediate it will be transparently loaded to an
 916  * address register using an OR instruction.
 917  */
 918 void
 919 brw_send_indirect_message(struct brw_codegen *p,
 920                           unsigned sfid,
 921                           struct brw_reg dst,
 922                           struct brw_reg payload,
 923                           struct brw_reg desc,
 924                           unsigned desc_imm,
 925                           bool eot);
 926
 927 void
 928 brw_send_indirect_split_message(struct brw_codegen *p,
 929                                 unsigned sfid,
 930                                 struct brw_reg dst,
 931                                 struct brw_reg payload0,
 932                                 struct brw_reg payload1,
 933                                 struct brw_reg desc,
 934                                 unsigned desc_imm,
 935                                 struct brw_reg ex_desc,
 936                                 unsigned ex_desc_imm,
 937                                 bool eot);
 938
 939 void brw_ff_sync(struct brw_codegen *p,
 940                    struct brw_reg dest,
 941                    unsigned msg_reg_nr,
 942                    struct brw_reg src0,
 943                    bool allocate,
 944                    unsigned response_length,
 945                    bool eot);
 946
 947 void brw_svb_write(struct brw_codegen *p,
 948                    struct brw_reg dest,
 949                    unsigned msg_reg_nr,
 950                    struct brw_reg src0,
 951                    unsigned binding_table_index,
 952                    bool   send_commit_msg);
 953
 954 brw_inst *brw_fb_WRITE(struct brw_codegen *p,
 955                        struct brw_reg payload,
 956                        struct brw_reg implied_header,
 957                        unsigned msg_control,
 958                        unsigned binding_table_index,
 959                        unsigned msg_length,
 960                        unsigned response_length,
 961                        bool eot,
 962                        bool last_render_target,
 963                        bool header_present);
 964
 965 brw_inst *gen9_fb_READ(struct brw_codegen *p,
 966                        struct brw_reg dst,
 967                        struct brw_reg payload,
 968                        unsigned binding_table_index,
 969                        unsigned msg_length,
 970                        unsigned response_length,
 971                        bool per_sample);
 972
 973 void brw_SAMPLE(struct brw_codegen *p,
 974                 struct brw_reg dest,
 975                 unsigned msg_reg_nr,
 976                 struct brw_reg src0,
 977                 unsigned binding_table_index,
 978                 unsigned sampler,
 979                 unsigned msg_type,
 980                 unsigned response_length,
 981                 unsigned msg_length,
 982                 unsigned header_present,
 983                 unsigned simd_mode,
 984                 unsigned return_format);
 985
 986 void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
 987                                       struct brw_reg header,
 988                                       struct brw_reg sampler_index);
 989
 990 void gen4_math(struct brw_codegen *p,
 991                struct brw_reg dest,
 992                unsigned function,
 993                unsigned msg_reg_nr,
 994                struct brw_reg src,
 995                unsigned precision );
 996
 997 void gen6_math(struct brw_codegen *p,
 998                struct brw_reg dest,
 999                unsigned function,
1000                struct brw_reg src0,
1001                struct brw_reg src1);
1002
1003 void brw_oword_block_read(struct brw_codegen *p,
1004                           struct brw_reg dest,
1005                           struct brw_reg mrf,
1006                           uint32_t offset,
1007                           uint32_t bind_table_index);
1008
1009 unsigned brw_scratch_surface_idx(const struct brw_codegen *p);
1010
1011 void brw_oword_block_read_scratch(struct brw_codegen *p,
1012                                   struct brw_reg dest,
1013                                   struct brw_reg mrf,
1014                                   int num_regs,
1015                                   unsigned offset);
1016
1017 void brw_oword_block_write_scratch(struct brw_codegen *p,
1018                                    struct brw_reg mrf,
1019                                    int num_regs,
1020                                    unsigned offset);
1021
1022 void gen7_block_read_scratch(struct brw_codegen *p,
1023                              struct brw_reg dest,
1024                              int num_regs,
1025                              unsigned offset);
1026
1027 void brw_shader_time_add(struct brw_codegen *p,
1028                          struct brw_reg payload,
1029                          uint32_t surf_index);
1030
1031 /**
1032  * Return the generation-specific jump distance scaling factor.
1033  *
1034  * Given the number of instructions to jump, we need to scale by
1035  * some number to obtain the actual jump distance to program in an
1036  * instruction.
1037  */
1038 static inline unsigned
1039 brw_jump_scale(const struct gen_device_info *devinfo)
1040 {
1041    /* Broadwell measures jump targets in bytes. */
1042    if (devinfo->gen >= 8)
1043       return 16;
1044
1045    /* Ironlake and later measure jump targets in 64-bit data chunks (in order
1046     * (to support compaction), so each 128-bit instruction requires 2 chunks.
1047     */
1048    if (devinfo->gen >= 5)
1049       return 2;
1050
1051    /* Gen4 simply uses the number of 128-bit instructions. */
1052    return 1;
1053 }
1054
1055 void brw_barrier(struct brw_codegen *p, struct brw_reg src);
1056
1057 /* If/else/endif.  Works by manipulating the execution flags on each
1058  * channel.
1059  */
1060 brw_inst *brw_IF(struct brw_codegen *p, unsigned execute_size);
1061 brw_inst *gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional,
1062                   struct brw_reg src0, struct brw_reg src1);
1063
1064 void brw_ELSE(struct brw_codegen *p);
1065 void brw_ENDIF(struct brw_codegen *p);
1066
1067 /* DO/WHILE loops:
1068  */
1069 brw_inst *brw_DO(struct brw_codegen *p, unsigned execute_size);
1070
1071 brw_inst *brw_WHILE(struct brw_codegen *p);
1072
1073 brw_inst *brw_BREAK(struct brw_codegen *p);
1074 brw_inst *brw_CONT(struct brw_codegen *p);
1075 brw_inst *gen6_HALT(struct brw_codegen *p);
1076
1077 /* Forward jumps:
1078  */
1079 void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx);
1080
1081 brw_inst *brw_JMPI(struct brw_codegen *p, struct brw_reg index,
1082                    unsigned predicate_control);
1083
1084 void brw_NOP(struct brw_codegen *p);
1085
1086 void brw_WAIT(struct brw_codegen *p);
1087
1088 void brw_SYNC(struct brw_codegen *p, enum tgl_sync_function func);
1089
1090 /* Special case: there is never a destination, execution size will be
1091  * taken from src0:
1092  */
1093 void brw_CMP(struct brw_codegen *p,
1094              struct brw_reg dest,
1095              unsigned conditional,
1096              struct brw_reg src0,
1097              struct brw_reg src1);
1098
1099 void
1100 brw_untyped_atomic(struct brw_codegen *p,
1101                    struct brw_reg dst,
1102                    struct brw_reg payload,
1103                    struct brw_reg surface,
1104                    unsigned atomic_op,
1105                    unsigned msg_length,
1106                    bool response_expected,
1107                    bool header_present);
1108
1109 void
1110 brw_untyped_surface_read(struct brw_codegen *p,
1111                          struct brw_reg dst,
1112                          struct brw_reg payload,
1113                          struct brw_reg surface,
1114                          unsigned msg_length,
1115                          unsigned num_channels);
1116
1117 void
1118 brw_untyped_surface_write(struct brw_codegen *p,
1119                           struct brw_reg payload,
1120                           struct brw_reg surface,
1121                           unsigned msg_length,
1122                           unsigned num_channels,
1123                           bool header_present);
1124
1125 void
1126 brw_memory_fence(struct brw_codegen *p,
1127                  struct brw_reg dst,
1128                  struct brw_reg src,
1129                  enum opcode send_op,
1130                  bool stall,
1131                  unsigned bti);
1132
1133 void
1134 brw_pixel_interpolator_query(struct brw_codegen *p,
1135                              struct brw_reg dest,
1136                              struct brw_reg mrf,
1137                              bool noperspective,
1138                              unsigned mode,
1139                              struct brw_reg data,
1140                              unsigned msg_length,
1141                              unsigned response_length);
1142
1143 void
1144 brw_find_live_channel(struct brw_codegen *p,
1145                       struct brw_reg dst,
1146                       struct brw_reg mask);
1147
1148 void
1149 brw_broadcast(struct brw_codegen *p,
1150               struct brw_reg dst,
1151               struct brw_reg src,
1152               struct brw_reg idx);
1153
1154 void
1155 brw_float_controls_mode(struct brw_codegen *p,
1156                         unsigned mode, unsigned mask);
1157
1158 /***********************************************************************
1159  * brw_eu_util.c:
1160  */
1161
1162 void brw_copy_indirect_to_indirect(struct brw_codegen *p,
1163                                    struct brw_indirect dst_ptr,
1164                                    struct brw_indirect src_ptr,
1165                                    unsigned count);
1166
1167 void brw_copy_from_indirect(struct brw_codegen *p,
1168                             struct brw_reg dst,
1169                             struct brw_indirect ptr,
1170                             unsigned count);
1171
1172 void brw_copy4(struct brw_codegen *p,
1173                struct brw_reg dst,
1174                struct brw_reg src,
1175                unsigned count);
1176
1177 void brw_copy8(struct brw_codegen *p,
1178                struct brw_reg dst,
1179                struct brw_reg src,
1180                unsigned count);
1181
1182 void brw_math_invert( struct brw_codegen *p,
1183                       struct brw_reg dst,
1184                       struct brw_reg src);
1185
1186 void brw_set_src1(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
1187
1188 void brw_set_desc_ex(struct brw_codegen *p, brw_inst *insn,
1189                      unsigned desc, unsigned ex_desc);
1190
1191 static inline void
1192 brw_set_desc(struct brw_codegen *p, brw_inst *insn, unsigned desc)
1193 {
1194    brw_set_desc_ex(p, insn, desc, 0);
1195 }
1196
1197 void brw_set_uip_jip(struct brw_codegen *p, int start_offset);
1198
1199 enum brw_conditional_mod brw_negate_cmod(enum brw_conditional_mod cmod);
1200 enum brw_conditional_mod brw_swap_cmod(enum brw_conditional_mod cmod);
1201
1202 /* brw_eu_compact.c */
1203 void brw_init_compaction_tables(const struct gen_device_info *devinfo);
1204 void brw_compact_instructions(struct brw_codegen *p, int start_offset,
1205                               struct disasm_info *disasm);
1206 void brw_uncompact_instruction(const struct gen_device_info *devinfo,
1207                                brw_inst *dst, brw_compact_inst *src);
1208 bool brw_try_compact_instruction(const struct gen_device_info *devinfo,
1209                                  brw_compact_inst *dst, const brw_inst *src);
1210
1211 void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
1212                                  brw_inst *orig, brw_inst *uncompacted);
1213
1214 /* brw_eu_validate.c */
1215 bool brw_validate_instructions(const struct gen_device_info *devinfo,
1216                                const void *assembly, int start_offset, int end_offset,
1217                                struct disasm_info *disasm);
1218
1219 static inline int
1220 next_offset(const struct gen_device_info *devinfo, void *store, int offset)
1221 {
1222    brw_inst *insn = (brw_inst *)((char *)store + offset);
1223
1224    if (brw_inst_cmpt_control(devinfo, insn))
1225       return offset + 8;
1226    else
1227       return offset + 16;
1228 }
1229
1230 struct opcode_desc {
1231    unsigned ir;
1232    unsigned hw;
1233    const char *name;
1234    int nsrc;
1235    int ndst;
1236    int gens;
1237 };
1238
1239 const struct opcode_desc *
1240 brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode);
1241
1242 const struct opcode_desc *
1243 brw_opcode_desc_from_hw(const struct gen_device_info *devinfo, unsigned hw);
1244
1245 static inline unsigned
1246 brw_opcode_encode(const struct gen_device_info *devinfo, enum opcode opcode)
1247 {
1248    return brw_opcode_desc(devinfo, opcode)->hw;
1249 }
1250
1251 static inline enum opcode
1252 brw_opcode_decode(const struct gen_device_info *devinfo, unsigned hw)
1253 {
1254    const struct opcode_desc *desc = brw_opcode_desc_from_hw(devinfo, hw);
1255    return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
1256 }
1257
1258 static inline void
1259 brw_inst_set_opcode(const struct gen_device_info *devinfo,
1260                     brw_inst *inst, enum opcode opcode)
1261 {
1262    brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
1263 }
1264
1265 static inline enum opcode
1266 brw_inst_opcode(const struct gen_device_info *devinfo, const brw_inst *inst)
1267 {
1268    return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
1269 }
1270
1271 static inline bool
1272 is_3src(const struct gen_device_info *devinfo, enum opcode opcode)
1273 {
1274    const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
1275    return desc && desc->nsrc == 3;
1276 }
1277
1278 /** Maximum SEND message length */
1279 #define BRW_MAX_MSG_LENGTH 15
1280
1281 /** First MRF register used by pull loads */
1282 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
1283
1284 /** First MRF register used by spills */
1285 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
1286
1287 #ifdef __cplusplus
1288 }
1289 #endif
1290
1291 #endif