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[mesa.git] / src / intel / compiler / brw_eu_defines.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32 #ifndef BRW_EU_DEFINES_H
33 #define BRW_EU_DEFINES_H
34
35 #include <stdint.h>
36 #include "util/macros.h"
37
38 /* The following hunk, up-to "Execution Unit" is used by both the
39 * intel/compiler and i965 codebase. */
40
41 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
42 /* Using the GNU statement expression extension */
43 #define SET_FIELD(value, field) \
44 ({ \
45 uint32_t fieldval = (uint32_t)(value) << field ## _SHIFT; \
46 assert((fieldval & ~ field ## _MASK) == 0); \
47 fieldval & field ## _MASK; \
48 })
49
50 #define SET_BITS(value, high, low) \
51 ({ \
52 const uint32_t fieldval = (uint32_t)(value) << (low); \
53 assert((fieldval & ~INTEL_MASK(high, low)) == 0); \
54 fieldval & INTEL_MASK(high, low); \
55 })
56
57 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
58 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
59
60 #define _3DPRIM_POINTLIST 0x01
61 #define _3DPRIM_LINELIST 0x02
62 #define _3DPRIM_LINESTRIP 0x03
63 #define _3DPRIM_TRILIST 0x04
64 #define _3DPRIM_TRISTRIP 0x05
65 #define _3DPRIM_TRIFAN 0x06
66 #define _3DPRIM_QUADLIST 0x07
67 #define _3DPRIM_QUADSTRIP 0x08
68 #define _3DPRIM_LINELIST_ADJ 0x09 /* G45+ */
69 #define _3DPRIM_LINESTRIP_ADJ 0x0A /* G45+ */
70 #define _3DPRIM_TRILIST_ADJ 0x0B /* G45+ */
71 #define _3DPRIM_TRISTRIP_ADJ 0x0C /* G45+ */
72 #define _3DPRIM_TRISTRIP_REVERSE 0x0D
73 #define _3DPRIM_POLYGON 0x0E
74 #define _3DPRIM_RECTLIST 0x0F
75 #define _3DPRIM_LINELOOP 0x10
76 #define _3DPRIM_POINTLIST_BF 0x11
77 #define _3DPRIM_LINESTRIP_CONT 0x12
78 #define _3DPRIM_LINESTRIP_BF 0x13
79 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
80 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x16
81 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
82
83 /* Bitfields for the URB_WRITE message, DW2 of message header: */
84 #define URB_WRITE_PRIM_END 0x1
85 #define URB_WRITE_PRIM_START 0x2
86 #define URB_WRITE_PRIM_TYPE_SHIFT 2
87
88 #define BRW_SPRITE_POINT_ENABLE 16
89
90 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
91 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
92
93 /* Execution Unit (EU) defines
94 */
95
96 #define BRW_ALIGN_1 0
97 #define BRW_ALIGN_16 1
98
99 #define BRW_ADDRESS_DIRECT 0
100 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
101
102 #define BRW_CHANNEL_X 0
103 #define BRW_CHANNEL_Y 1
104 #define BRW_CHANNEL_Z 2
105 #define BRW_CHANNEL_W 3
106
107 enum brw_compression {
108 BRW_COMPRESSION_NONE = 0,
109 BRW_COMPRESSION_2NDHALF = 1,
110 BRW_COMPRESSION_COMPRESSED = 2,
111 };
112
113 #define GEN6_COMPRESSION_1Q 0
114 #define GEN6_COMPRESSION_2Q 1
115 #define GEN6_COMPRESSION_3Q 2
116 #define GEN6_COMPRESSION_4Q 3
117 #define GEN6_COMPRESSION_1H 0
118 #define GEN6_COMPRESSION_2H 2
119
120 enum PACKED brw_conditional_mod {
121 BRW_CONDITIONAL_NONE = 0,
122 BRW_CONDITIONAL_Z = 1,
123 BRW_CONDITIONAL_NZ = 2,
124 BRW_CONDITIONAL_EQ = 1, /* Z */
125 BRW_CONDITIONAL_NEQ = 2, /* NZ */
126 BRW_CONDITIONAL_G = 3,
127 BRW_CONDITIONAL_GE = 4,
128 BRW_CONDITIONAL_L = 5,
129 BRW_CONDITIONAL_LE = 6,
130 BRW_CONDITIONAL_R = 7, /* Gen <= 5 */
131 BRW_CONDITIONAL_O = 8,
132 BRW_CONDITIONAL_U = 9,
133 };
134
135 #define BRW_DEBUG_NONE 0
136 #define BRW_DEBUG_BREAKPOINT 1
137
138 #define BRW_DEPENDENCY_NORMAL 0
139 #define BRW_DEPENDENCY_NOTCLEARED 1
140 #define BRW_DEPENDENCY_NOTCHECKED 2
141 #define BRW_DEPENDENCY_DISABLE 3
142
143 enum PACKED brw_execution_size {
144 BRW_EXECUTE_1 = 0,
145 BRW_EXECUTE_2 = 1,
146 BRW_EXECUTE_4 = 2,
147 BRW_EXECUTE_8 = 3,
148 BRW_EXECUTE_16 = 4,
149 BRW_EXECUTE_32 = 5,
150 };
151
152 enum PACKED brw_horizontal_stride {
153 BRW_HORIZONTAL_STRIDE_0 = 0,
154 BRW_HORIZONTAL_STRIDE_1 = 1,
155 BRW_HORIZONTAL_STRIDE_2 = 2,
156 BRW_HORIZONTAL_STRIDE_4 = 3,
157 };
158
159 enum PACKED gen10_align1_3src_src_horizontal_stride {
160 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
161 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
162 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
163 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
164 };
165
166 enum PACKED gen10_align1_3src_dst_horizontal_stride {
167 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
168 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
169 };
170
171 #define BRW_INSTRUCTION_NORMAL 0
172 #define BRW_INSTRUCTION_SATURATE 1
173
174 #define BRW_MASK_ENABLE 0
175 #define BRW_MASK_DISABLE 1
176
177 /** @{
178 *
179 * Gen6 has replaced "mask enable/disable" with WECtrl, which is
180 * effectively the same but much simpler to think about. Now, there
181 * are two contributors ANDed together to whether channels are
182 * executed: The predication on the instruction, and the channel write
183 * enable.
184 */
185 /**
186 * This is the default value. It means that a channel's write enable is set
187 * if the per-channel IP is pointing at this instruction.
188 */
189 #define BRW_WE_NORMAL 0
190 /**
191 * This is used like BRW_MASK_DISABLE, and causes all channels to have
192 * their write enable set. Note that predication still contributes to
193 * whether the channel actually gets written.
194 */
195 #define BRW_WE_ALL 1
196 /** @} */
197
198 enum opcode {
199 /* These are the actual hardware instructions. */
200 BRW_OPCODE_ILLEGAL,
201 BRW_OPCODE_SYNC,
202 BRW_OPCODE_MOV,
203 BRW_OPCODE_SEL,
204 BRW_OPCODE_MOVI, /**< G45+ */
205 BRW_OPCODE_NOT,
206 BRW_OPCODE_AND,
207 BRW_OPCODE_OR,
208 BRW_OPCODE_XOR,
209 BRW_OPCODE_SHR,
210 BRW_OPCODE_SHL,
211 BRW_OPCODE_DIM, /**< Gen7.5 only */
212 BRW_OPCODE_SMOV, /**< Gen8+ */
213 BRW_OPCODE_ASR,
214 BRW_OPCODE_ROR, /**< Gen11+ */
215 BRW_OPCODE_ROL, /**< Gen11+ */
216 BRW_OPCODE_CMP,
217 BRW_OPCODE_CMPN,
218 BRW_OPCODE_CSEL, /**< Gen8+ */
219 BRW_OPCODE_F32TO16, /**< Gen7 only */
220 BRW_OPCODE_F16TO32, /**< Gen7 only */
221 BRW_OPCODE_BFREV, /**< Gen7+ */
222 BRW_OPCODE_BFE, /**< Gen7+ */
223 BRW_OPCODE_BFI1, /**< Gen7+ */
224 BRW_OPCODE_BFI2, /**< Gen7+ */
225 BRW_OPCODE_JMPI,
226 BRW_OPCODE_BRD, /**< Gen7+ */
227 BRW_OPCODE_IF,
228 BRW_OPCODE_IFF, /**< Pre-Gen6 */
229 BRW_OPCODE_BRC, /**< Gen7+ */
230 BRW_OPCODE_ELSE,
231 BRW_OPCODE_ENDIF,
232 BRW_OPCODE_DO, /**< Pre-Gen6 */
233 BRW_OPCODE_CASE, /**< Gen6 only */
234 BRW_OPCODE_WHILE,
235 BRW_OPCODE_BREAK,
236 BRW_OPCODE_CONTINUE,
237 BRW_OPCODE_HALT,
238 BRW_OPCODE_CALLA, /**< Gen7.5+ */
239 BRW_OPCODE_MSAVE, /**< Pre-Gen6 */
240 BRW_OPCODE_CALL, /**< Gen6+ */
241 BRW_OPCODE_MREST, /**< Pre-Gen6 */
242 BRW_OPCODE_RET, /**< Gen6+ */
243 BRW_OPCODE_PUSH, /**< Pre-Gen6 */
244 BRW_OPCODE_FORK, /**< Gen6 only */
245 BRW_OPCODE_GOTO, /**< Gen8+ */
246 BRW_OPCODE_POP, /**< Pre-Gen6 */
247 BRW_OPCODE_WAIT,
248 BRW_OPCODE_SEND,
249 BRW_OPCODE_SENDC,
250 BRW_OPCODE_SENDS, /**< Gen9+ */
251 BRW_OPCODE_SENDSC, /**< Gen9+ */
252 BRW_OPCODE_MATH, /**< Gen6+ */
253 BRW_OPCODE_ADD,
254 BRW_OPCODE_MUL,
255 BRW_OPCODE_AVG,
256 BRW_OPCODE_FRC,
257 BRW_OPCODE_RNDU,
258 BRW_OPCODE_RNDD,
259 BRW_OPCODE_RNDE,
260 BRW_OPCODE_RNDZ,
261 BRW_OPCODE_MAC,
262 BRW_OPCODE_MACH,
263 BRW_OPCODE_LZD,
264 BRW_OPCODE_FBH, /**< Gen7+ */
265 BRW_OPCODE_FBL, /**< Gen7+ */
266 BRW_OPCODE_CBIT, /**< Gen7+ */
267 BRW_OPCODE_ADDC, /**< Gen7+ */
268 BRW_OPCODE_SUBB, /**< Gen7+ */
269 BRW_OPCODE_SAD2,
270 BRW_OPCODE_SADA2,
271 BRW_OPCODE_DP4,
272 BRW_OPCODE_DPH,
273 BRW_OPCODE_DP3,
274 BRW_OPCODE_DP2,
275 BRW_OPCODE_LINE,
276 BRW_OPCODE_PLN, /**< G45+ */
277 BRW_OPCODE_MAD, /**< Gen6+ */
278 BRW_OPCODE_LRP, /**< Gen6+ */
279 BRW_OPCODE_MADM, /**< Gen8+ */
280 BRW_OPCODE_NENOP, /**< G45 only */
281 BRW_OPCODE_NOP,
282
283 NUM_BRW_OPCODES,
284
285 /* These are compiler backend opcodes that get translated into other
286 * instructions.
287 */
288 FS_OPCODE_FB_WRITE = NUM_BRW_OPCODES,
289
290 /**
291 * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
292 * individual sources instead of as a single payload blob. The
293 * position/ordering of the arguments are defined by the enum
294 * fb_write_logical_srcs.
295 */
296 FS_OPCODE_FB_WRITE_LOGICAL,
297
298 FS_OPCODE_REP_FB_WRITE,
299
300 FS_OPCODE_FB_READ,
301 FS_OPCODE_FB_READ_LOGICAL,
302
303 SHADER_OPCODE_RCP,
304 SHADER_OPCODE_RSQ,
305 SHADER_OPCODE_SQRT,
306 SHADER_OPCODE_EXP2,
307 SHADER_OPCODE_LOG2,
308 SHADER_OPCODE_POW,
309 SHADER_OPCODE_INT_QUOTIENT,
310 SHADER_OPCODE_INT_REMAINDER,
311 SHADER_OPCODE_SIN,
312 SHADER_OPCODE_COS,
313
314 /**
315 * A generic "send" opcode. The first two sources are the message
316 * descriptor and extended message descriptor respectively. The third
317 * and optional fourth sources are the message payload
318 */
319 SHADER_OPCODE_SEND,
320
321 /**
322 * An "undefined" write which does nothing but indicates to liveness that
323 * we don't care about any values in the register which predate this
324 * instruction. Used to prevent partial writes from causing issues with
325 * live ranges.
326 */
327 SHADER_OPCODE_UNDEF,
328
329 /**
330 * Texture sampling opcodes.
331 *
332 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
333 * opcode but instead of taking a single payload blob they expect their
334 * arguments separately as individual sources. The position/ordering of the
335 * arguments are defined by the enum tex_logical_srcs.
336 */
337 SHADER_OPCODE_TEX,
338 SHADER_OPCODE_TEX_LOGICAL,
339 SHADER_OPCODE_TXD,
340 SHADER_OPCODE_TXD_LOGICAL,
341 SHADER_OPCODE_TXF,
342 SHADER_OPCODE_TXF_LOGICAL,
343 SHADER_OPCODE_TXF_LZ,
344 SHADER_OPCODE_TXL,
345 SHADER_OPCODE_TXL_LOGICAL,
346 SHADER_OPCODE_TXL_LZ,
347 SHADER_OPCODE_TXS,
348 SHADER_OPCODE_TXS_LOGICAL,
349 FS_OPCODE_TXB,
350 FS_OPCODE_TXB_LOGICAL,
351 SHADER_OPCODE_TXF_CMS,
352 SHADER_OPCODE_TXF_CMS_LOGICAL,
353 SHADER_OPCODE_TXF_CMS_W,
354 SHADER_OPCODE_TXF_CMS_W_LOGICAL,
355 SHADER_OPCODE_TXF_UMS,
356 SHADER_OPCODE_TXF_UMS_LOGICAL,
357 SHADER_OPCODE_TXF_MCS,
358 SHADER_OPCODE_TXF_MCS_LOGICAL,
359 SHADER_OPCODE_LOD,
360 SHADER_OPCODE_LOD_LOGICAL,
361 SHADER_OPCODE_TG4,
362 SHADER_OPCODE_TG4_LOGICAL,
363 SHADER_OPCODE_TG4_OFFSET,
364 SHADER_OPCODE_TG4_OFFSET_LOGICAL,
365 SHADER_OPCODE_SAMPLEINFO,
366 SHADER_OPCODE_SAMPLEINFO_LOGICAL,
367
368 SHADER_OPCODE_IMAGE_SIZE_LOGICAL,
369
370 /**
371 * Combines multiple sources of size 1 into a larger virtual GRF.
372 * For example, parameters for a send-from-GRF message. Or, updating
373 * channels of a size 4 VGRF used to store vec4s such as texturing results.
374 *
375 * This will be lowered into MOVs from each source to consecutive offsets
376 * of the destination VGRF.
377 *
378 * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV,
379 * but still reserves the first channel of the destination VGRF. This can be
380 * used to reserve space for, say, a message header set up by the generators.
381 */
382 SHADER_OPCODE_LOAD_PAYLOAD,
383
384 /**
385 * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
386 * acts intra-channel, obtaining the final value for each channel by
387 * combining the sources values for the same channel, the first source
388 * occupying the lowest bits and the last source occupying the highest
389 * bits.
390 */
391 FS_OPCODE_PACK,
392
393 SHADER_OPCODE_SHADER_TIME_ADD,
394
395 /**
396 * Typed and untyped surface access opcodes.
397 *
398 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
399 * opcode but instead of taking a single payload blob they expect their
400 * arguments separately as individual sources:
401 *
402 * Source 0: [required] Surface coordinates.
403 * Source 1: [optional] Operation source.
404 * Source 2: [required] Surface index.
405 * Source 3: [required] Number of coordinate components (as UD immediate).
406 * Source 4: [required] Opcode-specific control immediate, same as source 2
407 * of the matching non-LOGICAL opcode.
408 */
409 VEC4_OPCODE_UNTYPED_ATOMIC,
410 SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
411 SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
412 VEC4_OPCODE_UNTYPED_SURFACE_READ,
413 SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
414 VEC4_OPCODE_UNTYPED_SURFACE_WRITE,
415 SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
416
417 /**
418 * Untyped A64 surface access opcodes.
419 *
420 * Source 0: 64-bit address
421 * Source 1: Operational source
422 * Source 2: [required] Opcode-specific control immediate, same as source 2
423 * of the matching non-LOGICAL opcode.
424 */
425 SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL,
426 SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL,
427 SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL,
428 SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL,
429 SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL,
430 SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL,
431 SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL,
432
433 SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
434 SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
435 SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
436
437 SHADER_OPCODE_RND_MODE,
438 SHADER_OPCODE_FLOAT_CONTROL_MODE,
439
440 /**
441 * Byte scattered write/read opcodes.
442 *
443 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
444 * opcode, but instead of taking a single payload blog they expect their
445 * arguments separately as individual sources, like untyped write/read.
446 */
447 SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
448 SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
449 SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL,
450 SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL,
451
452 /**
453 * Memory fence messages.
454 *
455 * Source 0: Must be register g0, used as header.
456 * Source 1: Immediate bool to indicate whether or not we need to stall
457 * until memory transactions prior to the fence are completed.
458 * Source 2: Immediate byte indicating which memory to fence. Zero means
459 * global memory; GEN7_BTI_SLM means SLM (for Gen11+ only).
460 *
461 * Vec4 backend only uses Source 0.
462 */
463 SHADER_OPCODE_MEMORY_FENCE,
464
465 /**
466 * Scheduling-only fence.
467 */
468 FS_OPCODE_SCHEDULING_FENCE,
469
470 SHADER_OPCODE_GEN4_SCRATCH_READ,
471 SHADER_OPCODE_GEN4_SCRATCH_WRITE,
472 SHADER_OPCODE_GEN7_SCRATCH_READ,
473
474 /**
475 * Gen8+ SIMD8 URB Read messages.
476 */
477 SHADER_OPCODE_URB_READ_SIMD8,
478 SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
479
480 SHADER_OPCODE_URB_WRITE_SIMD8,
481 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
482 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
483 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
484
485 /**
486 * Return the index of an arbitrary live channel (i.e. one of the channels
487 * enabled in the current execution mask) and assign it to the first
488 * component of the destination. Expected to be used as input for the
489 * BROADCAST pseudo-opcode.
490 */
491 SHADER_OPCODE_FIND_LIVE_CHANNEL,
492
493 /**
494 * Return the current execution mask in the specified flag subregister.
495 * Can be CSE'ed more easily than a plain MOV from the ce0 ARF register.
496 */
497 FS_OPCODE_LOAD_LIVE_CHANNELS,
498
499 /**
500 * Pick the channel from its first source register given by the index
501 * specified as second source. Useful for variable indexing of surfaces.
502 *
503 * Note that because the result of this instruction is by definition
504 * uniform and it can always be splatted to multiple channels using a
505 * scalar regioning mode, only the first channel of the destination region
506 * is guaranteed to be updated, which implies that BROADCAST instructions
507 * should usually be marked force_writemask_all.
508 */
509 SHADER_OPCODE_BROADCAST,
510
511 /* Pick the channel from its first source register given by the index
512 * specified as second source.
513 *
514 * This is similar to the BROADCAST instruction except that it takes a
515 * dynamic index and potentially puts a different value in each output
516 * channel.
517 */
518 SHADER_OPCODE_SHUFFLE,
519
520 /* Select between src0 and src1 based on channel enables.
521 *
522 * This instruction copies src0 into the enabled channels of the
523 * destination and copies src1 into the disabled channels.
524 */
525 SHADER_OPCODE_SEL_EXEC,
526
527 /* This turns into an align16 mov from src0 to dst with a swizzle
528 * provided as an immediate in src1.
529 */
530 SHADER_OPCODE_QUAD_SWIZZLE,
531
532 /* Take every Nth element in src0 and broadcast it to the group of N
533 * channels in which it lives in the destination. The offset within the
534 * cluster is given by src1 and the cluster size is given by src2.
535 */
536 SHADER_OPCODE_CLUSTER_BROADCAST,
537
538 SHADER_OPCODE_GET_BUFFER_SIZE,
539
540 SHADER_OPCODE_INTERLOCK,
541
542 VEC4_OPCODE_MOV_BYTES,
543 VEC4_OPCODE_PACK_BYTES,
544 VEC4_OPCODE_UNPACK_UNIFORM,
545 VEC4_OPCODE_DOUBLE_TO_F32,
546 VEC4_OPCODE_DOUBLE_TO_D32,
547 VEC4_OPCODE_DOUBLE_TO_U32,
548 VEC4_OPCODE_TO_DOUBLE,
549 VEC4_OPCODE_PICK_LOW_32BIT,
550 VEC4_OPCODE_PICK_HIGH_32BIT,
551 VEC4_OPCODE_SET_LOW_32BIT,
552 VEC4_OPCODE_SET_HIGH_32BIT,
553
554 FS_OPCODE_DDX_COARSE,
555 FS_OPCODE_DDX_FINE,
556 /**
557 * Compute dFdy(), dFdyCoarse(), or dFdyFine().
558 */
559 FS_OPCODE_DDY_COARSE,
560 FS_OPCODE_DDY_FINE,
561 FS_OPCODE_LINTERP,
562 FS_OPCODE_PIXEL_X,
563 FS_OPCODE_PIXEL_Y,
564 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
565 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
566 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
567 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
568 FS_OPCODE_DISCARD_JUMP,
569 FS_OPCODE_SET_SAMPLE_ID,
570 FS_OPCODE_PACK_HALF_2x16_SPLIT,
571 FS_OPCODE_PLACEHOLDER_HALT,
572 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
573 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
574 FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
575
576 VS_OPCODE_URB_WRITE,
577 VS_OPCODE_PULL_CONSTANT_LOAD,
578 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
579 VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
580
581 VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
582
583 /**
584 * Write geometry shader output data to the URB.
585 *
586 * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
587 * R0 to the first MRF. This allows the geometry shader to override the
588 * "Slot {0,1} Offset" fields in the message header.
589 */
590 GS_OPCODE_URB_WRITE,
591
592 /**
593 * Write geometry shader output data to the URB and request a new URB
594 * handle (gen6).
595 *
596 * This opcode doesn't do an implied move from R0 to the first MRF.
597 */
598 GS_OPCODE_URB_WRITE_ALLOCATE,
599
600 /**
601 * Terminate the geometry shader thread by doing an empty URB write.
602 *
603 * This opcode doesn't do an implied move from R0 to the first MRF. This
604 * allows the geometry shader to override the "GS Number of Output Vertices
605 * for Slot {0,1}" fields in the message header.
606 */
607 GS_OPCODE_THREAD_END,
608
609 /**
610 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
611 *
612 * - dst is the MRF containing the message header.
613 *
614 * - src0.x indicates which portion of the URB should be written to (e.g. a
615 * vertex number)
616 *
617 * - src1 is an immediate multiplier which will be applied to src0
618 * (e.g. the size of a single vertex in the URB).
619 *
620 * Note: the hardware will apply this offset *in addition to* the offset in
621 * vec4_instruction::offset.
622 */
623 GS_OPCODE_SET_WRITE_OFFSET,
624
625 /**
626 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
627 * URB_WRITE message header.
628 *
629 * - dst is the MRF containing the message header.
630 *
631 * - src0.x is the vertex count. The upper 16 bits will be ignored.
632 */
633 GS_OPCODE_SET_VERTEX_COUNT,
634
635 /**
636 * Set DWORD 2 of dst to the value in src.
637 */
638 GS_OPCODE_SET_DWORD_2,
639
640 /**
641 * Prepare the dst register for storage in the "Channel Mask" fields of a
642 * URB_WRITE message header.
643 *
644 * DWORD 4 of dst is shifted left by 4 bits, so that later,
645 * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
646 * final channel mask.
647 *
648 * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
649 * form the final channel mask, DWORDs 0 and 4 of the dst register must not
650 * have any extraneous bits set prior to execution of this opcode (that is,
651 * they should be in the range 0x0 to 0xf).
652 */
653 GS_OPCODE_PREPARE_CHANNEL_MASKS,
654
655 /**
656 * Set the "Channel Mask" fields of a URB_WRITE message header.
657 *
658 * - dst is the MRF containing the message header.
659 *
660 * - src.x is the channel mask, as prepared by
661 * GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to
662 * form the final channel mask.
663 */
664 GS_OPCODE_SET_CHANNEL_MASKS,
665
666 /**
667 * Get the "Instance ID" fields from the payload.
668 *
669 * - dst is the GRF for gl_InvocationID.
670 */
671 GS_OPCODE_GET_INSTANCE_ID,
672
673 /**
674 * Send a FF_SYNC message to allocate initial URB handles (gen6).
675 *
676 * - dst will be used as the writeback register for the FF_SYNC operation.
677 *
678 * - src0 is the number of primitives written.
679 *
680 * - src1 is the value to hold in M0.0: number of SO vertices to write
681 * and number of SO primitives needed. Its value will be overwritten
682 * with the SVBI values if transform feedback is enabled.
683 *
684 * Note: This opcode uses an implicit MRF register for the ff_sync message
685 * header, so the caller is expected to set inst->base_mrf and initialize
686 * that MRF register to r0. This opcode will also write to this MRF register
687 * to include the allocated URB handle so it can then be reused directly as
688 * the header in the URB write operation we are allocating the handle for.
689 */
690 GS_OPCODE_FF_SYNC,
691
692 /**
693 * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
694 * register.
695 *
696 * - dst is the GRF where PrimitiveID information will be moved.
697 */
698 GS_OPCODE_SET_PRIMITIVE_ID,
699
700 /**
701 * Write transform feedback data to the SVB by sending a SVB WRITE message.
702 * Used in gen6.
703 *
704 * - dst is the MRF register containing the message header.
705 *
706 * - src0 is the register where the vertex data is going to be copied from.
707 *
708 * - src1 is the destination register when write commit occurs.
709 */
710 GS_OPCODE_SVB_WRITE,
711
712 /**
713 * Set destination index in the SVB write message payload (M0.5). Used
714 * in gen6 for transform feedback.
715 *
716 * - dst is the header to save the destination indices for SVB WRITE.
717 * - src is the register that holds the destination indices value.
718 */
719 GS_OPCODE_SVB_SET_DST_INDEX,
720
721 /**
722 * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
723 * Used in gen6 for transform feedback.
724 *
725 * - dst will hold the register with the final Mx.0 value.
726 *
727 * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
728 *
729 * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
730 *
731 * - src2 is the value to hold in M0: number of SO vertices to write
732 * and number of SO primitives needed.
733 */
734 GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
735
736 /**
737 * Terminate the compute shader.
738 */
739 CS_OPCODE_CS_TERMINATE,
740
741 /**
742 * GLSL barrier()
743 */
744 SHADER_OPCODE_BARRIER,
745
746 /**
747 * Calculate the high 32-bits of a 32x32 multiply.
748 */
749 SHADER_OPCODE_MULH,
750
751 /** Signed subtraction with saturation. */
752 SHADER_OPCODE_ISUB_SAT,
753
754 /** Unsigned subtraction with saturation. */
755 SHADER_OPCODE_USUB_SAT,
756
757 /**
758 * A MOV that uses VxH indirect addressing.
759 *
760 * Source 0: A register to start from (HW_REG).
761 * Source 1: An indirect offset (in bytes, UD GRF).
762 * Source 2: The length of the region that could be accessed (in bytes,
763 * UD immediate).
764 */
765 SHADER_OPCODE_MOV_INDIRECT,
766
767 VEC4_OPCODE_URB_READ,
768 TCS_OPCODE_GET_INSTANCE_ID,
769 TCS_OPCODE_URB_WRITE,
770 TCS_OPCODE_SET_INPUT_URB_OFFSETS,
771 TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
772 TCS_OPCODE_GET_PRIMITIVE_ID,
773 TCS_OPCODE_CREATE_BARRIER_HEADER,
774 TCS_OPCODE_SRC0_010_IS_ZERO,
775 TCS_OPCODE_RELEASE_INPUT,
776 TCS_OPCODE_THREAD_END,
777
778 TES_OPCODE_GET_PRIMITIVE_ID,
779 TES_OPCODE_CREATE_INPUT_READ_HEADER,
780 TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
781 };
782
783 enum brw_urb_write_flags {
784 BRW_URB_WRITE_NO_FLAGS = 0,
785
786 /**
787 * Causes a new URB entry to be allocated, and its address stored in the
788 * destination register (gen < 7).
789 */
790 BRW_URB_WRITE_ALLOCATE = 0x1,
791
792 /**
793 * Causes the current URB entry to be deallocated (gen < 7).
794 */
795 BRW_URB_WRITE_UNUSED = 0x2,
796
797 /**
798 * Causes the thread to terminate.
799 */
800 BRW_URB_WRITE_EOT = 0x4,
801
802 /**
803 * Indicates that the given URB entry is complete, and may be sent further
804 * down the 3D pipeline (gen < 7).
805 */
806 BRW_URB_WRITE_COMPLETE = 0x8,
807
808 /**
809 * Indicates that an additional offset (which may be different for the two
810 * vec4 slots) is stored in the message header (gen == 7).
811 */
812 BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
813
814 /**
815 * Indicates that the channel masks in the URB_WRITE message header should
816 * not be overridden to 0xff (gen == 7).
817 */
818 BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
819
820 /**
821 * Indicates that the data should be sent to the URB using the
822 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This
823 * causes offsets to be interpreted as multiples of an OWORD instead of an
824 * HWORD, and only allows one OWORD to be written.
825 */
826 BRW_URB_WRITE_OWORD = 0x40,
827
828 /**
829 * Convenient combination of flags: end the thread while simultaneously
830 * marking the given URB entry as complete.
831 */
832 BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
833
834 /**
835 * Convenient combination of flags: mark the given URB entry as complete
836 * and simultaneously allocate a new one.
837 */
838 BRW_URB_WRITE_ALLOCATE_COMPLETE =
839 BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
840 };
841
842 enum fb_write_logical_srcs {
843 FB_WRITE_LOGICAL_SRC_COLOR0, /* REQUIRED */
844 FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */
845 FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
846 FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */
847 FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GEN4-5: passthrough from thread */
848 FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
849 FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */
850 FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */
851 FB_WRITE_LOGICAL_NUM_SRCS
852 };
853
854 enum tex_logical_srcs {
855 /** Texture coordinates */
856 TEX_LOGICAL_SRC_COORDINATE,
857 /** Shadow comparator */
858 TEX_LOGICAL_SRC_SHADOW_C,
859 /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
860 TEX_LOGICAL_SRC_LOD,
861 /** dPdy if the operation takes explicit derivatives */
862 TEX_LOGICAL_SRC_LOD2,
863 /** Min LOD */
864 TEX_LOGICAL_SRC_MIN_LOD,
865 /** Sample index */
866 TEX_LOGICAL_SRC_SAMPLE_INDEX,
867 /** MCS data */
868 TEX_LOGICAL_SRC_MCS,
869 /** REQUIRED: Texture surface index */
870 TEX_LOGICAL_SRC_SURFACE,
871 /** Texture sampler index */
872 TEX_LOGICAL_SRC_SAMPLER,
873 /** Texture surface bindless handle */
874 TEX_LOGICAL_SRC_SURFACE_HANDLE,
875 /** Texture sampler bindless handle */
876 TEX_LOGICAL_SRC_SAMPLER_HANDLE,
877 /** Texel offset for gathers */
878 TEX_LOGICAL_SRC_TG4_OFFSET,
879 /** REQUIRED: Number of coordinate components (as UD immediate) */
880 TEX_LOGICAL_SRC_COORD_COMPONENTS,
881 /** REQUIRED: Number of derivative components (as UD immediate) */
882 TEX_LOGICAL_SRC_GRAD_COMPONENTS,
883
884 TEX_LOGICAL_NUM_SRCS,
885 };
886
887 enum surface_logical_srcs {
888 /** Surface binding table index */
889 SURFACE_LOGICAL_SRC_SURFACE,
890 /** Surface bindless handle */
891 SURFACE_LOGICAL_SRC_SURFACE_HANDLE,
892 /** Surface address; could be multi-dimensional for typed opcodes */
893 SURFACE_LOGICAL_SRC_ADDRESS,
894 /** Data to be written or used in an atomic op */
895 SURFACE_LOGICAL_SRC_DATA,
896 /** Surface number of dimensions. Affects the size of ADDRESS */
897 SURFACE_LOGICAL_SRC_IMM_DIMS,
898 /** Per-opcode immediate argument. For atomics, this is the atomic opcode */
899 SURFACE_LOGICAL_SRC_IMM_ARG,
900
901 SURFACE_LOGICAL_NUM_SRCS
902 };
903
904 #ifdef __cplusplus
905 /**
906 * Allow brw_urb_write_flags enums to be ORed together.
907 */
908 inline brw_urb_write_flags
909 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
910 {
911 return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
912 static_cast<int>(y));
913 }
914 #endif
915
916 enum PACKED brw_predicate {
917 BRW_PREDICATE_NONE = 0,
918 BRW_PREDICATE_NORMAL = 1,
919 BRW_PREDICATE_ALIGN1_ANYV = 2,
920 BRW_PREDICATE_ALIGN1_ALLV = 3,
921 BRW_PREDICATE_ALIGN1_ANY2H = 4,
922 BRW_PREDICATE_ALIGN1_ALL2H = 5,
923 BRW_PREDICATE_ALIGN1_ANY4H = 6,
924 BRW_PREDICATE_ALIGN1_ALL4H = 7,
925 BRW_PREDICATE_ALIGN1_ANY8H = 8,
926 BRW_PREDICATE_ALIGN1_ALL8H = 9,
927 BRW_PREDICATE_ALIGN1_ANY16H = 10,
928 BRW_PREDICATE_ALIGN1_ALL16H = 11,
929 BRW_PREDICATE_ALIGN1_ANY32H = 12,
930 BRW_PREDICATE_ALIGN1_ALL32H = 13,
931 BRW_PREDICATE_ALIGN16_REPLICATE_X = 2,
932 BRW_PREDICATE_ALIGN16_REPLICATE_Y = 3,
933 BRW_PREDICATE_ALIGN16_REPLICATE_Z = 4,
934 BRW_PREDICATE_ALIGN16_REPLICATE_W = 5,
935 BRW_PREDICATE_ALIGN16_ANY4H = 6,
936 BRW_PREDICATE_ALIGN16_ALL4H = 7,
937 };
938
939 enum PACKED brw_reg_file {
940 BRW_ARCHITECTURE_REGISTER_FILE = 0,
941 BRW_GENERAL_REGISTER_FILE = 1,
942 BRW_MESSAGE_REGISTER_FILE = 2,
943 BRW_IMMEDIATE_VALUE = 3,
944
945 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
946 FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
947 MRF = BRW_MESSAGE_REGISTER_FILE,
948 IMM = BRW_IMMEDIATE_VALUE,
949
950 /* These are not hardware values */
951 VGRF,
952 ATTR,
953 UNIFORM, /* prog_data->params[reg] */
954 BAD_FILE,
955 };
956
957 enum PACKED gen10_align1_3src_reg_file {
958 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0,
959 BRW_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */
960 BRW_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */
961 };
962
963 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction
964 * word is "Execution Datatype" which controls whether the instruction operates
965 * on float or integer types. The register arguments have fields that offer
966 * more fine control their respective types.
967 */
968 enum PACKED gen10_align1_3src_exec_type {
969 BRW_ALIGN1_3SRC_EXEC_TYPE_INT = 0,
970 BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
971 };
972
973 #define BRW_ARF_NULL 0x00
974 #define BRW_ARF_ADDRESS 0x10
975 #define BRW_ARF_ACCUMULATOR 0x20
976 #define BRW_ARF_FLAG 0x30
977 #define BRW_ARF_MASK 0x40
978 #define BRW_ARF_MASK_STACK 0x50
979 #define BRW_ARF_MASK_STACK_DEPTH 0x60
980 #define BRW_ARF_STATE 0x70
981 #define BRW_ARF_CONTROL 0x80
982 #define BRW_ARF_NOTIFICATION_COUNT 0x90
983 #define BRW_ARF_IP 0xA0
984 #define BRW_ARF_TDR 0xB0
985 #define BRW_ARF_TIMESTAMP 0xC0
986
987 #define BRW_MRF_COMPR4 (1 << 7)
988
989 #define BRW_AMASK 0
990 #define BRW_IMASK 1
991 #define BRW_LMASK 2
992 #define BRW_CMASK 3
993
994
995
996 #define BRW_THREAD_NORMAL 0
997 #define BRW_THREAD_ATOMIC 1
998 #define BRW_THREAD_SWITCH 2
999
1000 enum PACKED brw_vertical_stride {
1001 BRW_VERTICAL_STRIDE_0 = 0,
1002 BRW_VERTICAL_STRIDE_1 = 1,
1003 BRW_VERTICAL_STRIDE_2 = 2,
1004 BRW_VERTICAL_STRIDE_4 = 3,
1005 BRW_VERTICAL_STRIDE_8 = 4,
1006 BRW_VERTICAL_STRIDE_16 = 5,
1007 BRW_VERTICAL_STRIDE_32 = 6,
1008 BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
1009 };
1010
1011 enum PACKED gen10_align1_3src_vertical_stride {
1012 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
1013 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1,
1014 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
1015 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2,
1016 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,
1017 };
1018
1019 enum PACKED brw_width {
1020 BRW_WIDTH_1 = 0,
1021 BRW_WIDTH_2 = 1,
1022 BRW_WIDTH_4 = 2,
1023 BRW_WIDTH_8 = 3,
1024 BRW_WIDTH_16 = 4,
1025 };
1026
1027 /**
1028 * Gen12+ SWSB SBID synchronization mode.
1029 *
1030 * This is represented as a bitmask including any required SBID token
1031 * synchronization modes, used to synchronize out-of-order instructions. Only
1032 * the strongest mode of the mask will be provided to the hardware in the SWSB
1033 * field of an actual hardware instruction, but virtual instructions may be
1034 * able to take into account multiple of them.
1035 */
1036 enum tgl_sbid_mode {
1037 TGL_SBID_NULL = 0,
1038 TGL_SBID_SRC = 1,
1039 TGL_SBID_DST = 2,
1040 TGL_SBID_SET = 4
1041 };
1042
1043 #ifdef __cplusplus
1044 /**
1045 * Allow bitwise arithmetic of tgl_sbid_mode enums.
1046 */
1047 inline tgl_sbid_mode
1048 operator|(tgl_sbid_mode x, tgl_sbid_mode y)
1049 {
1050 return tgl_sbid_mode(unsigned(x) | unsigned(y));
1051 }
1052
1053 inline tgl_sbid_mode
1054 operator&(tgl_sbid_mode x, tgl_sbid_mode y)
1055 {
1056 return tgl_sbid_mode(unsigned(x) & unsigned(y));
1057 }
1058
1059 inline tgl_sbid_mode &
1060 operator|=(tgl_sbid_mode &x, tgl_sbid_mode y)
1061 {
1062 return x = x | y;
1063 }
1064
1065 #endif
1066
1067 /**
1068 * Logical representation of the SWSB scheduling information of a hardware
1069 * instruction. The binary representation is slightly more compact.
1070 */
1071 struct tgl_swsb {
1072 unsigned regdist : 3;
1073 unsigned sbid : 4;
1074 enum tgl_sbid_mode mode : 3;
1075 };
1076
1077 /**
1078 * Construct a scheduling annotation with a single RegDist dependency. This
1079 * synchronizes with the completion of the d-th previous in-order instruction.
1080 * The index is one-based, zero causes a no-op tgl_swsb to be constructed.
1081 */
1082 static inline struct tgl_swsb
1083 tgl_swsb_regdist(unsigned d)
1084 {
1085 const struct tgl_swsb swsb = { d };
1086 assert(swsb.regdist == d);
1087 return swsb;
1088 }
1089
1090 /**
1091 * Construct a scheduling annotation that synchronizes with the specified SBID
1092 * token.
1093 */
1094 static inline struct tgl_swsb
1095 tgl_swsb_sbid(enum tgl_sbid_mode mode, unsigned sbid)
1096 {
1097 const struct tgl_swsb swsb = { 0, sbid, mode };
1098 assert(swsb.sbid == sbid);
1099 return swsb;
1100 }
1101
1102 /**
1103 * Construct a no-op scheduling annotation.
1104 */
1105 static inline struct tgl_swsb
1106 tgl_swsb_null(void)
1107 {
1108 return tgl_swsb_regdist(0);
1109 }
1110
1111 /**
1112 * Return a scheduling annotation that allocates the same SBID synchronization
1113 * token as \p swsb. In addition it will synchronize against a previous
1114 * in-order instruction if \p regdist is non-zero.
1115 */
1116 static inline struct tgl_swsb
1117 tgl_swsb_dst_dep(struct tgl_swsb swsb, unsigned regdist)
1118 {
1119 swsb.regdist = regdist;
1120 swsb.mode = swsb.mode & TGL_SBID_SET;
1121 return swsb;
1122 }
1123
1124 /**
1125 * Return a scheduling annotation that synchronizes against the same SBID and
1126 * RegDist dependencies as \p swsb, but doesn't allocate any SBID token.
1127 */
1128 static inline struct tgl_swsb
1129 tgl_swsb_src_dep(struct tgl_swsb swsb)
1130 {
1131 swsb.mode = swsb.mode & (TGL_SBID_SRC | TGL_SBID_DST);
1132 return swsb;
1133 }
1134
1135 /**
1136 * Convert the provided tgl_swsb to the hardware's binary representation of an
1137 * SWSB annotation.
1138 */
1139 static inline uint8_t
1140 tgl_swsb_encode(struct tgl_swsb swsb)
1141 {
1142 if (!swsb.mode) {
1143 return swsb.regdist;
1144 } else if (swsb.regdist) {
1145 return 0x80 | swsb.regdist << 4 | swsb.sbid;
1146 } else {
1147 return swsb.sbid | (swsb.mode & TGL_SBID_SET ? 0x40 :
1148 swsb.mode & TGL_SBID_DST ? 0x20 : 0x30);
1149 }
1150 }
1151
1152 /**
1153 * Convert the provided binary representation of an SWSB annotation to a
1154 * tgl_swsb.
1155 */
1156 static inline struct tgl_swsb
1157 tgl_swsb_decode(enum opcode opcode, uint8_t x)
1158 {
1159 if (x & 0x80) {
1160 const struct tgl_swsb swsb = { (x & 0x70u) >> 4, x & 0xfu,
1161 (opcode == BRW_OPCODE_SEND ||
1162 opcode == BRW_OPCODE_SENDC ||
1163 opcode == BRW_OPCODE_MATH) ?
1164 TGL_SBID_SET : TGL_SBID_DST };
1165 return swsb;
1166 } else if ((x & 0x70) == 0x20) {
1167 return tgl_swsb_sbid(TGL_SBID_DST, x & 0xfu);
1168 } else if ((x & 0x70) == 0x30) {
1169 return tgl_swsb_sbid(TGL_SBID_SRC, x & 0xfu);
1170 } else if ((x & 0x70) == 0x40) {
1171 return tgl_swsb_sbid(TGL_SBID_SET, x & 0xfu);
1172 } else {
1173 return tgl_swsb_regdist(x & 0x7u);
1174 }
1175 }
1176
1177 enum tgl_sync_function {
1178 TGL_SYNC_NOP = 0x0,
1179 TGL_SYNC_ALLRD = 0x2,
1180 TGL_SYNC_ALLWR = 0x3,
1181 TGL_SYNC_BAR = 0xe,
1182 TGL_SYNC_HOST = 0xf
1183 };
1184
1185 /**
1186 * Message target: Shared Function ID for where to SEND a message.
1187 *
1188 * These are enumerated in the ISA reference under "send - Send Message".
1189 * In particular, see the following tables:
1190 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
1191 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
1192 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
1193 */
1194 enum brw_message_target {
1195 BRW_SFID_NULL = 0,
1196 BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */
1197 BRW_SFID_SAMPLER = 2,
1198 BRW_SFID_MESSAGE_GATEWAY = 3,
1199 BRW_SFID_DATAPORT_READ = 4,
1200 BRW_SFID_DATAPORT_WRITE = 5,
1201 BRW_SFID_URB = 6,
1202 BRW_SFID_THREAD_SPAWNER = 7,
1203 BRW_SFID_VME = 8,
1204
1205 GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4,
1206 GEN6_SFID_DATAPORT_RENDER_CACHE = 5,
1207 GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
1208
1209 GEN7_SFID_DATAPORT_DATA_CACHE = 10,
1210 GEN7_SFID_PIXEL_INTERPOLATOR = 11,
1211 HSW_SFID_DATAPORT_DATA_CACHE_1 = 12,
1212 HSW_SFID_CRE = 13,
1213 };
1214
1215 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
1216
1217 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
1218 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
1219 #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
1220
1221 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
1222 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
1223 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
1224 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
1225 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
1226 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
1227 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
1228 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
1229 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
1230 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
1231 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
1232 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
1233 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1
1234 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
1235 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
1236 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
1237 #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
1238 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
1239
1240 #define GEN5_SAMPLER_MESSAGE_SAMPLE 0
1241 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
1242 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2
1243 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3
1244 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4
1245 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
1246 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
1247 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
1248 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
1249 #define GEN5_SAMPLER_MESSAGE_LOD 9
1250 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
1251 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
1252 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
1253 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
1254 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
1255 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
1256 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ 24
1257 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ 25
1258 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ 26
1259 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28
1260 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
1261 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
1262 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
1263
1264 /* for GEN5 only */
1265 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
1266 #define BRW_SAMPLER_SIMD_MODE_SIMD8 1
1267 #define BRW_SAMPLER_SIMD_MODE_SIMD16 2
1268 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
1269
1270 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
1271 * behavior by setting bit 22 of dword 2 in the message header. */
1272 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D 0
1273 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22)
1274
1275 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
1276 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
1277 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
1278 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
1279 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
1280 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n) \
1281 ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \
1282 (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \
1283 (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \
1284 (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \
1285 (abort(), ~0))
1286
1287 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
1288 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
1289
1290 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
1291 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
1292
1293 /* This one stays the same across generations. */
1294 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
1295 /* GEN4 */
1296 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
1297 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
1298 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
1299 /* G45, GEN5 */
1300 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1301 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1302 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3
1303 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1304 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1305 /* GEN6 */
1306 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1307 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1308 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1309 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
1310 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1311
1312 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
1313 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
1314 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
1315
1316 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
1317 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
1318 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
1319 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
1320 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
1321
1322 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
1323 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
1324 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2
1325 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
1326 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
1327 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
1328 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
1329
1330 /* GEN6 */
1331 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
1332 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
1333 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9
1334 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10
1335 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11
1336 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12
1337 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
1338 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
1339
1340 /* GEN7 */
1341 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ 4
1342 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ 5
1343 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP 6
1344 #define GEN7_DATAPORT_RC_MEMORY_FENCE 7
1345 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10
1346 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE 12
1347 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE 13
1348 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0
1349 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1
1350 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2
1351 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3
1352 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4
1353 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5
1354 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6
1355 #define GEN7_DATAPORT_DC_MEMORY_FENCE 7
1356 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8
1357 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10
1358 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11
1359 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
1360 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
1361
1362 #define GEN7_DATAPORT_SCRATCH_READ ((1 << 18) | \
1363 (0 << 17))
1364 #define GEN7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \
1365 (1 << 17))
1366 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12
1367
1368 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0
1369 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1
1370 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID 2
1371 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3
1372
1373 /* HSW */
1374 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0
1375 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1
1376 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2
1377 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3
1378 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4
1379 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7
1380 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8
1381 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10
1382 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11
1383 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12
1384
1385 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1
1386 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2
1387 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3
1388 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4
1389 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5
1390 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6
1391 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7
1392 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9
1393 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10
1394 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11
1395 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12
1396 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13
1397 #define GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ 0x10
1398 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ 0x11
1399 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP 0x12
1400 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE 0x19
1401 #define GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE 0x1a
1402 #define GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP 0x1b
1403 #define GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP 0x1d
1404
1405 /* GEN9 */
1406 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE 12
1407 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ 13
1408
1409 /* A64 scattered message subtype */
1410 #define GEN8_A64_SCATTERED_SUBTYPE_BYTE 0
1411 #define GEN8_A64_SCATTERED_SUBTYPE_DWORD 1
1412 #define GEN8_A64_SCATTERED_SUBTYPE_QWORD 2
1413 #define GEN8_A64_SCATTERED_SUBTYPE_HWORD 3
1414
1415 /* Dataport special binding table indices: */
1416 #define BRW_BTI_STATELESS 255
1417 #define GEN7_BTI_SLM 254
1418 /* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the
1419 * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW,
1420 * CHV and at least some pre-production steppings of SKL due to
1421 * WaForceEnableNonCoherent, HDC memory access may have been overridden by the
1422 * kernel to be non-coherent (matching the behavior of the same BTI on
1423 * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253.
1424 */
1425 #define GEN8_BTI_STATELESS_IA_COHERENT 255
1426 #define GEN8_BTI_STATELESS_NON_COHERENT 253
1427 #define GEN9_BTI_BINDLESS 252
1428
1429 /* Dataport atomic operations for Untyped Atomic Integer Operation message
1430 * (and others).
1431 */
1432 #define BRW_AOP_AND 1
1433 #define BRW_AOP_OR 2
1434 #define BRW_AOP_XOR 3
1435 #define BRW_AOP_MOV 4
1436 #define BRW_AOP_INC 5
1437 #define BRW_AOP_DEC 6
1438 #define BRW_AOP_ADD 7
1439 #define BRW_AOP_SUB 8
1440 #define BRW_AOP_REVSUB 9
1441 #define BRW_AOP_IMAX 10
1442 #define BRW_AOP_IMIN 11
1443 #define BRW_AOP_UMAX 12
1444 #define BRW_AOP_UMIN 13
1445 #define BRW_AOP_CMPWR 14
1446 #define BRW_AOP_PREDEC 15
1447
1448 /* Dataport atomic operations for Untyped Atomic Float Operation message. */
1449 #define BRW_AOP_FMAX 1
1450 #define BRW_AOP_FMIN 2
1451 #define BRW_AOP_FCMPWR 3
1452
1453 #define BRW_MATH_FUNCTION_INV 1
1454 #define BRW_MATH_FUNCTION_LOG 2
1455 #define BRW_MATH_FUNCTION_EXP 3
1456 #define BRW_MATH_FUNCTION_SQRT 4
1457 #define BRW_MATH_FUNCTION_RSQ 5
1458 #define BRW_MATH_FUNCTION_SIN 6
1459 #define BRW_MATH_FUNCTION_COS 7
1460 #define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */
1461 #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
1462 #define BRW_MATH_FUNCTION_POW 10
1463 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
1464 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
1465 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
1466 #define GEN8_MATH_FUNCTION_INVM 14
1467 #define GEN8_MATH_FUNCTION_RSQRTM 15
1468
1469 #define BRW_MATH_INTEGER_UNSIGNED 0
1470 #define BRW_MATH_INTEGER_SIGNED 1
1471
1472 #define BRW_MATH_PRECISION_FULL 0
1473 #define BRW_MATH_PRECISION_PARTIAL 1
1474
1475 #define BRW_MATH_SATURATE_NONE 0
1476 #define BRW_MATH_SATURATE_SATURATE 1
1477
1478 #define BRW_MATH_DATA_VECTOR 0
1479 #define BRW_MATH_DATA_SCALAR 1
1480
1481 #define BRW_URB_OPCODE_WRITE_HWORD 0
1482 #define BRW_URB_OPCODE_WRITE_OWORD 1
1483 #define BRW_URB_OPCODE_READ_HWORD 2
1484 #define BRW_URB_OPCODE_READ_OWORD 3
1485 #define GEN7_URB_OPCODE_ATOMIC_MOV 4
1486 #define GEN7_URB_OPCODE_ATOMIC_INC 5
1487 #define GEN8_URB_OPCODE_ATOMIC_ADD 6
1488 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1489 #define GEN8_URB_OPCODE_SIMD8_READ 8
1490
1491 #define BRW_URB_SWIZZLE_NONE 0
1492 #define BRW_URB_SWIZZLE_INTERLEAVE 1
1493 #define BRW_URB_SWIZZLE_TRANSPOSE 2
1494
1495 #define BRW_SCRATCH_SPACE_SIZE_1K 0
1496 #define BRW_SCRATCH_SPACE_SIZE_2K 1
1497 #define BRW_SCRATCH_SPACE_SIZE_4K 2
1498 #define BRW_SCRATCH_SPACE_SIZE_8K 3
1499 #define BRW_SCRATCH_SPACE_SIZE_16K 4
1500 #define BRW_SCRATCH_SPACE_SIZE_32K 5
1501 #define BRW_SCRATCH_SPACE_SIZE_64K 6
1502 #define BRW_SCRATCH_SPACE_SIZE_128K 7
1503 #define BRW_SCRATCH_SPACE_SIZE_256K 8
1504 #define BRW_SCRATCH_SPACE_SIZE_512K 9
1505 #define BRW_SCRATCH_SPACE_SIZE_1M 10
1506 #define BRW_SCRATCH_SPACE_SIZE_2M 11
1507
1508 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0
1509 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1
1510 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2
1511 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3
1512 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4
1513 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1514 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6
1515
1516
1517 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1518 * is 2^9, or 512. It's counted in multiples of 64 bytes.
1519 *
1520 * Identical for VS, DS, and HS.
1521 */
1522 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
1523 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64)
1524 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64)
1525 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64)
1526
1527 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1528 * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1529 */
1530 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128)
1531
1532 /* GS Thread Payload
1533 */
1534
1535 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1536 * counted in multiples of 16 bytes.
1537 */
1538 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16)
1539
1540
1541 /* R0 */
1542 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
1543
1544 /* CR0.0[5:4] Floating-Point Rounding Modes
1545 * Skylake PRM, Volume 7 Part 1, "Control Register", page 756
1546 */
1547
1548 #define BRW_CR0_RND_MODE_MASK 0x30
1549 #define BRW_CR0_RND_MODE_SHIFT 4
1550
1551 enum PACKED brw_rnd_mode {
1552 BRW_RND_MODE_RTNE = 0, /* Round to Nearest or Even */
1553 BRW_RND_MODE_RU = 1, /* Round Up, toward +inf */
1554 BRW_RND_MODE_RD = 2, /* Round Down, toward -inf */
1555 BRW_RND_MODE_RTZ = 3, /* Round Toward Zero */
1556 BRW_RND_MODE_UNSPECIFIED, /* Unspecified rounding mode */
1557 };
1558
1559 #define BRW_CR0_FP64_DENORM_PRESERVE (1 << 6)
1560 #define BRW_CR0_FP32_DENORM_PRESERVE (1 << 7)
1561 #define BRW_CR0_FP16_DENORM_PRESERVE (1 << 10)
1562
1563 #define BRW_CR0_FP_MODE_MASK (BRW_CR0_FP64_DENORM_PRESERVE | \
1564 BRW_CR0_FP32_DENORM_PRESERVE | \
1565 BRW_CR0_FP16_DENORM_PRESERVE | \
1566 BRW_CR0_RND_MODE_MASK)
1567
1568 /* MDC_DS - Data Size Message Descriptor Control Field
1569 * Skylake PRM, Volume 2d, page 129
1570 *
1571 * Specifies the number of Bytes to be read or written per Dword used at
1572 * byte_scattered read/write and byte_scaled read/write messages.
1573 */
1574 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE 0
1575 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD 1
1576 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2
1577
1578 #endif /* BRW_EU_DEFINES_H */