projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
i965/fs/generator: add new opcode to set float controls modes in control register
[mesa.git] / src / intel / compiler / brw_eu_defines.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32 #ifndef BRW_EU_DEFINES_H
33 #define BRW_EU_DEFINES_H
34
35 #include "util/macros.h"
36
37 /* The following hunk, up-to "Execution Unit" is used by both the
38 * intel/compiler and i965 codebase. */
39
40 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
41 /* Using the GNU statement expression extension */
42 #define SET_FIELD(value, field) \
43 ({ \
44 uint32_t fieldval = (uint32_t)(value) << field ## _SHIFT; \
45 assert((fieldval & ~ field ## _MASK) == 0); \
46 fieldval & field ## _MASK; \
47 })
48
49 #define SET_BITS(value, high, low) \
50 ({ \
51 const uint32_t fieldval = (uint32_t)(value) << (low); \
52 assert((fieldval & ~INTEL_MASK(high, low)) == 0); \
53 fieldval & INTEL_MASK(high, low); \
54 })
55
56 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
57 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
58
59 #define _3DPRIM_POINTLIST 0x01
60 #define _3DPRIM_LINELIST 0x02
61 #define _3DPRIM_LINESTRIP 0x03
62 #define _3DPRIM_TRILIST 0x04
63 #define _3DPRIM_TRISTRIP 0x05
64 #define _3DPRIM_TRIFAN 0x06
65 #define _3DPRIM_QUADLIST 0x07
66 #define _3DPRIM_QUADSTRIP 0x08
67 #define _3DPRIM_LINELIST_ADJ 0x09 /* G45+ */
68 #define _3DPRIM_LINESTRIP_ADJ 0x0A /* G45+ */
69 #define _3DPRIM_TRILIST_ADJ 0x0B /* G45+ */
70 #define _3DPRIM_TRISTRIP_ADJ 0x0C /* G45+ */
71 #define _3DPRIM_TRISTRIP_REVERSE 0x0D
72 #define _3DPRIM_POLYGON 0x0E
73 #define _3DPRIM_RECTLIST 0x0F
74 #define _3DPRIM_LINELOOP 0x10
75 #define _3DPRIM_POINTLIST_BF 0x11
76 #define _3DPRIM_LINESTRIP_CONT 0x12
77 #define _3DPRIM_LINESTRIP_BF 0x13
78 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
79 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x16
80 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
81
82 /* Bitfields for the URB_WRITE message, DW2 of message header: */
83 #define URB_WRITE_PRIM_END 0x1
84 #define URB_WRITE_PRIM_START 0x2
85 #define URB_WRITE_PRIM_TYPE_SHIFT 2
86
87 #define BRW_SPRITE_POINT_ENABLE 16
88
89 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
90 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
91
92 /* Execution Unit (EU) defines
93 */
94
95 #define BRW_ALIGN_1 0
96 #define BRW_ALIGN_16 1
97
98 #define BRW_ADDRESS_DIRECT 0
99 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
100
101 #define BRW_CHANNEL_X 0
102 #define BRW_CHANNEL_Y 1
103 #define BRW_CHANNEL_Z 2
104 #define BRW_CHANNEL_W 3
105
106 enum brw_compression {
107 BRW_COMPRESSION_NONE = 0,
108 BRW_COMPRESSION_2NDHALF = 1,
109 BRW_COMPRESSION_COMPRESSED = 2,
110 };
111
112 #define GEN6_COMPRESSION_1Q 0
113 #define GEN6_COMPRESSION_2Q 1
114 #define GEN6_COMPRESSION_3Q 2
115 #define GEN6_COMPRESSION_4Q 3
116 #define GEN6_COMPRESSION_1H 0
117 #define GEN6_COMPRESSION_2H 2
118
119 enum PACKED brw_conditional_mod {
120 BRW_CONDITIONAL_NONE = 0,
121 BRW_CONDITIONAL_Z = 1,
122 BRW_CONDITIONAL_NZ = 2,
123 BRW_CONDITIONAL_EQ = 1, /* Z */
124 BRW_CONDITIONAL_NEQ = 2, /* NZ */
125 BRW_CONDITIONAL_G = 3,
126 BRW_CONDITIONAL_GE = 4,
127 BRW_CONDITIONAL_L = 5,
128 BRW_CONDITIONAL_LE = 6,
129 BRW_CONDITIONAL_R = 7, /* Gen <= 5 */
130 BRW_CONDITIONAL_O = 8,
131 BRW_CONDITIONAL_U = 9,
132 };
133
134 #define BRW_DEBUG_NONE 0
135 #define BRW_DEBUG_BREAKPOINT 1
136
137 #define BRW_DEPENDENCY_NORMAL 0
138 #define BRW_DEPENDENCY_NOTCLEARED 1
139 #define BRW_DEPENDENCY_NOTCHECKED 2
140 #define BRW_DEPENDENCY_DISABLE 3
141
142 enum PACKED brw_execution_size {
143 BRW_EXECUTE_1 = 0,
144 BRW_EXECUTE_2 = 1,
145 BRW_EXECUTE_4 = 2,
146 BRW_EXECUTE_8 = 3,
147 BRW_EXECUTE_16 = 4,
148 BRW_EXECUTE_32 = 5,
149 };
150
151 enum PACKED brw_horizontal_stride {
152 BRW_HORIZONTAL_STRIDE_0 = 0,
153 BRW_HORIZONTAL_STRIDE_1 = 1,
154 BRW_HORIZONTAL_STRIDE_2 = 2,
155 BRW_HORIZONTAL_STRIDE_4 = 3,
156 };
157
158 enum PACKED gen10_align1_3src_src_horizontal_stride {
159 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
160 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
161 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
162 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
163 };
164
165 enum PACKED gen10_align1_3src_dst_horizontal_stride {
166 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
167 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
168 };
169
170 #define BRW_INSTRUCTION_NORMAL 0
171 #define BRW_INSTRUCTION_SATURATE 1
172
173 #define BRW_MASK_ENABLE 0
174 #define BRW_MASK_DISABLE 1
175
176 /** @{
177 *
178 * Gen6 has replaced "mask enable/disable" with WECtrl, which is
179 * effectively the same but much simpler to think about. Now, there
180 * are two contributors ANDed together to whether channels are
181 * executed: The predication on the instruction, and the channel write
182 * enable.
183 */
184 /**
185 * This is the default value. It means that a channel's write enable is set
186 * if the per-channel IP is pointing at this instruction.
187 */
188 #define BRW_WE_NORMAL 0
189 /**
190 * This is used like BRW_MASK_DISABLE, and causes all channels to have
191 * their write enable set. Note that predication still contributes to
192 * whether the channel actually gets written.
193 */
194 #define BRW_WE_ALL 1
195 /** @} */
196
197 enum opcode {
198 /* These are the actual hardware opcodes. */
199 BRW_OPCODE_ILLEGAL = 0,
200 BRW_OPCODE_MOV = 1,
201 BRW_OPCODE_SEL = 2,
202 BRW_OPCODE_MOVI = 3, /**< G45+ */
203 BRW_OPCODE_NOT = 4,
204 BRW_OPCODE_AND = 5,
205 BRW_OPCODE_OR = 6,
206 BRW_OPCODE_XOR = 7,
207 BRW_OPCODE_SHR = 8,
208 BRW_OPCODE_SHL = 9,
209 BRW_OPCODE_DIM = 10, /**< Gen7.5 only */ /* Reused */
210 BRW_OPCODE_SMOV = 10, /**< Gen8+ */ /* Reused */
211 /* Reserved - 11 */
212 BRW_OPCODE_ASR = 12,
213 /* Reserved - 13 */
214 BRW_OPCODE_ROR = 14, /**< Gen11+ */
215 BRW_OPCODE_ROL = 15, /**< Gen11+ */
216 BRW_OPCODE_CMP = 16,
217 BRW_OPCODE_CMPN = 17,
218 BRW_OPCODE_CSEL = 18, /**< Gen8+ */
219 BRW_OPCODE_F32TO16 = 19, /**< Gen7 only */
220 BRW_OPCODE_F16TO32 = 20, /**< Gen7 only */
221 /* Reserved - 21-22 */
222 BRW_OPCODE_BFREV = 23, /**< Gen7+ */
223 BRW_OPCODE_BFE = 24, /**< Gen7+ */
224 BRW_OPCODE_BFI1 = 25, /**< Gen7+ */
225 BRW_OPCODE_BFI2 = 26, /**< Gen7+ */
226 /* Reserved - 27-31 */
227 BRW_OPCODE_JMPI = 32,
228 BRW_OPCODE_BRD = 33, /**< Gen7+ */
229 BRW_OPCODE_IF = 34,
230 BRW_OPCODE_IFF = 35, /**< Pre-Gen6 */ /* Reused */
231 BRW_OPCODE_BRC = 35, /**< Gen7+ */ /* Reused */
232 BRW_OPCODE_ELSE = 36,
233 BRW_OPCODE_ENDIF = 37,
234 BRW_OPCODE_DO = 38, /**< Pre-Gen6 */ /* Reused */
235 BRW_OPCODE_CASE = 38, /**< Gen6 only */ /* Reused */
236 BRW_OPCODE_WHILE = 39,
237 BRW_OPCODE_BREAK = 40,
238 BRW_OPCODE_CONTINUE = 41,
239 BRW_OPCODE_HALT = 42,
240 BRW_OPCODE_CALLA = 43, /**< Gen7.5+ */
241 BRW_OPCODE_MSAVE = 44, /**< Pre-Gen6 */ /* Reused */
242 BRW_OPCODE_CALL = 44, /**< Gen6+ */ /* Reused */
243 BRW_OPCODE_MREST = 45, /**< Pre-Gen6 */ /* Reused */
244 BRW_OPCODE_RET = 45, /**< Gen6+ */ /* Reused */
245 BRW_OPCODE_PUSH = 46, /**< Pre-Gen6 */ /* Reused */
246 BRW_OPCODE_FORK = 46, /**< Gen6 only */ /* Reused */
247 BRW_OPCODE_GOTO = 46, /**< Gen8+ */ /* Reused */
248 BRW_OPCODE_POP = 47, /**< Pre-Gen6 */
249 BRW_OPCODE_WAIT = 48,
250 BRW_OPCODE_SEND = 49,
251 BRW_OPCODE_SENDC = 50,
252 BRW_OPCODE_SENDS = 51, /**< Gen9+ */
253 BRW_OPCODE_SENDSC = 52, /**< Gen9+ */
254 /* Reserved 53-55 */
255 BRW_OPCODE_MATH = 56, /**< Gen6+ */
256 /* Reserved 57-63 */
257 BRW_OPCODE_ADD = 64,
258 BRW_OPCODE_MUL = 65,
259 BRW_OPCODE_AVG = 66,
260 BRW_OPCODE_FRC = 67,
261 BRW_OPCODE_RNDU = 68,
262 BRW_OPCODE_RNDD = 69,
263 BRW_OPCODE_RNDE = 70,
264 BRW_OPCODE_RNDZ = 71,
265 BRW_OPCODE_MAC = 72,
266 BRW_OPCODE_MACH = 73,
267 BRW_OPCODE_LZD = 74,
268 BRW_OPCODE_FBH = 75, /**< Gen7+ */
269 BRW_OPCODE_FBL = 76, /**< Gen7+ */
270 BRW_OPCODE_CBIT = 77, /**< Gen7+ */
271 BRW_OPCODE_ADDC = 78, /**< Gen7+ */
272 BRW_OPCODE_SUBB = 79, /**< Gen7+ */
273 BRW_OPCODE_SAD2 = 80,
274 BRW_OPCODE_SADA2 = 81,
275 /* Reserved 82-83 */
276 BRW_OPCODE_DP4 = 84,
277 BRW_OPCODE_DPH = 85,
278 BRW_OPCODE_DP3 = 86,
279 BRW_OPCODE_DP2 = 87,
280 /* Reserved 88 */
281 BRW_OPCODE_LINE = 89,
282 BRW_OPCODE_PLN = 90, /**< G45+ */
283 BRW_OPCODE_MAD = 91, /**< Gen6+ */
284 BRW_OPCODE_LRP = 92, /**< Gen6+ */
285 BRW_OPCODE_MADM = 93, /**< Gen8+ */
286 /* Reserved 94-124 */
287 BRW_OPCODE_NENOP = 125, /**< G45 only */
288 BRW_OPCODE_NOP = 126,
289 /* Reserved 127 */
290
291 /* These are compiler backend opcodes that get translated into other
292 * instructions.
293 */
294 FS_OPCODE_FB_WRITE = 128,
295
296 /**
297 * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
298 * individual sources instead of as a single payload blob. The
299 * position/ordering of the arguments are defined by the enum
300 * fb_write_logical_srcs.
301 */
302 FS_OPCODE_FB_WRITE_LOGICAL,
303
304 FS_OPCODE_REP_FB_WRITE,
305
306 FS_OPCODE_FB_READ,
307 FS_OPCODE_FB_READ_LOGICAL,
308
309 SHADER_OPCODE_RCP,
310 SHADER_OPCODE_RSQ,
311 SHADER_OPCODE_SQRT,
312 SHADER_OPCODE_EXP2,
313 SHADER_OPCODE_LOG2,
314 SHADER_OPCODE_POW,
315 SHADER_OPCODE_INT_QUOTIENT,
316 SHADER_OPCODE_INT_REMAINDER,
317 SHADER_OPCODE_SIN,
318 SHADER_OPCODE_COS,
319
320 /**
321 * A generic "send" opcode. The first two sources are the message
322 * descriptor and extended message descriptor respectively. The third
323 * and optional fourth sources are the message payload
324 */
325 SHADER_OPCODE_SEND,
326
327 /**
328 * An "undefined" write which does nothing but indicates to liveness that
329 * we don't care about any values in the register which predate this
330 * instruction. Used to prevent partial writes from causing issues with
331 * live ranges.
332 */
333 SHADER_OPCODE_UNDEF,
334
335 /**
336 * Texture sampling opcodes.
337 *
338 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
339 * opcode but instead of taking a single payload blob they expect their
340 * arguments separately as individual sources. The position/ordering of the
341 * arguments are defined by the enum tex_logical_srcs.
342 */
343 SHADER_OPCODE_TEX,
344 SHADER_OPCODE_TEX_LOGICAL,
345 SHADER_OPCODE_TXD,
346 SHADER_OPCODE_TXD_LOGICAL,
347 SHADER_OPCODE_TXF,
348 SHADER_OPCODE_TXF_LOGICAL,
349 SHADER_OPCODE_TXF_LZ,
350 SHADER_OPCODE_TXL,
351 SHADER_OPCODE_TXL_LOGICAL,
352 SHADER_OPCODE_TXL_LZ,
353 SHADER_OPCODE_TXS,
354 SHADER_OPCODE_TXS_LOGICAL,
355 FS_OPCODE_TXB,
356 FS_OPCODE_TXB_LOGICAL,
357 SHADER_OPCODE_TXF_CMS,
358 SHADER_OPCODE_TXF_CMS_LOGICAL,
359 SHADER_OPCODE_TXF_CMS_W,
360 SHADER_OPCODE_TXF_CMS_W_LOGICAL,
361 SHADER_OPCODE_TXF_UMS,
362 SHADER_OPCODE_TXF_UMS_LOGICAL,
363 SHADER_OPCODE_TXF_MCS,
364 SHADER_OPCODE_TXF_MCS_LOGICAL,
365 SHADER_OPCODE_LOD,
366 SHADER_OPCODE_LOD_LOGICAL,
367 SHADER_OPCODE_TG4,
368 SHADER_OPCODE_TG4_LOGICAL,
369 SHADER_OPCODE_TG4_OFFSET,
370 SHADER_OPCODE_TG4_OFFSET_LOGICAL,
371 SHADER_OPCODE_SAMPLEINFO,
372 SHADER_OPCODE_SAMPLEINFO_LOGICAL,
373
374 SHADER_OPCODE_IMAGE_SIZE_LOGICAL,
375
376 /**
377 * Combines multiple sources of size 1 into a larger virtual GRF.
378 * For example, parameters for a send-from-GRF message. Or, updating
379 * channels of a size 4 VGRF used to store vec4s such as texturing results.
380 *
381 * This will be lowered into MOVs from each source to consecutive offsets
382 * of the destination VGRF.
383 *
384 * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV,
385 * but still reserves the first channel of the destination VGRF. This can be
386 * used to reserve space for, say, a message header set up by the generators.
387 */
388 SHADER_OPCODE_LOAD_PAYLOAD,
389
390 /**
391 * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
392 * acts intra-channel, obtaining the final value for each channel by
393 * combining the sources values for the same channel, the first source
394 * occupying the lowest bits and the last source occupying the highest
395 * bits.
396 */
397 FS_OPCODE_PACK,
398
399 SHADER_OPCODE_SHADER_TIME_ADD,
400
401 /**
402 * Typed and untyped surface access opcodes.
403 *
404 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
405 * opcode but instead of taking a single payload blob they expect their
406 * arguments separately as individual sources:
407 *
408 * Source 0: [required] Surface coordinates.
409 * Source 1: [optional] Operation source.
410 * Source 2: [required] Surface index.
411 * Source 3: [required] Number of coordinate components (as UD immediate).
412 * Source 4: [required] Opcode-specific control immediate, same as source 2
413 * of the matching non-LOGICAL opcode.
414 */
415 VEC4_OPCODE_UNTYPED_ATOMIC,
416 SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
417 SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
418 VEC4_OPCODE_UNTYPED_SURFACE_READ,
419 SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
420 VEC4_OPCODE_UNTYPED_SURFACE_WRITE,
421 SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
422
423 /**
424 * Untyped A64 surface access opcodes.
425 *
426 * Source 0: 64-bit address
427 * Source 1: Operational source
428 * Source 2: [required] Opcode-specific control immediate, same as source 2
429 * of the matching non-LOGICAL opcode.
430 */
431 SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL,
432 SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL,
433 SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL,
434 SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL,
435 SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL,
436 SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL,
437 SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL,
438
439 SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
440 SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
441 SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
442
443 SHADER_OPCODE_RND_MODE,
444 SHADER_OPCODE_FLOAT_CONTROL_MODE,
445
446 /**
447 * Byte scattered write/read opcodes.
448 *
449 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
450 * opcode, but instead of taking a single payload blog they expect their
451 * arguments separately as individual sources, like untyped write/read.
452 */
453 SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
454 SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
455
456 /**
457 * Memory fence messages.
458 *
459 * Source 0: Must be register g0, used as header.
460 * Source 1: Immediate bool to indicate whether or not we need to stall
461 * until memory transactions prior to the fence are completed.
462 * Source 2: Immediate byte indicating which memory to fence. Zero means
463 * global memory; GEN7_BTI_SLM means SLM (for Gen11+ only).
464 *
465 * Vec4 backend only uses Source 0.
466 */
467 SHADER_OPCODE_MEMORY_FENCE,
468
469 SHADER_OPCODE_GEN4_SCRATCH_READ,
470 SHADER_OPCODE_GEN4_SCRATCH_WRITE,
471 SHADER_OPCODE_GEN7_SCRATCH_READ,
472
473 /**
474 * Gen8+ SIMD8 URB Read messages.
475 */
476 SHADER_OPCODE_URB_READ_SIMD8,
477 SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
478
479 SHADER_OPCODE_URB_WRITE_SIMD8,
480 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
481 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
482 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
483
484 /**
485 * Return the index of an arbitrary live channel (i.e. one of the channels
486 * enabled in the current execution mask) and assign it to the first
487 * component of the destination. Expected to be used as input for the
488 * BROADCAST pseudo-opcode.
489 */
490 SHADER_OPCODE_FIND_LIVE_CHANNEL,
491
492 /**
493 * Pick the channel from its first source register given by the index
494 * specified as second source. Useful for variable indexing of surfaces.
495 *
496 * Note that because the result of this instruction is by definition
497 * uniform and it can always be splatted to multiple channels using a
498 * scalar regioning mode, only the first channel of the destination region
499 * is guaranteed to be updated, which implies that BROADCAST instructions
500 * should usually be marked force_writemask_all.
501 */
502 SHADER_OPCODE_BROADCAST,
503
504 /* Pick the channel from its first source register given by the index
505 * specified as second source.
506 *
507 * This is similar to the BROADCAST instruction except that it takes a
508 * dynamic index and potentially puts a different value in each output
509 * channel.
510 */
511 SHADER_OPCODE_SHUFFLE,
512
513 /* Select between src0 and src1 based on channel enables.
514 *
515 * This instruction copies src0 into the enabled channels of the
516 * destination and copies src1 into the disabled channels.
517 */
518 SHADER_OPCODE_SEL_EXEC,
519
520 /* This turns into an align16 mov from src0 to dst with a swizzle
521 * provided as an immediate in src1.
522 */
523 SHADER_OPCODE_QUAD_SWIZZLE,
524
525 /* Take every Nth element in src0 and broadcast it to the group of N
526 * channels in which it lives in the destination. The offset within the
527 * cluster is given by src1 and the cluster size is given by src2.
528 */
529 SHADER_OPCODE_CLUSTER_BROADCAST,
530
531 SHADER_OPCODE_GET_BUFFER_SIZE,
532
533 SHADER_OPCODE_INTERLOCK,
534
535 VEC4_OPCODE_MOV_BYTES,
536 VEC4_OPCODE_PACK_BYTES,
537 VEC4_OPCODE_UNPACK_UNIFORM,
538 VEC4_OPCODE_DOUBLE_TO_F32,
539 VEC4_OPCODE_DOUBLE_TO_D32,
540 VEC4_OPCODE_DOUBLE_TO_U32,
541 VEC4_OPCODE_TO_DOUBLE,
542 VEC4_OPCODE_PICK_LOW_32BIT,
543 VEC4_OPCODE_PICK_HIGH_32BIT,
544 VEC4_OPCODE_SET_LOW_32BIT,
545 VEC4_OPCODE_SET_HIGH_32BIT,
546
547 FS_OPCODE_DDX_COARSE,
548 FS_OPCODE_DDX_FINE,
549 /**
550 * Compute dFdy(), dFdyCoarse(), or dFdyFine().
551 */
552 FS_OPCODE_DDY_COARSE,
553 FS_OPCODE_DDY_FINE,
554 FS_OPCODE_LINTERP,
555 FS_OPCODE_PIXEL_X,
556 FS_OPCODE_PIXEL_Y,
557 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
558 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
559 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
560 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
561 FS_OPCODE_DISCARD_JUMP,
562 FS_OPCODE_SET_SAMPLE_ID,
563 FS_OPCODE_PACK_HALF_2x16_SPLIT,
564 FS_OPCODE_PLACEHOLDER_HALT,
565 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
566 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
567 FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
568
569 VS_OPCODE_URB_WRITE,
570 VS_OPCODE_PULL_CONSTANT_LOAD,
571 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
572 VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
573
574 VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
575
576 /**
577 * Write geometry shader output data to the URB.
578 *
579 * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
580 * R0 to the first MRF. This allows the geometry shader to override the
581 * "Slot {0,1} Offset" fields in the message header.
582 */
583 GS_OPCODE_URB_WRITE,
584
585 /**
586 * Write geometry shader output data to the URB and request a new URB
587 * handle (gen6).
588 *
589 * This opcode doesn't do an implied move from R0 to the first MRF.
590 */
591 GS_OPCODE_URB_WRITE_ALLOCATE,
592
593 /**
594 * Terminate the geometry shader thread by doing an empty URB write.
595 *
596 * This opcode doesn't do an implied move from R0 to the first MRF. This
597 * allows the geometry shader to override the "GS Number of Output Vertices
598 * for Slot {0,1}" fields in the message header.
599 */
600 GS_OPCODE_THREAD_END,
601
602 /**
603 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
604 *
605 * - dst is the MRF containing the message header.
606 *
607 * - src0.x indicates which portion of the URB should be written to (e.g. a
608 * vertex number)
609 *
610 * - src1 is an immediate multiplier which will be applied to src0
611 * (e.g. the size of a single vertex in the URB).
612 *
613 * Note: the hardware will apply this offset *in addition to* the offset in
614 * vec4_instruction::offset.
615 */
616 GS_OPCODE_SET_WRITE_OFFSET,
617
618 /**
619 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
620 * URB_WRITE message header.
621 *
622 * - dst is the MRF containing the message header.
623 *
624 * - src0.x is the vertex count. The upper 16 bits will be ignored.
625 */
626 GS_OPCODE_SET_VERTEX_COUNT,
627
628 /**
629 * Set DWORD 2 of dst to the value in src.
630 */
631 GS_OPCODE_SET_DWORD_2,
632
633 /**
634 * Prepare the dst register for storage in the "Channel Mask" fields of a
635 * URB_WRITE message header.
636 *
637 * DWORD 4 of dst is shifted left by 4 bits, so that later,
638 * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
639 * final channel mask.
640 *
641 * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
642 * form the final channel mask, DWORDs 0 and 4 of the dst register must not
643 * have any extraneous bits set prior to execution of this opcode (that is,
644 * they should be in the range 0x0 to 0xf).
645 */
646 GS_OPCODE_PREPARE_CHANNEL_MASKS,
647
648 /**
649 * Set the "Channel Mask" fields of a URB_WRITE message header.
650 *
651 * - dst is the MRF containing the message header.
652 *
653 * - src.x is the channel mask, as prepared by
654 * GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to
655 * form the final channel mask.
656 */
657 GS_OPCODE_SET_CHANNEL_MASKS,
658
659 /**
660 * Get the "Instance ID" fields from the payload.
661 *
662 * - dst is the GRF for gl_InvocationID.
663 */
664 GS_OPCODE_GET_INSTANCE_ID,
665
666 /**
667 * Send a FF_SYNC message to allocate initial URB handles (gen6).
668 *
669 * - dst will be used as the writeback register for the FF_SYNC operation.
670 *
671 * - src0 is the number of primitives written.
672 *
673 * - src1 is the value to hold in M0.0: number of SO vertices to write
674 * and number of SO primitives needed. Its value will be overwritten
675 * with the SVBI values if transform feedback is enabled.
676 *
677 * Note: This opcode uses an implicit MRF register for the ff_sync message
678 * header, so the caller is expected to set inst->base_mrf and initialize
679 * that MRF register to r0. This opcode will also write to this MRF register
680 * to include the allocated URB handle so it can then be reused directly as
681 * the header in the URB write operation we are allocating the handle for.
682 */
683 GS_OPCODE_FF_SYNC,
684
685 /**
686 * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
687 * register.
688 *
689 * - dst is the GRF where PrimitiveID information will be moved.
690 */
691 GS_OPCODE_SET_PRIMITIVE_ID,
692
693 /**
694 * Write transform feedback data to the SVB by sending a SVB WRITE message.
695 * Used in gen6.
696 *
697 * - dst is the MRF register containing the message header.
698 *
699 * - src0 is the register where the vertex data is going to be copied from.
700 *
701 * - src1 is the destination register when write commit occurs.
702 */
703 GS_OPCODE_SVB_WRITE,
704
705 /**
706 * Set destination index in the SVB write message payload (M0.5). Used
707 * in gen6 for transform feedback.
708 *
709 * - dst is the header to save the destination indices for SVB WRITE.
710 * - src is the register that holds the destination indices value.
711 */
712 GS_OPCODE_SVB_SET_DST_INDEX,
713
714 /**
715 * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
716 * Used in gen6 for transform feedback.
717 *
718 * - dst will hold the register with the final Mx.0 value.
719 *
720 * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
721 *
722 * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
723 *
724 * - src2 is the value to hold in M0: number of SO vertices to write
725 * and number of SO primitives needed.
726 */
727 GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
728
729 /**
730 * Terminate the compute shader.
731 */
732 CS_OPCODE_CS_TERMINATE,
733
734 /**
735 * GLSL barrier()
736 */
737 SHADER_OPCODE_BARRIER,
738
739 /**
740 * Calculate the high 32-bits of a 32x32 multiply.
741 */
742 SHADER_OPCODE_MULH,
743
744 /**
745 * A MOV that uses VxH indirect addressing.
746 *
747 * Source 0: A register to start from (HW_REG).
748 * Source 1: An indirect offset (in bytes, UD GRF).
749 * Source 2: The length of the region that could be accessed (in bytes,
750 * UD immediate).
751 */
752 SHADER_OPCODE_MOV_INDIRECT,
753
754 VEC4_OPCODE_URB_READ,
755 TCS_OPCODE_GET_INSTANCE_ID,
756 TCS_OPCODE_URB_WRITE,
757 TCS_OPCODE_SET_INPUT_URB_OFFSETS,
758 TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
759 TCS_OPCODE_GET_PRIMITIVE_ID,
760 TCS_OPCODE_CREATE_BARRIER_HEADER,
761 TCS_OPCODE_SRC0_010_IS_ZERO,
762 TCS_OPCODE_RELEASE_INPUT,
763 TCS_OPCODE_THREAD_END,
764
765 TES_OPCODE_GET_PRIMITIVE_ID,
766 TES_OPCODE_CREATE_INPUT_READ_HEADER,
767 TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
768 };
769
770 enum brw_urb_write_flags {
771 BRW_URB_WRITE_NO_FLAGS = 0,
772
773 /**
774 * Causes a new URB entry to be allocated, and its address stored in the
775 * destination register (gen < 7).
776 */
777 BRW_URB_WRITE_ALLOCATE = 0x1,
778
779 /**
780 * Causes the current URB entry to be deallocated (gen < 7).
781 */
782 BRW_URB_WRITE_UNUSED = 0x2,
783
784 /**
785 * Causes the thread to terminate.
786 */
787 BRW_URB_WRITE_EOT = 0x4,
788
789 /**
790 * Indicates that the given URB entry is complete, and may be sent further
791 * down the 3D pipeline (gen < 7).
792 */
793 BRW_URB_WRITE_COMPLETE = 0x8,
794
795 /**
796 * Indicates that an additional offset (which may be different for the two
797 * vec4 slots) is stored in the message header (gen == 7).
798 */
799 BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
800
801 /**
802 * Indicates that the channel masks in the URB_WRITE message header should
803 * not be overridden to 0xff (gen == 7).
804 */
805 BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
806
807 /**
808 * Indicates that the data should be sent to the URB using the
809 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This
810 * causes offsets to be interpreted as multiples of an OWORD instead of an
811 * HWORD, and only allows one OWORD to be written.
812 */
813 BRW_URB_WRITE_OWORD = 0x40,
814
815 /**
816 * Convenient combination of flags: end the thread while simultaneously
817 * marking the given URB entry as complete.
818 */
819 BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
820
821 /**
822 * Convenient combination of flags: mark the given URB entry as complete
823 * and simultaneously allocate a new one.
824 */
825 BRW_URB_WRITE_ALLOCATE_COMPLETE =
826 BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
827 };
828
829 enum fb_write_logical_srcs {
830 FB_WRITE_LOGICAL_SRC_COLOR0, /* REQUIRED */
831 FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */
832 FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
833 FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */
834 FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GEN4-5: passthrough from thread */
835 FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
836 FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */
837 FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */
838 FB_WRITE_LOGICAL_NUM_SRCS
839 };
840
841 enum tex_logical_srcs {
842 /** Texture coordinates */
843 TEX_LOGICAL_SRC_COORDINATE,
844 /** Shadow comparator */
845 TEX_LOGICAL_SRC_SHADOW_C,
846 /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
847 TEX_LOGICAL_SRC_LOD,
848 /** dPdy if the operation takes explicit derivatives */
849 TEX_LOGICAL_SRC_LOD2,
850 /** Min LOD */
851 TEX_LOGICAL_SRC_MIN_LOD,
852 /** Sample index */
853 TEX_LOGICAL_SRC_SAMPLE_INDEX,
854 /** MCS data */
855 TEX_LOGICAL_SRC_MCS,
856 /** REQUIRED: Texture surface index */
857 TEX_LOGICAL_SRC_SURFACE,
858 /** Texture sampler index */
859 TEX_LOGICAL_SRC_SAMPLER,
860 /** Texture surface bindless handle */
861 TEX_LOGICAL_SRC_SURFACE_HANDLE,
862 /** Texture sampler bindless handle */
863 TEX_LOGICAL_SRC_SAMPLER_HANDLE,
864 /** Texel offset for gathers */
865 TEX_LOGICAL_SRC_TG4_OFFSET,
866 /** REQUIRED: Number of coordinate components (as UD immediate) */
867 TEX_LOGICAL_SRC_COORD_COMPONENTS,
868 /** REQUIRED: Number of derivative components (as UD immediate) */
869 TEX_LOGICAL_SRC_GRAD_COMPONENTS,
870
871 TEX_LOGICAL_NUM_SRCS,
872 };
873
874 enum surface_logical_srcs {
875 /** Surface binding table index */
876 SURFACE_LOGICAL_SRC_SURFACE,
877 /** Surface bindless handle */
878 SURFACE_LOGICAL_SRC_SURFACE_HANDLE,
879 /** Surface address; could be multi-dimensional for typed opcodes */
880 SURFACE_LOGICAL_SRC_ADDRESS,
881 /** Data to be written or used in an atomic op */
882 SURFACE_LOGICAL_SRC_DATA,
883 /** Surface number of dimensions. Affects the size of ADDRESS */
884 SURFACE_LOGICAL_SRC_IMM_DIMS,
885 /** Per-opcode immediate argument. For atomics, this is the atomic opcode */
886 SURFACE_LOGICAL_SRC_IMM_ARG,
887
888 SURFACE_LOGICAL_NUM_SRCS
889 };
890
891 #ifdef __cplusplus
892 /**
893 * Allow brw_urb_write_flags enums to be ORed together.
894 */
895 inline brw_urb_write_flags
896 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
897 {
898 return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
899 static_cast<int>(y));
900 }
901 #endif
902
903 enum PACKED brw_predicate {
904 BRW_PREDICATE_NONE = 0,
905 BRW_PREDICATE_NORMAL = 1,
906 BRW_PREDICATE_ALIGN1_ANYV = 2,
907 BRW_PREDICATE_ALIGN1_ALLV = 3,
908 BRW_PREDICATE_ALIGN1_ANY2H = 4,
909 BRW_PREDICATE_ALIGN1_ALL2H = 5,
910 BRW_PREDICATE_ALIGN1_ANY4H = 6,
911 BRW_PREDICATE_ALIGN1_ALL4H = 7,
912 BRW_PREDICATE_ALIGN1_ANY8H = 8,
913 BRW_PREDICATE_ALIGN1_ALL8H = 9,
914 BRW_PREDICATE_ALIGN1_ANY16H = 10,
915 BRW_PREDICATE_ALIGN1_ALL16H = 11,
916 BRW_PREDICATE_ALIGN1_ANY32H = 12,
917 BRW_PREDICATE_ALIGN1_ALL32H = 13,
918 BRW_PREDICATE_ALIGN16_REPLICATE_X = 2,
919 BRW_PREDICATE_ALIGN16_REPLICATE_Y = 3,
920 BRW_PREDICATE_ALIGN16_REPLICATE_Z = 4,
921 BRW_PREDICATE_ALIGN16_REPLICATE_W = 5,
922 BRW_PREDICATE_ALIGN16_ANY4H = 6,
923 BRW_PREDICATE_ALIGN16_ALL4H = 7,
924 };
925
926 enum PACKED brw_reg_file {
927 BRW_ARCHITECTURE_REGISTER_FILE = 0,
928 BRW_GENERAL_REGISTER_FILE = 1,
929 BRW_MESSAGE_REGISTER_FILE = 2,
930 BRW_IMMEDIATE_VALUE = 3,
931
932 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
933 FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
934 MRF = BRW_MESSAGE_REGISTER_FILE,
935 IMM = BRW_IMMEDIATE_VALUE,
936
937 /* These are not hardware values */
938 VGRF,
939 ATTR,
940 UNIFORM, /* prog_data->params[reg] */
941 BAD_FILE,
942 };
943
944 enum PACKED gen10_align1_3src_reg_file {
945 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0,
946 BRW_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */
947 BRW_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */
948 };
949
950 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction
951 * word is "Execution Datatype" which controls whether the instruction operates
952 * on float or integer types. The register arguments have fields that offer
953 * more fine control their respective types.
954 */
955 enum PACKED gen10_align1_3src_exec_type {
956 BRW_ALIGN1_3SRC_EXEC_TYPE_INT = 0,
957 BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
958 };
959
960 #define BRW_ARF_NULL 0x00
961 #define BRW_ARF_ADDRESS 0x10
962 #define BRW_ARF_ACCUMULATOR 0x20
963 #define BRW_ARF_FLAG 0x30
964 #define BRW_ARF_MASK 0x40
965 #define BRW_ARF_MASK_STACK 0x50
966 #define BRW_ARF_MASK_STACK_DEPTH 0x60
967 #define BRW_ARF_STATE 0x70
968 #define BRW_ARF_CONTROL 0x80
969 #define BRW_ARF_NOTIFICATION_COUNT 0x90
970 #define BRW_ARF_IP 0xA0
971 #define BRW_ARF_TDR 0xB0
972 #define BRW_ARF_TIMESTAMP 0xC0
973
974 #define BRW_MRF_COMPR4 (1 << 7)
975
976 #define BRW_AMASK 0
977 #define BRW_IMASK 1
978 #define BRW_LMASK 2
979 #define BRW_CMASK 3
980
981
982
983 #define BRW_THREAD_NORMAL 0
984 #define BRW_THREAD_ATOMIC 1
985 #define BRW_THREAD_SWITCH 2
986
987 enum PACKED brw_vertical_stride {
988 BRW_VERTICAL_STRIDE_0 = 0,
989 BRW_VERTICAL_STRIDE_1 = 1,
990 BRW_VERTICAL_STRIDE_2 = 2,
991 BRW_VERTICAL_STRIDE_4 = 3,
992 BRW_VERTICAL_STRIDE_8 = 4,
993 BRW_VERTICAL_STRIDE_16 = 5,
994 BRW_VERTICAL_STRIDE_32 = 6,
995 BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
996 };
997
998 enum PACKED gen10_align1_3src_vertical_stride {
999 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
1000 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
1001 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2,
1002 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,
1003 };
1004
1005 enum PACKED brw_width {
1006 BRW_WIDTH_1 = 0,
1007 BRW_WIDTH_2 = 1,
1008 BRW_WIDTH_4 = 2,
1009 BRW_WIDTH_8 = 3,
1010 BRW_WIDTH_16 = 4,
1011 };
1012
1013 /**
1014 * Message target: Shared Function ID for where to SEND a message.
1015 *
1016 * These are enumerated in the ISA reference under "send - Send Message".
1017 * In particular, see the following tables:
1018 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
1019 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
1020 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
1021 */
1022 enum brw_message_target {
1023 BRW_SFID_NULL = 0,
1024 BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */
1025 BRW_SFID_SAMPLER = 2,
1026 BRW_SFID_MESSAGE_GATEWAY = 3,
1027 BRW_SFID_DATAPORT_READ = 4,
1028 BRW_SFID_DATAPORT_WRITE = 5,
1029 BRW_SFID_URB = 6,
1030 BRW_SFID_THREAD_SPAWNER = 7,
1031 BRW_SFID_VME = 8,
1032
1033 GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4,
1034 GEN6_SFID_DATAPORT_RENDER_CACHE = 5,
1035 GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
1036
1037 GEN7_SFID_DATAPORT_DATA_CACHE = 10,
1038 GEN7_SFID_PIXEL_INTERPOLATOR = 11,
1039 HSW_SFID_DATAPORT_DATA_CACHE_1 = 12,
1040 HSW_SFID_CRE = 13,
1041 };
1042
1043 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
1044
1045 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
1046 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
1047 #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
1048
1049 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
1050 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
1051 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
1052 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
1053 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
1054 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
1055 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
1056 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
1057 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
1058 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
1059 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
1060 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
1061 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1
1062 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
1063 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
1064 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
1065 #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
1066 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
1067
1068 #define GEN5_SAMPLER_MESSAGE_SAMPLE 0
1069 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
1070 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2
1071 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3
1072 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4
1073 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
1074 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
1075 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
1076 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
1077 #define GEN5_SAMPLER_MESSAGE_LOD 9
1078 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
1079 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
1080 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
1081 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
1082 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
1083 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
1084 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ 24
1085 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ 25
1086 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ 26
1087 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28
1088 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
1089 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
1090 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
1091
1092 /* for GEN5 only */
1093 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
1094 #define BRW_SAMPLER_SIMD_MODE_SIMD8 1
1095 #define BRW_SAMPLER_SIMD_MODE_SIMD16 2
1096 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
1097
1098 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
1099 * behavior by setting bit 22 of dword 2 in the message header. */
1100 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D 0
1101 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22)
1102
1103 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
1104 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
1105 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
1106 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
1107 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
1108 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n) \
1109 ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \
1110 (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \
1111 (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \
1112 (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \
1113 (abort(), ~0))
1114
1115 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
1116 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
1117
1118 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
1119 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
1120
1121 /* This one stays the same across generations. */
1122 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
1123 /* GEN4 */
1124 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
1125 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
1126 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
1127 /* G45, GEN5 */
1128 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1129 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1130 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3
1131 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1132 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1133 /* GEN6 */
1134 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1135 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1136 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1137 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
1138 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1139
1140 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
1141 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
1142 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
1143
1144 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
1145 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
1146 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
1147 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
1148 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
1149
1150 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
1151 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
1152 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2
1153 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
1154 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
1155 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
1156 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
1157
1158 /* GEN6 */
1159 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
1160 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
1161 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9
1162 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10
1163 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11
1164 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12
1165 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
1166 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
1167
1168 /* GEN7 */
1169 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ 4
1170 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ 5
1171 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP 6
1172 #define GEN7_DATAPORT_RC_MEMORY_FENCE 7
1173 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10
1174 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE 12
1175 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE 13
1176 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0
1177 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1
1178 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2
1179 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3
1180 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4
1181 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5
1182 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6
1183 #define GEN7_DATAPORT_DC_MEMORY_FENCE 7
1184 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8
1185 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10
1186 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11
1187 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
1188 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
1189
1190 #define GEN7_DATAPORT_SCRATCH_READ ((1 << 18) | \
1191 (0 << 17))
1192 #define GEN7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \
1193 (1 << 17))
1194 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12
1195
1196 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0
1197 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1
1198 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID 2
1199 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3
1200
1201 /* HSW */
1202 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0
1203 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1
1204 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2
1205 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3
1206 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4
1207 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7
1208 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8
1209 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10
1210 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11
1211 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12
1212
1213 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1
1214 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2
1215 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3
1216 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4
1217 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5
1218 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6
1219 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7
1220 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9
1221 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10
1222 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11
1223 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12
1224 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13
1225 #define GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ 0x10
1226 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ 0x11
1227 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP 0x12
1228 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE 0x19
1229 #define GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE 0x1a
1230 #define GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP 0x1b
1231 #define GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP 0x1d
1232
1233 /* GEN9 */
1234 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE 12
1235 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ 13
1236
1237 /* A64 scattered message subtype */
1238 #define GEN8_A64_SCATTERED_SUBTYPE_BYTE 0
1239 #define GEN8_A64_SCATTERED_SUBTYPE_DWORD 1
1240 #define GEN8_A64_SCATTERED_SUBTYPE_QWORD 2
1241 #define GEN8_A64_SCATTERED_SUBTYPE_HWORD 3
1242
1243 /* Dataport special binding table indices: */
1244 #define BRW_BTI_STATELESS 255
1245 #define GEN7_BTI_SLM 254
1246 /* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the
1247 * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW,
1248 * CHV and at least some pre-production steppings of SKL due to
1249 * WaForceEnableNonCoherent, HDC memory access may have been overridden by the
1250 * kernel to be non-coherent (matching the behavior of the same BTI on
1251 * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253.
1252 */
1253 #define GEN8_BTI_STATELESS_IA_COHERENT 255
1254 #define GEN8_BTI_STATELESS_NON_COHERENT 253
1255 #define GEN9_BTI_BINDLESS 252
1256
1257 /* Dataport atomic operations for Untyped Atomic Integer Operation message
1258 * (and others).
1259 */
1260 #define BRW_AOP_AND 1
1261 #define BRW_AOP_OR 2
1262 #define BRW_AOP_XOR 3
1263 #define BRW_AOP_MOV 4
1264 #define BRW_AOP_INC 5
1265 #define BRW_AOP_DEC 6
1266 #define BRW_AOP_ADD 7
1267 #define BRW_AOP_SUB 8
1268 #define BRW_AOP_REVSUB 9
1269 #define BRW_AOP_IMAX 10
1270 #define BRW_AOP_IMIN 11
1271 #define BRW_AOP_UMAX 12
1272 #define BRW_AOP_UMIN 13
1273 #define BRW_AOP_CMPWR 14
1274 #define BRW_AOP_PREDEC 15
1275
1276 /* Dataport atomic operations for Untyped Atomic Float Operation message. */
1277 #define BRW_AOP_FMAX 1
1278 #define BRW_AOP_FMIN 2
1279 #define BRW_AOP_FCMPWR 3
1280
1281 #define BRW_MATH_FUNCTION_INV 1
1282 #define BRW_MATH_FUNCTION_LOG 2
1283 #define BRW_MATH_FUNCTION_EXP 3
1284 #define BRW_MATH_FUNCTION_SQRT 4
1285 #define BRW_MATH_FUNCTION_RSQ 5
1286 #define BRW_MATH_FUNCTION_SIN 6
1287 #define BRW_MATH_FUNCTION_COS 7
1288 #define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */
1289 #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
1290 #define BRW_MATH_FUNCTION_POW 10
1291 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
1292 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
1293 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
1294 #define GEN8_MATH_FUNCTION_INVM 14
1295 #define GEN8_MATH_FUNCTION_RSQRTM 15
1296
1297 #define BRW_MATH_INTEGER_UNSIGNED 0
1298 #define BRW_MATH_INTEGER_SIGNED 1
1299
1300 #define BRW_MATH_PRECISION_FULL 0
1301 #define BRW_MATH_PRECISION_PARTIAL 1
1302
1303 #define BRW_MATH_SATURATE_NONE 0
1304 #define BRW_MATH_SATURATE_SATURATE 1
1305
1306 #define BRW_MATH_DATA_VECTOR 0
1307 #define BRW_MATH_DATA_SCALAR 1
1308
1309 #define BRW_URB_OPCODE_WRITE_HWORD 0
1310 #define BRW_URB_OPCODE_WRITE_OWORD 1
1311 #define BRW_URB_OPCODE_READ_HWORD 2
1312 #define BRW_URB_OPCODE_READ_OWORD 3
1313 #define GEN7_URB_OPCODE_ATOMIC_MOV 4
1314 #define GEN7_URB_OPCODE_ATOMIC_INC 5
1315 #define GEN8_URB_OPCODE_ATOMIC_ADD 6
1316 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1317 #define GEN8_URB_OPCODE_SIMD8_READ 8
1318
1319 #define BRW_URB_SWIZZLE_NONE 0
1320 #define BRW_URB_SWIZZLE_INTERLEAVE 1
1321 #define BRW_URB_SWIZZLE_TRANSPOSE 2
1322
1323 #define BRW_SCRATCH_SPACE_SIZE_1K 0
1324 #define BRW_SCRATCH_SPACE_SIZE_2K 1
1325 #define BRW_SCRATCH_SPACE_SIZE_4K 2
1326 #define BRW_SCRATCH_SPACE_SIZE_8K 3
1327 #define BRW_SCRATCH_SPACE_SIZE_16K 4
1328 #define BRW_SCRATCH_SPACE_SIZE_32K 5
1329 #define BRW_SCRATCH_SPACE_SIZE_64K 6
1330 #define BRW_SCRATCH_SPACE_SIZE_128K 7
1331 #define BRW_SCRATCH_SPACE_SIZE_256K 8
1332 #define BRW_SCRATCH_SPACE_SIZE_512K 9
1333 #define BRW_SCRATCH_SPACE_SIZE_1M 10
1334 #define BRW_SCRATCH_SPACE_SIZE_2M 11
1335
1336 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0
1337 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1
1338 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2
1339 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3
1340 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4
1341 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1342 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6
1343
1344
1345 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1346 * is 2^9, or 512. It's counted in multiples of 64 bytes.
1347 *
1348 * Identical for VS, DS, and HS.
1349 */
1350 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
1351 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64)
1352 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64)
1353 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64)
1354
1355 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1356 * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1357 */
1358 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128)
1359
1360 /* GS Thread Payload
1361 */
1362
1363 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1364 * counted in multiples of 16 bytes.
1365 */
1366 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16)
1367
1368
1369 /* R0 */
1370 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
1371
1372 /* CR0.0[5:4] Floating-Point Rounding Modes
1373 * Skylake PRM, Volume 7 Part 1, "Control Register", page 756
1374 */
1375
1376 #define BRW_CR0_RND_MODE_MASK 0x30
1377 #define BRW_CR0_RND_MODE_SHIFT 4
1378
1379 enum PACKED brw_rnd_mode {
1380 BRW_RND_MODE_RTNE = 0, /* Round to Nearest or Even */
1381 BRW_RND_MODE_RU = 1, /* Round Up, toward +inf */
1382 BRW_RND_MODE_RD = 2, /* Round Down, toward -inf */
1383 BRW_RND_MODE_RTZ = 3, /* Round Toward Zero */
1384 BRW_RND_MODE_UNSPECIFIED, /* Unspecified rounding mode */
1385 };
1386
1387 #define BRW_CR0_FP64_DENORM_PRESERVE (1 << 6)
1388 #define BRW_CR0_FP32_DENORM_PRESERVE (1 << 7)
1389 #define BRW_CR0_FP16_DENORM_PRESERVE (1 << 10)
1390
1391 #define BRW_CR0_FP_MODE_MASK (BRW_CR0_FP64_DENORM_PRESERVE | \
1392 BRW_CR0_FP32_DENORM_PRESERVE | \
1393 BRW_CR0_FP16_DENORM_PRESERVE | \
1394 BRW_CR0_RND_MODE_MASK)
1395
1396 /* MDC_DS - Data Size Message Descriptor Control Field
1397 * Skylake PRM, Volume 2d, page 129
1398 *
1399 * Specifies the number of Bytes to be read or written per Dword used at
1400 * byte_scattered read/write and byte_scaled read/write messages.
1401 */
1402 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE 0
1403 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD 1
1404 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2
1405
1406 #endif /* BRW_EU_DEFINES_H */