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i965: Move SF compilation to the compiler
[mesa.git] / src / intel / compiler / brw_eu_defines.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32 #ifndef BRW_EU_DEFINES_H
33 #define BRW_EU_DEFINES_H
34
35 #include "util/macros.h"
36
37 /* The following hunk, up-to "Execution Unit" is used by both the
38 * intel/compiler and i965 codebase. */
39
40 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
41 /* Using the GNU statement expression extension */
42 #define SET_FIELD(value, field) \
43 ({ \
44 uint32_t fieldval = (value) << field ## _SHIFT; \
45 assert((fieldval & ~ field ## _MASK) == 0); \
46 fieldval & field ## _MASK; \
47 })
48
49 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
50 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
51
52 #define _3DPRIM_POINTLIST 0x01
53 #define _3DPRIM_LINELIST 0x02
54 #define _3DPRIM_LINESTRIP 0x03
55 #define _3DPRIM_TRILIST 0x04
56 #define _3DPRIM_TRISTRIP 0x05
57 #define _3DPRIM_TRIFAN 0x06
58 #define _3DPRIM_QUADLIST 0x07
59 #define _3DPRIM_QUADSTRIP 0x08
60 #define _3DPRIM_LINELIST_ADJ 0x09 /* G45+ */
61 #define _3DPRIM_LINESTRIP_ADJ 0x0A /* G45+ */
62 #define _3DPRIM_TRILIST_ADJ 0x0B /* G45+ */
63 #define _3DPRIM_TRISTRIP_ADJ 0x0C /* G45+ */
64 #define _3DPRIM_TRISTRIP_REVERSE 0x0D
65 #define _3DPRIM_POLYGON 0x0E
66 #define _3DPRIM_RECTLIST 0x0F
67 #define _3DPRIM_LINELOOP 0x10
68 #define _3DPRIM_POINTLIST_BF 0x11
69 #define _3DPRIM_LINESTRIP_CONT 0x12
70 #define _3DPRIM_LINESTRIP_BF 0x13
71 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
72 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x16
73 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
74
75 /* Bitfields for the URB_WRITE message, DW2 of message header: */
76 #define URB_WRITE_PRIM_END 0x1
77 #define URB_WRITE_PRIM_START 0x2
78 #define URB_WRITE_PRIM_TYPE_SHIFT 2
79
80 #define BRW_SPRITE_POINT_ENABLE 16
81
82 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
83 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
84
85 /* Execution Unit (EU) defines
86 */
87
88 #define BRW_ALIGN_1 0
89 #define BRW_ALIGN_16 1
90
91 #define BRW_ADDRESS_DIRECT 0
92 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
93
94 #define BRW_CHANNEL_X 0
95 #define BRW_CHANNEL_Y 1
96 #define BRW_CHANNEL_Z 2
97 #define BRW_CHANNEL_W 3
98
99 enum brw_compression {
100 BRW_COMPRESSION_NONE = 0,
101 BRW_COMPRESSION_2NDHALF = 1,
102 BRW_COMPRESSION_COMPRESSED = 2,
103 };
104
105 #define GEN6_COMPRESSION_1Q 0
106 #define GEN6_COMPRESSION_2Q 1
107 #define GEN6_COMPRESSION_3Q 2
108 #define GEN6_COMPRESSION_4Q 3
109 #define GEN6_COMPRESSION_1H 0
110 #define GEN6_COMPRESSION_2H 2
111
112 enum PACKED brw_conditional_mod {
113 BRW_CONDITIONAL_NONE = 0,
114 BRW_CONDITIONAL_Z = 1,
115 BRW_CONDITIONAL_NZ = 2,
116 BRW_CONDITIONAL_EQ = 1, /* Z */
117 BRW_CONDITIONAL_NEQ = 2, /* NZ */
118 BRW_CONDITIONAL_G = 3,
119 BRW_CONDITIONAL_GE = 4,
120 BRW_CONDITIONAL_L = 5,
121 BRW_CONDITIONAL_LE = 6,
122 BRW_CONDITIONAL_R = 7, /* Gen <= 5 */
123 BRW_CONDITIONAL_O = 8,
124 BRW_CONDITIONAL_U = 9,
125 };
126
127 #define BRW_DEBUG_NONE 0
128 #define BRW_DEBUG_BREAKPOINT 1
129
130 #define BRW_DEPENDENCY_NORMAL 0
131 #define BRW_DEPENDENCY_NOTCLEARED 1
132 #define BRW_DEPENDENCY_NOTCHECKED 2
133 #define BRW_DEPENDENCY_DISABLE 3
134
135 enum PACKED brw_execution_size {
136 BRW_EXECUTE_1 = 0,
137 BRW_EXECUTE_2 = 1,
138 BRW_EXECUTE_4 = 2,
139 BRW_EXECUTE_8 = 3,
140 BRW_EXECUTE_16 = 4,
141 BRW_EXECUTE_32 = 5,
142 };
143
144 enum PACKED brw_horizontal_stride {
145 BRW_HORIZONTAL_STRIDE_0 = 0,
146 BRW_HORIZONTAL_STRIDE_1 = 1,
147 BRW_HORIZONTAL_STRIDE_2 = 2,
148 BRW_HORIZONTAL_STRIDE_4 = 3,
149 };
150
151 #define BRW_INSTRUCTION_NORMAL 0
152 #define BRW_INSTRUCTION_SATURATE 1
153
154 #define BRW_MASK_ENABLE 0
155 #define BRW_MASK_DISABLE 1
156
157 /** @{
158 *
159 * Gen6 has replaced "mask enable/disable" with WECtrl, which is
160 * effectively the same but much simpler to think about. Now, there
161 * are two contributors ANDed together to whether channels are
162 * executed: The predication on the instruction, and the channel write
163 * enable.
164 */
165 /**
166 * This is the default value. It means that a channel's write enable is set
167 * if the per-channel IP is pointing at this instruction.
168 */
169 #define BRW_WE_NORMAL 0
170 /**
171 * This is used like BRW_MASK_DISABLE, and causes all channels to have
172 * their write enable set. Note that predication still contributes to
173 * whether the channel actually gets written.
174 */
175 #define BRW_WE_ALL 1
176 /** @} */
177
178 enum opcode {
179 /* These are the actual hardware opcodes. */
180 BRW_OPCODE_ILLEGAL = 0,
181 BRW_OPCODE_MOV = 1,
182 BRW_OPCODE_SEL = 2,
183 BRW_OPCODE_MOVI = 3, /**< G45+ */
184 BRW_OPCODE_NOT = 4,
185 BRW_OPCODE_AND = 5,
186 BRW_OPCODE_OR = 6,
187 BRW_OPCODE_XOR = 7,
188 BRW_OPCODE_SHR = 8,
189 BRW_OPCODE_SHL = 9,
190 BRW_OPCODE_DIM = 10, /**< Gen7.5 only */ /* Reused */
191 // BRW_OPCODE_SMOV = 10, /**< Gen8+ */ /* Reused */
192 /* Reserved - 11 */
193 BRW_OPCODE_ASR = 12,
194 /* Reserved - 13-15 */
195 BRW_OPCODE_CMP = 16,
196 BRW_OPCODE_CMPN = 17,
197 BRW_OPCODE_CSEL = 18, /**< Gen8+ */
198 BRW_OPCODE_F32TO16 = 19, /**< Gen7 only */
199 BRW_OPCODE_F16TO32 = 20, /**< Gen7 only */
200 /* Reserved - 21-22 */
201 BRW_OPCODE_BFREV = 23, /**< Gen7+ */
202 BRW_OPCODE_BFE = 24, /**< Gen7+ */
203 BRW_OPCODE_BFI1 = 25, /**< Gen7+ */
204 BRW_OPCODE_BFI2 = 26, /**< Gen7+ */
205 /* Reserved - 27-31 */
206 BRW_OPCODE_JMPI = 32,
207 // BRW_OPCODE_BRD = 33, /**< Gen7+ */
208 BRW_OPCODE_IF = 34,
209 BRW_OPCODE_IFF = 35, /**< Pre-Gen6 */ /* Reused */
210 // BRW_OPCODE_BRC = 35, /**< Gen7+ */ /* Reused */
211 BRW_OPCODE_ELSE = 36,
212 BRW_OPCODE_ENDIF = 37,
213 BRW_OPCODE_DO = 38, /**< Pre-Gen6 */ /* Reused */
214 // BRW_OPCODE_CASE = 38, /**< Gen6 only */ /* Reused */
215 BRW_OPCODE_WHILE = 39,
216 BRW_OPCODE_BREAK = 40,
217 BRW_OPCODE_CONTINUE = 41,
218 BRW_OPCODE_HALT = 42,
219 // BRW_OPCODE_CALLA = 43, /**< Gen7.5+ */
220 // BRW_OPCODE_MSAVE = 44, /**< Pre-Gen6 */ /* Reused */
221 // BRW_OPCODE_CALL = 44, /**< Gen6+ */ /* Reused */
222 // BRW_OPCODE_MREST = 45, /**< Pre-Gen6 */ /* Reused */
223 // BRW_OPCODE_RET = 45, /**< Gen6+ */ /* Reused */
224 // BRW_OPCODE_PUSH = 46, /**< Pre-Gen6 */ /* Reused */
225 // BRW_OPCODE_FORK = 46, /**< Gen6 only */ /* Reused */
226 // BRW_OPCODE_GOTO = 46, /**< Gen8+ */ /* Reused */
227 // BRW_OPCODE_POP = 47, /**< Pre-Gen6 */
228 BRW_OPCODE_WAIT = 48,
229 BRW_OPCODE_SEND = 49,
230 BRW_OPCODE_SENDC = 50,
231 BRW_OPCODE_SENDS = 51, /**< Gen9+ */
232 BRW_OPCODE_SENDSC = 52, /**< Gen9+ */
233 /* Reserved 53-55 */
234 BRW_OPCODE_MATH = 56, /**< Gen6+ */
235 /* Reserved 57-63 */
236 BRW_OPCODE_ADD = 64,
237 BRW_OPCODE_MUL = 65,
238 BRW_OPCODE_AVG = 66,
239 BRW_OPCODE_FRC = 67,
240 BRW_OPCODE_RNDU = 68,
241 BRW_OPCODE_RNDD = 69,
242 BRW_OPCODE_RNDE = 70,
243 BRW_OPCODE_RNDZ = 71,
244 BRW_OPCODE_MAC = 72,
245 BRW_OPCODE_MACH = 73,
246 BRW_OPCODE_LZD = 74,
247 BRW_OPCODE_FBH = 75, /**< Gen7+ */
248 BRW_OPCODE_FBL = 76, /**< Gen7+ */
249 BRW_OPCODE_CBIT = 77, /**< Gen7+ */
250 BRW_OPCODE_ADDC = 78, /**< Gen7+ */
251 BRW_OPCODE_SUBB = 79, /**< Gen7+ */
252 BRW_OPCODE_SAD2 = 80,
253 BRW_OPCODE_SADA2 = 81,
254 /* Reserved 82-83 */
255 BRW_OPCODE_DP4 = 84,
256 BRW_OPCODE_DPH = 85,
257 BRW_OPCODE_DP3 = 86,
258 BRW_OPCODE_DP2 = 87,
259 /* Reserved 88 */
260 BRW_OPCODE_LINE = 89,
261 BRW_OPCODE_PLN = 90, /**< G45+ */
262 BRW_OPCODE_MAD = 91, /**< Gen6+ */
263 BRW_OPCODE_LRP = 92, /**< Gen6+ */
264 // BRW_OPCODE_MADM = 93, /**< Gen8+ */
265 /* Reserved 94-124 */
266 BRW_OPCODE_NENOP = 125, /**< G45 only */
267 BRW_OPCODE_NOP = 126,
268 /* Reserved 127 */
269
270 /* These are compiler backend opcodes that get translated into other
271 * instructions.
272 */
273 FS_OPCODE_FB_WRITE = 128,
274
275 /**
276 * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
277 * individual sources instead of as a single payload blob. The
278 * position/ordering of the arguments are defined by the enum
279 * fb_write_logical_srcs.
280 */
281 FS_OPCODE_FB_WRITE_LOGICAL,
282
283 FS_OPCODE_REP_FB_WRITE,
284
285 FS_OPCODE_FB_READ,
286 FS_OPCODE_FB_READ_LOGICAL,
287
288 SHADER_OPCODE_RCP,
289 SHADER_OPCODE_RSQ,
290 SHADER_OPCODE_SQRT,
291 SHADER_OPCODE_EXP2,
292 SHADER_OPCODE_LOG2,
293 SHADER_OPCODE_POW,
294 SHADER_OPCODE_INT_QUOTIENT,
295 SHADER_OPCODE_INT_REMAINDER,
296 SHADER_OPCODE_SIN,
297 SHADER_OPCODE_COS,
298
299 /**
300 * Texture sampling opcodes.
301 *
302 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
303 * opcode but instead of taking a single payload blob they expect their
304 * arguments separately as individual sources. The position/ordering of the
305 * arguments are defined by the enum tex_logical_srcs.
306 */
307 SHADER_OPCODE_TEX,
308 SHADER_OPCODE_TEX_LOGICAL,
309 SHADER_OPCODE_TXD,
310 SHADER_OPCODE_TXD_LOGICAL,
311 SHADER_OPCODE_TXF,
312 SHADER_OPCODE_TXF_LOGICAL,
313 SHADER_OPCODE_TXF_LZ,
314 SHADER_OPCODE_TXL,
315 SHADER_OPCODE_TXL_LOGICAL,
316 SHADER_OPCODE_TXL_LZ,
317 SHADER_OPCODE_TXS,
318 SHADER_OPCODE_TXS_LOGICAL,
319 FS_OPCODE_TXB,
320 FS_OPCODE_TXB_LOGICAL,
321 SHADER_OPCODE_TXF_CMS,
322 SHADER_OPCODE_TXF_CMS_LOGICAL,
323 SHADER_OPCODE_TXF_CMS_W,
324 SHADER_OPCODE_TXF_CMS_W_LOGICAL,
325 SHADER_OPCODE_TXF_UMS,
326 SHADER_OPCODE_TXF_UMS_LOGICAL,
327 SHADER_OPCODE_TXF_MCS,
328 SHADER_OPCODE_TXF_MCS_LOGICAL,
329 SHADER_OPCODE_LOD,
330 SHADER_OPCODE_LOD_LOGICAL,
331 SHADER_OPCODE_TG4,
332 SHADER_OPCODE_TG4_LOGICAL,
333 SHADER_OPCODE_TG4_OFFSET,
334 SHADER_OPCODE_TG4_OFFSET_LOGICAL,
335 SHADER_OPCODE_SAMPLEINFO,
336 SHADER_OPCODE_SAMPLEINFO_LOGICAL,
337
338 /**
339 * Combines multiple sources of size 1 into a larger virtual GRF.
340 * For example, parameters for a send-from-GRF message. Or, updating
341 * channels of a size 4 VGRF used to store vec4s such as texturing results.
342 *
343 * This will be lowered into MOVs from each source to consecutive offsets
344 * of the destination VGRF.
345 *
346 * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV,
347 * but still reserves the first channel of the destination VGRF. This can be
348 * used to reserve space for, say, a message header set up by the generators.
349 */
350 SHADER_OPCODE_LOAD_PAYLOAD,
351
352 /**
353 * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
354 * acts intra-channel, obtaining the final value for each channel by
355 * combining the sources values for the same channel, the first source
356 * occupying the lowest bits and the last source occupying the highest
357 * bits.
358 */
359 FS_OPCODE_PACK,
360
361 SHADER_OPCODE_SHADER_TIME_ADD,
362
363 /**
364 * Typed and untyped surface access opcodes.
365 *
366 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
367 * opcode but instead of taking a single payload blob they expect their
368 * arguments separately as individual sources:
369 *
370 * Source 0: [required] Surface coordinates.
371 * Source 1: [optional] Operation source.
372 * Source 2: [required] Surface index.
373 * Source 3: [required] Number of coordinate components (as UD immediate).
374 * Source 4: [required] Opcode-specific control immediate, same as source 2
375 * of the matching non-LOGICAL opcode.
376 */
377 SHADER_OPCODE_UNTYPED_ATOMIC,
378 SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
379 SHADER_OPCODE_UNTYPED_SURFACE_READ,
380 SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
381 SHADER_OPCODE_UNTYPED_SURFACE_WRITE,
382 SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
383
384 SHADER_OPCODE_TYPED_ATOMIC,
385 SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
386 SHADER_OPCODE_TYPED_SURFACE_READ,
387 SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
388 SHADER_OPCODE_TYPED_SURFACE_WRITE,
389 SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
390
391 SHADER_OPCODE_MEMORY_FENCE,
392
393 SHADER_OPCODE_GEN4_SCRATCH_READ,
394 SHADER_OPCODE_GEN4_SCRATCH_WRITE,
395 SHADER_OPCODE_GEN7_SCRATCH_READ,
396
397 /**
398 * Gen8+ SIMD8 URB Read messages.
399 */
400 SHADER_OPCODE_URB_READ_SIMD8,
401 SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
402
403 SHADER_OPCODE_URB_WRITE_SIMD8,
404 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
405 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
406 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
407
408 /**
409 * Return the index of an arbitrary live channel (i.e. one of the channels
410 * enabled in the current execution mask) and assign it to the first
411 * component of the destination. Expected to be used as input for the
412 * BROADCAST pseudo-opcode.
413 */
414 SHADER_OPCODE_FIND_LIVE_CHANNEL,
415
416 /**
417 * Pick the channel from its first source register given by the index
418 * specified as second source. Useful for variable indexing of surfaces.
419 *
420 * Note that because the result of this instruction is by definition
421 * uniform and it can always be splatted to multiple channels using a
422 * scalar regioning mode, only the first channel of the destination region
423 * is guaranteed to be updated, which implies that BROADCAST instructions
424 * should usually be marked force_writemask_all.
425 */
426 SHADER_OPCODE_BROADCAST,
427
428 VEC4_OPCODE_MOV_BYTES,
429 VEC4_OPCODE_PACK_BYTES,
430 VEC4_OPCODE_UNPACK_UNIFORM,
431 VEC4_OPCODE_DOUBLE_TO_F32,
432 VEC4_OPCODE_DOUBLE_TO_D32,
433 VEC4_OPCODE_DOUBLE_TO_U32,
434 VEC4_OPCODE_TO_DOUBLE,
435 VEC4_OPCODE_PICK_LOW_32BIT,
436 VEC4_OPCODE_PICK_HIGH_32BIT,
437 VEC4_OPCODE_SET_LOW_32BIT,
438 VEC4_OPCODE_SET_HIGH_32BIT,
439
440 FS_OPCODE_DDX_COARSE,
441 FS_OPCODE_DDX_FINE,
442 /**
443 * Compute dFdy(), dFdyCoarse(), or dFdyFine().
444 */
445 FS_OPCODE_DDY_COARSE,
446 FS_OPCODE_DDY_FINE,
447 FS_OPCODE_CINTERP,
448 FS_OPCODE_LINTERP,
449 FS_OPCODE_PIXEL_X,
450 FS_OPCODE_PIXEL_Y,
451 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
452 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
453 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
454 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,
455 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
456 FS_OPCODE_GET_BUFFER_SIZE,
457 FS_OPCODE_MOV_DISPATCH_TO_FLAGS,
458 FS_OPCODE_DISCARD_JUMP,
459 FS_OPCODE_SET_SAMPLE_ID,
460 FS_OPCODE_PACK_HALF_2x16_SPLIT,
461 FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X,
462 FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y,
463 FS_OPCODE_PLACEHOLDER_HALT,
464 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
465 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
466 FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
467
468 VS_OPCODE_URB_WRITE,
469 VS_OPCODE_PULL_CONSTANT_LOAD,
470 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
471 VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
472
473 VS_OPCODE_GET_BUFFER_SIZE,
474
475 VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
476
477 /**
478 * Write geometry shader output data to the URB.
479 *
480 * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
481 * R0 to the first MRF. This allows the geometry shader to override the
482 * "Slot {0,1} Offset" fields in the message header.
483 */
484 GS_OPCODE_URB_WRITE,
485
486 /**
487 * Write geometry shader output data to the URB and request a new URB
488 * handle (gen6).
489 *
490 * This opcode doesn't do an implied move from R0 to the first MRF.
491 */
492 GS_OPCODE_URB_WRITE_ALLOCATE,
493
494 /**
495 * Terminate the geometry shader thread by doing an empty URB write.
496 *
497 * This opcode doesn't do an implied move from R0 to the first MRF. This
498 * allows the geometry shader to override the "GS Number of Output Vertices
499 * for Slot {0,1}" fields in the message header.
500 */
501 GS_OPCODE_THREAD_END,
502
503 /**
504 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
505 *
506 * - dst is the MRF containing the message header.
507 *
508 * - src0.x indicates which portion of the URB should be written to (e.g. a
509 * vertex number)
510 *
511 * - src1 is an immediate multiplier which will be applied to src0
512 * (e.g. the size of a single vertex in the URB).
513 *
514 * Note: the hardware will apply this offset *in addition to* the offset in
515 * vec4_instruction::offset.
516 */
517 GS_OPCODE_SET_WRITE_OFFSET,
518
519 /**
520 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
521 * URB_WRITE message header.
522 *
523 * - dst is the MRF containing the message header.
524 *
525 * - src0.x is the vertex count. The upper 16 bits will be ignored.
526 */
527 GS_OPCODE_SET_VERTEX_COUNT,
528
529 /**
530 * Set DWORD 2 of dst to the value in src.
531 */
532 GS_OPCODE_SET_DWORD_2,
533
534 /**
535 * Prepare the dst register for storage in the "Channel Mask" fields of a
536 * URB_WRITE message header.
537 *
538 * DWORD 4 of dst is shifted left by 4 bits, so that later,
539 * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
540 * final channel mask.
541 *
542 * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
543 * form the final channel mask, DWORDs 0 and 4 of the dst register must not
544 * have any extraneous bits set prior to execution of this opcode (that is,
545 * they should be in the range 0x0 to 0xf).
546 */
547 GS_OPCODE_PREPARE_CHANNEL_MASKS,
548
549 /**
550 * Set the "Channel Mask" fields of a URB_WRITE message header.
551 *
552 * - dst is the MRF containing the message header.
553 *
554 * - src.x is the channel mask, as prepared by
555 * GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to
556 * form the final channel mask.
557 */
558 GS_OPCODE_SET_CHANNEL_MASKS,
559
560 /**
561 * Get the "Instance ID" fields from the payload.
562 *
563 * - dst is the GRF for gl_InvocationID.
564 */
565 GS_OPCODE_GET_INSTANCE_ID,
566
567 /**
568 * Send a FF_SYNC message to allocate initial URB handles (gen6).
569 *
570 * - dst will be used as the writeback register for the FF_SYNC operation.
571 *
572 * - src0 is the number of primitives written.
573 *
574 * - src1 is the value to hold in M0.0: number of SO vertices to write
575 * and number of SO primitives needed. Its value will be overwritten
576 * with the SVBI values if transform feedback is enabled.
577 *
578 * Note: This opcode uses an implicit MRF register for the ff_sync message
579 * header, so the caller is expected to set inst->base_mrf and initialize
580 * that MRF register to r0. This opcode will also write to this MRF register
581 * to include the allocated URB handle so it can then be reused directly as
582 * the header in the URB write operation we are allocating the handle for.
583 */
584 GS_OPCODE_FF_SYNC,
585
586 /**
587 * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
588 * register.
589 *
590 * - dst is the GRF where PrimitiveID information will be moved.
591 */
592 GS_OPCODE_SET_PRIMITIVE_ID,
593
594 /**
595 * Write transform feedback data to the SVB by sending a SVB WRITE message.
596 * Used in gen6.
597 *
598 * - dst is the MRF register containing the message header.
599 *
600 * - src0 is the register where the vertex data is going to be copied from.
601 *
602 * - src1 is the destination register when write commit occurs.
603 */
604 GS_OPCODE_SVB_WRITE,
605
606 /**
607 * Set destination index in the SVB write message payload (M0.5). Used
608 * in gen6 for transform feedback.
609 *
610 * - dst is the header to save the destination indices for SVB WRITE.
611 * - src is the register that holds the destination indices value.
612 */
613 GS_OPCODE_SVB_SET_DST_INDEX,
614
615 /**
616 * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
617 * Used in gen6 for transform feedback.
618 *
619 * - dst will hold the register with the final Mx.0 value.
620 *
621 * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
622 *
623 * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
624 *
625 * - src2 is the value to hold in M0: number of SO vertices to write
626 * and number of SO primitives needed.
627 */
628 GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
629
630 /**
631 * Terminate the compute shader.
632 */
633 CS_OPCODE_CS_TERMINATE,
634
635 /**
636 * GLSL barrier()
637 */
638 SHADER_OPCODE_BARRIER,
639
640 /**
641 * Calculate the high 32-bits of a 32x32 multiply.
642 */
643 SHADER_OPCODE_MULH,
644
645 /**
646 * A MOV that uses VxH indirect addressing.
647 *
648 * Source 0: A register to start from (HW_REG).
649 * Source 1: An indirect offset (in bytes, UD GRF).
650 * Source 2: The length of the region that could be accessed (in bytes,
651 * UD immediate).
652 */
653 SHADER_OPCODE_MOV_INDIRECT,
654
655 VEC4_OPCODE_URB_READ,
656 TCS_OPCODE_GET_INSTANCE_ID,
657 TCS_OPCODE_URB_WRITE,
658 TCS_OPCODE_SET_INPUT_URB_OFFSETS,
659 TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
660 TCS_OPCODE_GET_PRIMITIVE_ID,
661 TCS_OPCODE_CREATE_BARRIER_HEADER,
662 TCS_OPCODE_SRC0_010_IS_ZERO,
663 TCS_OPCODE_RELEASE_INPUT,
664 TCS_OPCODE_THREAD_END,
665
666 TES_OPCODE_GET_PRIMITIVE_ID,
667 TES_OPCODE_CREATE_INPUT_READ_HEADER,
668 TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
669 };
670
671 enum brw_urb_write_flags {
672 BRW_URB_WRITE_NO_FLAGS = 0,
673
674 /**
675 * Causes a new URB entry to be allocated, and its address stored in the
676 * destination register (gen < 7).
677 */
678 BRW_URB_WRITE_ALLOCATE = 0x1,
679
680 /**
681 * Causes the current URB entry to be deallocated (gen < 7).
682 */
683 BRW_URB_WRITE_UNUSED = 0x2,
684
685 /**
686 * Causes the thread to terminate.
687 */
688 BRW_URB_WRITE_EOT = 0x4,
689
690 /**
691 * Indicates that the given URB entry is complete, and may be sent further
692 * down the 3D pipeline (gen < 7).
693 */
694 BRW_URB_WRITE_COMPLETE = 0x8,
695
696 /**
697 * Indicates that an additional offset (which may be different for the two
698 * vec4 slots) is stored in the message header (gen == 7).
699 */
700 BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
701
702 /**
703 * Indicates that the channel masks in the URB_WRITE message header should
704 * not be overridden to 0xff (gen == 7).
705 */
706 BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
707
708 /**
709 * Indicates that the data should be sent to the URB using the
710 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This
711 * causes offsets to be interpreted as multiples of an OWORD instead of an
712 * HWORD, and only allows one OWORD to be written.
713 */
714 BRW_URB_WRITE_OWORD = 0x40,
715
716 /**
717 * Convenient combination of flags: end the thread while simultaneously
718 * marking the given URB entry as complete.
719 */
720 BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
721
722 /**
723 * Convenient combination of flags: mark the given URB entry as complete
724 * and simultaneously allocate a new one.
725 */
726 BRW_URB_WRITE_ALLOCATE_COMPLETE =
727 BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
728 };
729
730 enum fb_write_logical_srcs {
731 FB_WRITE_LOGICAL_SRC_COLOR0, /* REQUIRED */
732 FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */
733 FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
734 FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */
735 FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GEN4-5: passthrough from thread */
736 FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
737 FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */
738 FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */
739 FB_WRITE_LOGICAL_NUM_SRCS
740 };
741
742 enum tex_logical_srcs {
743 /** Texture coordinates */
744 TEX_LOGICAL_SRC_COORDINATE,
745 /** Shadow comparator */
746 TEX_LOGICAL_SRC_SHADOW_C,
747 /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
748 TEX_LOGICAL_SRC_LOD,
749 /** dPdy if the operation takes explicit derivatives */
750 TEX_LOGICAL_SRC_LOD2,
751 /** Sample index */
752 TEX_LOGICAL_SRC_SAMPLE_INDEX,
753 /** MCS data */
754 TEX_LOGICAL_SRC_MCS,
755 /** REQUIRED: Texture surface index */
756 TEX_LOGICAL_SRC_SURFACE,
757 /** Texture sampler index */
758 TEX_LOGICAL_SRC_SAMPLER,
759 /** Texel offset for gathers */
760 TEX_LOGICAL_SRC_TG4_OFFSET,
761 /** REQUIRED: Number of coordinate components (as UD immediate) */
762 TEX_LOGICAL_SRC_COORD_COMPONENTS,
763 /** REQUIRED: Number of derivative components (as UD immediate) */
764 TEX_LOGICAL_SRC_GRAD_COMPONENTS,
765
766 TEX_LOGICAL_NUM_SRCS,
767 };
768
769 #ifdef __cplusplus
770 /**
771 * Allow brw_urb_write_flags enums to be ORed together.
772 */
773 inline brw_urb_write_flags
774 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
775 {
776 return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
777 static_cast<int>(y));
778 }
779 #endif
780
781 enum PACKED brw_predicate {
782 BRW_PREDICATE_NONE = 0,
783 BRW_PREDICATE_NORMAL = 1,
784 BRW_PREDICATE_ALIGN1_ANYV = 2,
785 BRW_PREDICATE_ALIGN1_ALLV = 3,
786 BRW_PREDICATE_ALIGN1_ANY2H = 4,
787 BRW_PREDICATE_ALIGN1_ALL2H = 5,
788 BRW_PREDICATE_ALIGN1_ANY4H = 6,
789 BRW_PREDICATE_ALIGN1_ALL4H = 7,
790 BRW_PREDICATE_ALIGN1_ANY8H = 8,
791 BRW_PREDICATE_ALIGN1_ALL8H = 9,
792 BRW_PREDICATE_ALIGN1_ANY16H = 10,
793 BRW_PREDICATE_ALIGN1_ALL16H = 11,
794 BRW_PREDICATE_ALIGN1_ANY32H = 12,
795 BRW_PREDICATE_ALIGN1_ALL32H = 13,
796 BRW_PREDICATE_ALIGN16_REPLICATE_X = 2,
797 BRW_PREDICATE_ALIGN16_REPLICATE_Y = 3,
798 BRW_PREDICATE_ALIGN16_REPLICATE_Z = 4,
799 BRW_PREDICATE_ALIGN16_REPLICATE_W = 5,
800 BRW_PREDICATE_ALIGN16_ANY4H = 6,
801 BRW_PREDICATE_ALIGN16_ALL4H = 7,
802 };
803
804 enum PACKED brw_reg_file {
805 BRW_ARCHITECTURE_REGISTER_FILE = 0,
806 BRW_GENERAL_REGISTER_FILE = 1,
807 BRW_MESSAGE_REGISTER_FILE = 2,
808 BRW_IMMEDIATE_VALUE = 3,
809
810 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
811 FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
812 MRF = BRW_MESSAGE_REGISTER_FILE,
813 IMM = BRW_IMMEDIATE_VALUE,
814
815 /* These are not hardware values */
816 VGRF,
817 ATTR,
818 UNIFORM, /* prog_data->params[reg] */
819 BAD_FILE,
820 };
821
822 #define BRW_HW_REG_TYPE_UD 0
823 #define BRW_HW_REG_TYPE_D 1
824 #define BRW_HW_REG_TYPE_UW 2
825 #define BRW_HW_REG_TYPE_W 3
826 #define BRW_HW_REG_TYPE_F 7
827 #define GEN8_HW_REG_TYPE_UQ 8
828 #define GEN8_HW_REG_TYPE_Q 9
829
830 #define BRW_HW_REG_NON_IMM_TYPE_UB 4
831 #define BRW_HW_REG_NON_IMM_TYPE_B 5
832 #define GEN7_HW_REG_NON_IMM_TYPE_DF 6
833 #define GEN8_HW_REG_NON_IMM_TYPE_HF 10
834
835 #define BRW_HW_REG_IMM_TYPE_UV 4 /* Gen6+ packed unsigned immediate vector */
836 #define BRW_HW_REG_IMM_TYPE_VF 5 /* packed float immediate vector */
837 #define BRW_HW_REG_IMM_TYPE_V 6 /* packed int imm. vector; uword dest only */
838 #define GEN8_HW_REG_IMM_TYPE_DF 10
839 #define GEN8_HW_REG_IMM_TYPE_HF 11
840
841 /* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
842 * the types were implied. IVB adds BFE and BFI2 that operate on doublewords
843 * and unsigned doublewords, so a new field is also available in the da3src
844 * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select
845 * dst and shared-src types. The values are different from BRW_REGISTER_TYPE_*.
846 */
847 #define BRW_3SRC_TYPE_F 0
848 #define BRW_3SRC_TYPE_D 1
849 #define BRW_3SRC_TYPE_UD 2
850 #define BRW_3SRC_TYPE_DF 3
851
852 #define BRW_ARF_NULL 0x00
853 #define BRW_ARF_ADDRESS 0x10
854 #define BRW_ARF_ACCUMULATOR 0x20
855 #define BRW_ARF_FLAG 0x30
856 #define BRW_ARF_MASK 0x40
857 #define BRW_ARF_MASK_STACK 0x50
858 #define BRW_ARF_MASK_STACK_DEPTH 0x60
859 #define BRW_ARF_STATE 0x70
860 #define BRW_ARF_CONTROL 0x80
861 #define BRW_ARF_NOTIFICATION_COUNT 0x90
862 #define BRW_ARF_IP 0xA0
863 #define BRW_ARF_TDR 0xB0
864 #define BRW_ARF_TIMESTAMP 0xC0
865
866 #define BRW_MRF_COMPR4 (1 << 7)
867
868 #define BRW_AMASK 0
869 #define BRW_IMASK 1
870 #define BRW_LMASK 2
871 #define BRW_CMASK 3
872
873
874
875 #define BRW_THREAD_NORMAL 0
876 #define BRW_THREAD_ATOMIC 1
877 #define BRW_THREAD_SWITCH 2
878
879 enum PACKED brw_vertical_stride {
880 BRW_VERTICAL_STRIDE_0 = 0,
881 BRW_VERTICAL_STRIDE_1 = 1,
882 BRW_VERTICAL_STRIDE_2 = 2,
883 BRW_VERTICAL_STRIDE_4 = 3,
884 BRW_VERTICAL_STRIDE_8 = 4,
885 BRW_VERTICAL_STRIDE_16 = 5,
886 BRW_VERTICAL_STRIDE_32 = 6,
887 BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
888 };
889
890 enum PACKED brw_width {
891 BRW_WIDTH_1 = 0,
892 BRW_WIDTH_2 = 1,
893 BRW_WIDTH_4 = 2,
894 BRW_WIDTH_8 = 3,
895 BRW_WIDTH_16 = 4,
896 };
897
898 /**
899 * Message target: Shared Function ID for where to SEND a message.
900 *
901 * These are enumerated in the ISA reference under "send - Send Message".
902 * In particular, see the following tables:
903 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
904 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
905 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
906 */
907 enum brw_message_target {
908 BRW_SFID_NULL = 0,
909 BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */
910 BRW_SFID_SAMPLER = 2,
911 BRW_SFID_MESSAGE_GATEWAY = 3,
912 BRW_SFID_DATAPORT_READ = 4,
913 BRW_SFID_DATAPORT_WRITE = 5,
914 BRW_SFID_URB = 6,
915 BRW_SFID_THREAD_SPAWNER = 7,
916 BRW_SFID_VME = 8,
917
918 GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4,
919 GEN6_SFID_DATAPORT_RENDER_CACHE = 5,
920 GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
921
922 GEN7_SFID_DATAPORT_DATA_CACHE = 10,
923 GEN7_SFID_PIXEL_INTERPOLATOR = 11,
924 HSW_SFID_DATAPORT_DATA_CACHE_1 = 12,
925 HSW_SFID_CRE = 13,
926 };
927
928 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
929
930 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
931 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
932 #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
933
934 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
935 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
936 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
937 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
938 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
939 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
940 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
941 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
942 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
943 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
944 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
945 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
946 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1
947 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
948 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
949 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
950 #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
951 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
952
953 #define GEN5_SAMPLER_MESSAGE_SAMPLE 0
954 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
955 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2
956 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3
957 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4
958 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
959 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
960 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
961 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
962 #define GEN5_SAMPLER_MESSAGE_LOD 9
963 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
964 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
965 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
966 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
967 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
968 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
969 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ 24
970 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ 25
971 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ 26
972 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28
973 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
974 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
975 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
976
977 /* for GEN5 only */
978 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
979 #define BRW_SAMPLER_SIMD_MODE_SIMD8 1
980 #define BRW_SAMPLER_SIMD_MODE_SIMD16 2
981 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
982
983 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
984 * behavior by setting bit 22 of dword 2 in the message header. */
985 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D 0
986 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22)
987
988 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
989 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
990 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
991 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
992 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
993 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n) \
994 ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \
995 (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \
996 (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \
997 (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \
998 (abort(), ~0))
999
1000 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
1001 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
1002
1003 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
1004 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
1005
1006 /* This one stays the same across generations. */
1007 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
1008 /* GEN4 */
1009 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
1010 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
1011 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
1012 /* G45, GEN5 */
1013 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1014 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1015 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3
1016 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1017 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1018 /* GEN6 */
1019 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1020 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1021 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1022 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
1023 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1024
1025 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
1026 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
1027 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
1028
1029 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
1030 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
1031 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
1032 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
1033 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
1034
1035 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
1036 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
1037 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2
1038 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
1039 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
1040 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
1041 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
1042
1043 /* GEN6 */
1044 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
1045 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
1046 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9
1047 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10
1048 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11
1049 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12
1050 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
1051 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
1052
1053 /* GEN7 */
1054 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ 4
1055 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ 5
1056 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP 6
1057 #define GEN7_DATAPORT_RC_MEMORY_FENCE 7
1058 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10
1059 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE 12
1060 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE 13
1061 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0
1062 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1
1063 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2
1064 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3
1065 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4
1066 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5
1067 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6
1068 #define GEN7_DATAPORT_DC_MEMORY_FENCE 7
1069 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8
1070 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10
1071 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11
1072 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
1073 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
1074
1075 #define GEN7_DATAPORT_SCRATCH_READ ((1 << 18) | \
1076 (0 << 17))
1077 #define GEN7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \
1078 (1 << 17))
1079 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12
1080
1081 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0
1082 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1
1083 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID 2
1084 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3
1085
1086 /* HSW */
1087 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0
1088 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1
1089 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2
1090 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3
1091 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4
1092 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7
1093 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8
1094 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10
1095 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11
1096 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12
1097
1098 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1
1099 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2
1100 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3
1101 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4
1102 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5
1103 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6
1104 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7
1105 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9
1106 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10
1107 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11
1108 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12
1109 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13
1110
1111 /* GEN9 */
1112 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE 12
1113 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ 13
1114
1115 /* Dataport special binding table indices: */
1116 #define BRW_BTI_STATELESS 255
1117 #define GEN7_BTI_SLM 254
1118 /* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the
1119 * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW,
1120 * CHV and at least some pre-production steppings of SKL due to
1121 * WaForceEnableNonCoherent, HDC memory access may have been overridden by the
1122 * kernel to be non-coherent (matching the behavior of the same BTI on
1123 * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253.
1124 */
1125 #define GEN8_BTI_STATELESS_IA_COHERENT 255
1126 #define GEN8_BTI_STATELESS_NON_COHERENT 253
1127
1128 /* dataport atomic operations. */
1129 #define BRW_AOP_AND 1
1130 #define BRW_AOP_OR 2
1131 #define BRW_AOP_XOR 3
1132 #define BRW_AOP_MOV 4
1133 #define BRW_AOP_INC 5
1134 #define BRW_AOP_DEC 6
1135 #define BRW_AOP_ADD 7
1136 #define BRW_AOP_SUB 8
1137 #define BRW_AOP_REVSUB 9
1138 #define BRW_AOP_IMAX 10
1139 #define BRW_AOP_IMIN 11
1140 #define BRW_AOP_UMAX 12
1141 #define BRW_AOP_UMIN 13
1142 #define BRW_AOP_CMPWR 14
1143 #define BRW_AOP_PREDEC 15
1144
1145 #define BRW_MATH_FUNCTION_INV 1
1146 #define BRW_MATH_FUNCTION_LOG 2
1147 #define BRW_MATH_FUNCTION_EXP 3
1148 #define BRW_MATH_FUNCTION_SQRT 4
1149 #define BRW_MATH_FUNCTION_RSQ 5
1150 #define BRW_MATH_FUNCTION_SIN 6
1151 #define BRW_MATH_FUNCTION_COS 7
1152 #define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */
1153 #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
1154 #define BRW_MATH_FUNCTION_POW 10
1155 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
1156 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
1157 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
1158 #define GEN8_MATH_FUNCTION_INVM 14
1159 #define GEN8_MATH_FUNCTION_RSQRTM 15
1160
1161 #define BRW_MATH_INTEGER_UNSIGNED 0
1162 #define BRW_MATH_INTEGER_SIGNED 1
1163
1164 #define BRW_MATH_PRECISION_FULL 0
1165 #define BRW_MATH_PRECISION_PARTIAL 1
1166
1167 #define BRW_MATH_SATURATE_NONE 0
1168 #define BRW_MATH_SATURATE_SATURATE 1
1169
1170 #define BRW_MATH_DATA_VECTOR 0
1171 #define BRW_MATH_DATA_SCALAR 1
1172
1173 #define BRW_URB_OPCODE_WRITE_HWORD 0
1174 #define BRW_URB_OPCODE_WRITE_OWORD 1
1175 #define BRW_URB_OPCODE_READ_HWORD 2
1176 #define BRW_URB_OPCODE_READ_OWORD 3
1177 #define GEN7_URB_OPCODE_ATOMIC_MOV 4
1178 #define GEN7_URB_OPCODE_ATOMIC_INC 5
1179 #define GEN8_URB_OPCODE_ATOMIC_ADD 6
1180 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1181 #define GEN8_URB_OPCODE_SIMD8_READ 8
1182
1183 #define BRW_URB_SWIZZLE_NONE 0
1184 #define BRW_URB_SWIZZLE_INTERLEAVE 1
1185 #define BRW_URB_SWIZZLE_TRANSPOSE 2
1186
1187 #define BRW_SCRATCH_SPACE_SIZE_1K 0
1188 #define BRW_SCRATCH_SPACE_SIZE_2K 1
1189 #define BRW_SCRATCH_SPACE_SIZE_4K 2
1190 #define BRW_SCRATCH_SPACE_SIZE_8K 3
1191 #define BRW_SCRATCH_SPACE_SIZE_16K 4
1192 #define BRW_SCRATCH_SPACE_SIZE_32K 5
1193 #define BRW_SCRATCH_SPACE_SIZE_64K 6
1194 #define BRW_SCRATCH_SPACE_SIZE_128K 7
1195 #define BRW_SCRATCH_SPACE_SIZE_256K 8
1196 #define BRW_SCRATCH_SPACE_SIZE_512K 9
1197 #define BRW_SCRATCH_SPACE_SIZE_1M 10
1198 #define BRW_SCRATCH_SPACE_SIZE_2M 11
1199
1200 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0
1201 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1
1202 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2
1203 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3
1204 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4
1205 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1206 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6
1207
1208
1209 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1210 * is 2^9, or 512. It's counted in multiples of 64 bytes.
1211 *
1212 * Identical for VS, DS, and HS.
1213 */
1214 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
1215 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64)
1216 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64)
1217 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64)
1218
1219 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1220 * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1221 */
1222 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128)
1223
1224 /* GS Thread Payload
1225 */
1226
1227 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1228 * counted in multiples of 16 bytes.
1229 */
1230 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16)
1231
1232
1233 /* R0 */
1234 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
1235
1236 #endif /* BRW_EU_DEFINES_H */