src/intel/compiler/brw_eu_defines.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32 #ifndef BRW_EU_DEFINES_H
  33 #define BRW_EU_DEFINES_H
  34
  35 #include <stdint.h>
  36 #include "util/macros.h"
  37
  38 /* The following hunk, up-to "Execution Unit" is used by both the
  39  * intel/compiler and i965 codebase. */
  40
  41 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
  42 /* Using the GNU statement expression extension */
  43 #define SET_FIELD(value, field)                                         \
  44    ({                                                                   \
  45       uint32_t fieldval = (uint32_t)(value) << field ## _SHIFT;         \
  46       assert((fieldval & ~ field ## _MASK) == 0);                       \
  47       fieldval & field ## _MASK;                                        \
  48    })
  49
  50 #define SET_BITS(value, high, low)                                      \
  51    ({                                                                   \
  52       const uint32_t fieldval = (uint32_t)(value) << (low);             \
  53       assert((fieldval & ~INTEL_MASK(high, low)) == 0);                 \
  54       fieldval & INTEL_MASK(high, low);                                 \
  55    })
  56
  57 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
  58 #define GET_FIELD(word, field) (((word)  & field ## _MASK) >> field ## _SHIFT)
  59
  60 #define _3DPRIM_POINTLIST         0x01
  61 #define _3DPRIM_LINELIST          0x02
  62 #define _3DPRIM_LINESTRIP         0x03
  63 #define _3DPRIM_TRILIST           0x04
  64 #define _3DPRIM_TRISTRIP          0x05
  65 #define _3DPRIM_TRIFAN            0x06
  66 #define _3DPRIM_QUADLIST          0x07
  67 #define _3DPRIM_QUADSTRIP         0x08
  68 #define _3DPRIM_LINELIST_ADJ      0x09 /* G45+ */
  69 #define _3DPRIM_LINESTRIP_ADJ     0x0A /* G45+ */
  70 #define _3DPRIM_TRILIST_ADJ       0x0B /* G45+ */
  71 #define _3DPRIM_TRISTRIP_ADJ      0x0C /* G45+ */
  72 #define _3DPRIM_TRISTRIP_REVERSE  0x0D
  73 #define _3DPRIM_POLYGON           0x0E
  74 #define _3DPRIM_RECTLIST          0x0F
  75 #define _3DPRIM_LINELOOP          0x10
  76 #define _3DPRIM_POINTLIST_BF      0x11
  77 #define _3DPRIM_LINESTRIP_CONT    0x12
  78 #define _3DPRIM_LINESTRIP_BF      0x13
  79 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
  80 #define _3DPRIM_TRIFAN_NOSTIPPLE  0x16
  81 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
  82
  83 /* Bitfields for the URB_WRITE message, DW2 of message header: */
  84 #define URB_WRITE_PRIM_END              0x1
  85 #define URB_WRITE_PRIM_START            0x2
  86 #define URB_WRITE_PRIM_TYPE_SHIFT       2
  87
  88 #define BRW_SPRITE_POINT_ENABLE  16
  89
  90 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT          0
  91 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID          1
  92
  93 /* Execution Unit (EU) defines
  94  */
  95
  96 #define BRW_ALIGN_1   0
  97 #define BRW_ALIGN_16  1
  98
  99 #define BRW_ADDRESS_DIRECT                        0
 100 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER    1
 101
 102 #define BRW_CHANNEL_X     0
 103 #define BRW_CHANNEL_Y     1
 104 #define BRW_CHANNEL_Z     2
 105 #define BRW_CHANNEL_W     3
 106
 107 enum brw_compression {
 108    BRW_COMPRESSION_NONE       = 0,
 109    BRW_COMPRESSION_2NDHALF    = 1,
 110    BRW_COMPRESSION_COMPRESSED = 2,
 111 };
 112
 113 #define GEN6_COMPRESSION_1Q             0
 114 #define GEN6_COMPRESSION_2Q             1
 115 #define GEN6_COMPRESSION_3Q             2
 116 #define GEN6_COMPRESSION_4Q             3
 117 #define GEN6_COMPRESSION_1H             0
 118 #define GEN6_COMPRESSION_2H             2
 119
 120 enum PACKED brw_conditional_mod {
 121    BRW_CONDITIONAL_NONE = 0,
 122    BRW_CONDITIONAL_Z    = 1,
 123    BRW_CONDITIONAL_NZ   = 2,
 124    BRW_CONDITIONAL_EQ   = 1,    /* Z */
 125    BRW_CONDITIONAL_NEQ  = 2,    /* NZ */
 126    BRW_CONDITIONAL_G    = 3,
 127    BRW_CONDITIONAL_GE   = 4,
 128    BRW_CONDITIONAL_L    = 5,
 129    BRW_CONDITIONAL_LE   = 6,
 130    BRW_CONDITIONAL_R    = 7,    /* Gen <= 5 */
 131    BRW_CONDITIONAL_O    = 8,
 132    BRW_CONDITIONAL_U    = 9,
 133 };
 134
 135 #define BRW_DEBUG_NONE        0
 136 #define BRW_DEBUG_BREAKPOINT  1
 137
 138 #define BRW_DEPENDENCY_NORMAL         0
 139 #define BRW_DEPENDENCY_NOTCLEARED     1
 140 #define BRW_DEPENDENCY_NOTCHECKED     2
 141 #define BRW_DEPENDENCY_DISABLE        3
 142
 143 enum PACKED brw_execution_size {
 144    BRW_EXECUTE_1  = 0,
 145    BRW_EXECUTE_2  = 1,
 146    BRW_EXECUTE_4  = 2,
 147    BRW_EXECUTE_8  = 3,
 148    BRW_EXECUTE_16 = 4,
 149    BRW_EXECUTE_32 = 5,
 150 };
 151
 152 enum PACKED brw_horizontal_stride {
 153    BRW_HORIZONTAL_STRIDE_0 = 0,
 154    BRW_HORIZONTAL_STRIDE_1 = 1,
 155    BRW_HORIZONTAL_STRIDE_2 = 2,
 156    BRW_HORIZONTAL_STRIDE_4 = 3,
 157 };
 158
 159 enum PACKED gen10_align1_3src_src_horizontal_stride {
 160    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
 161    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
 162    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
 163    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
 164 };
 165
 166 enum PACKED gen10_align1_3src_dst_horizontal_stride {
 167    BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
 168    BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
 169 };
 170
 171 #define BRW_INSTRUCTION_NORMAL    0
 172 #define BRW_INSTRUCTION_SATURATE  1
 173
 174 #define BRW_MASK_ENABLE   0
 175 #define BRW_MASK_DISABLE  1
 176
 177 /** @{
 178  *
 179  * Gen6 has replaced "mask enable/disable" with WECtrl, which is
 180  * effectively the same but much simpler to think about.  Now, there
 181  * are two contributors ANDed together to whether channels are
 182  * executed: The predication on the instruction, and the channel write
 183  * enable.
 184  */
 185 /**
 186  * This is the default value.  It means that a channel's write enable is set
 187  * if the per-channel IP is pointing at this instruction.
 188  */
 189 #define BRW_WE_NORMAL           0
 190 /**
 191  * This is used like BRW_MASK_DISABLE, and causes all channels to have
 192  * their write enable set.  Note that predication still contributes to
 193  * whether the channel actually gets written.
 194  */
 195 #define BRW_WE_ALL              1
 196 /** @} */
 197
 198 enum opcode {
 199    /* These are the actual hardware instructions. */
 200    BRW_OPCODE_ILLEGAL,
 201    BRW_OPCODE_SYNC,
 202    BRW_OPCODE_MOV,
 203    BRW_OPCODE_SEL,
 204    BRW_OPCODE_MOVI, /**< G45+ */
 205    BRW_OPCODE_NOT,
 206    BRW_OPCODE_AND,
 207    BRW_OPCODE_OR,
 208    BRW_OPCODE_XOR,
 209    BRW_OPCODE_SHR,
 210    BRW_OPCODE_SHL,
 211    BRW_OPCODE_DIM, /**< Gen7.5 only */
 212    BRW_OPCODE_SMOV, /**< Gen8+ */
 213    BRW_OPCODE_ASR,
 214    BRW_OPCODE_ROR,  /**< Gen11+ */
 215    BRW_OPCODE_ROL,  /**< Gen11+ */
 216    BRW_OPCODE_CMP,
 217    BRW_OPCODE_CMPN,
 218    BRW_OPCODE_CSEL, /**< Gen8+ */
 219    BRW_OPCODE_F32TO16, /**< Gen7 only */
 220    BRW_OPCODE_F16TO32, /**< Gen7 only */
 221    BRW_OPCODE_BFREV, /**< Gen7+ */
 222    BRW_OPCODE_BFE, /**< Gen7+ */
 223    BRW_OPCODE_BFI1, /**< Gen7+ */
 224    BRW_OPCODE_BFI2, /**< Gen7+ */
 225    BRW_OPCODE_JMPI,
 226    BRW_OPCODE_BRD, /**< Gen7+ */
 227    BRW_OPCODE_IF,
 228    BRW_OPCODE_IFF, /**< Pre-Gen6 */
 229    BRW_OPCODE_BRC, /**< Gen7+ */
 230    BRW_OPCODE_ELSE,
 231    BRW_OPCODE_ENDIF,
 232    BRW_OPCODE_DO, /**< Pre-Gen6 */
 233    BRW_OPCODE_CASE, /**< Gen6 only */
 234    BRW_OPCODE_WHILE,
 235    BRW_OPCODE_BREAK,
 236    BRW_OPCODE_CONTINUE,
 237    BRW_OPCODE_HALT,
 238    BRW_OPCODE_CALLA, /**< Gen7.5+ */
 239    BRW_OPCODE_MSAVE, /**< Pre-Gen6 */
 240    BRW_OPCODE_CALL, /**< Gen6+ */
 241    BRW_OPCODE_MREST, /**< Pre-Gen6 */
 242    BRW_OPCODE_RET, /**< Gen6+ */
 243    BRW_OPCODE_PUSH, /**< Pre-Gen6 */
 244    BRW_OPCODE_FORK, /**< Gen6 only */
 245    BRW_OPCODE_GOTO, /**< Gen8+ */
 246    BRW_OPCODE_POP, /**< Pre-Gen6 */
 247    BRW_OPCODE_WAIT,
 248    BRW_OPCODE_SEND,
 249    BRW_OPCODE_SENDC,
 250    BRW_OPCODE_SENDS, /**< Gen9+ */
 251    BRW_OPCODE_SENDSC, /**< Gen9+ */
 252    BRW_OPCODE_MATH, /**< Gen6+ */
 253    BRW_OPCODE_ADD,
 254    BRW_OPCODE_MUL,
 255    BRW_OPCODE_AVG,
 256    BRW_OPCODE_FRC,
 257    BRW_OPCODE_RNDU,
 258    BRW_OPCODE_RNDD,
 259    BRW_OPCODE_RNDE,
 260    BRW_OPCODE_RNDZ,
 261    BRW_OPCODE_MAC,
 262    BRW_OPCODE_MACH,
 263    BRW_OPCODE_LZD,
 264    BRW_OPCODE_FBH, /**< Gen7+ */
 265    BRW_OPCODE_FBL, /**< Gen7+ */
 266    BRW_OPCODE_CBIT, /**< Gen7+ */
 267    BRW_OPCODE_ADDC, /**< Gen7+ */
 268    BRW_OPCODE_SUBB, /**< Gen7+ */
 269    BRW_OPCODE_SAD2,
 270    BRW_OPCODE_SADA2,
 271    BRW_OPCODE_DP4,
 272    BRW_OPCODE_DPH,
 273    BRW_OPCODE_DP3,
 274    BRW_OPCODE_DP2,
 275    BRW_OPCODE_LINE,
 276    BRW_OPCODE_PLN, /**< G45+ */
 277    BRW_OPCODE_MAD, /**< Gen6+ */
 278    BRW_OPCODE_LRP, /**< Gen6+ */
 279    BRW_OPCODE_MADM, /**< Gen8+ */
 280    BRW_OPCODE_NENOP, /**< G45 only */
 281    BRW_OPCODE_NOP,
 282
 283    NUM_BRW_OPCODES,
 284
 285    /* These are compiler backend opcodes that get translated into other
 286     * instructions.
 287     */
 288    FS_OPCODE_FB_WRITE = NUM_BRW_OPCODES,
 289
 290    /**
 291     * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
 292     * individual sources instead of as a single payload blob. The
 293     * position/ordering of the arguments are defined by the enum
 294     * fb_write_logical_srcs.
 295     */
 296    FS_OPCODE_FB_WRITE_LOGICAL,
 297
 298    FS_OPCODE_REP_FB_WRITE,
 299
 300    FS_OPCODE_FB_READ,
 301    FS_OPCODE_FB_READ_LOGICAL,
 302
 303    SHADER_OPCODE_RCP,
 304    SHADER_OPCODE_RSQ,
 305    SHADER_OPCODE_SQRT,
 306    SHADER_OPCODE_EXP2,
 307    SHADER_OPCODE_LOG2,
 308    SHADER_OPCODE_POW,
 309    SHADER_OPCODE_INT_QUOTIENT,
 310    SHADER_OPCODE_INT_REMAINDER,
 311    SHADER_OPCODE_SIN,
 312    SHADER_OPCODE_COS,
 313
 314    /**
 315     * A generic "send" opcode.  The first two sources are the message
 316     * descriptor and extended message descriptor respectively.  The third
 317     * and optional fourth sources are the message payload
 318     */
 319    SHADER_OPCODE_SEND,
 320
 321    /**
 322     * An "undefined" write which does nothing but indicates to liveness that
 323     * we don't care about any values in the register which predate this
 324     * instruction.  Used to prevent partial writes from causing issues with
 325     * live ranges.
 326     */
 327    SHADER_OPCODE_UNDEF,
 328
 329    /**
 330     * Texture sampling opcodes.
 331     *
 332     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
 333     * opcode but instead of taking a single payload blob they expect their
 334     * arguments separately as individual sources. The position/ordering of the
 335     * arguments are defined by the enum tex_logical_srcs.
 336     */
 337    SHADER_OPCODE_TEX,
 338    SHADER_OPCODE_TEX_LOGICAL,
 339    SHADER_OPCODE_TXD,
 340    SHADER_OPCODE_TXD_LOGICAL,
 341    SHADER_OPCODE_TXF,
 342    SHADER_OPCODE_TXF_LOGICAL,
 343    SHADER_OPCODE_TXF_LZ,
 344    SHADER_OPCODE_TXL,
 345    SHADER_OPCODE_TXL_LOGICAL,
 346    SHADER_OPCODE_TXL_LZ,
 347    SHADER_OPCODE_TXS,
 348    SHADER_OPCODE_TXS_LOGICAL,
 349    FS_OPCODE_TXB,
 350    FS_OPCODE_TXB_LOGICAL,
 351    SHADER_OPCODE_TXF_CMS,
 352    SHADER_OPCODE_TXF_CMS_LOGICAL,
 353    SHADER_OPCODE_TXF_CMS_W,
 354    SHADER_OPCODE_TXF_CMS_W_LOGICAL,
 355    SHADER_OPCODE_TXF_UMS,
 356    SHADER_OPCODE_TXF_UMS_LOGICAL,
 357    SHADER_OPCODE_TXF_MCS,
 358    SHADER_OPCODE_TXF_MCS_LOGICAL,
 359    SHADER_OPCODE_LOD,
 360    SHADER_OPCODE_LOD_LOGICAL,
 361    SHADER_OPCODE_TG4,
 362    SHADER_OPCODE_TG4_LOGICAL,
 363    SHADER_OPCODE_TG4_OFFSET,
 364    SHADER_OPCODE_TG4_OFFSET_LOGICAL,
 365    SHADER_OPCODE_SAMPLEINFO,
 366    SHADER_OPCODE_SAMPLEINFO_LOGICAL,
 367
 368    SHADER_OPCODE_IMAGE_SIZE_LOGICAL,
 369
 370    /**
 371     * Combines multiple sources of size 1 into a larger virtual GRF.
 372     * For example, parameters for a send-from-GRF message.  Or, updating
 373     * channels of a size 4 VGRF used to store vec4s such as texturing results.
 374     *
 375     * This will be lowered into MOVs from each source to consecutive offsets
 376     * of the destination VGRF.
 377     *
 378     * src[0] may be BAD_FILE.  If so, the lowering pass skips emitting the MOV,
 379     * but still reserves the first channel of the destination VGRF.  This can be
 380     * used to reserve space for, say, a message header set up by the generators.
 381     */
 382    SHADER_OPCODE_LOAD_PAYLOAD,
 383
 384    /**
 385     * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
 386     * acts intra-channel, obtaining the final value for each channel by
 387     * combining the sources values for the same channel, the first source
 388     * occupying the lowest bits and the last source occupying the highest
 389     * bits.
 390     */
 391    FS_OPCODE_PACK,
 392
 393    SHADER_OPCODE_SHADER_TIME_ADD,
 394
 395    /**
 396     * Typed and untyped surface access opcodes.
 397     *
 398     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
 399     * opcode but instead of taking a single payload blob they expect their
 400     * arguments separately as individual sources:
 401     *
 402     * Source 0: [required] Surface coordinates.
 403     * Source 1: [optional] Operation source.
 404     * Source 2: [required] Surface index.
 405     * Source 3: [required] Number of coordinate components (as UD immediate).
 406     * Source 4: [required] Opcode-specific control immediate, same as source 2
 407     *                      of the matching non-LOGICAL opcode.
 408     */
 409    VEC4_OPCODE_UNTYPED_ATOMIC,
 410    SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
 411    SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
 412    VEC4_OPCODE_UNTYPED_SURFACE_READ,
 413    SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
 414    VEC4_OPCODE_UNTYPED_SURFACE_WRITE,
 415    SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
 416
 417    /**
 418     * Untyped A64 surface access opcodes.
 419     *
 420     * Source 0: 64-bit address
 421     * Source 1: Operational source
 422     * Source 2: [required] Opcode-specific control immediate, same as source 2
 423     *                      of the matching non-LOGICAL opcode.
 424     */
 425    SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL,
 426    SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL,
 427    SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL,
 428    SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL,
 429    SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL,
 430    SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL,
 431    SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL,
 432
 433    SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
 434    SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
 435    SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
 436
 437    SHADER_OPCODE_RND_MODE,
 438    SHADER_OPCODE_FLOAT_CONTROL_MODE,
 439
 440    /**
 441     * Byte scattered write/read opcodes.
 442     *
 443     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
 444     * opcode, but instead of taking a single payload blog they expect their
 445     * arguments separately as individual sources, like untyped write/read.
 446     */
 447    SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
 448    SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
 449    SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL,
 450    SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL,
 451
 452    /**
 453     * Memory fence messages.
 454     *
 455     * Source 0: Must be register g0, used as header.
 456     * Source 1: Immediate bool to indicate whether or not we need to stall
 457     *           until memory transactions prior to the fence are completed.
 458     * Source 2: Immediate byte indicating which memory to fence.  Zero means
 459     *           global memory; GEN7_BTI_SLM means SLM (for Gen11+ only).
 460     *
 461     * Vec4 backend only uses Source 0.
 462     */
 463    SHADER_OPCODE_MEMORY_FENCE,
 464
 465    SHADER_OPCODE_GEN4_SCRATCH_READ,
 466    SHADER_OPCODE_GEN4_SCRATCH_WRITE,
 467    SHADER_OPCODE_GEN7_SCRATCH_READ,
 468
 469    /**
 470     * Gen8+ SIMD8 URB Read messages.
 471     */
 472    SHADER_OPCODE_URB_READ_SIMD8,
 473    SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
 474
 475    SHADER_OPCODE_URB_WRITE_SIMD8,
 476    SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
 477    SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
 478    SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
 479
 480    /**
 481     * Return the index of an arbitrary live channel (i.e. one of the channels
 482     * enabled in the current execution mask) and assign it to the first
 483     * component of the destination.  Expected to be used as input for the
 484     * BROADCAST pseudo-opcode.
 485     */
 486    SHADER_OPCODE_FIND_LIVE_CHANNEL,
 487
 488    /**
 489     * Pick the channel from its first source register given by the index
 490     * specified as second source.  Useful for variable indexing of surfaces.
 491     *
 492     * Note that because the result of this instruction is by definition
 493     * uniform and it can always be splatted to multiple channels using a
 494     * scalar regioning mode, only the first channel of the destination region
 495     * is guaranteed to be updated, which implies that BROADCAST instructions
 496     * should usually be marked force_writemask_all.
 497     */
 498    SHADER_OPCODE_BROADCAST,
 499
 500    /* Pick the channel from its first source register given by the index
 501     * specified as second source.
 502     *
 503     * This is similar to the BROADCAST instruction except that it takes a
 504     * dynamic index and potentially puts a different value in each output
 505     * channel.
 506     */
 507    SHADER_OPCODE_SHUFFLE,
 508
 509    /* Select between src0 and src1 based on channel enables.
 510     *
 511     * This instruction copies src0 into the enabled channels of the
 512     * destination and copies src1 into the disabled channels.
 513     */
 514    SHADER_OPCODE_SEL_EXEC,
 515
 516    /* This turns into an align16 mov from src0 to dst with a swizzle
 517     * provided as an immediate in src1.
 518     */
 519    SHADER_OPCODE_QUAD_SWIZZLE,
 520
 521    /* Take every Nth element in src0 and broadcast it to the group of N
 522     * channels in which it lives in the destination.  The offset within the
 523     * cluster is given by src1 and the cluster size is given by src2.
 524     */
 525    SHADER_OPCODE_CLUSTER_BROADCAST,
 526
 527    SHADER_OPCODE_GET_BUFFER_SIZE,
 528
 529    SHADER_OPCODE_INTERLOCK,
 530
 531    VEC4_OPCODE_MOV_BYTES,
 532    VEC4_OPCODE_PACK_BYTES,
 533    VEC4_OPCODE_UNPACK_UNIFORM,
 534    VEC4_OPCODE_DOUBLE_TO_F32,
 535    VEC4_OPCODE_DOUBLE_TO_D32,
 536    VEC4_OPCODE_DOUBLE_TO_U32,
 537    VEC4_OPCODE_TO_DOUBLE,
 538    VEC4_OPCODE_PICK_LOW_32BIT,
 539    VEC4_OPCODE_PICK_HIGH_32BIT,
 540    VEC4_OPCODE_SET_LOW_32BIT,
 541    VEC4_OPCODE_SET_HIGH_32BIT,
 542
 543    FS_OPCODE_DDX_COARSE,
 544    FS_OPCODE_DDX_FINE,
 545    /**
 546     * Compute dFdy(), dFdyCoarse(), or dFdyFine().
 547     */
 548    FS_OPCODE_DDY_COARSE,
 549    FS_OPCODE_DDY_FINE,
 550    FS_OPCODE_LINTERP,
 551    FS_OPCODE_PIXEL_X,
 552    FS_OPCODE_PIXEL_Y,
 553    FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
 554    FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
 555    FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
 556    FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
 557    FS_OPCODE_DISCARD_JUMP,
 558    FS_OPCODE_SET_SAMPLE_ID,
 559    FS_OPCODE_PACK_HALF_2x16_SPLIT,
 560    FS_OPCODE_PLACEHOLDER_HALT,
 561    FS_OPCODE_INTERPOLATE_AT_SAMPLE,
 562    FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
 563    FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
 564
 565    VS_OPCODE_URB_WRITE,
 566    VS_OPCODE_PULL_CONSTANT_LOAD,
 567    VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
 568    VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
 569
 570    VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
 571
 572    /**
 573     * Write geometry shader output data to the URB.
 574     *
 575     * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
 576     * R0 to the first MRF.  This allows the geometry shader to override the
 577     * "Slot {0,1} Offset" fields in the message header.
 578     */
 579    GS_OPCODE_URB_WRITE,
 580
 581    /**
 582     * Write geometry shader output data to the URB and request a new URB
 583     * handle (gen6).
 584     *
 585     * This opcode doesn't do an implied move from R0 to the first MRF.
 586     */
 587    GS_OPCODE_URB_WRITE_ALLOCATE,
 588
 589    /**
 590     * Terminate the geometry shader thread by doing an empty URB write.
 591     *
 592     * This opcode doesn't do an implied move from R0 to the first MRF.  This
 593     * allows the geometry shader to override the "GS Number of Output Vertices
 594     * for Slot {0,1}" fields in the message header.
 595     */
 596    GS_OPCODE_THREAD_END,
 597
 598    /**
 599     * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
 600     *
 601     * - dst is the MRF containing the message header.
 602     *
 603     * - src0.x indicates which portion of the URB should be written to (e.g. a
 604     *   vertex number)
 605     *
 606     * - src1 is an immediate multiplier which will be applied to src0
 607     *   (e.g. the size of a single vertex in the URB).
 608     *
 609     * Note: the hardware will apply this offset *in addition to* the offset in
 610     * vec4_instruction::offset.
 611     */
 612    GS_OPCODE_SET_WRITE_OFFSET,
 613
 614    /**
 615     * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
 616     * URB_WRITE message header.
 617     *
 618     * - dst is the MRF containing the message header.
 619     *
 620     * - src0.x is the vertex count.  The upper 16 bits will be ignored.
 621     */
 622    GS_OPCODE_SET_VERTEX_COUNT,
 623
 624    /**
 625     * Set DWORD 2 of dst to the value in src.
 626     */
 627    GS_OPCODE_SET_DWORD_2,
 628
 629    /**
 630     * Prepare the dst register for storage in the "Channel Mask" fields of a
 631     * URB_WRITE message header.
 632     *
 633     * DWORD 4 of dst is shifted left by 4 bits, so that later,
 634     * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
 635     * final channel mask.
 636     *
 637     * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
 638     * form the final channel mask, DWORDs 0 and 4 of the dst register must not
 639     * have any extraneous bits set prior to execution of this opcode (that is,
 640     * they should be in the range 0x0 to 0xf).
 641     */
 642    GS_OPCODE_PREPARE_CHANNEL_MASKS,
 643
 644    /**
 645     * Set the "Channel Mask" fields of a URB_WRITE message header.
 646     *
 647     * - dst is the MRF containing the message header.
 648     *
 649     * - src.x is the channel mask, as prepared by
 650     *   GS_OPCODE_PREPARE_CHANNEL_MASKS.  DWORDs 0 and 4 are OR'ed together to
 651     *   form the final channel mask.
 652     */
 653    GS_OPCODE_SET_CHANNEL_MASKS,
 654
 655    /**
 656     * Get the "Instance ID" fields from the payload.
 657     *
 658     * - dst is the GRF for gl_InvocationID.
 659     */
 660    GS_OPCODE_GET_INSTANCE_ID,
 661
 662    /**
 663     * Send a FF_SYNC message to allocate initial URB handles (gen6).
 664     *
 665     * - dst will be used as the writeback register for the FF_SYNC operation.
 666     *
 667     * - src0 is the number of primitives written.
 668     *
 669     * - src1 is the value to hold in M0.0: number of SO vertices to write
 670     *   and number of SO primitives needed. Its value will be overwritten
 671     *   with the SVBI values if transform feedback is enabled.
 672     *
 673     * Note: This opcode uses an implicit MRF register for the ff_sync message
 674     * header, so the caller is expected to set inst->base_mrf and initialize
 675     * that MRF register to r0. This opcode will also write to this MRF register
 676     * to include the allocated URB handle so it can then be reused directly as
 677     * the header in the URB write operation we are allocating the handle for.
 678     */
 679    GS_OPCODE_FF_SYNC,
 680
 681    /**
 682     * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
 683     * register.
 684     *
 685     * - dst is the GRF where PrimitiveID information will be moved.
 686     */
 687    GS_OPCODE_SET_PRIMITIVE_ID,
 688
 689    /**
 690     * Write transform feedback data to the SVB by sending a SVB WRITE message.
 691     * Used in gen6.
 692     *
 693     * - dst is the MRF register containing the message header.
 694     *
 695     * - src0 is the register where the vertex data is going to be copied from.
 696     *
 697     * - src1 is the destination register when write commit occurs.
 698     */
 699    GS_OPCODE_SVB_WRITE,
 700
 701    /**
 702     * Set destination index in the SVB write message payload (M0.5). Used
 703     * in gen6 for transform feedback.
 704     *
 705     * - dst is the header to save the destination indices for SVB WRITE.
 706     * - src is the register that holds the destination indices value.
 707     */
 708    GS_OPCODE_SVB_SET_DST_INDEX,
 709
 710    /**
 711     * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
 712     * Used in gen6 for transform feedback.
 713     *
 714     * - dst will hold the register with the final Mx.0 value.
 715     *
 716     * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
 717     *
 718     * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
 719     *
 720     * - src2 is the value to hold in M0: number of SO vertices to write
 721     *   and number of SO primitives needed.
 722     */
 723    GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
 724
 725    /**
 726     * Terminate the compute shader.
 727     */
 728    CS_OPCODE_CS_TERMINATE,
 729
 730    /**
 731     * GLSL barrier()
 732     */
 733    SHADER_OPCODE_BARRIER,
 734
 735    /**
 736     * Calculate the high 32-bits of a 32x32 multiply.
 737     */
 738    SHADER_OPCODE_MULH,
 739
 740    /**
 741     * A MOV that uses VxH indirect addressing.
 742     *
 743     * Source 0: A register to start from (HW_REG).
 744     * Source 1: An indirect offset (in bytes, UD GRF).
 745     * Source 2: The length of the region that could be accessed (in bytes,
 746     *           UD immediate).
 747     */
 748    SHADER_OPCODE_MOV_INDIRECT,
 749
 750    VEC4_OPCODE_URB_READ,
 751    TCS_OPCODE_GET_INSTANCE_ID,
 752    TCS_OPCODE_URB_WRITE,
 753    TCS_OPCODE_SET_INPUT_URB_OFFSETS,
 754    TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
 755    TCS_OPCODE_GET_PRIMITIVE_ID,
 756    TCS_OPCODE_CREATE_BARRIER_HEADER,
 757    TCS_OPCODE_SRC0_010_IS_ZERO,
 758    TCS_OPCODE_RELEASE_INPUT,
 759    TCS_OPCODE_THREAD_END,
 760
 761    TES_OPCODE_GET_PRIMITIVE_ID,
 762    TES_OPCODE_CREATE_INPUT_READ_HEADER,
 763    TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
 764 };
 765
 766 enum brw_urb_write_flags {
 767    BRW_URB_WRITE_NO_FLAGS = 0,
 768
 769    /**
 770     * Causes a new URB entry to be allocated, and its address stored in the
 771     * destination register (gen < 7).
 772     */
 773    BRW_URB_WRITE_ALLOCATE = 0x1,
 774
 775    /**
 776     * Causes the current URB entry to be deallocated (gen < 7).
 777     */
 778    BRW_URB_WRITE_UNUSED = 0x2,
 779
 780    /**
 781     * Causes the thread to terminate.
 782     */
 783    BRW_URB_WRITE_EOT = 0x4,
 784
 785    /**
 786     * Indicates that the given URB entry is complete, and may be sent further
 787     * down the 3D pipeline (gen < 7).
 788     */
 789    BRW_URB_WRITE_COMPLETE = 0x8,
 790
 791    /**
 792     * Indicates that an additional offset (which may be different for the two
 793     * vec4 slots) is stored in the message header (gen == 7).
 794     */
 795    BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
 796
 797    /**
 798     * Indicates that the channel masks in the URB_WRITE message header should
 799     * not be overridden to 0xff (gen == 7).
 800     */
 801    BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
 802
 803    /**
 804     * Indicates that the data should be sent to the URB using the
 805     * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7).  This
 806     * causes offsets to be interpreted as multiples of an OWORD instead of an
 807     * HWORD, and only allows one OWORD to be written.
 808     */
 809    BRW_URB_WRITE_OWORD = 0x40,
 810
 811    /**
 812     * Convenient combination of flags: end the thread while simultaneously
 813     * marking the given URB entry as complete.
 814     */
 815    BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
 816
 817    /**
 818     * Convenient combination of flags: mark the given URB entry as complete
 819     * and simultaneously allocate a new one.
 820     */
 821    BRW_URB_WRITE_ALLOCATE_COMPLETE =
 822       BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
 823 };
 824
 825 enum fb_write_logical_srcs {
 826    FB_WRITE_LOGICAL_SRC_COLOR0,      /* REQUIRED */
 827    FB_WRITE_LOGICAL_SRC_COLOR1,      /* for dual source blend messages */
 828    FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
 829    FB_WRITE_LOGICAL_SRC_SRC_DEPTH,   /* gl_FragDepth */
 830    FB_WRITE_LOGICAL_SRC_DST_DEPTH,   /* GEN4-5: passthrough from thread */
 831    FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
 832    FB_WRITE_LOGICAL_SRC_OMASK,       /* Sample Mask (gl_SampleMask) */
 833    FB_WRITE_LOGICAL_SRC_COMPONENTS,  /* REQUIRED */
 834    FB_WRITE_LOGICAL_NUM_SRCS
 835 };
 836
 837 enum tex_logical_srcs {
 838    /** Texture coordinates */
 839    TEX_LOGICAL_SRC_COORDINATE,
 840    /** Shadow comparator */
 841    TEX_LOGICAL_SRC_SHADOW_C,
 842    /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
 843    TEX_LOGICAL_SRC_LOD,
 844    /** dPdy if the operation takes explicit derivatives */
 845    TEX_LOGICAL_SRC_LOD2,
 846    /** Min LOD */
 847    TEX_LOGICAL_SRC_MIN_LOD,
 848    /** Sample index */
 849    TEX_LOGICAL_SRC_SAMPLE_INDEX,
 850    /** MCS data */
 851    TEX_LOGICAL_SRC_MCS,
 852    /** REQUIRED: Texture surface index */
 853    TEX_LOGICAL_SRC_SURFACE,
 854    /** Texture sampler index */
 855    TEX_LOGICAL_SRC_SAMPLER,
 856    /** Texture surface bindless handle */
 857    TEX_LOGICAL_SRC_SURFACE_HANDLE,
 858    /** Texture sampler bindless handle */
 859    TEX_LOGICAL_SRC_SAMPLER_HANDLE,
 860    /** Texel offset for gathers */
 861    TEX_LOGICAL_SRC_TG4_OFFSET,
 862    /** REQUIRED: Number of coordinate components (as UD immediate) */
 863    TEX_LOGICAL_SRC_COORD_COMPONENTS,
 864    /** REQUIRED: Number of derivative components (as UD immediate) */
 865    TEX_LOGICAL_SRC_GRAD_COMPONENTS,
 866
 867    TEX_LOGICAL_NUM_SRCS,
 868 };
 869
 870 enum surface_logical_srcs {
 871    /** Surface binding table index */
 872    SURFACE_LOGICAL_SRC_SURFACE,
 873    /** Surface bindless handle */
 874    SURFACE_LOGICAL_SRC_SURFACE_HANDLE,
 875    /** Surface address; could be multi-dimensional for typed opcodes */
 876    SURFACE_LOGICAL_SRC_ADDRESS,
 877    /** Data to be written or used in an atomic op */
 878    SURFACE_LOGICAL_SRC_DATA,
 879    /** Surface number of dimensions.  Affects the size of ADDRESS */
 880    SURFACE_LOGICAL_SRC_IMM_DIMS,
 881    /** Per-opcode immediate argument.  For atomics, this is the atomic opcode */
 882    SURFACE_LOGICAL_SRC_IMM_ARG,
 883
 884    SURFACE_LOGICAL_NUM_SRCS
 885 };
 886
 887 #ifdef __cplusplus
 888 /**
 889  * Allow brw_urb_write_flags enums to be ORed together.
 890  */
 891 inline brw_urb_write_flags
 892 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
 893 {
 894    return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
 895                                            static_cast<int>(y));
 896 }
 897 #endif
 898
 899 enum PACKED brw_predicate {
 900    BRW_PREDICATE_NONE                =  0,
 901    BRW_PREDICATE_NORMAL              =  1,
 902    BRW_PREDICATE_ALIGN1_ANYV         =  2,
 903    BRW_PREDICATE_ALIGN1_ALLV         =  3,
 904    BRW_PREDICATE_ALIGN1_ANY2H        =  4,
 905    BRW_PREDICATE_ALIGN1_ALL2H        =  5,
 906    BRW_PREDICATE_ALIGN1_ANY4H        =  6,
 907    BRW_PREDICATE_ALIGN1_ALL4H        =  7,
 908    BRW_PREDICATE_ALIGN1_ANY8H        =  8,
 909    BRW_PREDICATE_ALIGN1_ALL8H        =  9,
 910    BRW_PREDICATE_ALIGN1_ANY16H       = 10,
 911    BRW_PREDICATE_ALIGN1_ALL16H       = 11,
 912    BRW_PREDICATE_ALIGN1_ANY32H       = 12,
 913    BRW_PREDICATE_ALIGN1_ALL32H       = 13,
 914    BRW_PREDICATE_ALIGN16_REPLICATE_X =  2,
 915    BRW_PREDICATE_ALIGN16_REPLICATE_Y =  3,
 916    BRW_PREDICATE_ALIGN16_REPLICATE_Z =  4,
 917    BRW_PREDICATE_ALIGN16_REPLICATE_W =  5,
 918    BRW_PREDICATE_ALIGN16_ANY4H       =  6,
 919    BRW_PREDICATE_ALIGN16_ALL4H       =  7,
 920 };
 921
 922 enum PACKED brw_reg_file {
 923    BRW_ARCHITECTURE_REGISTER_FILE = 0,
 924    BRW_GENERAL_REGISTER_FILE      = 1,
 925    BRW_MESSAGE_REGISTER_FILE      = 2,
 926    BRW_IMMEDIATE_VALUE            = 3,
 927
 928    ARF = BRW_ARCHITECTURE_REGISTER_FILE,
 929    FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
 930    MRF = BRW_MESSAGE_REGISTER_FILE,
 931    IMM = BRW_IMMEDIATE_VALUE,
 932
 933    /* These are not hardware values */
 934    VGRF,
 935    ATTR,
 936    UNIFORM, /* prog_data->params[reg] */
 937    BAD_FILE,
 938 };
 939
 940 enum PACKED gen10_align1_3src_reg_file {
 941    BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0,
 942    BRW_ALIGN1_3SRC_IMMEDIATE_VALUE       = 1, /* src0, src2 */
 943    BRW_ALIGN1_3SRC_ACCUMULATOR           = 1, /* dest, src1 */
 944 };
 945
 946 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction
 947  * word is "Execution Datatype" which controls whether the instruction operates
 948  * on float or integer types. The register arguments have fields that offer
 949  * more fine control their respective types.
 950  */
 951 enum PACKED gen10_align1_3src_exec_type {
 952    BRW_ALIGN1_3SRC_EXEC_TYPE_INT   = 0,
 953    BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
 954 };
 955
 956 #define BRW_ARF_NULL                  0x00
 957 #define BRW_ARF_ADDRESS               0x10
 958 #define BRW_ARF_ACCUMULATOR           0x20
 959 #define BRW_ARF_FLAG                  0x30
 960 #define BRW_ARF_MASK                  0x40
 961 #define BRW_ARF_MASK_STACK            0x50
 962 #define BRW_ARF_MASK_STACK_DEPTH      0x60
 963 #define BRW_ARF_STATE                 0x70
 964 #define BRW_ARF_CONTROL               0x80
 965 #define BRW_ARF_NOTIFICATION_COUNT    0x90
 966 #define BRW_ARF_IP                    0xA0
 967 #define BRW_ARF_TDR                   0xB0
 968 #define BRW_ARF_TIMESTAMP             0xC0
 969
 970 #define BRW_MRF_COMPR4                  (1 << 7)
 971
 972 #define BRW_AMASK   0
 973 #define BRW_IMASK   1
 974 #define BRW_LMASK   2
 975 #define BRW_CMASK   3
 976
 977
 978
 979 #define BRW_THREAD_NORMAL     0
 980 #define BRW_THREAD_ATOMIC     1
 981 #define BRW_THREAD_SWITCH     2
 982
 983 enum PACKED brw_vertical_stride {
 984    BRW_VERTICAL_STRIDE_0               = 0,
 985    BRW_VERTICAL_STRIDE_1               = 1,
 986    BRW_VERTICAL_STRIDE_2               = 2,
 987    BRW_VERTICAL_STRIDE_4               = 3,
 988    BRW_VERTICAL_STRIDE_8               = 4,
 989    BRW_VERTICAL_STRIDE_16              = 5,
 990    BRW_VERTICAL_STRIDE_32              = 6,
 991    BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
 992 };
 993
 994 enum PACKED gen10_align1_3src_vertical_stride {
 995    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
 996    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1,
 997    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
 998    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2,
 999    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,
1000 };
1001
1002 enum PACKED brw_width {
1003    BRW_WIDTH_1  = 0,
1004    BRW_WIDTH_2  = 1,
1005    BRW_WIDTH_4  = 2,
1006    BRW_WIDTH_8  = 3,
1007    BRW_WIDTH_16 = 4,
1008 };
1009
1010 /**
1011  * Gen12+ SWSB SBID synchronization mode.
1012  *
1013  * This is represented as a bitmask including any required SBID token
1014  * synchronization modes, used to synchronize out-of-order instructions.  Only
1015  * the strongest mode of the mask will be provided to the hardware in the SWSB
1016  * field of an actual hardware instruction, but virtual instructions may be
1017  * able to take into account multiple of them.
1018  */
1019 enum tgl_sbid_mode {
1020    TGL_SBID_NULL = 0,
1021    TGL_SBID_SRC = 1,
1022    TGL_SBID_DST = 2,
1023    TGL_SBID_SET = 4
1024 };
1025
1026 #ifdef __cplusplus
1027 /**
1028  * Allow bitwise arithmetic of tgl_sbid_mode enums.
1029  */
1030 inline tgl_sbid_mode
1031 operator|(tgl_sbid_mode x, tgl_sbid_mode y)
1032 {
1033    return tgl_sbid_mode(unsigned(x) | unsigned(y));
1034 }
1035
1036 inline tgl_sbid_mode
1037 operator&(tgl_sbid_mode x, tgl_sbid_mode y)
1038 {
1039    return tgl_sbid_mode(unsigned(x) & unsigned(y));
1040 }
1041
1042 inline tgl_sbid_mode &
1043 operator|=(tgl_sbid_mode &x, tgl_sbid_mode y)
1044 {
1045    return x = x | y;
1046 }
1047
1048 #endif
1049
1050 /**
1051  * Logical representation of the SWSB scheduling information of a hardware
1052  * instruction.  The binary representation is slightly more compact.
1053  */
1054 struct tgl_swsb {
1055    unsigned regdist : 3;
1056    unsigned sbid : 4;
1057    enum tgl_sbid_mode mode : 3;
1058 };
1059
1060 /**
1061  * Construct a scheduling annotation with a single RegDist dependency.  This
1062  * synchronizes with the completion of the d-th previous in-order instruction.
1063  * The index is one-based, zero causes a no-op tgl_swsb to be constructed.
1064  */
1065 static inline struct tgl_swsb
1066 tgl_swsb_regdist(unsigned d)
1067 {
1068    const struct tgl_swsb swsb = { d };
1069    assert(swsb.regdist == d);
1070    return swsb;
1071 }
1072
1073 /**
1074  * Construct a scheduling annotation that synchronizes with the specified SBID
1075  * token.
1076  */
1077 static inline struct tgl_swsb
1078 tgl_swsb_sbid(enum tgl_sbid_mode mode, unsigned sbid)
1079 {
1080    const struct tgl_swsb swsb = { 0, sbid, mode };
1081    assert(swsb.sbid == sbid);
1082    return swsb;
1083 }
1084
1085 /**
1086  * Construct a no-op scheduling annotation.
1087  */
1088 static inline struct tgl_swsb
1089 tgl_swsb_null(void)
1090 {
1091    return tgl_swsb_regdist(0);
1092 }
1093
1094 /**
1095  * Return a scheduling annotation that allocates the same SBID synchronization
1096  * token as \p swsb.  In addition it will synchronize against a previous
1097  * in-order instruction if \p regdist is non-zero.
1098  */
1099 static inline struct tgl_swsb
1100 tgl_swsb_dst_dep(struct tgl_swsb swsb, unsigned regdist)
1101 {
1102    swsb.regdist = regdist;
1103    swsb.mode = swsb.mode & TGL_SBID_SET;
1104    return swsb;
1105 }
1106
1107 /**
1108  * Return a scheduling annotation that synchronizes against the same SBID and
1109  * RegDist dependencies as \p swsb, but doesn't allocate any SBID token.
1110  */
1111 static inline struct tgl_swsb
1112 tgl_swsb_src_dep(struct tgl_swsb swsb)
1113 {
1114    swsb.mode = swsb.mode & (TGL_SBID_SRC | TGL_SBID_DST);
1115    return swsb;
1116 }
1117
1118 /**
1119  * Convert the provided tgl_swsb to the hardware's binary representation of an
1120  * SWSB annotation.
1121  */
1122 static inline uint8_t
1123 tgl_swsb_encode(struct tgl_swsb swsb)
1124 {
1125    if (!swsb.mode) {
1126       return swsb.regdist;
1127    } else if (swsb.regdist) {
1128       return 0x80 | swsb.regdist << 4 | swsb.sbid;
1129    } else {
1130       return swsb.sbid | (swsb.mode & TGL_SBID_SET ? 0x40 :
1131                           swsb.mode & TGL_SBID_DST ? 0x20 : 0x30);
1132    }
1133 }
1134
1135 /**
1136  * Convert the provided binary representation of an SWSB annotation to a
1137  * tgl_swsb.
1138  */
1139 static inline struct tgl_swsb
1140 tgl_swsb_decode(uint8_t x)
1141 {
1142    if (x & 0x80) {
1143       const struct tgl_swsb swsb = { (x & 0x70u) >> 4, x & 0xfu,
1144                                      TGL_SBID_DST | TGL_SBID_SET };
1145       return swsb;
1146    } else if ((x & 0x70) == 0x20) {
1147       return tgl_swsb_sbid(TGL_SBID_DST, x & 0xfu);
1148    } else if ((x & 0x70) == 0x30) {
1149       return tgl_swsb_sbid(TGL_SBID_SRC, x & 0xfu);
1150    } else if ((x & 0x70) == 0x40) {
1151       return tgl_swsb_sbid(TGL_SBID_SET, x & 0xfu);
1152    } else {
1153       return tgl_swsb_regdist(x & 0x7u);
1154    }
1155 }
1156
1157 enum tgl_sync_function {
1158    TGL_SYNC_NOP = 0x0,
1159    TGL_SYNC_ALLRD = 0x2,
1160    TGL_SYNC_ALLWR = 0x3,
1161    TGL_SYNC_BAR = 0xe,
1162    TGL_SYNC_HOST = 0xf
1163 };
1164
1165 /**
1166  * Message target: Shared Function ID for where to SEND a message.
1167  *
1168  * These are enumerated in the ISA reference under "send - Send Message".
1169  * In particular, see the following tables:
1170  * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
1171  * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
1172  * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
1173  */
1174 enum brw_message_target {
1175    BRW_SFID_NULL                     = 0,
1176    BRW_SFID_MATH                     = 1, /* Only valid on Gen4-5 */
1177    BRW_SFID_SAMPLER                  = 2,
1178    BRW_SFID_MESSAGE_GATEWAY          = 3,
1179    BRW_SFID_DATAPORT_READ            = 4,
1180    BRW_SFID_DATAPORT_WRITE           = 5,
1181    BRW_SFID_URB                      = 6,
1182    BRW_SFID_THREAD_SPAWNER           = 7,
1183    BRW_SFID_VME                      = 8,
1184
1185    GEN6_SFID_DATAPORT_SAMPLER_CACHE  = 4,
1186    GEN6_SFID_DATAPORT_RENDER_CACHE   = 5,
1187    GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
1188
1189    GEN7_SFID_DATAPORT_DATA_CACHE     = 10,
1190    GEN7_SFID_PIXEL_INTERPOLATOR      = 11,
1191    HSW_SFID_DATAPORT_DATA_CACHE_1    = 12,
1192    HSW_SFID_CRE                      = 13,
1193 };
1194
1195 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE     10
1196
1197 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32     0
1198 #define BRW_SAMPLER_RETURN_FORMAT_UINT32      2
1199 #define BRW_SAMPLER_RETURN_FORMAT_SINT32      3
1200
1201 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE              0
1202 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE             0
1203 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS        0
1204 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX             1
1205 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD        1
1206 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD         1
1207 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS  2
1208 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS    2
1209 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE    0
1210 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE     2
1211 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
1212 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
1213 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE  1
1214 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO           2
1215 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO            2
1216 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD                3
1217 #define BRW_SAMPLER_MESSAGE_SIMD8_LD                  3
1218 #define BRW_SAMPLER_MESSAGE_SIMD16_LD                 3
1219
1220 #define GEN5_SAMPLER_MESSAGE_SAMPLE              0
1221 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS         1
1222 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD          2
1223 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE      3
1224 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS       4
1225 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
1226 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE  6
1227 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD           7
1228 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4      8
1229 #define GEN5_SAMPLER_MESSAGE_LOD                 9
1230 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO      10
1231 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO   11
1232 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C    16
1233 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO   17
1234 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
1235 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
1236 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ           24
1237 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ         25
1238 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ        26
1239 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W     28
1240 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS       29
1241 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS       30
1242 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS       31
1243
1244 /* for GEN5 only */
1245 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2                   0
1246 #define BRW_SAMPLER_SIMD_MODE_SIMD8                     1
1247 #define BRW_SAMPLER_SIMD_MODE_SIMD16                    2
1248 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64                 3
1249
1250 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
1251  * behavior by setting bit 22 of dword 2 in the message header. */
1252 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D                   0
1253 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2        (1 << 22)
1254
1255 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW   0
1256 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH  1
1257 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS     2
1258 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS     3
1259 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS     4
1260 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n)              \
1261    ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW :    \
1262     (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS :      \
1263     (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS :     \
1264     (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS :     \
1265     (abort(), ~0))
1266
1267 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD     0
1268 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS    2
1269
1270 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS   2
1271 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS  3
1272
1273 /* This one stays the same across generations. */
1274 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ          0
1275 /* GEN4 */
1276 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     1
1277 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          2
1278 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      3
1279 /* G45, GEN5 */
1280 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ         1
1281 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     2
1282 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ      3
1283 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          4
1284 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      6
1285 /* GEN6 */
1286 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ        1
1287 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     2
1288 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          4
1289 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ  5
1290 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      6
1291
1292 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE      0
1293 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE    1
1294 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE   2
1295
1296 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE                0
1297 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED     1
1298 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01         2
1299 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23         3
1300 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01       4
1301
1302 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE                0
1303 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE           1
1304 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE                2
1305 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE            3
1306 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE              4
1307 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE     5
1308 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE               7
1309
1310 /* GEN6 */
1311 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE              7
1312 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE               8
1313 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE          9
1314 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE               10
1315 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE           11
1316 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE             12
1317 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE               13
1318 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE       14
1319
1320 /* GEN7 */
1321 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ                           4
1322 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ                         5
1323 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP                            6
1324 #define GEN7_DATAPORT_RC_MEMORY_FENCE                               7
1325 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE                          10
1326 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE                        12
1327 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE                        13
1328 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ                           0
1329 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ                 1
1330 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ                      2
1331 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ                       3
1332 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ                        4
1333 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ                       5
1334 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP                          6
1335 #define GEN7_DATAPORT_DC_MEMORY_FENCE                               7
1336 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE                          8
1337 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE                     10
1338 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE                      11
1339 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE                       12
1340 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE                      13
1341
1342 #define GEN7_DATAPORT_SCRATCH_READ                            ((1 << 18) | \
1343                                                                (0 << 17))
1344 #define GEN7_DATAPORT_SCRATCH_WRITE                           ((1 << 18) | \
1345                                                                (1 << 17))
1346 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT                        12
1347
1348 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET     0
1349 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE            1
1350 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID          2
1351 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET   3
1352
1353 /* HSW */
1354 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ                      0
1355 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ            1
1356 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ                 2
1357 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ                  3
1358 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ                   4
1359 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE                          7
1360 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE                     8
1361 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE                10
1362 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE                 11
1363 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE                  12
1364
1365 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ                  1
1366 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP                     2
1367 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2             3
1368 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ                      4
1369 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ                    5
1370 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP                       6
1371 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2               7
1372 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE                 9
1373 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE                     10
1374 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP                     11
1375 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2             12
1376 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE                   13
1377 #define GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ                   0x10
1378 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ             0x11
1379 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP                0x12
1380 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE            0x19
1381 #define GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE                  0x1a
1382 #define GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP              0x1b
1383 #define GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP          0x1d
1384
1385 /* GEN9 */
1386 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE                        12
1387 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ                         13
1388
1389 /* A64 scattered message subtype */
1390 #define GEN8_A64_SCATTERED_SUBTYPE_BYTE                             0
1391 #define GEN8_A64_SCATTERED_SUBTYPE_DWORD                            1
1392 #define GEN8_A64_SCATTERED_SUBTYPE_QWORD                            2
1393 #define GEN8_A64_SCATTERED_SUBTYPE_HWORD                            3
1394
1395 /* Dataport special binding table indices: */
1396 #define BRW_BTI_STATELESS                255
1397 #define GEN7_BTI_SLM                     254
1398 /* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the
1399  * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW,
1400  * CHV and at least some pre-production steppings of SKL due to
1401  * WaForceEnableNonCoherent, HDC memory access may have been overridden by the
1402  * kernel to be non-coherent (matching the behavior of the same BTI on
1403  * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253.
1404  */
1405 #define GEN8_BTI_STATELESS_IA_COHERENT   255
1406 #define GEN8_BTI_STATELESS_NON_COHERENT  253
1407 #define GEN9_BTI_BINDLESS                252
1408
1409 /* Dataport atomic operations for Untyped Atomic Integer Operation message
1410  * (and others).
1411  */
1412 #define BRW_AOP_AND                   1
1413 #define BRW_AOP_OR                    2
1414 #define BRW_AOP_XOR                   3
1415 #define BRW_AOP_MOV                   4
1416 #define BRW_AOP_INC                   5
1417 #define BRW_AOP_DEC                   6
1418 #define BRW_AOP_ADD                   7
1419 #define BRW_AOP_SUB                   8
1420 #define BRW_AOP_REVSUB                9
1421 #define BRW_AOP_IMAX                  10
1422 #define BRW_AOP_IMIN                  11
1423 #define BRW_AOP_UMAX                  12
1424 #define BRW_AOP_UMIN                  13
1425 #define BRW_AOP_CMPWR                 14
1426 #define BRW_AOP_PREDEC                15
1427
1428 /* Dataport atomic operations for Untyped Atomic Float Operation message. */
1429 #define BRW_AOP_FMAX                  1
1430 #define BRW_AOP_FMIN                  2
1431 #define BRW_AOP_FCMPWR                3
1432
1433 #define BRW_MATH_FUNCTION_INV                              1
1434 #define BRW_MATH_FUNCTION_LOG                              2
1435 #define BRW_MATH_FUNCTION_EXP                              3
1436 #define BRW_MATH_FUNCTION_SQRT                             4
1437 #define BRW_MATH_FUNCTION_RSQ                              5
1438 #define BRW_MATH_FUNCTION_SIN                              6
1439 #define BRW_MATH_FUNCTION_COS                              7
1440 #define BRW_MATH_FUNCTION_SINCOS                           8 /* gen4, gen5 */
1441 #define BRW_MATH_FUNCTION_FDIV                             9 /* gen6+ */
1442 #define BRW_MATH_FUNCTION_POW                              10
1443 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER   11
1444 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT                 12
1445 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER                13
1446 #define GEN8_MATH_FUNCTION_INVM                            14
1447 #define GEN8_MATH_FUNCTION_RSQRTM                          15
1448
1449 #define BRW_MATH_INTEGER_UNSIGNED     0
1450 #define BRW_MATH_INTEGER_SIGNED       1
1451
1452 #define BRW_MATH_PRECISION_FULL        0
1453 #define BRW_MATH_PRECISION_PARTIAL     1
1454
1455 #define BRW_MATH_SATURATE_NONE         0
1456 #define BRW_MATH_SATURATE_SATURATE     1
1457
1458 #define BRW_MATH_DATA_VECTOR  0
1459 #define BRW_MATH_DATA_SCALAR  1
1460
1461 #define BRW_URB_OPCODE_WRITE_HWORD  0
1462 #define BRW_URB_OPCODE_WRITE_OWORD  1
1463 #define BRW_URB_OPCODE_READ_HWORD   2
1464 #define BRW_URB_OPCODE_READ_OWORD   3
1465 #define GEN7_URB_OPCODE_ATOMIC_MOV  4
1466 #define GEN7_URB_OPCODE_ATOMIC_INC  5
1467 #define GEN8_URB_OPCODE_ATOMIC_ADD  6
1468 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1469 #define GEN8_URB_OPCODE_SIMD8_READ  8
1470
1471 #define BRW_URB_SWIZZLE_NONE          0
1472 #define BRW_URB_SWIZZLE_INTERLEAVE    1
1473 #define BRW_URB_SWIZZLE_TRANSPOSE     2
1474
1475 #define BRW_SCRATCH_SPACE_SIZE_1K     0
1476 #define BRW_SCRATCH_SPACE_SIZE_2K     1
1477 #define BRW_SCRATCH_SPACE_SIZE_4K     2
1478 #define BRW_SCRATCH_SPACE_SIZE_8K     3
1479 #define BRW_SCRATCH_SPACE_SIZE_16K    4
1480 #define BRW_SCRATCH_SPACE_SIZE_32K    5
1481 #define BRW_SCRATCH_SPACE_SIZE_64K    6
1482 #define BRW_SCRATCH_SPACE_SIZE_128K   7
1483 #define BRW_SCRATCH_SPACE_SIZE_256K   8
1484 #define BRW_SCRATCH_SPACE_SIZE_512K   9
1485 #define BRW_SCRATCH_SPACE_SIZE_1M     10
1486 #define BRW_SCRATCH_SPACE_SIZE_2M     11
1487
1488 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY         0
1489 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY        1
1490 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG          2
1491 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP        3
1492 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG          4
1493 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1494 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE      6
1495
1496
1497 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1498  * is 2^9, or 512.  It's counted in multiples of 64 bytes.
1499  *
1500  * Identical for VS, DS, and HS.
1501  */
1502 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES                (512*64)
1503 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES                (512*64)
1504 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES                (512*64)
1505 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES                (512*64)
1506
1507 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1508  * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1509  */
1510 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES                (5*128)
1511
1512 /* GS Thread Payload
1513  */
1514
1515 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1516  * counted in multiples of 16 bytes.
1517  */
1518 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES            (62*16)
1519
1520
1521 /* R0 */
1522 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT              27
1523
1524 /* CR0.0[5:4] Floating-Point Rounding Modes
1525  *  Skylake PRM, Volume 7 Part 1, "Control Register", page 756
1526  */
1527
1528 #define BRW_CR0_RND_MODE_MASK     0x30
1529 #define BRW_CR0_RND_MODE_SHIFT    4
1530
1531 enum PACKED brw_rnd_mode {
1532    BRW_RND_MODE_RTNE = 0,  /* Round to Nearest or Even */
1533    BRW_RND_MODE_RU = 1,    /* Round Up, toward +inf */
1534    BRW_RND_MODE_RD = 2,    /* Round Down, toward -inf */
1535    BRW_RND_MODE_RTZ = 3,   /* Round Toward Zero */
1536    BRW_RND_MODE_UNSPECIFIED,  /* Unspecified rounding mode */
1537 };
1538
1539 #define BRW_CR0_FP64_DENORM_PRESERVE (1 << 6)
1540 #define BRW_CR0_FP32_DENORM_PRESERVE (1 << 7)
1541 #define BRW_CR0_FP16_DENORM_PRESERVE (1 << 10)
1542
1543 #define BRW_CR0_FP_MODE_MASK (BRW_CR0_FP64_DENORM_PRESERVE | \
1544                               BRW_CR0_FP32_DENORM_PRESERVE | \
1545                               BRW_CR0_FP16_DENORM_PRESERVE | \
1546                               BRW_CR0_RND_MODE_MASK)
1547
1548 /* MDC_DS - Data Size Message Descriptor Control Field
1549  * Skylake PRM, Volume 2d, page 129
1550  *
1551  * Specifies the number of Bytes to be read or written per Dword used at
1552  * byte_scattered read/write and byte_scaled read/write messages.
1553  */
1554 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE     0
1555 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD     1
1556 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD    2
1557
1558 #endif /* BRW_EU_DEFINES_H */