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intel/fs: Add support for SLM fence in Gen11
[mesa.git] / src / intel / compiler / brw_eu_defines.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32 #ifndef BRW_EU_DEFINES_H
33 #define BRW_EU_DEFINES_H
34
35 #include "util/macros.h"
36
37 /* The following hunk, up-to "Execution Unit" is used by both the
38 * intel/compiler and i965 codebase. */
39
40 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
41 /* Using the GNU statement expression extension */
42 #define SET_FIELD(value, field) \
43 ({ \
44 uint32_t fieldval = (uint32_t)(value) << field ## _SHIFT; \
45 assert((fieldval & ~ field ## _MASK) == 0); \
46 fieldval & field ## _MASK; \
47 })
48
49 #define SET_BITS(value, high, low) \
50 ({ \
51 const uint32_t fieldval = (uint32_t)(value) << (low); \
52 assert((fieldval & ~INTEL_MASK(high, low)) == 0); \
53 fieldval & INTEL_MASK(high, low); \
54 })
55
56 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
57 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
58
59 #define _3DPRIM_POINTLIST 0x01
60 #define _3DPRIM_LINELIST 0x02
61 #define _3DPRIM_LINESTRIP 0x03
62 #define _3DPRIM_TRILIST 0x04
63 #define _3DPRIM_TRISTRIP 0x05
64 #define _3DPRIM_TRIFAN 0x06
65 #define _3DPRIM_QUADLIST 0x07
66 #define _3DPRIM_QUADSTRIP 0x08
67 #define _3DPRIM_LINELIST_ADJ 0x09 /* G45+ */
68 #define _3DPRIM_LINESTRIP_ADJ 0x0A /* G45+ */
69 #define _3DPRIM_TRILIST_ADJ 0x0B /* G45+ */
70 #define _3DPRIM_TRISTRIP_ADJ 0x0C /* G45+ */
71 #define _3DPRIM_TRISTRIP_REVERSE 0x0D
72 #define _3DPRIM_POLYGON 0x0E
73 #define _3DPRIM_RECTLIST 0x0F
74 #define _3DPRIM_LINELOOP 0x10
75 #define _3DPRIM_POINTLIST_BF 0x11
76 #define _3DPRIM_LINESTRIP_CONT 0x12
77 #define _3DPRIM_LINESTRIP_BF 0x13
78 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
79 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x16
80 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
81
82 /* Bitfields for the URB_WRITE message, DW2 of message header: */
83 #define URB_WRITE_PRIM_END 0x1
84 #define URB_WRITE_PRIM_START 0x2
85 #define URB_WRITE_PRIM_TYPE_SHIFT 2
86
87 #define BRW_SPRITE_POINT_ENABLE 16
88
89 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
90 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
91
92 /* Execution Unit (EU) defines
93 */
94
95 #define BRW_ALIGN_1 0
96 #define BRW_ALIGN_16 1
97
98 #define BRW_ADDRESS_DIRECT 0
99 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
100
101 #define BRW_CHANNEL_X 0
102 #define BRW_CHANNEL_Y 1
103 #define BRW_CHANNEL_Z 2
104 #define BRW_CHANNEL_W 3
105
106 enum brw_compression {
107 BRW_COMPRESSION_NONE = 0,
108 BRW_COMPRESSION_2NDHALF = 1,
109 BRW_COMPRESSION_COMPRESSED = 2,
110 };
111
112 #define GEN6_COMPRESSION_1Q 0
113 #define GEN6_COMPRESSION_2Q 1
114 #define GEN6_COMPRESSION_3Q 2
115 #define GEN6_COMPRESSION_4Q 3
116 #define GEN6_COMPRESSION_1H 0
117 #define GEN6_COMPRESSION_2H 2
118
119 enum PACKED brw_conditional_mod {
120 BRW_CONDITIONAL_NONE = 0,
121 BRW_CONDITIONAL_Z = 1,
122 BRW_CONDITIONAL_NZ = 2,
123 BRW_CONDITIONAL_EQ = 1, /* Z */
124 BRW_CONDITIONAL_NEQ = 2, /* NZ */
125 BRW_CONDITIONAL_G = 3,
126 BRW_CONDITIONAL_GE = 4,
127 BRW_CONDITIONAL_L = 5,
128 BRW_CONDITIONAL_LE = 6,
129 BRW_CONDITIONAL_R = 7, /* Gen <= 5 */
130 BRW_CONDITIONAL_O = 8,
131 BRW_CONDITIONAL_U = 9,
132 };
133
134 #define BRW_DEBUG_NONE 0
135 #define BRW_DEBUG_BREAKPOINT 1
136
137 #define BRW_DEPENDENCY_NORMAL 0
138 #define BRW_DEPENDENCY_NOTCLEARED 1
139 #define BRW_DEPENDENCY_NOTCHECKED 2
140 #define BRW_DEPENDENCY_DISABLE 3
141
142 enum PACKED brw_execution_size {
143 BRW_EXECUTE_1 = 0,
144 BRW_EXECUTE_2 = 1,
145 BRW_EXECUTE_4 = 2,
146 BRW_EXECUTE_8 = 3,
147 BRW_EXECUTE_16 = 4,
148 BRW_EXECUTE_32 = 5,
149 };
150
151 enum PACKED brw_horizontal_stride {
152 BRW_HORIZONTAL_STRIDE_0 = 0,
153 BRW_HORIZONTAL_STRIDE_1 = 1,
154 BRW_HORIZONTAL_STRIDE_2 = 2,
155 BRW_HORIZONTAL_STRIDE_4 = 3,
156 };
157
158 enum PACKED gen10_align1_3src_src_horizontal_stride {
159 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
160 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
161 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
162 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
163 };
164
165 enum PACKED gen10_align1_3src_dst_horizontal_stride {
166 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
167 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
168 };
169
170 #define BRW_INSTRUCTION_NORMAL 0
171 #define BRW_INSTRUCTION_SATURATE 1
172
173 #define BRW_MASK_ENABLE 0
174 #define BRW_MASK_DISABLE 1
175
176 /** @{
177 *
178 * Gen6 has replaced "mask enable/disable" with WECtrl, which is
179 * effectively the same but much simpler to think about. Now, there
180 * are two contributors ANDed together to whether channels are
181 * executed: The predication on the instruction, and the channel write
182 * enable.
183 */
184 /**
185 * This is the default value. It means that a channel's write enable is set
186 * if the per-channel IP is pointing at this instruction.
187 */
188 #define BRW_WE_NORMAL 0
189 /**
190 * This is used like BRW_MASK_DISABLE, and causes all channels to have
191 * their write enable set. Note that predication still contributes to
192 * whether the channel actually gets written.
193 */
194 #define BRW_WE_ALL 1
195 /** @} */
196
197 enum opcode {
198 /* These are the actual hardware opcodes. */
199 BRW_OPCODE_ILLEGAL = 0,
200 BRW_OPCODE_MOV = 1,
201 BRW_OPCODE_SEL = 2,
202 BRW_OPCODE_MOVI = 3, /**< G45+ */
203 BRW_OPCODE_NOT = 4,
204 BRW_OPCODE_AND = 5,
205 BRW_OPCODE_OR = 6,
206 BRW_OPCODE_XOR = 7,
207 BRW_OPCODE_SHR = 8,
208 BRW_OPCODE_SHL = 9,
209 BRW_OPCODE_DIM = 10, /**< Gen7.5 only */ /* Reused */
210 BRW_OPCODE_SMOV = 10, /**< Gen8+ */ /* Reused */
211 /* Reserved - 11 */
212 BRW_OPCODE_ASR = 12,
213 /* Reserved - 13 */
214 BRW_OPCODE_ROR = 14, /**< Gen11+ */
215 BRW_OPCODE_ROL = 15, /**< Gen11+ */
216 BRW_OPCODE_CMP = 16,
217 BRW_OPCODE_CMPN = 17,
218 BRW_OPCODE_CSEL = 18, /**< Gen8+ */
219 BRW_OPCODE_F32TO16 = 19, /**< Gen7 only */
220 BRW_OPCODE_F16TO32 = 20, /**< Gen7 only */
221 /* Reserved - 21-22 */
222 BRW_OPCODE_BFREV = 23, /**< Gen7+ */
223 BRW_OPCODE_BFE = 24, /**< Gen7+ */
224 BRW_OPCODE_BFI1 = 25, /**< Gen7+ */
225 BRW_OPCODE_BFI2 = 26, /**< Gen7+ */
226 /* Reserved - 27-31 */
227 BRW_OPCODE_JMPI = 32,
228 BRW_OPCODE_BRD = 33, /**< Gen7+ */
229 BRW_OPCODE_IF = 34,
230 BRW_OPCODE_IFF = 35, /**< Pre-Gen6 */ /* Reused */
231 BRW_OPCODE_BRC = 35, /**< Gen7+ */ /* Reused */
232 BRW_OPCODE_ELSE = 36,
233 BRW_OPCODE_ENDIF = 37,
234 BRW_OPCODE_DO = 38, /**< Pre-Gen6 */ /* Reused */
235 BRW_OPCODE_CASE = 38, /**< Gen6 only */ /* Reused */
236 BRW_OPCODE_WHILE = 39,
237 BRW_OPCODE_BREAK = 40,
238 BRW_OPCODE_CONTINUE = 41,
239 BRW_OPCODE_HALT = 42,
240 BRW_OPCODE_CALLA = 43, /**< Gen7.5+ */
241 BRW_OPCODE_MSAVE = 44, /**< Pre-Gen6 */ /* Reused */
242 BRW_OPCODE_CALL = 44, /**< Gen6+ */ /* Reused */
243 BRW_OPCODE_MREST = 45, /**< Pre-Gen6 */ /* Reused */
244 BRW_OPCODE_RET = 45, /**< Gen6+ */ /* Reused */
245 BRW_OPCODE_PUSH = 46, /**< Pre-Gen6 */ /* Reused */
246 BRW_OPCODE_FORK = 46, /**< Gen6 only */ /* Reused */
247 BRW_OPCODE_GOTO = 46, /**< Gen8+ */ /* Reused */
248 BRW_OPCODE_POP = 47, /**< Pre-Gen6 */
249 BRW_OPCODE_WAIT = 48,
250 BRW_OPCODE_SEND = 49,
251 BRW_OPCODE_SENDC = 50,
252 BRW_OPCODE_SENDS = 51, /**< Gen9+ */
253 BRW_OPCODE_SENDSC = 52, /**< Gen9+ */
254 /* Reserved 53-55 */
255 BRW_OPCODE_MATH = 56, /**< Gen6+ */
256 /* Reserved 57-63 */
257 BRW_OPCODE_ADD = 64,
258 BRW_OPCODE_MUL = 65,
259 BRW_OPCODE_AVG = 66,
260 BRW_OPCODE_FRC = 67,
261 BRW_OPCODE_RNDU = 68,
262 BRW_OPCODE_RNDD = 69,
263 BRW_OPCODE_RNDE = 70,
264 BRW_OPCODE_RNDZ = 71,
265 BRW_OPCODE_MAC = 72,
266 BRW_OPCODE_MACH = 73,
267 BRW_OPCODE_LZD = 74,
268 BRW_OPCODE_FBH = 75, /**< Gen7+ */
269 BRW_OPCODE_FBL = 76, /**< Gen7+ */
270 BRW_OPCODE_CBIT = 77, /**< Gen7+ */
271 BRW_OPCODE_ADDC = 78, /**< Gen7+ */
272 BRW_OPCODE_SUBB = 79, /**< Gen7+ */
273 BRW_OPCODE_SAD2 = 80,
274 BRW_OPCODE_SADA2 = 81,
275 /* Reserved 82-83 */
276 BRW_OPCODE_DP4 = 84,
277 BRW_OPCODE_DPH = 85,
278 BRW_OPCODE_DP3 = 86,
279 BRW_OPCODE_DP2 = 87,
280 /* Reserved 88 */
281 BRW_OPCODE_LINE = 89,
282 BRW_OPCODE_PLN = 90, /**< G45+ */
283 BRW_OPCODE_MAD = 91, /**< Gen6+ */
284 BRW_OPCODE_LRP = 92, /**< Gen6+ */
285 BRW_OPCODE_MADM = 93, /**< Gen8+ */
286 /* Reserved 94-124 */
287 BRW_OPCODE_NENOP = 125, /**< G45 only */
288 BRW_OPCODE_NOP = 126,
289 /* Reserved 127 */
290
291 /* These are compiler backend opcodes that get translated into other
292 * instructions.
293 */
294 FS_OPCODE_FB_WRITE = 128,
295
296 /**
297 * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
298 * individual sources instead of as a single payload blob. The
299 * position/ordering of the arguments are defined by the enum
300 * fb_write_logical_srcs.
301 */
302 FS_OPCODE_FB_WRITE_LOGICAL,
303
304 FS_OPCODE_REP_FB_WRITE,
305
306 FS_OPCODE_FB_READ,
307 FS_OPCODE_FB_READ_LOGICAL,
308
309 SHADER_OPCODE_RCP,
310 SHADER_OPCODE_RSQ,
311 SHADER_OPCODE_SQRT,
312 SHADER_OPCODE_EXP2,
313 SHADER_OPCODE_LOG2,
314 SHADER_OPCODE_POW,
315 SHADER_OPCODE_INT_QUOTIENT,
316 SHADER_OPCODE_INT_REMAINDER,
317 SHADER_OPCODE_SIN,
318 SHADER_OPCODE_COS,
319
320 /**
321 * A generic "send" opcode. The first two sources are the message
322 * descriptor and extended message descriptor respectively. The third
323 * and optional fourth sources are the message payload
324 */
325 SHADER_OPCODE_SEND,
326
327 /**
328 * An "undefined" write which does nothing but indicates to liveness that
329 * we don't care about any values in the register which predate this
330 * instruction. Used to prevent partial writes from causing issues with
331 * live ranges.
332 */
333 SHADER_OPCODE_UNDEF,
334
335 /**
336 * Texture sampling opcodes.
337 *
338 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
339 * opcode but instead of taking a single payload blob they expect their
340 * arguments separately as individual sources. The position/ordering of the
341 * arguments are defined by the enum tex_logical_srcs.
342 */
343 SHADER_OPCODE_TEX,
344 SHADER_OPCODE_TEX_LOGICAL,
345 SHADER_OPCODE_TXD,
346 SHADER_OPCODE_TXD_LOGICAL,
347 SHADER_OPCODE_TXF,
348 SHADER_OPCODE_TXF_LOGICAL,
349 SHADER_OPCODE_TXF_LZ,
350 SHADER_OPCODE_TXL,
351 SHADER_OPCODE_TXL_LOGICAL,
352 SHADER_OPCODE_TXL_LZ,
353 SHADER_OPCODE_TXS,
354 SHADER_OPCODE_TXS_LOGICAL,
355 FS_OPCODE_TXB,
356 FS_OPCODE_TXB_LOGICAL,
357 SHADER_OPCODE_TXF_CMS,
358 SHADER_OPCODE_TXF_CMS_LOGICAL,
359 SHADER_OPCODE_TXF_CMS_W,
360 SHADER_OPCODE_TXF_CMS_W_LOGICAL,
361 SHADER_OPCODE_TXF_UMS,
362 SHADER_OPCODE_TXF_UMS_LOGICAL,
363 SHADER_OPCODE_TXF_MCS,
364 SHADER_OPCODE_TXF_MCS_LOGICAL,
365 SHADER_OPCODE_LOD,
366 SHADER_OPCODE_LOD_LOGICAL,
367 SHADER_OPCODE_TG4,
368 SHADER_OPCODE_TG4_LOGICAL,
369 SHADER_OPCODE_TG4_OFFSET,
370 SHADER_OPCODE_TG4_OFFSET_LOGICAL,
371 SHADER_OPCODE_SAMPLEINFO,
372 SHADER_OPCODE_SAMPLEINFO_LOGICAL,
373
374 SHADER_OPCODE_IMAGE_SIZE_LOGICAL,
375
376 /**
377 * Combines multiple sources of size 1 into a larger virtual GRF.
378 * For example, parameters for a send-from-GRF message. Or, updating
379 * channels of a size 4 VGRF used to store vec4s such as texturing results.
380 *
381 * This will be lowered into MOVs from each source to consecutive offsets
382 * of the destination VGRF.
383 *
384 * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV,
385 * but still reserves the first channel of the destination VGRF. This can be
386 * used to reserve space for, say, a message header set up by the generators.
387 */
388 SHADER_OPCODE_LOAD_PAYLOAD,
389
390 /**
391 * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
392 * acts intra-channel, obtaining the final value for each channel by
393 * combining the sources values for the same channel, the first source
394 * occupying the lowest bits and the last source occupying the highest
395 * bits.
396 */
397 FS_OPCODE_PACK,
398
399 SHADER_OPCODE_SHADER_TIME_ADD,
400
401 /**
402 * Typed and untyped surface access opcodes.
403 *
404 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
405 * opcode but instead of taking a single payload blob they expect their
406 * arguments separately as individual sources:
407 *
408 * Source 0: [required] Surface coordinates.
409 * Source 1: [optional] Operation source.
410 * Source 2: [required] Surface index.
411 * Source 3: [required] Number of coordinate components (as UD immediate).
412 * Source 4: [required] Opcode-specific control immediate, same as source 2
413 * of the matching non-LOGICAL opcode.
414 */
415 VEC4_OPCODE_UNTYPED_ATOMIC,
416 SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
417 SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
418 VEC4_OPCODE_UNTYPED_SURFACE_READ,
419 SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
420 VEC4_OPCODE_UNTYPED_SURFACE_WRITE,
421 SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
422
423 /**
424 * Untyped A64 surface access opcodes.
425 *
426 * Source 0: 64-bit address
427 * Source 1: Operational source
428 * Source 2: [required] Opcode-specific control immediate, same as source 2
429 * of the matching non-LOGICAL opcode.
430 */
431 SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL,
432 SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL,
433 SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL,
434 SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL,
435 SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL,
436 SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL,
437 SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL,
438
439 SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
440 SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
441 SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
442
443 SHADER_OPCODE_RND_MODE,
444
445 /**
446 * Byte scattered write/read opcodes.
447 *
448 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
449 * opcode, but instead of taking a single payload blog they expect their
450 * arguments separately as individual sources, like untyped write/read.
451 */
452 SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
453 SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
454
455 /**
456 * Memory fence messages.
457 *
458 * Source 0: Must be register g0, used as header.
459 * Source 1: Immediate bool to indicate whether or not we need to stall
460 * until memory transactions prior to the fence are completed.
461 * Source 2: Immediate byte indicating which memory to fence. Zero means
462 * global memory; GEN7_BTI_SLM means SLM (for Gen11+ only).
463 *
464 * Vec4 backend only uses Source 0.
465 */
466 SHADER_OPCODE_MEMORY_FENCE,
467
468 SHADER_OPCODE_GEN4_SCRATCH_READ,
469 SHADER_OPCODE_GEN4_SCRATCH_WRITE,
470 SHADER_OPCODE_GEN7_SCRATCH_READ,
471
472 /**
473 * Gen8+ SIMD8 URB Read messages.
474 */
475 SHADER_OPCODE_URB_READ_SIMD8,
476 SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
477
478 SHADER_OPCODE_URB_WRITE_SIMD8,
479 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
480 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
481 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
482
483 /**
484 * Return the index of an arbitrary live channel (i.e. one of the channels
485 * enabled in the current execution mask) and assign it to the first
486 * component of the destination. Expected to be used as input for the
487 * BROADCAST pseudo-opcode.
488 */
489 SHADER_OPCODE_FIND_LIVE_CHANNEL,
490
491 /**
492 * Pick the channel from its first source register given by the index
493 * specified as second source. Useful for variable indexing of surfaces.
494 *
495 * Note that because the result of this instruction is by definition
496 * uniform and it can always be splatted to multiple channels using a
497 * scalar regioning mode, only the first channel of the destination region
498 * is guaranteed to be updated, which implies that BROADCAST instructions
499 * should usually be marked force_writemask_all.
500 */
501 SHADER_OPCODE_BROADCAST,
502
503 /* Pick the channel from its first source register given by the index
504 * specified as second source.
505 *
506 * This is similar to the BROADCAST instruction except that it takes a
507 * dynamic index and potentially puts a different value in each output
508 * channel.
509 */
510 SHADER_OPCODE_SHUFFLE,
511
512 /* Select between src0 and src1 based on channel enables.
513 *
514 * This instruction copies src0 into the enabled channels of the
515 * destination and copies src1 into the disabled channels.
516 */
517 SHADER_OPCODE_SEL_EXEC,
518
519 /* This turns into an align16 mov from src0 to dst with a swizzle
520 * provided as an immediate in src1.
521 */
522 SHADER_OPCODE_QUAD_SWIZZLE,
523
524 /* Take every Nth element in src0 and broadcast it to the group of N
525 * channels in which it lives in the destination. The offset within the
526 * cluster is given by src1 and the cluster size is given by src2.
527 */
528 SHADER_OPCODE_CLUSTER_BROADCAST,
529
530 SHADER_OPCODE_GET_BUFFER_SIZE,
531
532 SHADER_OPCODE_INTERLOCK,
533
534 VEC4_OPCODE_MOV_BYTES,
535 VEC4_OPCODE_PACK_BYTES,
536 VEC4_OPCODE_UNPACK_UNIFORM,
537 VEC4_OPCODE_DOUBLE_TO_F32,
538 VEC4_OPCODE_DOUBLE_TO_D32,
539 VEC4_OPCODE_DOUBLE_TO_U32,
540 VEC4_OPCODE_TO_DOUBLE,
541 VEC4_OPCODE_PICK_LOW_32BIT,
542 VEC4_OPCODE_PICK_HIGH_32BIT,
543 VEC4_OPCODE_SET_LOW_32BIT,
544 VEC4_OPCODE_SET_HIGH_32BIT,
545
546 FS_OPCODE_DDX_COARSE,
547 FS_OPCODE_DDX_FINE,
548 /**
549 * Compute dFdy(), dFdyCoarse(), or dFdyFine().
550 */
551 FS_OPCODE_DDY_COARSE,
552 FS_OPCODE_DDY_FINE,
553 FS_OPCODE_LINTERP,
554 FS_OPCODE_PIXEL_X,
555 FS_OPCODE_PIXEL_Y,
556 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
557 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
558 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
559 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
560 FS_OPCODE_DISCARD_JUMP,
561 FS_OPCODE_SET_SAMPLE_ID,
562 FS_OPCODE_PACK_HALF_2x16_SPLIT,
563 FS_OPCODE_PLACEHOLDER_HALT,
564 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
565 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
566 FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
567
568 VS_OPCODE_URB_WRITE,
569 VS_OPCODE_PULL_CONSTANT_LOAD,
570 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
571 VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
572
573 VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
574
575 /**
576 * Write geometry shader output data to the URB.
577 *
578 * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
579 * R0 to the first MRF. This allows the geometry shader to override the
580 * "Slot {0,1} Offset" fields in the message header.
581 */
582 GS_OPCODE_URB_WRITE,
583
584 /**
585 * Write geometry shader output data to the URB and request a new URB
586 * handle (gen6).
587 *
588 * This opcode doesn't do an implied move from R0 to the first MRF.
589 */
590 GS_OPCODE_URB_WRITE_ALLOCATE,
591
592 /**
593 * Terminate the geometry shader thread by doing an empty URB write.
594 *
595 * This opcode doesn't do an implied move from R0 to the first MRF. This
596 * allows the geometry shader to override the "GS Number of Output Vertices
597 * for Slot {0,1}" fields in the message header.
598 */
599 GS_OPCODE_THREAD_END,
600
601 /**
602 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
603 *
604 * - dst is the MRF containing the message header.
605 *
606 * - src0.x indicates which portion of the URB should be written to (e.g. a
607 * vertex number)
608 *
609 * - src1 is an immediate multiplier which will be applied to src0
610 * (e.g. the size of a single vertex in the URB).
611 *
612 * Note: the hardware will apply this offset *in addition to* the offset in
613 * vec4_instruction::offset.
614 */
615 GS_OPCODE_SET_WRITE_OFFSET,
616
617 /**
618 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
619 * URB_WRITE message header.
620 *
621 * - dst is the MRF containing the message header.
622 *
623 * - src0.x is the vertex count. The upper 16 bits will be ignored.
624 */
625 GS_OPCODE_SET_VERTEX_COUNT,
626
627 /**
628 * Set DWORD 2 of dst to the value in src.
629 */
630 GS_OPCODE_SET_DWORD_2,
631
632 /**
633 * Prepare the dst register for storage in the "Channel Mask" fields of a
634 * URB_WRITE message header.
635 *
636 * DWORD 4 of dst is shifted left by 4 bits, so that later,
637 * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
638 * final channel mask.
639 *
640 * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
641 * form the final channel mask, DWORDs 0 and 4 of the dst register must not
642 * have any extraneous bits set prior to execution of this opcode (that is,
643 * they should be in the range 0x0 to 0xf).
644 */
645 GS_OPCODE_PREPARE_CHANNEL_MASKS,
646
647 /**
648 * Set the "Channel Mask" fields of a URB_WRITE message header.
649 *
650 * - dst is the MRF containing the message header.
651 *
652 * - src.x is the channel mask, as prepared by
653 * GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to
654 * form the final channel mask.
655 */
656 GS_OPCODE_SET_CHANNEL_MASKS,
657
658 /**
659 * Get the "Instance ID" fields from the payload.
660 *
661 * - dst is the GRF for gl_InvocationID.
662 */
663 GS_OPCODE_GET_INSTANCE_ID,
664
665 /**
666 * Send a FF_SYNC message to allocate initial URB handles (gen6).
667 *
668 * - dst will be used as the writeback register for the FF_SYNC operation.
669 *
670 * - src0 is the number of primitives written.
671 *
672 * - src1 is the value to hold in M0.0: number of SO vertices to write
673 * and number of SO primitives needed. Its value will be overwritten
674 * with the SVBI values if transform feedback is enabled.
675 *
676 * Note: This opcode uses an implicit MRF register for the ff_sync message
677 * header, so the caller is expected to set inst->base_mrf and initialize
678 * that MRF register to r0. This opcode will also write to this MRF register
679 * to include the allocated URB handle so it can then be reused directly as
680 * the header in the URB write operation we are allocating the handle for.
681 */
682 GS_OPCODE_FF_SYNC,
683
684 /**
685 * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
686 * register.
687 *
688 * - dst is the GRF where PrimitiveID information will be moved.
689 */
690 GS_OPCODE_SET_PRIMITIVE_ID,
691
692 /**
693 * Write transform feedback data to the SVB by sending a SVB WRITE message.
694 * Used in gen6.
695 *
696 * - dst is the MRF register containing the message header.
697 *
698 * - src0 is the register where the vertex data is going to be copied from.
699 *
700 * - src1 is the destination register when write commit occurs.
701 */
702 GS_OPCODE_SVB_WRITE,
703
704 /**
705 * Set destination index in the SVB write message payload (M0.5). Used
706 * in gen6 for transform feedback.
707 *
708 * - dst is the header to save the destination indices for SVB WRITE.
709 * - src is the register that holds the destination indices value.
710 */
711 GS_OPCODE_SVB_SET_DST_INDEX,
712
713 /**
714 * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
715 * Used in gen6 for transform feedback.
716 *
717 * - dst will hold the register with the final Mx.0 value.
718 *
719 * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
720 *
721 * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
722 *
723 * - src2 is the value to hold in M0: number of SO vertices to write
724 * and number of SO primitives needed.
725 */
726 GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
727
728 /**
729 * Terminate the compute shader.
730 */
731 CS_OPCODE_CS_TERMINATE,
732
733 /**
734 * GLSL barrier()
735 */
736 SHADER_OPCODE_BARRIER,
737
738 /**
739 * Calculate the high 32-bits of a 32x32 multiply.
740 */
741 SHADER_OPCODE_MULH,
742
743 /**
744 * A MOV that uses VxH indirect addressing.
745 *
746 * Source 0: A register to start from (HW_REG).
747 * Source 1: An indirect offset (in bytes, UD GRF).
748 * Source 2: The length of the region that could be accessed (in bytes,
749 * UD immediate).
750 */
751 SHADER_OPCODE_MOV_INDIRECT,
752
753 VEC4_OPCODE_URB_READ,
754 TCS_OPCODE_GET_INSTANCE_ID,
755 TCS_OPCODE_URB_WRITE,
756 TCS_OPCODE_SET_INPUT_URB_OFFSETS,
757 TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
758 TCS_OPCODE_GET_PRIMITIVE_ID,
759 TCS_OPCODE_CREATE_BARRIER_HEADER,
760 TCS_OPCODE_SRC0_010_IS_ZERO,
761 TCS_OPCODE_RELEASE_INPUT,
762 TCS_OPCODE_THREAD_END,
763
764 TES_OPCODE_GET_PRIMITIVE_ID,
765 TES_OPCODE_CREATE_INPUT_READ_HEADER,
766 TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
767 };
768
769 enum brw_urb_write_flags {
770 BRW_URB_WRITE_NO_FLAGS = 0,
771
772 /**
773 * Causes a new URB entry to be allocated, and its address stored in the
774 * destination register (gen < 7).
775 */
776 BRW_URB_WRITE_ALLOCATE = 0x1,
777
778 /**
779 * Causes the current URB entry to be deallocated (gen < 7).
780 */
781 BRW_URB_WRITE_UNUSED = 0x2,
782
783 /**
784 * Causes the thread to terminate.
785 */
786 BRW_URB_WRITE_EOT = 0x4,
787
788 /**
789 * Indicates that the given URB entry is complete, and may be sent further
790 * down the 3D pipeline (gen < 7).
791 */
792 BRW_URB_WRITE_COMPLETE = 0x8,
793
794 /**
795 * Indicates that an additional offset (which may be different for the two
796 * vec4 slots) is stored in the message header (gen == 7).
797 */
798 BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
799
800 /**
801 * Indicates that the channel masks in the URB_WRITE message header should
802 * not be overridden to 0xff (gen == 7).
803 */
804 BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
805
806 /**
807 * Indicates that the data should be sent to the URB using the
808 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This
809 * causes offsets to be interpreted as multiples of an OWORD instead of an
810 * HWORD, and only allows one OWORD to be written.
811 */
812 BRW_URB_WRITE_OWORD = 0x40,
813
814 /**
815 * Convenient combination of flags: end the thread while simultaneously
816 * marking the given URB entry as complete.
817 */
818 BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
819
820 /**
821 * Convenient combination of flags: mark the given URB entry as complete
822 * and simultaneously allocate a new one.
823 */
824 BRW_URB_WRITE_ALLOCATE_COMPLETE =
825 BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
826 };
827
828 enum fb_write_logical_srcs {
829 FB_WRITE_LOGICAL_SRC_COLOR0, /* REQUIRED */
830 FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */
831 FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
832 FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */
833 FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GEN4-5: passthrough from thread */
834 FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
835 FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */
836 FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */
837 FB_WRITE_LOGICAL_NUM_SRCS
838 };
839
840 enum tex_logical_srcs {
841 /** Texture coordinates */
842 TEX_LOGICAL_SRC_COORDINATE,
843 /** Shadow comparator */
844 TEX_LOGICAL_SRC_SHADOW_C,
845 /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
846 TEX_LOGICAL_SRC_LOD,
847 /** dPdy if the operation takes explicit derivatives */
848 TEX_LOGICAL_SRC_LOD2,
849 /** Min LOD */
850 TEX_LOGICAL_SRC_MIN_LOD,
851 /** Sample index */
852 TEX_LOGICAL_SRC_SAMPLE_INDEX,
853 /** MCS data */
854 TEX_LOGICAL_SRC_MCS,
855 /** REQUIRED: Texture surface index */
856 TEX_LOGICAL_SRC_SURFACE,
857 /** Texture sampler index */
858 TEX_LOGICAL_SRC_SAMPLER,
859 /** Texture surface bindless handle */
860 TEX_LOGICAL_SRC_SURFACE_HANDLE,
861 /** Texture sampler bindless handle */
862 TEX_LOGICAL_SRC_SAMPLER_HANDLE,
863 /** Texel offset for gathers */
864 TEX_LOGICAL_SRC_TG4_OFFSET,
865 /** REQUIRED: Number of coordinate components (as UD immediate) */
866 TEX_LOGICAL_SRC_COORD_COMPONENTS,
867 /** REQUIRED: Number of derivative components (as UD immediate) */
868 TEX_LOGICAL_SRC_GRAD_COMPONENTS,
869
870 TEX_LOGICAL_NUM_SRCS,
871 };
872
873 enum surface_logical_srcs {
874 /** Surface binding table index */
875 SURFACE_LOGICAL_SRC_SURFACE,
876 /** Surface bindless handle */
877 SURFACE_LOGICAL_SRC_SURFACE_HANDLE,
878 /** Surface address; could be multi-dimensional for typed opcodes */
879 SURFACE_LOGICAL_SRC_ADDRESS,
880 /** Data to be written or used in an atomic op */
881 SURFACE_LOGICAL_SRC_DATA,
882 /** Surface number of dimensions. Affects the size of ADDRESS */
883 SURFACE_LOGICAL_SRC_IMM_DIMS,
884 /** Per-opcode immediate argument. For atomics, this is the atomic opcode */
885 SURFACE_LOGICAL_SRC_IMM_ARG,
886
887 SURFACE_LOGICAL_NUM_SRCS
888 };
889
890 #ifdef __cplusplus
891 /**
892 * Allow brw_urb_write_flags enums to be ORed together.
893 */
894 inline brw_urb_write_flags
895 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
896 {
897 return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
898 static_cast<int>(y));
899 }
900 #endif
901
902 enum PACKED brw_predicate {
903 BRW_PREDICATE_NONE = 0,
904 BRW_PREDICATE_NORMAL = 1,
905 BRW_PREDICATE_ALIGN1_ANYV = 2,
906 BRW_PREDICATE_ALIGN1_ALLV = 3,
907 BRW_PREDICATE_ALIGN1_ANY2H = 4,
908 BRW_PREDICATE_ALIGN1_ALL2H = 5,
909 BRW_PREDICATE_ALIGN1_ANY4H = 6,
910 BRW_PREDICATE_ALIGN1_ALL4H = 7,
911 BRW_PREDICATE_ALIGN1_ANY8H = 8,
912 BRW_PREDICATE_ALIGN1_ALL8H = 9,
913 BRW_PREDICATE_ALIGN1_ANY16H = 10,
914 BRW_PREDICATE_ALIGN1_ALL16H = 11,
915 BRW_PREDICATE_ALIGN1_ANY32H = 12,
916 BRW_PREDICATE_ALIGN1_ALL32H = 13,
917 BRW_PREDICATE_ALIGN16_REPLICATE_X = 2,
918 BRW_PREDICATE_ALIGN16_REPLICATE_Y = 3,
919 BRW_PREDICATE_ALIGN16_REPLICATE_Z = 4,
920 BRW_PREDICATE_ALIGN16_REPLICATE_W = 5,
921 BRW_PREDICATE_ALIGN16_ANY4H = 6,
922 BRW_PREDICATE_ALIGN16_ALL4H = 7,
923 };
924
925 enum PACKED brw_reg_file {
926 BRW_ARCHITECTURE_REGISTER_FILE = 0,
927 BRW_GENERAL_REGISTER_FILE = 1,
928 BRW_MESSAGE_REGISTER_FILE = 2,
929 BRW_IMMEDIATE_VALUE = 3,
930
931 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
932 FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
933 MRF = BRW_MESSAGE_REGISTER_FILE,
934 IMM = BRW_IMMEDIATE_VALUE,
935
936 /* These are not hardware values */
937 VGRF,
938 ATTR,
939 UNIFORM, /* prog_data->params[reg] */
940 BAD_FILE,
941 };
942
943 enum PACKED gen10_align1_3src_reg_file {
944 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0,
945 BRW_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */
946 BRW_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */
947 };
948
949 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction
950 * word is "Execution Datatype" which controls whether the instruction operates
951 * on float or integer types. The register arguments have fields that offer
952 * more fine control their respective types.
953 */
954 enum PACKED gen10_align1_3src_exec_type {
955 BRW_ALIGN1_3SRC_EXEC_TYPE_INT = 0,
956 BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
957 };
958
959 #define BRW_ARF_NULL 0x00
960 #define BRW_ARF_ADDRESS 0x10
961 #define BRW_ARF_ACCUMULATOR 0x20
962 #define BRW_ARF_FLAG 0x30
963 #define BRW_ARF_MASK 0x40
964 #define BRW_ARF_MASK_STACK 0x50
965 #define BRW_ARF_MASK_STACK_DEPTH 0x60
966 #define BRW_ARF_STATE 0x70
967 #define BRW_ARF_CONTROL 0x80
968 #define BRW_ARF_NOTIFICATION_COUNT 0x90
969 #define BRW_ARF_IP 0xA0
970 #define BRW_ARF_TDR 0xB0
971 #define BRW_ARF_TIMESTAMP 0xC0
972
973 #define BRW_MRF_COMPR4 (1 << 7)
974
975 #define BRW_AMASK 0
976 #define BRW_IMASK 1
977 #define BRW_LMASK 2
978 #define BRW_CMASK 3
979
980
981
982 #define BRW_THREAD_NORMAL 0
983 #define BRW_THREAD_ATOMIC 1
984 #define BRW_THREAD_SWITCH 2
985
986 enum PACKED brw_vertical_stride {
987 BRW_VERTICAL_STRIDE_0 = 0,
988 BRW_VERTICAL_STRIDE_1 = 1,
989 BRW_VERTICAL_STRIDE_2 = 2,
990 BRW_VERTICAL_STRIDE_4 = 3,
991 BRW_VERTICAL_STRIDE_8 = 4,
992 BRW_VERTICAL_STRIDE_16 = 5,
993 BRW_VERTICAL_STRIDE_32 = 6,
994 BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
995 };
996
997 enum PACKED gen10_align1_3src_vertical_stride {
998 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
999 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
1000 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2,
1001 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,
1002 };
1003
1004 enum PACKED brw_width {
1005 BRW_WIDTH_1 = 0,
1006 BRW_WIDTH_2 = 1,
1007 BRW_WIDTH_4 = 2,
1008 BRW_WIDTH_8 = 3,
1009 BRW_WIDTH_16 = 4,
1010 };
1011
1012 /**
1013 * Message target: Shared Function ID for where to SEND a message.
1014 *
1015 * These are enumerated in the ISA reference under "send - Send Message".
1016 * In particular, see the following tables:
1017 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
1018 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
1019 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
1020 */
1021 enum brw_message_target {
1022 BRW_SFID_NULL = 0,
1023 BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */
1024 BRW_SFID_SAMPLER = 2,
1025 BRW_SFID_MESSAGE_GATEWAY = 3,
1026 BRW_SFID_DATAPORT_READ = 4,
1027 BRW_SFID_DATAPORT_WRITE = 5,
1028 BRW_SFID_URB = 6,
1029 BRW_SFID_THREAD_SPAWNER = 7,
1030 BRW_SFID_VME = 8,
1031
1032 GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4,
1033 GEN6_SFID_DATAPORT_RENDER_CACHE = 5,
1034 GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
1035
1036 GEN7_SFID_DATAPORT_DATA_CACHE = 10,
1037 GEN7_SFID_PIXEL_INTERPOLATOR = 11,
1038 HSW_SFID_DATAPORT_DATA_CACHE_1 = 12,
1039 HSW_SFID_CRE = 13,
1040 };
1041
1042 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
1043
1044 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
1045 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
1046 #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
1047
1048 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
1049 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
1050 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
1051 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
1052 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
1053 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
1054 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
1055 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
1056 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
1057 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
1058 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
1059 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
1060 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1
1061 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
1062 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
1063 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
1064 #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
1065 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
1066
1067 #define GEN5_SAMPLER_MESSAGE_SAMPLE 0
1068 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
1069 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2
1070 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3
1071 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4
1072 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
1073 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
1074 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
1075 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
1076 #define GEN5_SAMPLER_MESSAGE_LOD 9
1077 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
1078 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
1079 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
1080 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
1081 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
1082 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
1083 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ 24
1084 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ 25
1085 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ 26
1086 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28
1087 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
1088 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
1089 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
1090
1091 /* for GEN5 only */
1092 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
1093 #define BRW_SAMPLER_SIMD_MODE_SIMD8 1
1094 #define BRW_SAMPLER_SIMD_MODE_SIMD16 2
1095 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
1096
1097 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
1098 * behavior by setting bit 22 of dword 2 in the message header. */
1099 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D 0
1100 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22)
1101
1102 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
1103 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
1104 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
1105 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
1106 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
1107 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n) \
1108 ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \
1109 (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \
1110 (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \
1111 (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \
1112 (abort(), ~0))
1113
1114 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
1115 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
1116
1117 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
1118 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
1119
1120 /* This one stays the same across generations. */
1121 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
1122 /* GEN4 */
1123 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
1124 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
1125 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
1126 /* G45, GEN5 */
1127 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1128 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1129 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3
1130 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1131 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1132 /* GEN6 */
1133 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1134 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1135 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1136 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
1137 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1138
1139 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
1140 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
1141 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
1142
1143 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
1144 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
1145 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
1146 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
1147 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
1148
1149 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
1150 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
1151 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2
1152 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
1153 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
1154 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
1155 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
1156
1157 /* GEN6 */
1158 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
1159 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
1160 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9
1161 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10
1162 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11
1163 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12
1164 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
1165 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
1166
1167 /* GEN7 */
1168 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ 4
1169 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ 5
1170 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP 6
1171 #define GEN7_DATAPORT_RC_MEMORY_FENCE 7
1172 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10
1173 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE 12
1174 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE 13
1175 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0
1176 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1
1177 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2
1178 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3
1179 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4
1180 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5
1181 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6
1182 #define GEN7_DATAPORT_DC_MEMORY_FENCE 7
1183 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8
1184 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10
1185 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11
1186 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
1187 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
1188
1189 #define GEN7_DATAPORT_SCRATCH_READ ((1 << 18) | \
1190 (0 << 17))
1191 #define GEN7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \
1192 (1 << 17))
1193 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12
1194
1195 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0
1196 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1
1197 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID 2
1198 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3
1199
1200 /* HSW */
1201 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0
1202 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1
1203 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2
1204 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3
1205 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4
1206 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7
1207 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8
1208 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10
1209 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11
1210 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12
1211
1212 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1
1213 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2
1214 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3
1215 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4
1216 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5
1217 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6
1218 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7
1219 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9
1220 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10
1221 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11
1222 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12
1223 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13
1224 #define GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ 0x10
1225 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ 0x11
1226 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP 0x12
1227 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE 0x19
1228 #define GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE 0x1a
1229 #define GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP 0x1b
1230 #define GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP 0x1d
1231
1232 /* GEN9 */
1233 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE 12
1234 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ 13
1235
1236 /* A64 scattered message subtype */
1237 #define GEN8_A64_SCATTERED_SUBTYPE_BYTE 0
1238 #define GEN8_A64_SCATTERED_SUBTYPE_DWORD 1
1239 #define GEN8_A64_SCATTERED_SUBTYPE_QWORD 2
1240 #define GEN8_A64_SCATTERED_SUBTYPE_HWORD 3
1241
1242 /* Dataport special binding table indices: */
1243 #define BRW_BTI_STATELESS 255
1244 #define GEN7_BTI_SLM 254
1245 /* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the
1246 * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW,
1247 * CHV and at least some pre-production steppings of SKL due to
1248 * WaForceEnableNonCoherent, HDC memory access may have been overridden by the
1249 * kernel to be non-coherent (matching the behavior of the same BTI on
1250 * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253.
1251 */
1252 #define GEN8_BTI_STATELESS_IA_COHERENT 255
1253 #define GEN8_BTI_STATELESS_NON_COHERENT 253
1254 #define GEN9_BTI_BINDLESS 252
1255
1256 /* Dataport atomic operations for Untyped Atomic Integer Operation message
1257 * (and others).
1258 */
1259 #define BRW_AOP_AND 1
1260 #define BRW_AOP_OR 2
1261 #define BRW_AOP_XOR 3
1262 #define BRW_AOP_MOV 4
1263 #define BRW_AOP_INC 5
1264 #define BRW_AOP_DEC 6
1265 #define BRW_AOP_ADD 7
1266 #define BRW_AOP_SUB 8
1267 #define BRW_AOP_REVSUB 9
1268 #define BRW_AOP_IMAX 10
1269 #define BRW_AOP_IMIN 11
1270 #define BRW_AOP_UMAX 12
1271 #define BRW_AOP_UMIN 13
1272 #define BRW_AOP_CMPWR 14
1273 #define BRW_AOP_PREDEC 15
1274
1275 /* Dataport atomic operations for Untyped Atomic Float Operation message. */
1276 #define BRW_AOP_FMAX 1
1277 #define BRW_AOP_FMIN 2
1278 #define BRW_AOP_FCMPWR 3
1279
1280 #define BRW_MATH_FUNCTION_INV 1
1281 #define BRW_MATH_FUNCTION_LOG 2
1282 #define BRW_MATH_FUNCTION_EXP 3
1283 #define BRW_MATH_FUNCTION_SQRT 4
1284 #define BRW_MATH_FUNCTION_RSQ 5
1285 #define BRW_MATH_FUNCTION_SIN 6
1286 #define BRW_MATH_FUNCTION_COS 7
1287 #define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */
1288 #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
1289 #define BRW_MATH_FUNCTION_POW 10
1290 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
1291 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
1292 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
1293 #define GEN8_MATH_FUNCTION_INVM 14
1294 #define GEN8_MATH_FUNCTION_RSQRTM 15
1295
1296 #define BRW_MATH_INTEGER_UNSIGNED 0
1297 #define BRW_MATH_INTEGER_SIGNED 1
1298
1299 #define BRW_MATH_PRECISION_FULL 0
1300 #define BRW_MATH_PRECISION_PARTIAL 1
1301
1302 #define BRW_MATH_SATURATE_NONE 0
1303 #define BRW_MATH_SATURATE_SATURATE 1
1304
1305 #define BRW_MATH_DATA_VECTOR 0
1306 #define BRW_MATH_DATA_SCALAR 1
1307
1308 #define BRW_URB_OPCODE_WRITE_HWORD 0
1309 #define BRW_URB_OPCODE_WRITE_OWORD 1
1310 #define BRW_URB_OPCODE_READ_HWORD 2
1311 #define BRW_URB_OPCODE_READ_OWORD 3
1312 #define GEN7_URB_OPCODE_ATOMIC_MOV 4
1313 #define GEN7_URB_OPCODE_ATOMIC_INC 5
1314 #define GEN8_URB_OPCODE_ATOMIC_ADD 6
1315 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1316 #define GEN8_URB_OPCODE_SIMD8_READ 8
1317
1318 #define BRW_URB_SWIZZLE_NONE 0
1319 #define BRW_URB_SWIZZLE_INTERLEAVE 1
1320 #define BRW_URB_SWIZZLE_TRANSPOSE 2
1321
1322 #define BRW_SCRATCH_SPACE_SIZE_1K 0
1323 #define BRW_SCRATCH_SPACE_SIZE_2K 1
1324 #define BRW_SCRATCH_SPACE_SIZE_4K 2
1325 #define BRW_SCRATCH_SPACE_SIZE_8K 3
1326 #define BRW_SCRATCH_SPACE_SIZE_16K 4
1327 #define BRW_SCRATCH_SPACE_SIZE_32K 5
1328 #define BRW_SCRATCH_SPACE_SIZE_64K 6
1329 #define BRW_SCRATCH_SPACE_SIZE_128K 7
1330 #define BRW_SCRATCH_SPACE_SIZE_256K 8
1331 #define BRW_SCRATCH_SPACE_SIZE_512K 9
1332 #define BRW_SCRATCH_SPACE_SIZE_1M 10
1333 #define BRW_SCRATCH_SPACE_SIZE_2M 11
1334
1335 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0
1336 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1
1337 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2
1338 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3
1339 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4
1340 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1341 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6
1342
1343
1344 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1345 * is 2^9, or 512. It's counted in multiples of 64 bytes.
1346 *
1347 * Identical for VS, DS, and HS.
1348 */
1349 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
1350 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64)
1351 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64)
1352 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64)
1353
1354 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1355 * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1356 */
1357 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128)
1358
1359 /* GS Thread Payload
1360 */
1361
1362 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1363 * counted in multiples of 16 bytes.
1364 */
1365 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16)
1366
1367
1368 /* R0 */
1369 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
1370
1371 /* CR0.0[5:4] Floating-Point Rounding Modes
1372 * Skylake PRM, Volume 7 Part 1, "Control Register", page 756
1373 */
1374
1375 #define BRW_CR0_RND_MODE_MASK 0x30
1376 #define BRW_CR0_RND_MODE_SHIFT 4
1377
1378 enum PACKED brw_rnd_mode {
1379 BRW_RND_MODE_RTNE = 0, /* Round to Nearest or Even */
1380 BRW_RND_MODE_RU = 1, /* Round Up, toward +inf */
1381 BRW_RND_MODE_RD = 2, /* Round Down, toward -inf */
1382 BRW_RND_MODE_RTZ = 3, /* Round Toward Zero */
1383 BRW_RND_MODE_UNSPECIFIED, /* Unspecified rounding mode */
1384 };
1385
1386 /* MDC_DS - Data Size Message Descriptor Control Field
1387 * Skylake PRM, Volume 2d, page 129
1388 *
1389 * Specifies the number of Bytes to be read or written per Dword used at
1390 * byte_scattered read/write and byte_scaled read/write messages.
1391 */
1392 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE 0
1393 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD 1
1394 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2
1395
1396 #endif /* BRW_EU_DEFINES_H */