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i965/fs: Define new shader opcode to set rounding modes
[mesa.git] / src / intel / compiler / brw_eu_defines.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32 #ifndef BRW_EU_DEFINES_H
33 #define BRW_EU_DEFINES_H
34
35 #include "util/macros.h"
36
37 /* The following hunk, up-to "Execution Unit" is used by both the
38 * intel/compiler and i965 codebase. */
39
40 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
41 /* Using the GNU statement expression extension */
42 #define SET_FIELD(value, field) \
43 ({ \
44 uint32_t fieldval = (value) << field ## _SHIFT; \
45 assert((fieldval & ~ field ## _MASK) == 0); \
46 fieldval & field ## _MASK; \
47 })
48
49 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
50 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
51
52 #define _3DPRIM_POINTLIST 0x01
53 #define _3DPRIM_LINELIST 0x02
54 #define _3DPRIM_LINESTRIP 0x03
55 #define _3DPRIM_TRILIST 0x04
56 #define _3DPRIM_TRISTRIP 0x05
57 #define _3DPRIM_TRIFAN 0x06
58 #define _3DPRIM_QUADLIST 0x07
59 #define _3DPRIM_QUADSTRIP 0x08
60 #define _3DPRIM_LINELIST_ADJ 0x09 /* G45+ */
61 #define _3DPRIM_LINESTRIP_ADJ 0x0A /* G45+ */
62 #define _3DPRIM_TRILIST_ADJ 0x0B /* G45+ */
63 #define _3DPRIM_TRISTRIP_ADJ 0x0C /* G45+ */
64 #define _3DPRIM_TRISTRIP_REVERSE 0x0D
65 #define _3DPRIM_POLYGON 0x0E
66 #define _3DPRIM_RECTLIST 0x0F
67 #define _3DPRIM_LINELOOP 0x10
68 #define _3DPRIM_POINTLIST_BF 0x11
69 #define _3DPRIM_LINESTRIP_CONT 0x12
70 #define _3DPRIM_LINESTRIP_BF 0x13
71 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
72 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x16
73 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
74
75 /* Bitfields for the URB_WRITE message, DW2 of message header: */
76 #define URB_WRITE_PRIM_END 0x1
77 #define URB_WRITE_PRIM_START 0x2
78 #define URB_WRITE_PRIM_TYPE_SHIFT 2
79
80 #define BRW_SPRITE_POINT_ENABLE 16
81
82 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
83 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
84
85 /* Execution Unit (EU) defines
86 */
87
88 #define BRW_ALIGN_1 0
89 #define BRW_ALIGN_16 1
90
91 #define BRW_ADDRESS_DIRECT 0
92 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
93
94 #define BRW_CHANNEL_X 0
95 #define BRW_CHANNEL_Y 1
96 #define BRW_CHANNEL_Z 2
97 #define BRW_CHANNEL_W 3
98
99 enum brw_compression {
100 BRW_COMPRESSION_NONE = 0,
101 BRW_COMPRESSION_2NDHALF = 1,
102 BRW_COMPRESSION_COMPRESSED = 2,
103 };
104
105 #define GEN6_COMPRESSION_1Q 0
106 #define GEN6_COMPRESSION_2Q 1
107 #define GEN6_COMPRESSION_3Q 2
108 #define GEN6_COMPRESSION_4Q 3
109 #define GEN6_COMPRESSION_1H 0
110 #define GEN6_COMPRESSION_2H 2
111
112 enum PACKED brw_conditional_mod {
113 BRW_CONDITIONAL_NONE = 0,
114 BRW_CONDITIONAL_Z = 1,
115 BRW_CONDITIONAL_NZ = 2,
116 BRW_CONDITIONAL_EQ = 1, /* Z */
117 BRW_CONDITIONAL_NEQ = 2, /* NZ */
118 BRW_CONDITIONAL_G = 3,
119 BRW_CONDITIONAL_GE = 4,
120 BRW_CONDITIONAL_L = 5,
121 BRW_CONDITIONAL_LE = 6,
122 BRW_CONDITIONAL_R = 7, /* Gen <= 5 */
123 BRW_CONDITIONAL_O = 8,
124 BRW_CONDITIONAL_U = 9,
125 };
126
127 #define BRW_DEBUG_NONE 0
128 #define BRW_DEBUG_BREAKPOINT 1
129
130 #define BRW_DEPENDENCY_NORMAL 0
131 #define BRW_DEPENDENCY_NOTCLEARED 1
132 #define BRW_DEPENDENCY_NOTCHECKED 2
133 #define BRW_DEPENDENCY_DISABLE 3
134
135 enum PACKED brw_execution_size {
136 BRW_EXECUTE_1 = 0,
137 BRW_EXECUTE_2 = 1,
138 BRW_EXECUTE_4 = 2,
139 BRW_EXECUTE_8 = 3,
140 BRW_EXECUTE_16 = 4,
141 BRW_EXECUTE_32 = 5,
142 };
143
144 enum PACKED brw_horizontal_stride {
145 BRW_HORIZONTAL_STRIDE_0 = 0,
146 BRW_HORIZONTAL_STRIDE_1 = 1,
147 BRW_HORIZONTAL_STRIDE_2 = 2,
148 BRW_HORIZONTAL_STRIDE_4 = 3,
149 };
150
151 enum PACKED gen10_align1_3src_src_horizontal_stride {
152 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
153 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
154 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
155 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
156 };
157
158 enum PACKED gen10_align1_3src_dst_horizontal_stride {
159 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
160 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
161 };
162
163 #define BRW_INSTRUCTION_NORMAL 0
164 #define BRW_INSTRUCTION_SATURATE 1
165
166 #define BRW_MASK_ENABLE 0
167 #define BRW_MASK_DISABLE 1
168
169 /** @{
170 *
171 * Gen6 has replaced "mask enable/disable" with WECtrl, which is
172 * effectively the same but much simpler to think about. Now, there
173 * are two contributors ANDed together to whether channels are
174 * executed: The predication on the instruction, and the channel write
175 * enable.
176 */
177 /**
178 * This is the default value. It means that a channel's write enable is set
179 * if the per-channel IP is pointing at this instruction.
180 */
181 #define BRW_WE_NORMAL 0
182 /**
183 * This is used like BRW_MASK_DISABLE, and causes all channels to have
184 * their write enable set. Note that predication still contributes to
185 * whether the channel actually gets written.
186 */
187 #define BRW_WE_ALL 1
188 /** @} */
189
190 enum opcode {
191 /* These are the actual hardware opcodes. */
192 BRW_OPCODE_ILLEGAL = 0,
193 BRW_OPCODE_MOV = 1,
194 BRW_OPCODE_SEL = 2,
195 BRW_OPCODE_MOVI = 3, /**< G45+ */
196 BRW_OPCODE_NOT = 4,
197 BRW_OPCODE_AND = 5,
198 BRW_OPCODE_OR = 6,
199 BRW_OPCODE_XOR = 7,
200 BRW_OPCODE_SHR = 8,
201 BRW_OPCODE_SHL = 9,
202 BRW_OPCODE_DIM = 10, /**< Gen7.5 only */ /* Reused */
203 // BRW_OPCODE_SMOV = 10, /**< Gen8+ */ /* Reused */
204 /* Reserved - 11 */
205 BRW_OPCODE_ASR = 12,
206 /* Reserved - 13-15 */
207 BRW_OPCODE_CMP = 16,
208 BRW_OPCODE_CMPN = 17,
209 BRW_OPCODE_CSEL = 18, /**< Gen8+ */
210 BRW_OPCODE_F32TO16 = 19, /**< Gen7 only */
211 BRW_OPCODE_F16TO32 = 20, /**< Gen7 only */
212 /* Reserved - 21-22 */
213 BRW_OPCODE_BFREV = 23, /**< Gen7+ */
214 BRW_OPCODE_BFE = 24, /**< Gen7+ */
215 BRW_OPCODE_BFI1 = 25, /**< Gen7+ */
216 BRW_OPCODE_BFI2 = 26, /**< Gen7+ */
217 /* Reserved - 27-31 */
218 BRW_OPCODE_JMPI = 32,
219 // BRW_OPCODE_BRD = 33, /**< Gen7+ */
220 BRW_OPCODE_IF = 34,
221 BRW_OPCODE_IFF = 35, /**< Pre-Gen6 */ /* Reused */
222 // BRW_OPCODE_BRC = 35, /**< Gen7+ */ /* Reused */
223 BRW_OPCODE_ELSE = 36,
224 BRW_OPCODE_ENDIF = 37,
225 BRW_OPCODE_DO = 38, /**< Pre-Gen6 */ /* Reused */
226 // BRW_OPCODE_CASE = 38, /**< Gen6 only */ /* Reused */
227 BRW_OPCODE_WHILE = 39,
228 BRW_OPCODE_BREAK = 40,
229 BRW_OPCODE_CONTINUE = 41,
230 BRW_OPCODE_HALT = 42,
231 // BRW_OPCODE_CALLA = 43, /**< Gen7.5+ */
232 // BRW_OPCODE_MSAVE = 44, /**< Pre-Gen6 */ /* Reused */
233 // BRW_OPCODE_CALL = 44, /**< Gen6+ */ /* Reused */
234 // BRW_OPCODE_MREST = 45, /**< Pre-Gen6 */ /* Reused */
235 // BRW_OPCODE_RET = 45, /**< Gen6+ */ /* Reused */
236 // BRW_OPCODE_PUSH = 46, /**< Pre-Gen6 */ /* Reused */
237 // BRW_OPCODE_FORK = 46, /**< Gen6 only */ /* Reused */
238 // BRW_OPCODE_GOTO = 46, /**< Gen8+ */ /* Reused */
239 // BRW_OPCODE_POP = 47, /**< Pre-Gen6 */
240 BRW_OPCODE_WAIT = 48,
241 BRW_OPCODE_SEND = 49,
242 BRW_OPCODE_SENDC = 50,
243 BRW_OPCODE_SENDS = 51, /**< Gen9+ */
244 BRW_OPCODE_SENDSC = 52, /**< Gen9+ */
245 /* Reserved 53-55 */
246 BRW_OPCODE_MATH = 56, /**< Gen6+ */
247 /* Reserved 57-63 */
248 BRW_OPCODE_ADD = 64,
249 BRW_OPCODE_MUL = 65,
250 BRW_OPCODE_AVG = 66,
251 BRW_OPCODE_FRC = 67,
252 BRW_OPCODE_RNDU = 68,
253 BRW_OPCODE_RNDD = 69,
254 BRW_OPCODE_RNDE = 70,
255 BRW_OPCODE_RNDZ = 71,
256 BRW_OPCODE_MAC = 72,
257 BRW_OPCODE_MACH = 73,
258 BRW_OPCODE_LZD = 74,
259 BRW_OPCODE_FBH = 75, /**< Gen7+ */
260 BRW_OPCODE_FBL = 76, /**< Gen7+ */
261 BRW_OPCODE_CBIT = 77, /**< Gen7+ */
262 BRW_OPCODE_ADDC = 78, /**< Gen7+ */
263 BRW_OPCODE_SUBB = 79, /**< Gen7+ */
264 BRW_OPCODE_SAD2 = 80,
265 BRW_OPCODE_SADA2 = 81,
266 /* Reserved 82-83 */
267 BRW_OPCODE_DP4 = 84,
268 BRW_OPCODE_DPH = 85,
269 BRW_OPCODE_DP3 = 86,
270 BRW_OPCODE_DP2 = 87,
271 /* Reserved 88 */
272 BRW_OPCODE_LINE = 89,
273 BRW_OPCODE_PLN = 90, /**< G45+ */
274 BRW_OPCODE_MAD = 91, /**< Gen6+ */
275 BRW_OPCODE_LRP = 92, /**< Gen6+ */
276 // BRW_OPCODE_MADM = 93, /**< Gen8+ */
277 /* Reserved 94-124 */
278 BRW_OPCODE_NENOP = 125, /**< G45 only */
279 BRW_OPCODE_NOP = 126,
280 /* Reserved 127 */
281
282 /* These are compiler backend opcodes that get translated into other
283 * instructions.
284 */
285 FS_OPCODE_FB_WRITE = 128,
286
287 /**
288 * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
289 * individual sources instead of as a single payload blob. The
290 * position/ordering of the arguments are defined by the enum
291 * fb_write_logical_srcs.
292 */
293 FS_OPCODE_FB_WRITE_LOGICAL,
294
295 FS_OPCODE_REP_FB_WRITE,
296
297 FS_OPCODE_FB_READ,
298 FS_OPCODE_FB_READ_LOGICAL,
299
300 SHADER_OPCODE_RCP,
301 SHADER_OPCODE_RSQ,
302 SHADER_OPCODE_SQRT,
303 SHADER_OPCODE_EXP2,
304 SHADER_OPCODE_LOG2,
305 SHADER_OPCODE_POW,
306 SHADER_OPCODE_INT_QUOTIENT,
307 SHADER_OPCODE_INT_REMAINDER,
308 SHADER_OPCODE_SIN,
309 SHADER_OPCODE_COS,
310
311 /**
312 * Texture sampling opcodes.
313 *
314 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
315 * opcode but instead of taking a single payload blob they expect their
316 * arguments separately as individual sources. The position/ordering of the
317 * arguments are defined by the enum tex_logical_srcs.
318 */
319 SHADER_OPCODE_TEX,
320 SHADER_OPCODE_TEX_LOGICAL,
321 SHADER_OPCODE_TXD,
322 SHADER_OPCODE_TXD_LOGICAL,
323 SHADER_OPCODE_TXF,
324 SHADER_OPCODE_TXF_LOGICAL,
325 SHADER_OPCODE_TXF_LZ,
326 SHADER_OPCODE_TXL,
327 SHADER_OPCODE_TXL_LOGICAL,
328 SHADER_OPCODE_TXL_LZ,
329 SHADER_OPCODE_TXS,
330 SHADER_OPCODE_TXS_LOGICAL,
331 FS_OPCODE_TXB,
332 FS_OPCODE_TXB_LOGICAL,
333 SHADER_OPCODE_TXF_CMS,
334 SHADER_OPCODE_TXF_CMS_LOGICAL,
335 SHADER_OPCODE_TXF_CMS_W,
336 SHADER_OPCODE_TXF_CMS_W_LOGICAL,
337 SHADER_OPCODE_TXF_UMS,
338 SHADER_OPCODE_TXF_UMS_LOGICAL,
339 SHADER_OPCODE_TXF_MCS,
340 SHADER_OPCODE_TXF_MCS_LOGICAL,
341 SHADER_OPCODE_LOD,
342 SHADER_OPCODE_LOD_LOGICAL,
343 SHADER_OPCODE_TG4,
344 SHADER_OPCODE_TG4_LOGICAL,
345 SHADER_OPCODE_TG4_OFFSET,
346 SHADER_OPCODE_TG4_OFFSET_LOGICAL,
347 SHADER_OPCODE_SAMPLEINFO,
348 SHADER_OPCODE_SAMPLEINFO_LOGICAL,
349
350 /**
351 * Combines multiple sources of size 1 into a larger virtual GRF.
352 * For example, parameters for a send-from-GRF message. Or, updating
353 * channels of a size 4 VGRF used to store vec4s such as texturing results.
354 *
355 * This will be lowered into MOVs from each source to consecutive offsets
356 * of the destination VGRF.
357 *
358 * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV,
359 * but still reserves the first channel of the destination VGRF. This can be
360 * used to reserve space for, say, a message header set up by the generators.
361 */
362 SHADER_OPCODE_LOAD_PAYLOAD,
363
364 /**
365 * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
366 * acts intra-channel, obtaining the final value for each channel by
367 * combining the sources values for the same channel, the first source
368 * occupying the lowest bits and the last source occupying the highest
369 * bits.
370 */
371 FS_OPCODE_PACK,
372
373 SHADER_OPCODE_SHADER_TIME_ADD,
374
375 /**
376 * Typed and untyped surface access opcodes.
377 *
378 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
379 * opcode but instead of taking a single payload blob they expect their
380 * arguments separately as individual sources:
381 *
382 * Source 0: [required] Surface coordinates.
383 * Source 1: [optional] Operation source.
384 * Source 2: [required] Surface index.
385 * Source 3: [required] Number of coordinate components (as UD immediate).
386 * Source 4: [required] Opcode-specific control immediate, same as source 2
387 * of the matching non-LOGICAL opcode.
388 */
389 SHADER_OPCODE_UNTYPED_ATOMIC,
390 SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
391 SHADER_OPCODE_UNTYPED_SURFACE_READ,
392 SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
393 SHADER_OPCODE_UNTYPED_SURFACE_WRITE,
394 SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
395
396 SHADER_OPCODE_TYPED_ATOMIC,
397 SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
398 SHADER_OPCODE_TYPED_SURFACE_READ,
399 SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
400 SHADER_OPCODE_TYPED_SURFACE_WRITE,
401 SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
402
403 SHADER_OPCODE_RND_MODE,
404
405 SHADER_OPCODE_MEMORY_FENCE,
406
407 SHADER_OPCODE_GEN4_SCRATCH_READ,
408 SHADER_OPCODE_GEN4_SCRATCH_WRITE,
409 SHADER_OPCODE_GEN7_SCRATCH_READ,
410
411 /**
412 * Gen8+ SIMD8 URB Read messages.
413 */
414 SHADER_OPCODE_URB_READ_SIMD8,
415 SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
416
417 SHADER_OPCODE_URB_WRITE_SIMD8,
418 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
419 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
420 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
421
422 /**
423 * Return the index of an arbitrary live channel (i.e. one of the channels
424 * enabled in the current execution mask) and assign it to the first
425 * component of the destination. Expected to be used as input for the
426 * BROADCAST pseudo-opcode.
427 */
428 SHADER_OPCODE_FIND_LIVE_CHANNEL,
429
430 /**
431 * Pick the channel from its first source register given by the index
432 * specified as second source. Useful for variable indexing of surfaces.
433 *
434 * Note that because the result of this instruction is by definition
435 * uniform and it can always be splatted to multiple channels using a
436 * scalar regioning mode, only the first channel of the destination region
437 * is guaranteed to be updated, which implies that BROADCAST instructions
438 * should usually be marked force_writemask_all.
439 */
440 SHADER_OPCODE_BROADCAST,
441
442 VEC4_OPCODE_MOV_BYTES,
443 VEC4_OPCODE_PACK_BYTES,
444 VEC4_OPCODE_UNPACK_UNIFORM,
445 VEC4_OPCODE_DOUBLE_TO_F32,
446 VEC4_OPCODE_DOUBLE_TO_D32,
447 VEC4_OPCODE_DOUBLE_TO_U32,
448 VEC4_OPCODE_TO_DOUBLE,
449 VEC4_OPCODE_PICK_LOW_32BIT,
450 VEC4_OPCODE_PICK_HIGH_32BIT,
451 VEC4_OPCODE_SET_LOW_32BIT,
452 VEC4_OPCODE_SET_HIGH_32BIT,
453
454 FS_OPCODE_DDX_COARSE,
455 FS_OPCODE_DDX_FINE,
456 /**
457 * Compute dFdy(), dFdyCoarse(), or dFdyFine().
458 */
459 FS_OPCODE_DDY_COARSE,
460 FS_OPCODE_DDY_FINE,
461 FS_OPCODE_CINTERP,
462 FS_OPCODE_LINTERP,
463 FS_OPCODE_PIXEL_X,
464 FS_OPCODE_PIXEL_Y,
465 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
466 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
467 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
468 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,
469 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
470 FS_OPCODE_GET_BUFFER_SIZE,
471 FS_OPCODE_MOV_DISPATCH_TO_FLAGS,
472 FS_OPCODE_DISCARD_JUMP,
473 FS_OPCODE_SET_SAMPLE_ID,
474 FS_OPCODE_PACK_HALF_2x16_SPLIT,
475 FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X,
476 FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y,
477 FS_OPCODE_PLACEHOLDER_HALT,
478 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
479 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
480 FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
481
482 VS_OPCODE_URB_WRITE,
483 VS_OPCODE_PULL_CONSTANT_LOAD,
484 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
485 VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
486
487 VS_OPCODE_GET_BUFFER_SIZE,
488
489 VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
490
491 /**
492 * Write geometry shader output data to the URB.
493 *
494 * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
495 * R0 to the first MRF. This allows the geometry shader to override the
496 * "Slot {0,1} Offset" fields in the message header.
497 */
498 GS_OPCODE_URB_WRITE,
499
500 /**
501 * Write geometry shader output data to the URB and request a new URB
502 * handle (gen6).
503 *
504 * This opcode doesn't do an implied move from R0 to the first MRF.
505 */
506 GS_OPCODE_URB_WRITE_ALLOCATE,
507
508 /**
509 * Terminate the geometry shader thread by doing an empty URB write.
510 *
511 * This opcode doesn't do an implied move from R0 to the first MRF. This
512 * allows the geometry shader to override the "GS Number of Output Vertices
513 * for Slot {0,1}" fields in the message header.
514 */
515 GS_OPCODE_THREAD_END,
516
517 /**
518 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
519 *
520 * - dst is the MRF containing the message header.
521 *
522 * - src0.x indicates which portion of the URB should be written to (e.g. a
523 * vertex number)
524 *
525 * - src1 is an immediate multiplier which will be applied to src0
526 * (e.g. the size of a single vertex in the URB).
527 *
528 * Note: the hardware will apply this offset *in addition to* the offset in
529 * vec4_instruction::offset.
530 */
531 GS_OPCODE_SET_WRITE_OFFSET,
532
533 /**
534 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
535 * URB_WRITE message header.
536 *
537 * - dst is the MRF containing the message header.
538 *
539 * - src0.x is the vertex count. The upper 16 bits will be ignored.
540 */
541 GS_OPCODE_SET_VERTEX_COUNT,
542
543 /**
544 * Set DWORD 2 of dst to the value in src.
545 */
546 GS_OPCODE_SET_DWORD_2,
547
548 /**
549 * Prepare the dst register for storage in the "Channel Mask" fields of a
550 * URB_WRITE message header.
551 *
552 * DWORD 4 of dst is shifted left by 4 bits, so that later,
553 * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
554 * final channel mask.
555 *
556 * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
557 * form the final channel mask, DWORDs 0 and 4 of the dst register must not
558 * have any extraneous bits set prior to execution of this opcode (that is,
559 * they should be in the range 0x0 to 0xf).
560 */
561 GS_OPCODE_PREPARE_CHANNEL_MASKS,
562
563 /**
564 * Set the "Channel Mask" fields of a URB_WRITE message header.
565 *
566 * - dst is the MRF containing the message header.
567 *
568 * - src.x is the channel mask, as prepared by
569 * GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to
570 * form the final channel mask.
571 */
572 GS_OPCODE_SET_CHANNEL_MASKS,
573
574 /**
575 * Get the "Instance ID" fields from the payload.
576 *
577 * - dst is the GRF for gl_InvocationID.
578 */
579 GS_OPCODE_GET_INSTANCE_ID,
580
581 /**
582 * Send a FF_SYNC message to allocate initial URB handles (gen6).
583 *
584 * - dst will be used as the writeback register for the FF_SYNC operation.
585 *
586 * - src0 is the number of primitives written.
587 *
588 * - src1 is the value to hold in M0.0: number of SO vertices to write
589 * and number of SO primitives needed. Its value will be overwritten
590 * with the SVBI values if transform feedback is enabled.
591 *
592 * Note: This opcode uses an implicit MRF register for the ff_sync message
593 * header, so the caller is expected to set inst->base_mrf and initialize
594 * that MRF register to r0. This opcode will also write to this MRF register
595 * to include the allocated URB handle so it can then be reused directly as
596 * the header in the URB write operation we are allocating the handle for.
597 */
598 GS_OPCODE_FF_SYNC,
599
600 /**
601 * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
602 * register.
603 *
604 * - dst is the GRF where PrimitiveID information will be moved.
605 */
606 GS_OPCODE_SET_PRIMITIVE_ID,
607
608 /**
609 * Write transform feedback data to the SVB by sending a SVB WRITE message.
610 * Used in gen6.
611 *
612 * - dst is the MRF register containing the message header.
613 *
614 * - src0 is the register where the vertex data is going to be copied from.
615 *
616 * - src1 is the destination register when write commit occurs.
617 */
618 GS_OPCODE_SVB_WRITE,
619
620 /**
621 * Set destination index in the SVB write message payload (M0.5). Used
622 * in gen6 for transform feedback.
623 *
624 * - dst is the header to save the destination indices for SVB WRITE.
625 * - src is the register that holds the destination indices value.
626 */
627 GS_OPCODE_SVB_SET_DST_INDEX,
628
629 /**
630 * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
631 * Used in gen6 for transform feedback.
632 *
633 * - dst will hold the register with the final Mx.0 value.
634 *
635 * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
636 *
637 * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
638 *
639 * - src2 is the value to hold in M0: number of SO vertices to write
640 * and number of SO primitives needed.
641 */
642 GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
643
644 /**
645 * Terminate the compute shader.
646 */
647 CS_OPCODE_CS_TERMINATE,
648
649 /**
650 * GLSL barrier()
651 */
652 SHADER_OPCODE_BARRIER,
653
654 /**
655 * Calculate the high 32-bits of a 32x32 multiply.
656 */
657 SHADER_OPCODE_MULH,
658
659 /**
660 * A MOV that uses VxH indirect addressing.
661 *
662 * Source 0: A register to start from (HW_REG).
663 * Source 1: An indirect offset (in bytes, UD GRF).
664 * Source 2: The length of the region that could be accessed (in bytes,
665 * UD immediate).
666 */
667 SHADER_OPCODE_MOV_INDIRECT,
668
669 VEC4_OPCODE_URB_READ,
670 TCS_OPCODE_GET_INSTANCE_ID,
671 TCS_OPCODE_URB_WRITE,
672 TCS_OPCODE_SET_INPUT_URB_OFFSETS,
673 TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
674 TCS_OPCODE_GET_PRIMITIVE_ID,
675 TCS_OPCODE_CREATE_BARRIER_HEADER,
676 TCS_OPCODE_SRC0_010_IS_ZERO,
677 TCS_OPCODE_RELEASE_INPUT,
678 TCS_OPCODE_THREAD_END,
679
680 TES_OPCODE_GET_PRIMITIVE_ID,
681 TES_OPCODE_CREATE_INPUT_READ_HEADER,
682 TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
683 };
684
685 enum brw_urb_write_flags {
686 BRW_URB_WRITE_NO_FLAGS = 0,
687
688 /**
689 * Causes a new URB entry to be allocated, and its address stored in the
690 * destination register (gen < 7).
691 */
692 BRW_URB_WRITE_ALLOCATE = 0x1,
693
694 /**
695 * Causes the current URB entry to be deallocated (gen < 7).
696 */
697 BRW_URB_WRITE_UNUSED = 0x2,
698
699 /**
700 * Causes the thread to terminate.
701 */
702 BRW_URB_WRITE_EOT = 0x4,
703
704 /**
705 * Indicates that the given URB entry is complete, and may be sent further
706 * down the 3D pipeline (gen < 7).
707 */
708 BRW_URB_WRITE_COMPLETE = 0x8,
709
710 /**
711 * Indicates that an additional offset (which may be different for the two
712 * vec4 slots) is stored in the message header (gen == 7).
713 */
714 BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
715
716 /**
717 * Indicates that the channel masks in the URB_WRITE message header should
718 * not be overridden to 0xff (gen == 7).
719 */
720 BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
721
722 /**
723 * Indicates that the data should be sent to the URB using the
724 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This
725 * causes offsets to be interpreted as multiples of an OWORD instead of an
726 * HWORD, and only allows one OWORD to be written.
727 */
728 BRW_URB_WRITE_OWORD = 0x40,
729
730 /**
731 * Convenient combination of flags: end the thread while simultaneously
732 * marking the given URB entry as complete.
733 */
734 BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
735
736 /**
737 * Convenient combination of flags: mark the given URB entry as complete
738 * and simultaneously allocate a new one.
739 */
740 BRW_URB_WRITE_ALLOCATE_COMPLETE =
741 BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
742 };
743
744 enum fb_write_logical_srcs {
745 FB_WRITE_LOGICAL_SRC_COLOR0, /* REQUIRED */
746 FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */
747 FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
748 FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */
749 FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GEN4-5: passthrough from thread */
750 FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
751 FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */
752 FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */
753 FB_WRITE_LOGICAL_NUM_SRCS
754 };
755
756 enum tex_logical_srcs {
757 /** Texture coordinates */
758 TEX_LOGICAL_SRC_COORDINATE,
759 /** Shadow comparator */
760 TEX_LOGICAL_SRC_SHADOW_C,
761 /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
762 TEX_LOGICAL_SRC_LOD,
763 /** dPdy if the operation takes explicit derivatives */
764 TEX_LOGICAL_SRC_LOD2,
765 /** Sample index */
766 TEX_LOGICAL_SRC_SAMPLE_INDEX,
767 /** MCS data */
768 TEX_LOGICAL_SRC_MCS,
769 /** REQUIRED: Texture surface index */
770 TEX_LOGICAL_SRC_SURFACE,
771 /** Texture sampler index */
772 TEX_LOGICAL_SRC_SAMPLER,
773 /** Texel offset for gathers */
774 TEX_LOGICAL_SRC_TG4_OFFSET,
775 /** REQUIRED: Number of coordinate components (as UD immediate) */
776 TEX_LOGICAL_SRC_COORD_COMPONENTS,
777 /** REQUIRED: Number of derivative components (as UD immediate) */
778 TEX_LOGICAL_SRC_GRAD_COMPONENTS,
779
780 TEX_LOGICAL_NUM_SRCS,
781 };
782
783 #ifdef __cplusplus
784 /**
785 * Allow brw_urb_write_flags enums to be ORed together.
786 */
787 inline brw_urb_write_flags
788 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
789 {
790 return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
791 static_cast<int>(y));
792 }
793 #endif
794
795 enum PACKED brw_predicate {
796 BRW_PREDICATE_NONE = 0,
797 BRW_PREDICATE_NORMAL = 1,
798 BRW_PREDICATE_ALIGN1_ANYV = 2,
799 BRW_PREDICATE_ALIGN1_ALLV = 3,
800 BRW_PREDICATE_ALIGN1_ANY2H = 4,
801 BRW_PREDICATE_ALIGN1_ALL2H = 5,
802 BRW_PREDICATE_ALIGN1_ANY4H = 6,
803 BRW_PREDICATE_ALIGN1_ALL4H = 7,
804 BRW_PREDICATE_ALIGN1_ANY8H = 8,
805 BRW_PREDICATE_ALIGN1_ALL8H = 9,
806 BRW_PREDICATE_ALIGN1_ANY16H = 10,
807 BRW_PREDICATE_ALIGN1_ALL16H = 11,
808 BRW_PREDICATE_ALIGN1_ANY32H = 12,
809 BRW_PREDICATE_ALIGN1_ALL32H = 13,
810 BRW_PREDICATE_ALIGN16_REPLICATE_X = 2,
811 BRW_PREDICATE_ALIGN16_REPLICATE_Y = 3,
812 BRW_PREDICATE_ALIGN16_REPLICATE_Z = 4,
813 BRW_PREDICATE_ALIGN16_REPLICATE_W = 5,
814 BRW_PREDICATE_ALIGN16_ANY4H = 6,
815 BRW_PREDICATE_ALIGN16_ALL4H = 7,
816 };
817
818 enum PACKED brw_reg_file {
819 BRW_ARCHITECTURE_REGISTER_FILE = 0,
820 BRW_GENERAL_REGISTER_FILE = 1,
821 BRW_MESSAGE_REGISTER_FILE = 2,
822 BRW_IMMEDIATE_VALUE = 3,
823
824 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
825 FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
826 MRF = BRW_MESSAGE_REGISTER_FILE,
827 IMM = BRW_IMMEDIATE_VALUE,
828
829 /* These are not hardware values */
830 VGRF,
831 ATTR,
832 UNIFORM, /* prog_data->params[reg] */
833 BAD_FILE,
834 };
835
836 enum PACKED gen10_align1_3src_reg_file {
837 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0,
838 BRW_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */
839 BRW_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */
840 };
841
842 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction
843 * word is "Execution Datatype" which controls whether the instruction operates
844 * on float or integer types. The register arguments have fields that offer
845 * more fine control their respective types.
846 */
847 enum PACKED gen10_align1_3src_exec_type {
848 BRW_ALIGN1_3SRC_EXEC_TYPE_INT = 0,
849 BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
850 };
851
852 #define BRW_ARF_NULL 0x00
853 #define BRW_ARF_ADDRESS 0x10
854 #define BRW_ARF_ACCUMULATOR 0x20
855 #define BRW_ARF_FLAG 0x30
856 #define BRW_ARF_MASK 0x40
857 #define BRW_ARF_MASK_STACK 0x50
858 #define BRW_ARF_MASK_STACK_DEPTH 0x60
859 #define BRW_ARF_STATE 0x70
860 #define BRW_ARF_CONTROL 0x80
861 #define BRW_ARF_NOTIFICATION_COUNT 0x90
862 #define BRW_ARF_IP 0xA0
863 #define BRW_ARF_TDR 0xB0
864 #define BRW_ARF_TIMESTAMP 0xC0
865
866 #define BRW_MRF_COMPR4 (1 << 7)
867
868 #define BRW_AMASK 0
869 #define BRW_IMASK 1
870 #define BRW_LMASK 2
871 #define BRW_CMASK 3
872
873
874
875 #define BRW_THREAD_NORMAL 0
876 #define BRW_THREAD_ATOMIC 1
877 #define BRW_THREAD_SWITCH 2
878
879 enum PACKED brw_vertical_stride {
880 BRW_VERTICAL_STRIDE_0 = 0,
881 BRW_VERTICAL_STRIDE_1 = 1,
882 BRW_VERTICAL_STRIDE_2 = 2,
883 BRW_VERTICAL_STRIDE_4 = 3,
884 BRW_VERTICAL_STRIDE_8 = 4,
885 BRW_VERTICAL_STRIDE_16 = 5,
886 BRW_VERTICAL_STRIDE_32 = 6,
887 BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
888 };
889
890 enum PACKED gen10_align1_3src_vertical_stride {
891 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
892 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
893 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2,
894 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,
895 };
896
897 enum PACKED brw_width {
898 BRW_WIDTH_1 = 0,
899 BRW_WIDTH_2 = 1,
900 BRW_WIDTH_4 = 2,
901 BRW_WIDTH_8 = 3,
902 BRW_WIDTH_16 = 4,
903 };
904
905 /**
906 * Message target: Shared Function ID for where to SEND a message.
907 *
908 * These are enumerated in the ISA reference under "send - Send Message".
909 * In particular, see the following tables:
910 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
911 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
912 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
913 */
914 enum brw_message_target {
915 BRW_SFID_NULL = 0,
916 BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */
917 BRW_SFID_SAMPLER = 2,
918 BRW_SFID_MESSAGE_GATEWAY = 3,
919 BRW_SFID_DATAPORT_READ = 4,
920 BRW_SFID_DATAPORT_WRITE = 5,
921 BRW_SFID_URB = 6,
922 BRW_SFID_THREAD_SPAWNER = 7,
923 BRW_SFID_VME = 8,
924
925 GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4,
926 GEN6_SFID_DATAPORT_RENDER_CACHE = 5,
927 GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
928
929 GEN7_SFID_DATAPORT_DATA_CACHE = 10,
930 GEN7_SFID_PIXEL_INTERPOLATOR = 11,
931 HSW_SFID_DATAPORT_DATA_CACHE_1 = 12,
932 HSW_SFID_CRE = 13,
933 };
934
935 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
936
937 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
938 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
939 #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
940
941 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
942 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
943 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
944 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
945 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
946 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
947 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
948 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
949 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
950 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
951 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
952 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
953 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1
954 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
955 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
956 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
957 #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
958 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
959
960 #define GEN5_SAMPLER_MESSAGE_SAMPLE 0
961 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
962 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2
963 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3
964 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4
965 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
966 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
967 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
968 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
969 #define GEN5_SAMPLER_MESSAGE_LOD 9
970 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
971 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
972 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
973 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
974 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
975 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
976 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ 24
977 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ 25
978 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ 26
979 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28
980 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
981 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
982 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
983
984 /* for GEN5 only */
985 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
986 #define BRW_SAMPLER_SIMD_MODE_SIMD8 1
987 #define BRW_SAMPLER_SIMD_MODE_SIMD16 2
988 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
989
990 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
991 * behavior by setting bit 22 of dword 2 in the message header. */
992 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D 0
993 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22)
994
995 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
996 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
997 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
998 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
999 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
1000 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n) \
1001 ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \
1002 (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \
1003 (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \
1004 (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \
1005 (abort(), ~0))
1006
1007 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
1008 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
1009
1010 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
1011 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
1012
1013 /* This one stays the same across generations. */
1014 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
1015 /* GEN4 */
1016 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
1017 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
1018 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
1019 /* G45, GEN5 */
1020 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1021 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1022 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3
1023 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1024 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1025 /* GEN6 */
1026 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1027 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1028 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1029 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
1030 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1031
1032 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
1033 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
1034 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
1035
1036 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
1037 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
1038 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
1039 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
1040 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
1041
1042 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
1043 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
1044 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2
1045 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
1046 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
1047 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
1048 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
1049
1050 /* GEN6 */
1051 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
1052 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
1053 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9
1054 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10
1055 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11
1056 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12
1057 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
1058 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
1059
1060 /* GEN7 */
1061 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ 4
1062 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ 5
1063 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP 6
1064 #define GEN7_DATAPORT_RC_MEMORY_FENCE 7
1065 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10
1066 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE 12
1067 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE 13
1068 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0
1069 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1
1070 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2
1071 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3
1072 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4
1073 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5
1074 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6
1075 #define GEN7_DATAPORT_DC_MEMORY_FENCE 7
1076 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8
1077 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10
1078 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11
1079 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
1080 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
1081
1082 #define GEN7_DATAPORT_SCRATCH_READ ((1 << 18) | \
1083 (0 << 17))
1084 #define GEN7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \
1085 (1 << 17))
1086 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12
1087
1088 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0
1089 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1
1090 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID 2
1091 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3
1092
1093 /* HSW */
1094 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0
1095 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1
1096 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2
1097 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3
1098 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4
1099 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7
1100 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8
1101 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10
1102 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11
1103 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12
1104
1105 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1
1106 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2
1107 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3
1108 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4
1109 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5
1110 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6
1111 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7
1112 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9
1113 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10
1114 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11
1115 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12
1116 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13
1117
1118 /* GEN9 */
1119 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE 12
1120 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ 13
1121
1122 /* Dataport special binding table indices: */
1123 #define BRW_BTI_STATELESS 255
1124 #define GEN7_BTI_SLM 254
1125 /* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the
1126 * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW,
1127 * CHV and at least some pre-production steppings of SKL due to
1128 * WaForceEnableNonCoherent, HDC memory access may have been overridden by the
1129 * kernel to be non-coherent (matching the behavior of the same BTI on
1130 * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253.
1131 */
1132 #define GEN8_BTI_STATELESS_IA_COHERENT 255
1133 #define GEN8_BTI_STATELESS_NON_COHERENT 253
1134
1135 /* dataport atomic operations. */
1136 #define BRW_AOP_AND 1
1137 #define BRW_AOP_OR 2
1138 #define BRW_AOP_XOR 3
1139 #define BRW_AOP_MOV 4
1140 #define BRW_AOP_INC 5
1141 #define BRW_AOP_DEC 6
1142 #define BRW_AOP_ADD 7
1143 #define BRW_AOP_SUB 8
1144 #define BRW_AOP_REVSUB 9
1145 #define BRW_AOP_IMAX 10
1146 #define BRW_AOP_IMIN 11
1147 #define BRW_AOP_UMAX 12
1148 #define BRW_AOP_UMIN 13
1149 #define BRW_AOP_CMPWR 14
1150 #define BRW_AOP_PREDEC 15
1151
1152 #define BRW_MATH_FUNCTION_INV 1
1153 #define BRW_MATH_FUNCTION_LOG 2
1154 #define BRW_MATH_FUNCTION_EXP 3
1155 #define BRW_MATH_FUNCTION_SQRT 4
1156 #define BRW_MATH_FUNCTION_RSQ 5
1157 #define BRW_MATH_FUNCTION_SIN 6
1158 #define BRW_MATH_FUNCTION_COS 7
1159 #define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */
1160 #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
1161 #define BRW_MATH_FUNCTION_POW 10
1162 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
1163 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
1164 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
1165 #define GEN8_MATH_FUNCTION_INVM 14
1166 #define GEN8_MATH_FUNCTION_RSQRTM 15
1167
1168 #define BRW_MATH_INTEGER_UNSIGNED 0
1169 #define BRW_MATH_INTEGER_SIGNED 1
1170
1171 #define BRW_MATH_PRECISION_FULL 0
1172 #define BRW_MATH_PRECISION_PARTIAL 1
1173
1174 #define BRW_MATH_SATURATE_NONE 0
1175 #define BRW_MATH_SATURATE_SATURATE 1
1176
1177 #define BRW_MATH_DATA_VECTOR 0
1178 #define BRW_MATH_DATA_SCALAR 1
1179
1180 #define BRW_URB_OPCODE_WRITE_HWORD 0
1181 #define BRW_URB_OPCODE_WRITE_OWORD 1
1182 #define BRW_URB_OPCODE_READ_HWORD 2
1183 #define BRW_URB_OPCODE_READ_OWORD 3
1184 #define GEN7_URB_OPCODE_ATOMIC_MOV 4
1185 #define GEN7_URB_OPCODE_ATOMIC_INC 5
1186 #define GEN8_URB_OPCODE_ATOMIC_ADD 6
1187 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1188 #define GEN8_URB_OPCODE_SIMD8_READ 8
1189
1190 #define BRW_URB_SWIZZLE_NONE 0
1191 #define BRW_URB_SWIZZLE_INTERLEAVE 1
1192 #define BRW_URB_SWIZZLE_TRANSPOSE 2
1193
1194 #define BRW_SCRATCH_SPACE_SIZE_1K 0
1195 #define BRW_SCRATCH_SPACE_SIZE_2K 1
1196 #define BRW_SCRATCH_SPACE_SIZE_4K 2
1197 #define BRW_SCRATCH_SPACE_SIZE_8K 3
1198 #define BRW_SCRATCH_SPACE_SIZE_16K 4
1199 #define BRW_SCRATCH_SPACE_SIZE_32K 5
1200 #define BRW_SCRATCH_SPACE_SIZE_64K 6
1201 #define BRW_SCRATCH_SPACE_SIZE_128K 7
1202 #define BRW_SCRATCH_SPACE_SIZE_256K 8
1203 #define BRW_SCRATCH_SPACE_SIZE_512K 9
1204 #define BRW_SCRATCH_SPACE_SIZE_1M 10
1205 #define BRW_SCRATCH_SPACE_SIZE_2M 11
1206
1207 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0
1208 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1
1209 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2
1210 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3
1211 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4
1212 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1213 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6
1214
1215
1216 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1217 * is 2^9, or 512. It's counted in multiples of 64 bytes.
1218 *
1219 * Identical for VS, DS, and HS.
1220 */
1221 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
1222 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64)
1223 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64)
1224 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64)
1225
1226 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1227 * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1228 */
1229 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128)
1230
1231 /* GS Thread Payload
1232 */
1233
1234 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1235 * counted in multiples of 16 bytes.
1236 */
1237 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16)
1238
1239
1240 /* R0 */
1241 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
1242
1243 /* CR0.0[5:4] Floating-Point Rounding Modes
1244 * Skylake PRM, Volume 7 Part 1, "Control Register", page 756
1245 */
1246
1247 #define BRW_CR0_RND_MODE_MASK 0x30
1248 #define BRW_CR0_RND_MODE_SHIFT 4
1249
1250 enum PACKED brw_rnd_mode {
1251 BRW_RND_MODE_RTNE = 0, /* Round to Nearest or Even */
1252 BRW_RND_MODE_RU = 1, /* Round Up, toward +inf */
1253 BRW_RND_MODE_RD = 2, /* Round Down, toward -inf */
1254 BRW_RND_MODE_RTZ = 3, /* Round Toward Zero */
1255 };
1256
1257 #endif /* BRW_EU_DEFINES_H */