2 * Copyright © 2015-2019 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_validate.c
26 * This file implements a pass that validates shader assembly.
28 * The restrictions implemented herein are intended to verify that instructions
29 * in shader assembly do not violate restrictions documented in the graphics
30 * programming reference manuals.
32 * The restrictions are difficult for humans to quickly verify due to their
33 * complexity and abundance.
35 * It is critical that this code is thoroughly unit tested because false
36 * results will lead developers astray, which is worse than having no validator
37 * at all. Functional changes to this file without corresponding unit tests (in
38 * test_eu_validate.cpp) will be rejected.
43 /* We're going to do lots of string concatenation, so this should help. */
50 cat(struct string
*dest
, const struct string src
)
52 dest
->str
= realloc(dest
->str
, dest
->len
+ src
.len
+ 1);
53 memcpy(dest
->str
+ dest
->len
, src
.str
, src
.len
);
54 dest
->str
[dest
->len
+ src
.len
] = '\0';
55 dest
->len
= dest
->len
+ src
.len
;
57 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
60 contains(const struct string haystack
, const struct string needle
)
62 return haystack
.str
&& memmem(haystack
.str
, haystack
.len
,
63 needle
.str
, needle
.len
) != NULL
;
65 #define CONTAINS(haystack, needle) \
66 contains(haystack, (struct string){needle, strlen(needle)})
68 #define error(str) "\tERROR: " str "\n"
69 #define ERROR_INDENT "\t "
71 #define ERROR(msg) ERROR_IF(true, msg)
72 #define ERROR_IF(cond, msg) \
74 if ((cond) && !CONTAINS(error_msg, error(msg))) { \
75 CAT(error_msg, error(msg)); \
79 #define CHECK(func, args...) \
81 struct string __msg = func(devinfo, inst, ##args); \
83 cat(&error_msg, __msg); \
88 #define STRIDE(stride) (stride != 0 ? 1 << ((stride) - 1) : 0)
89 #define WIDTH(width) (1 << (width))
92 inst_is_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
94 switch (brw_inst_opcode(devinfo
, inst
)) {
96 case BRW_OPCODE_SENDC
:
97 case BRW_OPCODE_SENDS
:
98 case BRW_OPCODE_SENDSC
:
106 signed_type(unsigned type
)
109 case BRW_REGISTER_TYPE_UD
: return BRW_REGISTER_TYPE_D
;
110 case BRW_REGISTER_TYPE_UW
: return BRW_REGISTER_TYPE_W
;
111 case BRW_REGISTER_TYPE_UB
: return BRW_REGISTER_TYPE_B
;
112 case BRW_REGISTER_TYPE_UQ
: return BRW_REGISTER_TYPE_Q
;
113 default: return type
;
118 inst_is_raw_move(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
120 unsigned dst_type
= signed_type(brw_inst_dst_type(devinfo
, inst
));
121 unsigned src_type
= signed_type(brw_inst_src0_type(devinfo
, inst
));
123 if (brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
) {
124 /* FIXME: not strictly true */
125 if (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_VF
||
126 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UV
||
127 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_V
) {
130 } else if (brw_inst_src0_negate(devinfo
, inst
) ||
131 brw_inst_src0_abs(devinfo
, inst
)) {
135 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MOV
&&
136 brw_inst_saturate(devinfo
, inst
) == 0 &&
137 dst_type
== src_type
;
141 dst_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
143 return brw_inst_dst_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
144 brw_inst_dst_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
148 src0_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
150 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
151 brw_inst_src0_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
155 src1_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
157 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
158 brw_inst_src1_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
162 src0_is_grf(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
164 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
;
168 src0_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
170 return brw_inst_src0_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
171 brw_inst_src0_width(devinfo
, inst
) == BRW_WIDTH_1
&&
172 brw_inst_src0_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
176 src1_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
178 return brw_inst_src1_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
179 brw_inst_src1_width(devinfo
, inst
) == BRW_WIDTH_1
&&
180 brw_inst_src1_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
184 num_sources_from_inst(const struct gen_device_info
*devinfo
,
185 const brw_inst
*inst
)
187 const struct opcode_desc
*desc
=
188 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
189 unsigned math_function
;
191 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
192 math_function
= brw_inst_math_function(devinfo
, inst
);
193 } else if (devinfo
->gen
< 6 &&
194 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
195 if (brw_inst_sfid(devinfo
, inst
) == BRW_SFID_MATH
) {
196 /* src1 must be a descriptor (including the information to determine
197 * that the SEND is doing an extended math operation), but src0 can
198 * actually be null since it serves as the source of the implicit GRF
201 * If we stop using that functionality, we'll have to revisit this.
205 /* Send instructions are allowed to have null sources since they use
206 * the base_mrf field to specify which message register source.
211 assert(desc
->nsrc
< 4);
215 switch (math_function
) {
216 case BRW_MATH_FUNCTION_INV
:
217 case BRW_MATH_FUNCTION_LOG
:
218 case BRW_MATH_FUNCTION_EXP
:
219 case BRW_MATH_FUNCTION_SQRT
:
220 case BRW_MATH_FUNCTION_RSQ
:
221 case BRW_MATH_FUNCTION_SIN
:
222 case BRW_MATH_FUNCTION_COS
:
223 case BRW_MATH_FUNCTION_SINCOS
:
224 case GEN8_MATH_FUNCTION_INVM
:
225 case GEN8_MATH_FUNCTION_RSQRTM
:
227 case BRW_MATH_FUNCTION_FDIV
:
228 case BRW_MATH_FUNCTION_POW
:
229 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
230 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
231 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
234 unreachable("not reached");
239 sources_not_null(const struct gen_device_info
*devinfo
,
240 const brw_inst
*inst
)
242 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
243 struct string error_msg
= { .str
= NULL
, .len
= 0 };
245 /* Nothing to test. 3-src instructions can only have GRF sources, and
246 * there's no bit to control the file.
248 if (num_sources
== 3)
249 return (struct string
){};
251 if (num_sources
>= 1)
252 ERROR_IF(src0_is_null(devinfo
, inst
), "src0 is null");
254 if (num_sources
== 2)
255 ERROR_IF(src1_is_null(devinfo
, inst
), "src1 is null");
261 send_restrictions(const struct gen_device_info
*devinfo
,
262 const brw_inst
*inst
)
264 struct string error_msg
= { .str
= NULL
, .len
= 0 };
266 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
267 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
,
268 "send must use direct addressing");
270 if (devinfo
->gen
>= 7) {
271 ERROR_IF(!src0_is_grf(devinfo
, inst
), "send from non-GRF");
272 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
273 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
274 "send with EOT must use g112-g127");
277 if (devinfo
->gen
>= 8) {
278 ERROR_IF(!dst_is_null(devinfo
, inst
) &&
279 (brw_inst_dst_da_reg_nr(devinfo
, inst
) +
280 brw_inst_rlen(devinfo
, inst
) > 127) &&
281 (brw_inst_src0_da_reg_nr(devinfo
, inst
) +
282 brw_inst_mlen(devinfo
, inst
) >
283 brw_inst_dst_da_reg_nr(devinfo
, inst
)),
284 "r127 must not be used for return address when there is "
285 "a src and dest overlap");
293 is_unsupported_inst(const struct gen_device_info
*devinfo
,
294 const brw_inst
*inst
)
296 return brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
)) == NULL
;
299 static enum brw_reg_type
300 execution_type_for_type(enum brw_reg_type type
)
303 case BRW_REGISTER_TYPE_NF
:
304 case BRW_REGISTER_TYPE_DF
:
305 case BRW_REGISTER_TYPE_F
:
306 case BRW_REGISTER_TYPE_HF
:
309 case BRW_REGISTER_TYPE_VF
:
310 return BRW_REGISTER_TYPE_F
;
312 case BRW_REGISTER_TYPE_Q
:
313 case BRW_REGISTER_TYPE_UQ
:
314 return BRW_REGISTER_TYPE_Q
;
316 case BRW_REGISTER_TYPE_D
:
317 case BRW_REGISTER_TYPE_UD
:
318 return BRW_REGISTER_TYPE_D
;
320 case BRW_REGISTER_TYPE_W
:
321 case BRW_REGISTER_TYPE_UW
:
322 case BRW_REGISTER_TYPE_B
:
323 case BRW_REGISTER_TYPE_UB
:
324 case BRW_REGISTER_TYPE_V
:
325 case BRW_REGISTER_TYPE_UV
:
326 return BRW_REGISTER_TYPE_W
;
328 unreachable("not reached");
332 * Returns the execution type of an instruction \p inst
334 static enum brw_reg_type
335 execution_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
337 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
338 enum brw_reg_type src0_exec_type
, src1_exec_type
;
340 /* Execution data type is independent of destination data type, except in
341 * mixed F/HF instructions on CHV and SKL+.
343 enum brw_reg_type dst_exec_type
= brw_inst_dst_type(devinfo
, inst
);
345 src0_exec_type
= execution_type_for_type(brw_inst_src0_type(devinfo
, inst
));
346 if (num_sources
== 1) {
347 if ((devinfo
->gen
>= 9 || devinfo
->is_cherryview
) &&
348 src0_exec_type
== BRW_REGISTER_TYPE_HF
) {
349 return dst_exec_type
;
351 return src0_exec_type
;
354 src1_exec_type
= execution_type_for_type(brw_inst_src1_type(devinfo
, inst
));
355 if (src0_exec_type
== src1_exec_type
)
356 return src0_exec_type
;
358 /* Mixed operand types where one is float is float on Gen < 6
359 * (and not allowed on later platforms)
361 if (devinfo
->gen
< 6 &&
362 (src0_exec_type
== BRW_REGISTER_TYPE_F
||
363 src1_exec_type
== BRW_REGISTER_TYPE_F
))
364 return BRW_REGISTER_TYPE_F
;
366 if (src0_exec_type
== BRW_REGISTER_TYPE_Q
||
367 src1_exec_type
== BRW_REGISTER_TYPE_Q
)
368 return BRW_REGISTER_TYPE_Q
;
370 if (src0_exec_type
== BRW_REGISTER_TYPE_D
||
371 src1_exec_type
== BRW_REGISTER_TYPE_D
)
372 return BRW_REGISTER_TYPE_D
;
374 if (src0_exec_type
== BRW_REGISTER_TYPE_W
||
375 src1_exec_type
== BRW_REGISTER_TYPE_W
)
376 return BRW_REGISTER_TYPE_W
;
378 if (src0_exec_type
== BRW_REGISTER_TYPE_DF
||
379 src1_exec_type
== BRW_REGISTER_TYPE_DF
)
380 return BRW_REGISTER_TYPE_DF
;
382 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
383 if (dst_exec_type
== BRW_REGISTER_TYPE_F
||
384 src0_exec_type
== BRW_REGISTER_TYPE_F
||
385 src1_exec_type
== BRW_REGISTER_TYPE_F
) {
386 return BRW_REGISTER_TYPE_F
;
388 return BRW_REGISTER_TYPE_HF
;
392 assert(src0_exec_type
== BRW_REGISTER_TYPE_F
);
393 return BRW_REGISTER_TYPE_F
;
397 * Returns whether a region is packed
399 * A region is packed if its elements are adjacent in memory, with no
400 * intervening space, no overlap, and no replicated values.
403 is_packed(unsigned vstride
, unsigned width
, unsigned hstride
)
405 if (vstride
== width
) {
417 * Checks restrictions listed in "General Restrictions Based on Operand Types"
418 * in the "Register Region Restrictions" section.
421 general_restrictions_based_on_operand_types(const struct gen_device_info
*devinfo
,
422 const brw_inst
*inst
)
424 const struct opcode_desc
*desc
=
425 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
426 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
427 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
428 struct string error_msg
= { .str
= NULL
, .len
= 0 };
430 if (num_sources
== 3)
431 return (struct string
){};
433 if (inst_is_send(devinfo
, inst
))
434 return (struct string
){};
437 return (struct string
){};
440 return (struct string
){};
444 * Where n is the largest element size in bytes for any source or
445 * destination operand type, ExecSize * n must be <= 64.
447 * But we do not attempt to enforce it, because it is implied by other
450 * - that the destination stride must match the execution data type
451 * - sources may not span more than two adjacent GRF registers
452 * - destination may not span more than two adjacent GRF registers
454 * In fact, checking it would weaken testing of the other rules.
457 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
458 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
459 bool dst_type_is_byte
=
460 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_B
||
461 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UB
;
463 if (dst_type_is_byte
) {
464 if (is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
)) {
465 if (!inst_is_raw_move(devinfo
, inst
)) {
466 ERROR("Only raw MOV supports a packed-byte destination");
469 return (struct string
){};
474 unsigned exec_type
= execution_type(devinfo
, inst
);
475 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
476 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
478 /* On IVB/BYT, region parameters and execution size for DF are in terms of
479 * 32-bit elements, so they are doubled. For evaluating the validity of an
480 * instruction, we halve them.
482 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
483 exec_type_size
== 8 && dst_type_size
== 4)
486 if (exec_type_size
> dst_type_size
) {
487 if (!(dst_type_is_byte
&& inst_is_raw_move(devinfo
, inst
))) {
488 ERROR_IF(dst_stride
* dst_type_size
!= exec_type_size
,
489 "Destination stride must be equal to the ratio of the sizes "
490 "of the execution data type to the destination type");
493 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
495 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
496 brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
) {
497 /* The i965 PRM says:
499 * Implementation Restriction: The relaxed alignment rule for byte
500 * destination (#10.5) is not supported.
502 if ((devinfo
->gen
> 4 || devinfo
->is_g4x
) && dst_type_is_byte
) {
503 ERROR_IF(subreg
% exec_type_size
!= 0 &&
504 subreg
% exec_type_size
!= 1,
505 "Destination subreg must be aligned to the size of the "
506 "execution data type (or to the next lowest byte for byte "
509 ERROR_IF(subreg
% exec_type_size
!= 0,
510 "Destination subreg must be aligned to the size of the "
511 "execution data type");
520 * Checks restrictions listed in "General Restrictions on Regioning Parameters"
521 * in the "Register Region Restrictions" section.
524 general_restrictions_on_region_parameters(const struct gen_device_info
*devinfo
,
525 const brw_inst
*inst
)
527 const struct opcode_desc
*desc
=
528 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
529 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
530 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
531 struct string error_msg
= { .str
= NULL
, .len
= 0 };
533 if (num_sources
== 3)
534 return (struct string
){};
536 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
) {
537 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
))
538 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) != BRW_HORIZONTAL_STRIDE_1
,
539 "Destination Horizontal Stride must be 1");
541 if (num_sources
>= 1) {
542 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
543 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
544 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
545 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
546 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
547 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
549 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
550 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
551 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
552 "In Align16 mode, only VertStride of 0 or 4 is allowed");
556 if (num_sources
== 2) {
557 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
558 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
559 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
560 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
561 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
562 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
564 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
565 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
566 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
567 "In Align16 mode, only VertStride of 0 or 4 is allowed");
574 for (unsigned i
= 0; i
< num_sources
; i
++) {
575 unsigned vstride
, width
, hstride
, element_size
, subreg
;
576 enum brw_reg_type type
;
579 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
580 BRW_IMMEDIATE_VALUE) \
583 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
584 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
585 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
586 type = brw_inst_src ## n ## _type(devinfo, inst); \
587 element_size = brw_reg_type_to_size(type); \
588 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
597 /* On IVB/BYT, region parameters and execution size for DF are in terms of
598 * 32-bit elements, so they are doubled. For evaluating the validity of an
599 * instruction, we halve them.
601 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
605 /* ExecSize must be greater than or equal to Width. */
606 ERROR_IF(exec_size
< width
, "ExecSize must be greater than or equal "
609 /* If ExecSize = Width and HorzStride ≠ 0,
610 * VertStride must be set to Width * HorzStride.
612 if (exec_size
== width
&& hstride
!= 0) {
613 ERROR_IF(vstride
!= width
* hstride
,
614 "If ExecSize = Width and HorzStride ≠ 0, "
615 "VertStride must be set to Width * HorzStride");
618 /* If Width = 1, HorzStride must be 0 regardless of the values of
619 * ExecSize and VertStride.
622 ERROR_IF(hstride
!= 0,
623 "If Width = 1, HorzStride must be 0 regardless "
624 "of the values of ExecSize and VertStride");
627 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
628 if (exec_size
== 1 && width
== 1) {
629 ERROR_IF(vstride
!= 0 || hstride
!= 0,
630 "If ExecSize = Width = 1, both VertStride "
631 "and HorzStride must be 0");
634 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the
637 if (vstride
== 0 && hstride
== 0) {
639 "If VertStride = HorzStride = 0, Width must be "
640 "1 regardless of the value of ExecSize");
643 /* VertStride must be used to cross GRF register boundaries. This rule
644 * implies that elements within a 'Width' cannot cross GRF boundaries.
646 const uint64_t mask
= (1ULL << element_size
) - 1;
647 unsigned rowbase
= subreg
;
649 for (int y
= 0; y
< exec_size
/ width
; y
++) {
650 uint64_t access_mask
= 0;
651 unsigned offset
= rowbase
;
653 for (int x
= 0; x
< width
; x
++) {
654 access_mask
|= mask
<< offset
;
655 offset
+= hstride
* element_size
;
658 rowbase
+= vstride
* element_size
;
660 if ((uint32_t)access_mask
!= 0 && (access_mask
>> 32) != 0) {
661 ERROR("VertStride must be used to cross GRF register boundaries");
667 /* Dst.HorzStride must not be 0. */
668 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
)) {
669 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
,
670 "Destination Horizontal Stride must not be 0");
677 * Creates an \p access_mask for an \p exec_size, \p element_size, and a region
679 * An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
680 * a bitmask of bytes accessed by the region.
682 * For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
683 * instruction would be
685 * access_mask[0] = 0x00000000000000F0
686 * access_mask[1] = 0x000000000000F000
687 * access_mask[2] = 0x0000000000F00000
688 * access_mask[3] = 0x00000000F0000000
689 * access_mask[4-31] = 0
691 * because the first execution channel accesses bytes 7-4 and the second
692 * execution channel accesses bytes 15-12, etc.
695 align1_access_mask(uint64_t access_mask
[static 32],
696 unsigned exec_size
, unsigned element_size
, unsigned subreg
,
697 unsigned vstride
, unsigned width
, unsigned hstride
)
699 const uint64_t mask
= (1ULL << element_size
) - 1;
700 unsigned rowbase
= subreg
;
701 unsigned element
= 0;
703 for (int y
= 0; y
< exec_size
/ width
; y
++) {
704 unsigned offset
= rowbase
;
706 for (int x
= 0; x
< width
; x
++) {
707 access_mask
[element
++] = mask
<< offset
;
708 offset
+= hstride
* element_size
;
711 rowbase
+= vstride
* element_size
;
714 assert(element
== 0 || element
== exec_size
);
718 * Returns the number of registers accessed according to the \p access_mask
721 registers_read(const uint64_t access_mask
[static 32])
725 for (unsigned i
= 0; i
< 32; i
++) {
726 if (access_mask
[i
] > 0xFFFFFFFF) {
728 } else if (access_mask
[i
]) {
737 * Checks restrictions listed in "Region Alignment Rules" in the "Register
738 * Region Restrictions" section.
741 region_alignment_rules(const struct gen_device_info
*devinfo
,
742 const brw_inst
*inst
)
744 const struct opcode_desc
*desc
=
745 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
746 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
747 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
748 uint64_t dst_access_mask
[32], src0_access_mask
[32], src1_access_mask
[32];
749 struct string error_msg
= { .str
= NULL
, .len
= 0 };
751 if (num_sources
== 3)
752 return (struct string
){};
754 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
)
755 return (struct string
){};
757 if (inst_is_send(devinfo
, inst
))
758 return (struct string
){};
760 memset(dst_access_mask
, 0, sizeof(dst_access_mask
));
761 memset(src0_access_mask
, 0, sizeof(src0_access_mask
));
762 memset(src1_access_mask
, 0, sizeof(src1_access_mask
));
764 for (unsigned i
= 0; i
< num_sources
; i
++) {
765 unsigned vstride
, width
, hstride
, element_size
, subreg
;
766 enum brw_reg_type type
;
768 /* In Direct Addressing mode, a source cannot span more than 2 adjacent
773 if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
774 BRW_ADDRESS_DIRECT) \
777 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
778 BRW_IMMEDIATE_VALUE) \
781 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
782 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
783 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
784 type = brw_inst_src ## n ## _type(devinfo, inst); \
785 element_size = brw_reg_type_to_size(type); \
786 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
787 align1_access_mask(src ## n ## _access_mask, \
788 exec_size, element_size, subreg, \
789 vstride, width, hstride)
798 unsigned num_vstride
= exec_size
/ width
;
799 unsigned num_hstride
= width
;
800 unsigned vstride_elements
= (num_vstride
- 1) * vstride
;
801 unsigned hstride_elements
= (num_hstride
- 1) * hstride
;
802 unsigned offset
= (vstride_elements
+ hstride_elements
) * element_size
+
804 ERROR_IF(offset
>= 64,
805 "A source cannot span more than 2 adjacent GRF registers");
808 if (desc
->ndst
== 0 || dst_is_null(devinfo
, inst
))
811 unsigned stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
812 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
813 unsigned element_size
= brw_reg_type_to_size(dst_type
);
814 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
815 unsigned offset
= ((exec_size
- 1) * stride
* element_size
) + subreg
;
816 ERROR_IF(offset
>= 64,
817 "A destination cannot span more than 2 adjacent GRF registers");
822 /* On IVB/BYT, region parameters and execution size for DF are in terms of
823 * 32-bit elements, so they are doubled. For evaluating the validity of an
824 * instruction, we halve them.
826 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
830 align1_access_mask(dst_access_mask
, exec_size
, element_size
, subreg
,
831 exec_size
== 1 ? 0 : exec_size
* stride
,
832 exec_size
== 1 ? 1 : exec_size
,
833 exec_size
== 1 ? 0 : stride
);
835 unsigned dst_regs
= registers_read(dst_access_mask
);
836 unsigned src0_regs
= registers_read(src0_access_mask
);
837 unsigned src1_regs
= registers_read(src1_access_mask
);
839 /* The SNB, IVB, HSW, BDW, and CHV PRMs say:
841 * When an instruction has a source region spanning two registers and a
842 * destination region contained in one register, the number of elements
843 * must be the same between two sources and one of the following must be
846 * 1. The destination region is entirely contained in the lower OWord
848 * 2. The destination region is entirely contained in the upper OWord
850 * 3. The destination elements are evenly split between the two OWords
853 if (devinfo
->gen
<= 8) {
854 if (dst_regs
== 1 && (src0_regs
== 2 || src1_regs
== 2)) {
855 unsigned upper_oword_writes
= 0, lower_oword_writes
= 0;
857 for (unsigned i
= 0; i
< exec_size
; i
++) {
858 if (dst_access_mask
[i
] > 0x0000FFFF) {
859 upper_oword_writes
++;
861 assert(dst_access_mask
[i
] != 0);
862 lower_oword_writes
++;
866 ERROR_IF(lower_oword_writes
!= 0 &&
867 upper_oword_writes
!= 0 &&
868 upper_oword_writes
!= lower_oword_writes
,
869 "Writes must be to only one OWord or "
870 "evenly split between OWords");
874 /* The IVB and HSW PRMs say:
876 * When an instruction has a source region that spans two registers and
877 * the destination spans two registers, the destination elements must be
878 * evenly split between the two registers [...]
880 * The SNB PRM contains similar wording (but written in a much more
885 * When destination spans two registers, the source may be one or two
886 * registers. The destination elements must be evenly split between the
891 * When destination of MATH instruction spans two registers, the
892 * destination elements must be evenly split between the two registers.
894 * It is not known whether this restriction applies to KBL other Gens after
897 if (devinfo
->gen
<= 8 ||
898 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
900 /* Nothing explicitly states that on Gen < 8 elements must be evenly
901 * split between two destination registers in the two exceptional
902 * source-region-spans-one-register cases, but since Broadwell requires
903 * evenly split writes regardless of source region, we assume that it was
904 * an oversight and require it.
907 unsigned upper_reg_writes
= 0, lower_reg_writes
= 0;
909 for (unsigned i
= 0; i
< exec_size
; i
++) {
910 if (dst_access_mask
[i
] > 0xFFFFFFFF) {
913 assert(dst_access_mask
[i
] != 0);
918 ERROR_IF(upper_reg_writes
!= lower_reg_writes
,
919 "Writes must be evenly split between the two "
920 "destination registers");
924 /* The IVB and HSW PRMs say:
926 * When an instruction has a source region that spans two registers and
927 * the destination spans two registers, the destination elements must be
928 * evenly split between the two registers and each destination register
929 * must be entirely derived from one source register.
931 * Note: In such cases, the regioning parameters must ensure that the
932 * offset from the two source registers is the same.
934 * The SNB PRM contains similar wording (but written in a much more
937 * There are effectively three rules stated here:
939 * For an instruction with a source and a destination spanning two
942 * (1) destination elements must be evenly split between the two
944 * (2) all destination elements in a register must be derived
945 * from one source register
946 * (3) the offset (i.e. the starting location in each of the two
947 * registers spanned by a region) must be the same in the two
948 * registers spanned by a region
950 * It is impossible to violate rule (1) without violating (2) or (3), so we
951 * do not attempt to validate it.
953 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
954 for (unsigned i
= 0; i
< num_sources
; i
++) {
956 if (src ## n ## _regs <= 1) \
959 for (unsigned i = 0; i < exec_size; i++) { \
960 if ((dst_access_mask[i] > 0xFFFFFFFF) != \
961 (src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
962 ERROR("Each destination register must be entirely derived " \
963 "from one source register"); \
968 unsigned offset_0 = \
969 brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
970 unsigned offset_1 = offset_0; \
972 for (unsigned i = 0; i < exec_size; i++) { \
973 if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
974 offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
979 ERROR_IF(num_sources == 2 && offset_0 != offset_1, \
980 "The offset from the two source registers " \
992 /* The IVB and HSW PRMs say:
994 * When destination spans two registers, the source MUST span two
995 * registers. The exception to the above rule:
996 * 1. When source is scalar, the source registers are not
998 * 2. When source is packed integer Word and destination is packed
999 * integer DWord, the source register is not incremented by the
1000 * source sub register is incremented.
1002 * The SNB PRM does not contain this rule, but the internal documentation
1003 * indicates that it applies to SNB as well. We assume that the rule applies
1004 * to Gen <= 5 although their PRMs do not state it.
1006 * While the documentation explicitly says in exception (2) that the
1007 * destination must be an integer DWord, the hardware allows at least a
1008 * float destination type as well. We emit such instructions from
1010 * fs_visitor::emit_interpolation_setup_gen6
1011 * fs_visitor::emit_fragcoord_interpolation
1013 * and have for years with no ill effects.
1015 * Additionally the simulator source code indicates that the real condition
1016 * is that the size of the destination type is 4 bytes.
1018 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
1019 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1020 bool dst_is_packed_dword
=
1021 is_packed(exec_size
* stride
, exec_size
, stride
) &&
1022 brw_reg_type_to_size(dst_type
) == 4;
1024 for (unsigned i
= 0; i
< num_sources
; i
++) {
1026 unsigned vstride, width, hstride; \
1027 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1028 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1029 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1030 bool src ## n ## _is_packed_word = \
1031 is_packed(vstride, width, hstride) && \
1032 (brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_W || \
1033 brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_UW); \
1035 ERROR_IF(src ## n ## _regs == 1 && \
1036 !src ## n ## _has_scalar_region(devinfo, inst) && \
1037 !(dst_is_packed_dword && src ## n ## _is_packed_word), \
1038 "When the destination spans two registers, the source must " \
1039 "span two registers\n" ERROR_INDENT "(exceptions for scalar " \
1040 "source and packed-word to packed-dword expansion)")
1054 static struct string
1055 vector_immediate_restrictions(const struct gen_device_info
*devinfo
,
1056 const brw_inst
*inst
)
1058 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1059 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1061 if (num_sources
== 3 || num_sources
== 0)
1062 return (struct string
){};
1064 unsigned file
= num_sources
== 1 ?
1065 brw_inst_src0_reg_file(devinfo
, inst
) :
1066 brw_inst_src1_reg_file(devinfo
, inst
);
1067 if (file
!= BRW_IMMEDIATE_VALUE
)
1068 return (struct string
){};
1070 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1071 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1072 unsigned dst_subreg
= brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
?
1073 brw_inst_dst_da1_subreg_nr(devinfo
, inst
) : 0;
1074 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1075 enum brw_reg_type type
= num_sources
== 1 ?
1076 brw_inst_src0_type(devinfo
, inst
) :
1077 brw_inst_src1_type(devinfo
, inst
);
1081 * When an immediate vector is used in an instruction, the destination
1082 * must be 128-bit aligned with destination horizontal stride equivalent
1083 * to a word for an immediate integer vector (v) and equivalent to a
1084 * DWord for an immediate float vector (vf).
1086 * The text has not been updated for the addition of the immediate unsigned
1087 * integer vector type (uv) on SNB, but presumably the same restriction
1091 case BRW_REGISTER_TYPE_V
:
1092 case BRW_REGISTER_TYPE_UV
:
1093 case BRW_REGISTER_TYPE_VF
:
1094 ERROR_IF(dst_subreg
% (128 / 8) != 0,
1095 "Destination must be 128-bit aligned in order to use immediate "
1098 if (type
== BRW_REGISTER_TYPE_VF
) {
1099 ERROR_IF(dst_type_size
* dst_stride
!= 4,
1100 "Destination must have stride equivalent to dword in order "
1101 "to use the VF type");
1103 ERROR_IF(dst_type_size
* dst_stride
!= 2,
1104 "Destination must have stride equivalent to word in order "
1105 "to use the V or UV type");
1115 static struct string
1116 special_requirements_for_handling_double_precision_data_types(
1117 const struct gen_device_info
*devinfo
,
1118 const brw_inst
*inst
)
1120 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1121 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1123 if (num_sources
== 3 || num_sources
== 0)
1124 return (struct string
){};
1126 enum brw_reg_type exec_type
= execution_type(devinfo
, inst
);
1127 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
1129 enum brw_reg_file dst_file
= brw_inst_dst_reg_file(devinfo
, inst
);
1130 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1131 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1132 unsigned dst_hstride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1133 unsigned dst_reg
= brw_inst_dst_da_reg_nr(devinfo
, inst
);
1134 unsigned dst_subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
1135 unsigned dst_address_mode
= brw_inst_dst_address_mode(devinfo
, inst
);
1137 bool is_integer_dword_multiply
=
1138 devinfo
->gen
>= 8 &&
1139 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MUL
&&
1140 (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1141 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
) &&
1142 (brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1143 brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
);
1145 if (dst_type_size
!= 8 && exec_type_size
!= 8 && !is_integer_dword_multiply
)
1146 return (struct string
){};
1148 for (unsigned i
= 0; i
< num_sources
; i
++) {
1149 unsigned vstride
, width
, hstride
, type_size
, reg
, subreg
, address_mode
;
1150 bool is_scalar_region
;
1151 enum brw_reg_file file
;
1152 enum brw_reg_type type
;
1155 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
1156 BRW_IMMEDIATE_VALUE) \
1159 is_scalar_region = src ## n ## _has_scalar_region(devinfo, inst); \
1160 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1161 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1162 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1163 file = brw_inst_src ## n ## _reg_file(devinfo, inst); \
1164 type = brw_inst_src ## n ## _type(devinfo, inst); \
1165 type_size = brw_reg_type_to_size(type); \
1166 reg = brw_inst_src ## n ## _da_reg_nr(devinfo, inst); \
1167 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1168 address_mode = brw_inst_src ## n ## _address_mode(devinfo, inst)
1177 /* The PRMs say that for CHV, BXT:
1179 * When source or destination datatype is 64b or operation is integer
1180 * DWord multiply, regioning in Align1 must follow these rules:
1182 * 1. Source and Destination horizontal stride must be aligned to the
1184 * 2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
1185 * 3. Source and Destination offset must be the same, except the case
1188 * We assume that the restriction applies to GLK as well.
1190 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
1191 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
1192 unsigned src_stride
= hstride
* type_size
;
1193 unsigned dst_stride
= dst_hstride
* dst_type_size
;
1195 ERROR_IF(!is_scalar_region
&&
1196 (src_stride
% 8 != 0 ||
1197 dst_stride
% 8 != 0 ||
1198 src_stride
!= dst_stride
),
1199 "Source and destination horizontal stride must equal and a "
1200 "multiple of a qword when the execution type is 64-bit");
1202 ERROR_IF(vstride
!= width
* hstride
,
1203 "Vstride must be Width * Hstride when the execution type is "
1206 ERROR_IF(!is_scalar_region
&& dst_subreg
!= subreg
,
1207 "Source and destination offset must be the same when the "
1208 "execution type is 64-bit");
1211 /* The PRMs say that for CHV, BXT:
1213 * When source or destination datatype is 64b or operation is integer
1214 * DWord multiply, indirect addressing must not be used.
1216 * We assume that the restriction applies to GLK as well.
1218 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1219 ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== address_mode
||
1220 BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== dst_address_mode
,
1221 "Indirect addressing is not allowed when the execution type "
1225 /* The PRMs say that for CHV, BXT:
1227 * ARF registers must never be used with 64b datatype or when
1228 * operation is integer DWord multiply.
1230 * We assume that the restriction applies to GLK as well.
1232 * We assume that the restriction does not apply to the null register.
1234 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1235 ERROR_IF(brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MAC
||
1236 brw_inst_acc_wr_control(devinfo
, inst
) ||
1237 (BRW_ARCHITECTURE_REGISTER_FILE
== file
&&
1238 reg
!= BRW_ARF_NULL
) ||
1239 (BRW_ARCHITECTURE_REGISTER_FILE
== dst_file
&&
1240 dst_reg
!= BRW_ARF_NULL
),
1241 "Architecture registers cannot be used when the execution "
1246 /* The PRMs say that for BDW, SKL:
1248 * If Align16 is required for an operation with QW destination and non-QW
1249 * source datatypes, the execution size cannot exceed 2.
1251 * We assume that the restriction applies to all Gen8+ parts.
1253 if (devinfo
->gen
>= 8) {
1254 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
1255 enum brw_reg_type src1_type
=
1256 num_sources
> 1 ? brw_inst_src1_type(devinfo
, inst
) : src0_type
;
1257 unsigned src0_type_size
= brw_reg_type_to_size(src0_type
);
1258 unsigned src1_type_size
= brw_reg_type_to_size(src1_type
);
1260 ERROR_IF(brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
&&
1261 dst_type_size
== 8 &&
1262 (src0_type_size
!= 8 || src1_type_size
!= 8) &&
1263 brw_inst_exec_size(devinfo
, inst
) > BRW_EXECUTE_2
,
1264 "In Align16 exec size cannot exceed 2 with a QWord destination "
1265 "and a non-QWord source");
1268 /* The PRMs say that for CHV, BXT:
1270 * When source or destination datatype is 64b or operation is integer
1271 * DWord multiply, DepCtrl must not be used.
1273 * We assume that the restriction applies to GLK as well.
1275 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1276 ERROR_IF(brw_inst_no_dd_check(devinfo
, inst
) ||
1277 brw_inst_no_dd_clear(devinfo
, inst
),
1278 "DepCtrl is not allowed when the execution type is 64-bit");
1285 brw_validate_instructions(const struct gen_device_info
*devinfo
,
1286 const void *assembly
, int start_offset
, int end_offset
,
1287 struct disasm_info
*disasm
)
1291 for (int src_offset
= start_offset
; src_offset
< end_offset
;) {
1292 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1293 const brw_inst
*inst
= assembly
+ src_offset
;
1294 bool is_compact
= brw_inst_cmpt_control(devinfo
, inst
);
1295 brw_inst uncompacted
;
1298 brw_compact_inst
*compacted
= (void *)inst
;
1299 brw_uncompact_instruction(devinfo
, &uncompacted
, compacted
);
1300 inst
= &uncompacted
;
1303 if (is_unsupported_inst(devinfo
, inst
)) {
1304 ERROR("Instruction not supported on this Gen");
1306 CHECK(sources_not_null
);
1307 CHECK(send_restrictions
);
1308 CHECK(general_restrictions_based_on_operand_types
);
1309 CHECK(general_restrictions_on_region_parameters
);
1310 CHECK(region_alignment_rules
);
1311 CHECK(vector_immediate_restrictions
);
1312 CHECK(special_requirements_for_handling_double_precision_data_types
);
1315 if (error_msg
.str
&& disasm
) {
1316 disasm_insert_error(disasm
, src_offset
, error_msg
.str
);
1318 valid
= valid
&& error_msg
.len
== 0;
1319 free(error_msg
.str
);
1322 src_offset
+= sizeof(brw_compact_inst
);
1324 src_offset
+= sizeof(brw_inst
);