2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_validate.c
26 * This file implements a pass that validates shader assembly.
31 /* We're going to do lots of string concatenation, so this should help. */
38 cat(struct string
*dest
, const struct string src
)
40 dest
->str
= realloc(dest
->str
, dest
->len
+ src
.len
+ 1);
41 memcpy(dest
->str
+ dest
->len
, src
.str
, src
.len
);
42 dest
->str
[dest
->len
+ src
.len
] = '\0';
43 dest
->len
= dest
->len
+ src
.len
;
45 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
47 #define error(str) "\tERROR: " str "\n"
48 #define ERROR_INDENT "\t "
50 #define ERROR(msg) ERROR_IF(true, msg)
51 #define ERROR_IF(cond, msg) \
54 CAT(error_msg, error(msg)); \
58 #define CHECK(func, args...) \
60 struct string __msg = func(devinfo, inst, ##args); \
62 cat(&error_msg, __msg); \
68 inst_is_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
70 switch (brw_inst_opcode(devinfo
, inst
)) {
72 case BRW_OPCODE_SENDC
:
73 case BRW_OPCODE_SENDS
:
74 case BRW_OPCODE_SENDSC
:
82 signed_type(unsigned type
)
85 case BRW_REGISTER_TYPE_UD
: return BRW_REGISTER_TYPE_D
;
86 case BRW_REGISTER_TYPE_UW
: return BRW_REGISTER_TYPE_W
;
87 case BRW_REGISTER_TYPE_UB
: return BRW_REGISTER_TYPE_B
;
88 case BRW_REGISTER_TYPE_UQ
: return BRW_REGISTER_TYPE_Q
;
94 inst_is_raw_move(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
96 unsigned dst_type
= signed_type(brw_inst_dst_type(devinfo
, inst
));
97 unsigned src_type
= signed_type(brw_inst_src0_type(devinfo
, inst
));
99 if (brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
) {
100 /* FIXME: not strictly true */
101 if (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_VF
||
102 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UV
||
103 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_V
) {
106 } else if (brw_inst_src0_negate(devinfo
, inst
) ||
107 brw_inst_src0_abs(devinfo
, inst
)) {
111 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MOV
&&
112 brw_inst_saturate(devinfo
, inst
) == 0 &&
113 dst_type
== src_type
;
117 dst_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
119 return brw_inst_dst_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
120 brw_inst_dst_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
124 src0_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
126 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
127 brw_inst_src0_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
131 src1_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
133 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
134 brw_inst_src1_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
138 src0_is_grf(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
140 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
;
144 src0_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
146 return brw_inst_src0_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
147 brw_inst_src0_width(devinfo
, inst
) == BRW_WIDTH_1
&&
148 brw_inst_src0_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
152 src1_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
154 return brw_inst_src1_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
155 brw_inst_src1_width(devinfo
, inst
) == BRW_WIDTH_1
&&
156 brw_inst_src1_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
160 num_sources_from_inst(const struct gen_device_info
*devinfo
,
161 const brw_inst
*inst
)
163 const struct opcode_desc
*desc
=
164 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
165 unsigned math_function
;
167 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
168 math_function
= brw_inst_math_function(devinfo
, inst
);
169 } else if (devinfo
->gen
< 6 &&
170 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
171 if (brw_inst_sfid(devinfo
, inst
) == BRW_SFID_MATH
) {
172 /* src1 must be a descriptor (including the information to determine
173 * that the SEND is doing an extended math operation), but src0 can
174 * actually be null since it serves as the source of the implicit GRF
177 * If we stop using that functionality, we'll have to revisit this.
181 /* Send instructions are allowed to have null sources since they use
182 * the base_mrf field to specify which message register source.
187 assert(desc
->nsrc
< 4);
191 switch (math_function
) {
192 case BRW_MATH_FUNCTION_INV
:
193 case BRW_MATH_FUNCTION_LOG
:
194 case BRW_MATH_FUNCTION_EXP
:
195 case BRW_MATH_FUNCTION_SQRT
:
196 case BRW_MATH_FUNCTION_RSQ
:
197 case BRW_MATH_FUNCTION_SIN
:
198 case BRW_MATH_FUNCTION_COS
:
199 case BRW_MATH_FUNCTION_SINCOS
:
200 case GEN8_MATH_FUNCTION_INVM
:
201 case GEN8_MATH_FUNCTION_RSQRTM
:
203 case BRW_MATH_FUNCTION_FDIV
:
204 case BRW_MATH_FUNCTION_POW
:
205 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
206 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
207 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
210 unreachable("not reached");
215 sources_not_null(const struct gen_device_info
*devinfo
,
216 const brw_inst
*inst
)
218 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
219 struct string error_msg
= { .str
= NULL
, .len
= 0 };
221 /* Nothing to test. 3-src instructions can only have GRF sources, and
222 * there's no bit to control the file.
224 if (num_sources
== 3)
225 return (struct string
){};
227 if (num_sources
>= 1)
228 ERROR_IF(src0_is_null(devinfo
, inst
), "src0 is null");
230 if (num_sources
== 2)
231 ERROR_IF(src1_is_null(devinfo
, inst
), "src1 is null");
237 send_restrictions(const struct gen_device_info
*devinfo
,
238 const brw_inst
*inst
)
240 struct string error_msg
= { .str
= NULL
, .len
= 0 };
242 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
243 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
,
244 "send must use direct addressing");
246 if (devinfo
->gen
>= 7) {
247 ERROR_IF(!src0_is_grf(devinfo
, inst
), "send from non-GRF");
248 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
249 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
250 "send with EOT must use g112-g127");
258 is_unsupported_inst(const struct gen_device_info
*devinfo
,
259 const brw_inst
*inst
)
261 return brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
)) == NULL
;
264 static enum brw_reg_type
265 execution_type_for_type(enum brw_reg_type type
)
268 case BRW_REGISTER_TYPE_DF
:
269 case BRW_REGISTER_TYPE_F
:
270 case BRW_REGISTER_TYPE_HF
:
273 case BRW_REGISTER_TYPE_VF
:
274 return BRW_REGISTER_TYPE_F
;
276 case BRW_REGISTER_TYPE_Q
:
277 case BRW_REGISTER_TYPE_UQ
:
278 return BRW_REGISTER_TYPE_Q
;
280 case BRW_REGISTER_TYPE_D
:
281 case BRW_REGISTER_TYPE_UD
:
282 return BRW_REGISTER_TYPE_D
;
284 case BRW_REGISTER_TYPE_W
:
285 case BRW_REGISTER_TYPE_UW
:
286 case BRW_REGISTER_TYPE_B
:
287 case BRW_REGISTER_TYPE_UB
:
288 case BRW_REGISTER_TYPE_V
:
289 case BRW_REGISTER_TYPE_UV
:
290 return BRW_REGISTER_TYPE_W
;
292 unreachable("not reached");
296 * Returns the execution type of an instruction \p inst
298 static enum brw_reg_type
299 execution_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
301 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
302 enum brw_reg_type src0_exec_type
, src1_exec_type
;
303 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
304 enum brw_reg_type src1_type
= brw_inst_src1_type(devinfo
, inst
);
306 /* Execution data type is independent of destination data type, except in
307 * mixed F/HF instructions on CHV and SKL+.
309 enum brw_reg_type dst_exec_type
= brw_inst_dst_type(devinfo
, inst
);
311 src0_exec_type
= execution_type_for_type(src0_type
);
312 if (num_sources
== 1) {
313 if ((devinfo
->gen
>= 9 || devinfo
->is_cherryview
) &&
314 src0_exec_type
== BRW_REGISTER_TYPE_HF
) {
315 return dst_exec_type
;
317 return src0_exec_type
;
320 src1_exec_type
= execution_type_for_type(src1_type
);
321 if (src0_exec_type
== src1_exec_type
)
322 return src0_exec_type
;
324 /* Mixed operand types where one is float is float on Gen < 6
325 * (and not allowed on later platforms)
327 if (devinfo
->gen
< 6 &&
328 (src0_exec_type
== BRW_REGISTER_TYPE_F
||
329 src1_exec_type
== BRW_REGISTER_TYPE_F
))
330 return BRW_REGISTER_TYPE_F
;
332 if (src0_exec_type
== BRW_REGISTER_TYPE_Q
||
333 src1_exec_type
== BRW_REGISTER_TYPE_Q
)
334 return BRW_REGISTER_TYPE_Q
;
336 if (src0_exec_type
== BRW_REGISTER_TYPE_D
||
337 src1_exec_type
== BRW_REGISTER_TYPE_D
)
338 return BRW_REGISTER_TYPE_D
;
340 if (src0_exec_type
== BRW_REGISTER_TYPE_W
||
341 src1_exec_type
== BRW_REGISTER_TYPE_W
)
342 return BRW_REGISTER_TYPE_W
;
344 if (src0_exec_type
== BRW_REGISTER_TYPE_DF
||
345 src1_exec_type
== BRW_REGISTER_TYPE_DF
)
346 return BRW_REGISTER_TYPE_DF
;
348 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
349 if (dst_exec_type
== BRW_REGISTER_TYPE_F
||
350 src0_exec_type
== BRW_REGISTER_TYPE_F
||
351 src1_exec_type
== BRW_REGISTER_TYPE_F
) {
352 return BRW_REGISTER_TYPE_F
;
354 return BRW_REGISTER_TYPE_HF
;
358 assert(src0_exec_type
== BRW_REGISTER_TYPE_F
);
359 return BRW_REGISTER_TYPE_F
;
363 * Returns whether a region is packed
365 * A region is packed if its elements are adjacent in memory, with no
366 * intervening space, no overlap, and no replicated values.
369 is_packed(unsigned vstride
, unsigned width
, unsigned hstride
)
371 if (vstride
== width
) {
383 * Checks restrictions listed in "General Restrictions Based on Operand Types"
384 * in the "Register Region Restrictions" section.
387 general_restrictions_based_on_operand_types(const struct gen_device_info
*devinfo
,
388 const brw_inst
*inst
)
390 const struct opcode_desc
*desc
=
391 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
392 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
393 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
394 struct string error_msg
= { .str
= NULL
, .len
= 0 };
396 if (num_sources
== 3)
397 return (struct string
){};
399 if (inst_is_send(devinfo
, inst
))
400 return (struct string
){};
403 return (struct string
){};
406 return (struct string
){};
410 * Where n is the largest element size in bytes for any source or
411 * destination operand type, ExecSize * n must be <= 64.
413 * But we do not attempt to enforce it, because it is implied by other
416 * - that the destination stride must match the execution data type
417 * - sources may not span more than two adjacent GRF registers
418 * - destination may not span more than two adjacent GRF registers
420 * In fact, checking it would weaken testing of the other rules.
423 unsigned dst_stride
= 1 << (brw_inst_dst_hstride(devinfo
, inst
) - 1);
424 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
425 bool dst_type_is_byte
=
426 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_B
||
427 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UB
;
429 if (dst_type_is_byte
) {
430 if (is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
)) {
431 if (!inst_is_raw_move(devinfo
, inst
)) {
432 ERROR("Only raw MOV supports a packed-byte destination");
435 return (struct string
){};
440 unsigned exec_type
= execution_type(devinfo
, inst
);
441 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
442 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
444 /* On IVB/BYT, region parameters and execution size for DF are in terms of
445 * 32-bit elements, so they are doubled. For evaluating the validity of an
446 * instruction, we halve them.
448 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
449 exec_type_size
== 8 && dst_type_size
== 4)
452 if (exec_type_size
> dst_type_size
) {
453 ERROR_IF(dst_stride
* dst_type_size
!= exec_type_size
,
454 "Destination stride must be equal to the ratio of the sizes of "
455 "the execution data type to the destination type");
457 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
459 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
460 brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
) {
461 /* The i965 PRM says:
463 * Implementation Restriction: The relaxed alignment rule for byte
464 * destination (#10.5) is not supported.
466 if ((devinfo
->gen
> 4 || devinfo
->is_g4x
) && dst_type_is_byte
) {
467 ERROR_IF(subreg
% exec_type_size
!= 0 &&
468 subreg
% exec_type_size
!= 1,
469 "Destination subreg must be aligned to the size of the "
470 "execution data type (or to the next lowest byte for byte "
473 ERROR_IF(subreg
% exec_type_size
!= 0,
474 "Destination subreg must be aligned to the size of the "
475 "execution data type");
484 * Checks restrictions listed in "General Restrictions on Regioning Parameters"
485 * in the "Register Region Restrictions" section.
488 general_restrictions_on_region_parameters(const struct gen_device_info
*devinfo
,
489 const brw_inst
*inst
)
491 const struct opcode_desc
*desc
=
492 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
493 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
494 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
495 struct string error_msg
= { .str
= NULL
, .len
= 0 };
497 if (num_sources
== 3)
498 return (struct string
){};
500 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
) {
501 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
))
502 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) != BRW_HORIZONTAL_STRIDE_1
,
503 "Destination Horizontal Stride must be 1");
505 if (num_sources
>= 1) {
506 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
507 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
508 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
509 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
510 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
511 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
513 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
514 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
515 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
516 "In Align16 mode, only VertStride of 0 or 4 is allowed");
520 if (num_sources
== 2) {
521 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
522 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
523 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
524 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
525 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
526 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
528 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
529 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
530 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
531 "In Align16 mode, only VertStride of 0 or 4 is allowed");
538 for (unsigned i
= 0; i
< num_sources
; i
++) {
539 unsigned vstride
, width
, hstride
, element_size
, subreg
;
540 enum brw_reg_type type
;
543 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
544 BRW_IMMEDIATE_VALUE) \
547 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
548 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
549 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
550 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
551 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
552 type = brw_inst_src ## n ## _type(devinfo, inst); \
553 element_size = brw_reg_type_to_size(type); \
554 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
563 /* On IVB/BYT, region parameters and execution size for DF are in terms of
564 * 32-bit elements, so they are doubled. For evaluating the validity of an
565 * instruction, we halve them.
567 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
571 /* ExecSize must be greater than or equal to Width. */
572 ERROR_IF(exec_size
< width
, "ExecSize must be greater than or equal "
575 /* If ExecSize = Width and HorzStride ≠ 0,
576 * VertStride must be set to Width * HorzStride.
578 if (exec_size
== width
&& hstride
!= 0) {
579 ERROR_IF(vstride
!= width
* hstride
,
580 "If ExecSize = Width and HorzStride ≠ 0, "
581 "VertStride must be set to Width * HorzStride");
584 /* If Width = 1, HorzStride must be 0 regardless of the values of
585 * ExecSize and VertStride.
588 ERROR_IF(hstride
!= 0,
589 "If Width = 1, HorzStride must be 0 regardless "
590 "of the values of ExecSize and VertStride");
593 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
594 if (exec_size
== 1 && width
== 1) {
595 ERROR_IF(vstride
!= 0 || hstride
!= 0,
596 "If ExecSize = Width = 1, both VertStride "
597 "and HorzStride must be 0");
600 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the
603 if (vstride
== 0 && hstride
== 0) {
605 "If VertStride = HorzStride = 0, Width must be "
606 "1 regardless of the value of ExecSize");
609 /* VertStride must be used to cross GRF register boundaries. This rule
610 * implies that elements within a 'Width' cannot cross GRF boundaries.
612 const uint64_t mask
= (1ULL << element_size
) - 1;
613 unsigned rowbase
= subreg
;
615 for (int y
= 0; y
< exec_size
/ width
; y
++) {
616 uint64_t access_mask
= 0;
617 unsigned offset
= rowbase
;
619 for (int x
= 0; x
< width
; x
++) {
620 access_mask
|= mask
<< offset
;
621 offset
+= hstride
* element_size
;
624 rowbase
+= vstride
* element_size
;
626 if ((uint32_t)access_mask
!= 0 && (access_mask
>> 32) != 0) {
627 ERROR("VertStride must be used to cross GRF register boundaries");
633 /* Dst.HorzStride must not be 0. */
634 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
)) {
635 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
,
636 "Destination Horizontal Stride must not be 0");
643 * Creates an \p access_mask for an \p exec_size, \p element_size, and a region
645 * An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
646 * a bitmask of bytes accessed by the region.
648 * For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
649 * instruction would be
651 * access_mask[0] = 0x00000000000000F0
652 * access_mask[1] = 0x000000000000F000
653 * access_mask[2] = 0x0000000000F00000
654 * access_mask[3] = 0x00000000F0000000
655 * access_mask[4-31] = 0
657 * because the first execution channel accesses bytes 7-4 and the second
658 * execution channel accesses bytes 15-12, etc.
661 align1_access_mask(uint64_t access_mask
[static 32],
662 unsigned exec_size
, unsigned element_size
, unsigned subreg
,
663 unsigned vstride
, unsigned width
, unsigned hstride
)
665 const uint64_t mask
= (1ULL << element_size
) - 1;
666 unsigned rowbase
= subreg
;
667 unsigned element
= 0;
669 for (int y
= 0; y
< exec_size
/ width
; y
++) {
670 unsigned offset
= rowbase
;
672 for (int x
= 0; x
< width
; x
++) {
673 access_mask
[element
++] = mask
<< offset
;
674 offset
+= hstride
* element_size
;
677 rowbase
+= vstride
* element_size
;
680 assert(element
== 0 || element
== exec_size
);
684 * Returns the number of registers accessed according to the \p access_mask
687 registers_read(const uint64_t access_mask
[static 32])
691 for (unsigned i
= 0; i
< 32; i
++) {
692 if (access_mask
[i
] > 0xFFFFFFFF) {
694 } else if (access_mask
[i
]) {
703 * Checks restrictions listed in "Region Alignment Rules" in the "Register
704 * Region Restrictions" section.
707 region_alignment_rules(const struct gen_device_info
*devinfo
,
708 const brw_inst
*inst
)
710 const struct opcode_desc
*desc
=
711 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
712 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
713 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
714 uint64_t dst_access_mask
[32], src0_access_mask
[32], src1_access_mask
[32];
715 struct string error_msg
= { .str
= NULL
, .len
= 0 };
717 if (num_sources
== 3)
718 return (struct string
){};
720 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
)
721 return (struct string
){};
723 if (inst_is_send(devinfo
, inst
))
724 return (struct string
){};
726 memset(dst_access_mask
, 0, sizeof(dst_access_mask
));
727 memset(src0_access_mask
, 0, sizeof(src0_access_mask
));
728 memset(src1_access_mask
, 0, sizeof(src1_access_mask
));
730 for (unsigned i
= 0; i
< num_sources
; i
++) {
731 unsigned vstride
, width
, hstride
, element_size
, subreg
;
732 enum brw_reg_type type
;
734 /* In Direct Addressing mode, a source cannot span more than 2 adjacent
739 if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
740 BRW_ADDRESS_DIRECT) \
743 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
744 BRW_IMMEDIATE_VALUE) \
747 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
748 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
749 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
750 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
751 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
752 type = brw_inst_src ## n ## _type(devinfo, inst); \
753 element_size = brw_reg_type_to_size(type); \
754 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
755 align1_access_mask(src ## n ## _access_mask, \
756 exec_size, element_size, subreg, \
757 vstride, width, hstride)
766 unsigned num_vstride
= exec_size
/ width
;
767 unsigned num_hstride
= width
;
768 unsigned vstride_elements
= (num_vstride
- 1) * vstride
;
769 unsigned hstride_elements
= (num_hstride
- 1) * hstride
;
770 unsigned offset
= (vstride_elements
+ hstride_elements
) * element_size
+
772 ERROR_IF(offset
>= 64,
773 "A source cannot span more than 2 adjacent GRF registers");
776 if (desc
->ndst
== 0 || dst_is_null(devinfo
, inst
))
779 unsigned stride
= 1 << (brw_inst_dst_hstride(devinfo
, inst
) - 1);
780 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
781 unsigned element_size
= brw_reg_type_to_size(dst_type
);
782 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
783 unsigned offset
= ((exec_size
- 1) * stride
* element_size
) + subreg
;
784 ERROR_IF(offset
>= 64,
785 "A destination cannot span more than 2 adjacent GRF registers");
790 /* On IVB/BYT, region parameters and execution size for DF are in terms of
791 * 32-bit elements, so they are doubled. For evaluating the validity of an
792 * instruction, we halve them.
794 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
798 align1_access_mask(dst_access_mask
, exec_size
, element_size
, subreg
,
799 exec_size
== 1 ? 0 : exec_size
* stride
,
800 exec_size
== 1 ? 1 : exec_size
,
801 exec_size
== 1 ? 0 : stride
);
803 unsigned dst_regs
= registers_read(dst_access_mask
);
804 unsigned src0_regs
= registers_read(src0_access_mask
);
805 unsigned src1_regs
= registers_read(src1_access_mask
);
807 /* The SNB, IVB, HSW, BDW, and CHV PRMs say:
809 * When an instruction has a source region spanning two registers and a
810 * destination region contained in one register, the number of elements
811 * must be the same between two sources and one of the following must be
814 * 1. The destination region is entirely contained in the lower OWord
816 * 2. The destination region is entirely contained in the upper OWord
818 * 3. The destination elements are evenly split between the two OWords
821 if (devinfo
->gen
<= 8) {
822 if (dst_regs
== 1 && (src0_regs
== 2 || src1_regs
== 2)) {
823 unsigned upper_oword_writes
= 0, lower_oword_writes
= 0;
825 for (unsigned i
= 0; i
< exec_size
; i
++) {
826 if (dst_access_mask
[i
] > 0x0000FFFF) {
827 upper_oword_writes
++;
829 assert(dst_access_mask
[i
] != 0);
830 lower_oword_writes
++;
834 ERROR_IF(lower_oword_writes
!= 0 &&
835 upper_oword_writes
!= 0 &&
836 upper_oword_writes
!= lower_oword_writes
,
837 "Writes must be to only one OWord or "
838 "evenly split between OWords");
842 /* The IVB and HSW PRMs say:
844 * When an instruction has a source region that spans two registers and
845 * the destination spans two registers, the destination elements must be
846 * evenly split between the two registers [...]
848 * The SNB PRM contains similar wording (but written in a much more
853 * When destination spans two registers, the source may be one or two
854 * registers. The destination elements must be evenly split between the
859 * When destination of MATH instruction spans two registers, the
860 * destination elements must be evenly split between the two registers.
862 * It is not known whether this restriction applies to KBL other Gens after
865 if (devinfo
->gen
<= 8 ||
866 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
868 /* Nothing explicitly states that on Gen < 8 elements must be evenly
869 * split between two destination registers in the two exceptional
870 * source-region-spans-one-register cases, but since Broadwell requires
871 * evenly split writes regardless of source region, we assume that it was
872 * an oversight and require it.
875 unsigned upper_reg_writes
= 0, lower_reg_writes
= 0;
877 for (unsigned i
= 0; i
< exec_size
; i
++) {
878 if (dst_access_mask
[i
] > 0xFFFFFFFF) {
881 assert(dst_access_mask
[i
] != 0);
886 ERROR_IF(upper_reg_writes
!= lower_reg_writes
,
887 "Writes must be evenly split between the two "
888 "destination registers");
892 /* The IVB and HSW PRMs say:
894 * When an instruction has a source region that spans two registers and
895 * the destination spans two registers, the destination elements must be
896 * evenly split between the two registers and each destination register
897 * must be entirely derived from one source register.
899 * Note: In such cases, the regioning parameters must ensure that the
900 * offset from the two source registers is the same.
902 * The SNB PRM contains similar wording (but written in a much more
905 * There are effectively three rules stated here:
907 * For an instruction with a source and a destination spanning two
910 * (1) destination elements must be evenly split between the two
912 * (2) all destination elements in a register must be derived
913 * from one source register
914 * (3) the offset (i.e. the starting location in each of the two
915 * registers spanned by a region) must be the same in the two
916 * registers spanned by a region
918 * It is impossible to violate rule (1) without violating (2) or (3), so we
919 * do not attempt to validate it.
921 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
922 for (unsigned i
= 0; i
< num_sources
; i
++) {
924 if (src ## n ## _regs <= 1) \
927 for (unsigned i = 0; i < exec_size; i++) { \
928 if ((dst_access_mask[i] > 0xFFFFFFFF) != \
929 (src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
930 ERROR("Each destination register must be entirely derived " \
931 "from one source register"); \
936 unsigned offset_0 = \
937 brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
938 unsigned offset_1 = offset_0; \
940 for (unsigned i = 0; i < exec_size; i++) { \
941 if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
942 offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
947 ERROR_IF(offset_0 != offset_1, \
948 "The offset from the two source registers " \
960 /* The IVB and HSW PRMs say:
962 * When destination spans two registers, the source MUST span two
963 * registers. The exception to the above rule:
964 * 1. When source is scalar, the source registers are not
966 * 2. When source is packed integer Word and destination is packed
967 * integer DWord, the source register is not incremented by the
968 * source sub register is incremented.
970 * The SNB PRM does not contain this rule, but the internal documentation
971 * indicates that it applies to SNB as well. We assume that the rule applies
972 * to Gen <= 5 although their PRMs do not state it.
974 * While the documentation explicitly says in exception (2) that the
975 * destination must be an integer DWord, the hardware allows at least a
976 * float destination type as well. We emit such instructions from
978 * fs_visitor::emit_interpolation_setup_gen6
979 * fs_visitor::emit_fragcoord_interpolation
981 * and have for years with no ill effects.
983 * Additionally the simulator source code indicates that the real condition
984 * is that the size of the destination type is 4 bytes.
986 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
987 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
988 bool dst_is_packed_dword
=
989 is_packed(exec_size
* stride
, exec_size
, stride
) &&
990 brw_reg_type_to_size(dst_type
) == 4;
992 for (unsigned i
= 0; i
< num_sources
; i
++) {
994 unsigned vstride, width, hstride; \
995 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
996 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
997 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
998 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
999 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
1000 bool src ## n ## _is_packed_word = \
1001 is_packed(vstride, width, hstride) && \
1002 (brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_W || \
1003 brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_UW); \
1005 ERROR_IF(src ## n ## _regs == 1 && \
1006 !src ## n ## _has_scalar_region(devinfo, inst) && \
1007 !(dst_is_packed_dword && src ## n ## _is_packed_word), \
1008 "When the destination spans two registers, the source must " \
1009 "span two registers\n" ERROR_INDENT "(exceptions for scalar " \
1010 "source and packed-word to packed-dword expansion)")
1014 } else if (i
== 1) {
1024 static struct string
1025 vector_immediate_restrictions(const struct gen_device_info
*devinfo
,
1026 const brw_inst
*inst
)
1028 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1029 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1031 if (num_sources
== 3 || num_sources
== 0)
1032 return (struct string
){};
1034 unsigned file
= num_sources
== 1 ?
1035 brw_inst_src0_reg_file(devinfo
, inst
) :
1036 brw_inst_src1_reg_file(devinfo
, inst
);
1037 if (file
!= BRW_IMMEDIATE_VALUE
)
1038 return (struct string
){};
1040 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1041 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1042 unsigned dst_subreg
= brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
?
1043 brw_inst_dst_da1_subreg_nr(devinfo
, inst
) : 0;
1044 unsigned dst_stride
= 1 << (brw_inst_dst_hstride(devinfo
, inst
) - 1);
1045 enum brw_reg_type type
= num_sources
== 1 ?
1046 brw_inst_src0_type(devinfo
, inst
) :
1047 brw_inst_src1_type(devinfo
, inst
);
1051 * When an immediate vector is used in an instruction, the destination
1052 * must be 128-bit aligned with destination horizontal stride equivalent
1053 * to a word for an immediate integer vector (v) and equivalent to a
1054 * DWord for an immediate float vector (vf).
1056 * The text has not been updated for the addition of the immediate unsigned
1057 * integer vector type (uv) on SNB, but presumably the same restriction
1061 case BRW_REGISTER_TYPE_V
:
1062 case BRW_REGISTER_TYPE_UV
:
1063 case BRW_REGISTER_TYPE_VF
:
1064 ERROR_IF(dst_subreg
% (128 / 8) != 0,
1065 "Destination must be 128-bit aligned in order to use immediate "
1068 if (type
== BRW_REGISTER_TYPE_VF
) {
1069 ERROR_IF(dst_type_size
* dst_stride
!= 4,
1070 "Destination must have stride equivalent to dword in order "
1071 "to use the VF type");
1073 ERROR_IF(dst_type_size
* dst_stride
!= 2,
1074 "Destination must have stride equivalent to word in order "
1075 "to use the V or UV type");
1086 brw_validate_instructions(const struct gen_device_info
*devinfo
,
1087 void *assembly
, int start_offset
, int end_offset
,
1088 struct annotation_info
*annotation
)
1092 for (int src_offset
= start_offset
; src_offset
< end_offset
;) {
1093 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1094 const brw_inst
*inst
= assembly
+ src_offset
;
1095 bool is_compact
= brw_inst_cmpt_control(devinfo
, inst
);
1096 brw_inst uncompacted
;
1099 brw_compact_inst
*compacted
= (void *)inst
;
1100 brw_uncompact_instruction(devinfo
, &uncompacted
, compacted
);
1101 inst
= &uncompacted
;
1104 if (is_unsupported_inst(devinfo
, inst
)) {
1105 ERROR("Instruction not supported on this Gen");
1107 CHECK(sources_not_null
);
1108 CHECK(send_restrictions
);
1109 CHECK(general_restrictions_based_on_operand_types
);
1110 CHECK(general_restrictions_on_region_parameters
);
1111 CHECK(region_alignment_rules
);
1112 CHECK(vector_immediate_restrictions
);
1115 if (error_msg
.str
&& annotation
) {
1116 annotation_insert_error(annotation
, src_offset
, error_msg
.str
);
1118 valid
= valid
&& error_msg
.len
== 0;
1119 free(error_msg
.str
);
1122 src_offset
+= sizeof(brw_compact_inst
);
1124 src_offset
+= sizeof(brw_inst
);