2 * Copyright © 2015-2019 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_validate.c
26 * This file implements a pass that validates shader assembly.
28 * The restrictions implemented herein are intended to verify that instructions
29 * in shader assembly do not violate restrictions documented in the graphics
30 * programming reference manuals.
32 * The restrictions are difficult for humans to quickly verify due to their
33 * complexity and abundance.
35 * It is critical that this code is thoroughly unit tested because false
36 * results will lead developers astray, which is worse than having no validator
37 * at all. Functional changes to this file without corresponding unit tests (in
38 * test_eu_validate.cpp) will be rejected.
43 /* We're going to do lots of string concatenation, so this should help. */
50 cat(struct string
*dest
, const struct string src
)
52 dest
->str
= realloc(dest
->str
, dest
->len
+ src
.len
+ 1);
53 memcpy(dest
->str
+ dest
->len
, src
.str
, src
.len
);
54 dest
->str
[dest
->len
+ src
.len
] = '\0';
55 dest
->len
= dest
->len
+ src
.len
;
57 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
60 contains(const struct string haystack
, const struct string needle
)
62 return haystack
.str
&& memmem(haystack
.str
, haystack
.len
,
63 needle
.str
, needle
.len
) != NULL
;
65 #define CONTAINS(haystack, needle) \
66 contains(haystack, (struct string){needle, strlen(needle)})
68 #define error(str) "\tERROR: " str "\n"
69 #define ERROR_INDENT "\t "
71 #define ERROR(msg) ERROR_IF(true, msg)
72 #define ERROR_IF(cond, msg) \
74 if ((cond) && !CONTAINS(error_msg, error(msg))) { \
75 CAT(error_msg, error(msg)); \
79 #define CHECK(func, args...) \
81 struct string __msg = func(devinfo, inst, ##args); \
83 cat(&error_msg, __msg); \
88 #define STRIDE(stride) (stride != 0 ? 1 << ((stride) - 1) : 0)
89 #define WIDTH(width) (1 << (width))
92 inst_is_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
94 switch (brw_inst_opcode(devinfo
, inst
)) {
96 case BRW_OPCODE_SENDC
:
97 case BRW_OPCODE_SENDS
:
98 case BRW_OPCODE_SENDSC
:
106 inst_is_split_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
108 switch (brw_inst_opcode(devinfo
, inst
)) {
109 case BRW_OPCODE_SENDS
:
110 case BRW_OPCODE_SENDSC
:
118 signed_type(unsigned type
)
121 case BRW_REGISTER_TYPE_UD
: return BRW_REGISTER_TYPE_D
;
122 case BRW_REGISTER_TYPE_UW
: return BRW_REGISTER_TYPE_W
;
123 case BRW_REGISTER_TYPE_UB
: return BRW_REGISTER_TYPE_B
;
124 case BRW_REGISTER_TYPE_UQ
: return BRW_REGISTER_TYPE_Q
;
125 default: return type
;
130 inst_is_raw_move(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
132 unsigned dst_type
= signed_type(brw_inst_dst_type(devinfo
, inst
));
133 unsigned src_type
= signed_type(brw_inst_src0_type(devinfo
, inst
));
135 if (brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
) {
136 /* FIXME: not strictly true */
137 if (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_VF
||
138 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UV
||
139 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_V
) {
142 } else if (brw_inst_src0_negate(devinfo
, inst
) ||
143 brw_inst_src0_abs(devinfo
, inst
)) {
147 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MOV
&&
148 brw_inst_saturate(devinfo
, inst
) == 0 &&
149 dst_type
== src_type
;
153 dst_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
155 return brw_inst_dst_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
156 brw_inst_dst_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
160 src0_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
162 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
163 brw_inst_src0_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
167 src1_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
169 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
170 brw_inst_src1_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
174 src0_is_grf(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
176 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
;
180 src0_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
182 return brw_inst_src0_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
183 brw_inst_src0_width(devinfo
, inst
) == BRW_WIDTH_1
&&
184 brw_inst_src0_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
188 src1_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
190 return brw_inst_src1_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
191 brw_inst_src1_width(devinfo
, inst
) == BRW_WIDTH_1
&&
192 brw_inst_src1_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
196 num_sources_from_inst(const struct gen_device_info
*devinfo
,
197 const brw_inst
*inst
)
199 const struct opcode_desc
*desc
=
200 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
201 unsigned math_function
;
203 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
204 math_function
= brw_inst_math_function(devinfo
, inst
);
205 } else if (devinfo
->gen
< 6 &&
206 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
207 if (brw_inst_sfid(devinfo
, inst
) == BRW_SFID_MATH
) {
208 /* src1 must be a descriptor (including the information to determine
209 * that the SEND is doing an extended math operation), but src0 can
210 * actually be null since it serves as the source of the implicit GRF
213 * If we stop using that functionality, we'll have to revisit this.
217 /* Send instructions are allowed to have null sources since they use
218 * the base_mrf field to specify which message register source.
223 assert(desc
->nsrc
< 4);
227 switch (math_function
) {
228 case BRW_MATH_FUNCTION_INV
:
229 case BRW_MATH_FUNCTION_LOG
:
230 case BRW_MATH_FUNCTION_EXP
:
231 case BRW_MATH_FUNCTION_SQRT
:
232 case BRW_MATH_FUNCTION_RSQ
:
233 case BRW_MATH_FUNCTION_SIN
:
234 case BRW_MATH_FUNCTION_COS
:
235 case BRW_MATH_FUNCTION_SINCOS
:
236 case GEN8_MATH_FUNCTION_INVM
:
237 case GEN8_MATH_FUNCTION_RSQRTM
:
239 case BRW_MATH_FUNCTION_FDIV
:
240 case BRW_MATH_FUNCTION_POW
:
241 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
242 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
243 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
246 unreachable("not reached");
251 sources_not_null(const struct gen_device_info
*devinfo
,
252 const brw_inst
*inst
)
254 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
255 struct string error_msg
= { .str
= NULL
, .len
= 0 };
257 /* Nothing to test. 3-src instructions can only have GRF sources, and
258 * there's no bit to control the file.
260 if (num_sources
== 3)
261 return (struct string
){};
263 /* Nothing to test. Split sends can only encode a file in sources that are
264 * allowed to be NULL.
266 if (inst_is_split_send(devinfo
, inst
))
267 return (struct string
){};
269 if (num_sources
>= 1)
270 ERROR_IF(src0_is_null(devinfo
, inst
), "src0 is null");
272 if (num_sources
== 2)
273 ERROR_IF(src1_is_null(devinfo
, inst
), "src1 is null");
279 send_restrictions(const struct gen_device_info
*devinfo
,
280 const brw_inst
*inst
)
282 struct string error_msg
= { .str
= NULL
, .len
= 0 };
284 if (inst_is_split_send(devinfo
, inst
)) {
285 ERROR_IF(brw_inst_send_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
286 brw_inst_send_src1_reg_nr(devinfo
, inst
) != BRW_ARF_NULL
,
287 "src1 of split send must be a GRF or NULL");
289 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
290 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
291 "send with EOT must use g112-g127");
292 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
293 brw_inst_send_src1_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
&&
294 brw_inst_send_src1_reg_nr(devinfo
, inst
) < 112,
295 "send with EOT must use g112-g127");
297 if (brw_inst_send_src1_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
) {
298 /* Assume minimums if we don't know */
300 if (!brw_inst_send_sel_reg32_desc(devinfo
, inst
)) {
301 const uint32_t desc
= brw_inst_send_desc(devinfo
, inst
);
302 mlen
= brw_message_desc_mlen(devinfo
, desc
);
305 unsigned ex_mlen
= 1;
306 if (!brw_inst_send_sel_reg32_ex_desc(devinfo
, inst
)) {
307 const uint32_t ex_desc
= brw_inst_send_ex_desc(devinfo
, inst
);
308 ex_mlen
= brw_message_ex_desc_ex_mlen(devinfo
, ex_desc
);
310 const unsigned src0_reg_nr
= brw_inst_src0_da_reg_nr(devinfo
, inst
);
311 const unsigned src1_reg_nr
= brw_inst_send_src1_reg_nr(devinfo
, inst
);
312 ERROR_IF((src0_reg_nr
<= src1_reg_nr
&&
313 src1_reg_nr
< src0_reg_nr
+ mlen
) ||
314 (src1_reg_nr
<= src0_reg_nr
&&
315 src0_reg_nr
< src1_reg_nr
+ ex_mlen
),
316 "split send payloads must not overlap");
318 } else if (inst_is_send(devinfo
, inst
)) {
319 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
,
320 "send must use direct addressing");
322 if (devinfo
->gen
>= 7) {
323 ERROR_IF(!src0_is_grf(devinfo
, inst
), "send from non-GRF");
324 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
325 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
326 "send with EOT must use g112-g127");
329 if (devinfo
->gen
>= 8) {
330 ERROR_IF(!dst_is_null(devinfo
, inst
) &&
331 (brw_inst_dst_da_reg_nr(devinfo
, inst
) +
332 brw_inst_rlen(devinfo
, inst
) > 127) &&
333 (brw_inst_src0_da_reg_nr(devinfo
, inst
) +
334 brw_inst_mlen(devinfo
, inst
) >
335 brw_inst_dst_da_reg_nr(devinfo
, inst
)),
336 "r127 must not be used for return address when there is "
337 "a src and dest overlap");
345 is_unsupported_inst(const struct gen_device_info
*devinfo
,
346 const brw_inst
*inst
)
348 return brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
)) == NULL
;
351 static enum brw_reg_type
352 execution_type_for_type(enum brw_reg_type type
)
355 case BRW_REGISTER_TYPE_NF
:
356 case BRW_REGISTER_TYPE_DF
:
357 case BRW_REGISTER_TYPE_F
:
358 case BRW_REGISTER_TYPE_HF
:
361 case BRW_REGISTER_TYPE_VF
:
362 return BRW_REGISTER_TYPE_F
;
364 case BRW_REGISTER_TYPE_Q
:
365 case BRW_REGISTER_TYPE_UQ
:
366 return BRW_REGISTER_TYPE_Q
;
368 case BRW_REGISTER_TYPE_D
:
369 case BRW_REGISTER_TYPE_UD
:
370 return BRW_REGISTER_TYPE_D
;
372 case BRW_REGISTER_TYPE_W
:
373 case BRW_REGISTER_TYPE_UW
:
374 case BRW_REGISTER_TYPE_B
:
375 case BRW_REGISTER_TYPE_UB
:
376 case BRW_REGISTER_TYPE_V
:
377 case BRW_REGISTER_TYPE_UV
:
378 return BRW_REGISTER_TYPE_W
;
380 unreachable("not reached");
384 * Returns the execution type of an instruction \p inst
386 static enum brw_reg_type
387 execution_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
389 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
390 enum brw_reg_type src0_exec_type
, src1_exec_type
;
392 /* Execution data type is independent of destination data type, except in
393 * mixed F/HF instructions on CHV and SKL+.
395 enum brw_reg_type dst_exec_type
= brw_inst_dst_type(devinfo
, inst
);
397 src0_exec_type
= execution_type_for_type(brw_inst_src0_type(devinfo
, inst
));
398 if (num_sources
== 1) {
399 if ((devinfo
->gen
>= 9 || devinfo
->is_cherryview
) &&
400 src0_exec_type
== BRW_REGISTER_TYPE_HF
) {
401 return dst_exec_type
;
403 return src0_exec_type
;
406 src1_exec_type
= execution_type_for_type(brw_inst_src1_type(devinfo
, inst
));
407 if (src0_exec_type
== src1_exec_type
)
408 return src0_exec_type
;
410 /* Mixed operand types where one is float is float on Gen < 6
411 * (and not allowed on later platforms)
413 if (devinfo
->gen
< 6 &&
414 (src0_exec_type
== BRW_REGISTER_TYPE_F
||
415 src1_exec_type
== BRW_REGISTER_TYPE_F
))
416 return BRW_REGISTER_TYPE_F
;
418 if (src0_exec_type
== BRW_REGISTER_TYPE_Q
||
419 src1_exec_type
== BRW_REGISTER_TYPE_Q
)
420 return BRW_REGISTER_TYPE_Q
;
422 if (src0_exec_type
== BRW_REGISTER_TYPE_D
||
423 src1_exec_type
== BRW_REGISTER_TYPE_D
)
424 return BRW_REGISTER_TYPE_D
;
426 if (src0_exec_type
== BRW_REGISTER_TYPE_W
||
427 src1_exec_type
== BRW_REGISTER_TYPE_W
)
428 return BRW_REGISTER_TYPE_W
;
430 if (src0_exec_type
== BRW_REGISTER_TYPE_DF
||
431 src1_exec_type
== BRW_REGISTER_TYPE_DF
)
432 return BRW_REGISTER_TYPE_DF
;
434 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
435 if (dst_exec_type
== BRW_REGISTER_TYPE_F
||
436 src0_exec_type
== BRW_REGISTER_TYPE_F
||
437 src1_exec_type
== BRW_REGISTER_TYPE_F
) {
438 return BRW_REGISTER_TYPE_F
;
440 return BRW_REGISTER_TYPE_HF
;
444 assert(src0_exec_type
== BRW_REGISTER_TYPE_F
);
445 return BRW_REGISTER_TYPE_F
;
449 * Returns whether a region is packed
451 * A region is packed if its elements are adjacent in memory, with no
452 * intervening space, no overlap, and no replicated values.
455 is_packed(unsigned vstride
, unsigned width
, unsigned hstride
)
457 if (vstride
== width
) {
469 * Checks restrictions listed in "General Restrictions Based on Operand Types"
470 * in the "Register Region Restrictions" section.
473 general_restrictions_based_on_operand_types(const struct gen_device_info
*devinfo
,
474 const brw_inst
*inst
)
476 const struct opcode_desc
*desc
=
477 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
478 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
479 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
480 struct string error_msg
= { .str
= NULL
, .len
= 0 };
482 if (num_sources
== 3)
483 return (struct string
){};
485 if (inst_is_send(devinfo
, inst
))
486 return (struct string
){};
489 return (struct string
){};
492 return (struct string
){};
496 * Where n is the largest element size in bytes for any source or
497 * destination operand type, ExecSize * n must be <= 64.
499 * But we do not attempt to enforce it, because it is implied by other
502 * - that the destination stride must match the execution data type
503 * - sources may not span more than two adjacent GRF registers
504 * - destination may not span more than two adjacent GRF registers
506 * In fact, checking it would weaken testing of the other rules.
509 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
510 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
511 bool dst_type_is_byte
=
512 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_B
||
513 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UB
;
515 if (dst_type_is_byte
) {
516 if (is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
)) {
517 if (!inst_is_raw_move(devinfo
, inst
)) {
518 ERROR("Only raw MOV supports a packed-byte destination");
521 return (struct string
){};
526 unsigned exec_type
= execution_type(devinfo
, inst
);
527 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
528 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
530 /* On IVB/BYT, region parameters and execution size for DF are in terms of
531 * 32-bit elements, so they are doubled. For evaluating the validity of an
532 * instruction, we halve them.
534 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
535 exec_type_size
== 8 && dst_type_size
== 4)
538 if (exec_type_size
> dst_type_size
) {
539 if (!(dst_type_is_byte
&& inst_is_raw_move(devinfo
, inst
))) {
540 ERROR_IF(dst_stride
* dst_type_size
!= exec_type_size
,
541 "Destination stride must be equal to the ratio of the sizes "
542 "of the execution data type to the destination type");
545 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
547 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
548 brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
) {
549 /* The i965 PRM says:
551 * Implementation Restriction: The relaxed alignment rule for byte
552 * destination (#10.5) is not supported.
554 if ((devinfo
->gen
> 4 || devinfo
->is_g4x
) && dst_type_is_byte
) {
555 ERROR_IF(subreg
% exec_type_size
!= 0 &&
556 subreg
% exec_type_size
!= 1,
557 "Destination subreg must be aligned to the size of the "
558 "execution data type (or to the next lowest byte for byte "
561 ERROR_IF(subreg
% exec_type_size
!= 0,
562 "Destination subreg must be aligned to the size of the "
563 "execution data type");
572 * Checks restrictions listed in "General Restrictions on Regioning Parameters"
573 * in the "Register Region Restrictions" section.
576 general_restrictions_on_region_parameters(const struct gen_device_info
*devinfo
,
577 const brw_inst
*inst
)
579 const struct opcode_desc
*desc
=
580 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
581 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
582 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
583 struct string error_msg
= { .str
= NULL
, .len
= 0 };
585 if (num_sources
== 3)
586 return (struct string
){};
588 /* Split sends don't have the bits in the instruction to encode regions so
589 * there's nothing to check.
591 if (inst_is_split_send(devinfo
, inst
))
592 return (struct string
){};
594 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
) {
595 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
))
596 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) != BRW_HORIZONTAL_STRIDE_1
,
597 "Destination Horizontal Stride must be 1");
599 if (num_sources
>= 1) {
600 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
601 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
602 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
603 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
604 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
605 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
607 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
608 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
609 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
610 "In Align16 mode, only VertStride of 0 or 4 is allowed");
614 if (num_sources
== 2) {
615 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
616 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
617 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
618 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
619 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
620 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
622 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
623 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
624 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
625 "In Align16 mode, only VertStride of 0 or 4 is allowed");
632 for (unsigned i
= 0; i
< num_sources
; i
++) {
633 unsigned vstride
, width
, hstride
, element_size
, subreg
;
634 enum brw_reg_type type
;
637 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
638 BRW_IMMEDIATE_VALUE) \
641 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
642 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
643 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
644 type = brw_inst_src ## n ## _type(devinfo, inst); \
645 element_size = brw_reg_type_to_size(type); \
646 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
655 /* On IVB/BYT, region parameters and execution size for DF are in terms of
656 * 32-bit elements, so they are doubled. For evaluating the validity of an
657 * instruction, we halve them.
659 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
663 /* ExecSize must be greater than or equal to Width. */
664 ERROR_IF(exec_size
< width
, "ExecSize must be greater than or equal "
667 /* If ExecSize = Width and HorzStride ≠ 0,
668 * VertStride must be set to Width * HorzStride.
670 if (exec_size
== width
&& hstride
!= 0) {
671 ERROR_IF(vstride
!= width
* hstride
,
672 "If ExecSize = Width and HorzStride ≠ 0, "
673 "VertStride must be set to Width * HorzStride");
676 /* If Width = 1, HorzStride must be 0 regardless of the values of
677 * ExecSize and VertStride.
680 ERROR_IF(hstride
!= 0,
681 "If Width = 1, HorzStride must be 0 regardless "
682 "of the values of ExecSize and VertStride");
685 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
686 if (exec_size
== 1 && width
== 1) {
687 ERROR_IF(vstride
!= 0 || hstride
!= 0,
688 "If ExecSize = Width = 1, both VertStride "
689 "and HorzStride must be 0");
692 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the
695 if (vstride
== 0 && hstride
== 0) {
697 "If VertStride = HorzStride = 0, Width must be "
698 "1 regardless of the value of ExecSize");
701 /* VertStride must be used to cross GRF register boundaries. This rule
702 * implies that elements within a 'Width' cannot cross GRF boundaries.
704 const uint64_t mask
= (1ULL << element_size
) - 1;
705 unsigned rowbase
= subreg
;
707 for (int y
= 0; y
< exec_size
/ width
; y
++) {
708 uint64_t access_mask
= 0;
709 unsigned offset
= rowbase
;
711 for (int x
= 0; x
< width
; x
++) {
712 access_mask
|= mask
<< offset
;
713 offset
+= hstride
* element_size
;
716 rowbase
+= vstride
* element_size
;
718 if ((uint32_t)access_mask
!= 0 && (access_mask
>> 32) != 0) {
719 ERROR("VertStride must be used to cross GRF register boundaries");
725 /* Dst.HorzStride must not be 0. */
726 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
)) {
727 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
,
728 "Destination Horizontal Stride must not be 0");
735 * Creates an \p access_mask for an \p exec_size, \p element_size, and a region
737 * An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
738 * a bitmask of bytes accessed by the region.
740 * For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
741 * instruction would be
743 * access_mask[0] = 0x00000000000000F0
744 * access_mask[1] = 0x000000000000F000
745 * access_mask[2] = 0x0000000000F00000
746 * access_mask[3] = 0x00000000F0000000
747 * access_mask[4-31] = 0
749 * because the first execution channel accesses bytes 7-4 and the second
750 * execution channel accesses bytes 15-12, etc.
753 align1_access_mask(uint64_t access_mask
[static 32],
754 unsigned exec_size
, unsigned element_size
, unsigned subreg
,
755 unsigned vstride
, unsigned width
, unsigned hstride
)
757 const uint64_t mask
= (1ULL << element_size
) - 1;
758 unsigned rowbase
= subreg
;
759 unsigned element
= 0;
761 for (int y
= 0; y
< exec_size
/ width
; y
++) {
762 unsigned offset
= rowbase
;
764 for (int x
= 0; x
< width
; x
++) {
765 access_mask
[element
++] = mask
<< offset
;
766 offset
+= hstride
* element_size
;
769 rowbase
+= vstride
* element_size
;
772 assert(element
== 0 || element
== exec_size
);
776 * Returns the number of registers accessed according to the \p access_mask
779 registers_read(const uint64_t access_mask
[static 32])
783 for (unsigned i
= 0; i
< 32; i
++) {
784 if (access_mask
[i
] > 0xFFFFFFFF) {
786 } else if (access_mask
[i
]) {
795 * Checks restrictions listed in "Region Alignment Rules" in the "Register
796 * Region Restrictions" section.
799 region_alignment_rules(const struct gen_device_info
*devinfo
,
800 const brw_inst
*inst
)
802 const struct opcode_desc
*desc
=
803 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
804 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
805 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
806 uint64_t dst_access_mask
[32], src0_access_mask
[32], src1_access_mask
[32];
807 struct string error_msg
= { .str
= NULL
, .len
= 0 };
809 if (num_sources
== 3)
810 return (struct string
){};
812 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
)
813 return (struct string
){};
815 if (inst_is_send(devinfo
, inst
))
816 return (struct string
){};
818 memset(dst_access_mask
, 0, sizeof(dst_access_mask
));
819 memset(src0_access_mask
, 0, sizeof(src0_access_mask
));
820 memset(src1_access_mask
, 0, sizeof(src1_access_mask
));
822 for (unsigned i
= 0; i
< num_sources
; i
++) {
823 unsigned vstride
, width
, hstride
, element_size
, subreg
;
824 enum brw_reg_type type
;
826 /* In Direct Addressing mode, a source cannot span more than 2 adjacent
831 if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
832 BRW_ADDRESS_DIRECT) \
835 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
836 BRW_IMMEDIATE_VALUE) \
839 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
840 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
841 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
842 type = brw_inst_src ## n ## _type(devinfo, inst); \
843 element_size = brw_reg_type_to_size(type); \
844 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
845 align1_access_mask(src ## n ## _access_mask, \
846 exec_size, element_size, subreg, \
847 vstride, width, hstride)
856 unsigned num_vstride
= exec_size
/ width
;
857 unsigned num_hstride
= width
;
858 unsigned vstride_elements
= (num_vstride
- 1) * vstride
;
859 unsigned hstride_elements
= (num_hstride
- 1) * hstride
;
860 unsigned offset
= (vstride_elements
+ hstride_elements
) * element_size
+
862 ERROR_IF(offset
>= 64,
863 "A source cannot span more than 2 adjacent GRF registers");
866 if (desc
->ndst
== 0 || dst_is_null(devinfo
, inst
))
869 unsigned stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
870 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
871 unsigned element_size
= brw_reg_type_to_size(dst_type
);
872 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
873 unsigned offset
= ((exec_size
- 1) * stride
* element_size
) + subreg
;
874 ERROR_IF(offset
>= 64,
875 "A destination cannot span more than 2 adjacent GRF registers");
880 /* On IVB/BYT, region parameters and execution size for DF are in terms of
881 * 32-bit elements, so they are doubled. For evaluating the validity of an
882 * instruction, we halve them.
884 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
888 align1_access_mask(dst_access_mask
, exec_size
, element_size
, subreg
,
889 exec_size
== 1 ? 0 : exec_size
* stride
,
890 exec_size
== 1 ? 1 : exec_size
,
891 exec_size
== 1 ? 0 : stride
);
893 unsigned dst_regs
= registers_read(dst_access_mask
);
894 unsigned src0_regs
= registers_read(src0_access_mask
);
895 unsigned src1_regs
= registers_read(src1_access_mask
);
897 /* The SNB, IVB, HSW, BDW, and CHV PRMs say:
899 * When an instruction has a source region spanning two registers and a
900 * destination region contained in one register, the number of elements
901 * must be the same between two sources and one of the following must be
904 * 1. The destination region is entirely contained in the lower OWord
906 * 2. The destination region is entirely contained in the upper OWord
908 * 3. The destination elements are evenly split between the two OWords
911 if (devinfo
->gen
<= 8) {
912 if (dst_regs
== 1 && (src0_regs
== 2 || src1_regs
== 2)) {
913 unsigned upper_oword_writes
= 0, lower_oword_writes
= 0;
915 for (unsigned i
= 0; i
< exec_size
; i
++) {
916 if (dst_access_mask
[i
] > 0x0000FFFF) {
917 upper_oword_writes
++;
919 assert(dst_access_mask
[i
] != 0);
920 lower_oword_writes
++;
924 ERROR_IF(lower_oword_writes
!= 0 &&
925 upper_oword_writes
!= 0 &&
926 upper_oword_writes
!= lower_oword_writes
,
927 "Writes must be to only one OWord or "
928 "evenly split between OWords");
932 /* The IVB and HSW PRMs say:
934 * When an instruction has a source region that spans two registers and
935 * the destination spans two registers, the destination elements must be
936 * evenly split between the two registers [...]
938 * The SNB PRM contains similar wording (but written in a much more
943 * When destination spans two registers, the source may be one or two
944 * registers. The destination elements must be evenly split between the
949 * When destination of MATH instruction spans two registers, the
950 * destination elements must be evenly split between the two registers.
952 * It is not known whether this restriction applies to KBL other Gens after
955 if (devinfo
->gen
<= 8 ||
956 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
958 /* Nothing explicitly states that on Gen < 8 elements must be evenly
959 * split between two destination registers in the two exceptional
960 * source-region-spans-one-register cases, but since Broadwell requires
961 * evenly split writes regardless of source region, we assume that it was
962 * an oversight and require it.
965 unsigned upper_reg_writes
= 0, lower_reg_writes
= 0;
967 for (unsigned i
= 0; i
< exec_size
; i
++) {
968 if (dst_access_mask
[i
] > 0xFFFFFFFF) {
971 assert(dst_access_mask
[i
] != 0);
976 ERROR_IF(upper_reg_writes
!= lower_reg_writes
,
977 "Writes must be evenly split between the two "
978 "destination registers");
982 /* The IVB and HSW PRMs say:
984 * When an instruction has a source region that spans two registers and
985 * the destination spans two registers, the destination elements must be
986 * evenly split between the two registers and each destination register
987 * must be entirely derived from one source register.
989 * Note: In such cases, the regioning parameters must ensure that the
990 * offset from the two source registers is the same.
992 * The SNB PRM contains similar wording (but written in a much more
995 * There are effectively three rules stated here:
997 * For an instruction with a source and a destination spanning two
1000 * (1) destination elements must be evenly split between the two
1002 * (2) all destination elements in a register must be derived
1003 * from one source register
1004 * (3) the offset (i.e. the starting location in each of the two
1005 * registers spanned by a region) must be the same in the two
1006 * registers spanned by a region
1008 * It is impossible to violate rule (1) without violating (2) or (3), so we
1009 * do not attempt to validate it.
1011 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
1012 for (unsigned i
= 0; i
< num_sources
; i
++) {
1014 if (src ## n ## _regs <= 1) \
1017 for (unsigned i = 0; i < exec_size; i++) { \
1018 if ((dst_access_mask[i] > 0xFFFFFFFF) != \
1019 (src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
1020 ERROR("Each destination register must be entirely derived " \
1021 "from one source register"); \
1026 unsigned offset_0 = \
1027 brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1028 unsigned offset_1 = offset_0; \
1030 for (unsigned i = 0; i < exec_size; i++) { \
1031 if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
1032 offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
1037 ERROR_IF(num_sources == 2 && offset_0 != offset_1, \
1038 "The offset from the two source registers " \
1050 /* The IVB and HSW PRMs say:
1052 * When destination spans two registers, the source MUST span two
1053 * registers. The exception to the above rule:
1054 * 1. When source is scalar, the source registers are not
1056 * 2. When source is packed integer Word and destination is packed
1057 * integer DWord, the source register is not incremented by the
1058 * source sub register is incremented.
1060 * The SNB PRM does not contain this rule, but the internal documentation
1061 * indicates that it applies to SNB as well. We assume that the rule applies
1062 * to Gen <= 5 although their PRMs do not state it.
1064 * While the documentation explicitly says in exception (2) that the
1065 * destination must be an integer DWord, the hardware allows at least a
1066 * float destination type as well. We emit such instructions from
1068 * fs_visitor::emit_interpolation_setup_gen6
1069 * fs_visitor::emit_fragcoord_interpolation
1071 * and have for years with no ill effects.
1073 * Additionally the simulator source code indicates that the real condition
1074 * is that the size of the destination type is 4 bytes.
1076 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
1077 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1078 bool dst_is_packed_dword
=
1079 is_packed(exec_size
* stride
, exec_size
, stride
) &&
1080 brw_reg_type_to_size(dst_type
) == 4;
1082 for (unsigned i
= 0; i
< num_sources
; i
++) {
1084 unsigned vstride, width, hstride; \
1085 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1086 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1087 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1088 bool src ## n ## _is_packed_word = \
1089 is_packed(vstride, width, hstride) && \
1090 (brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_W || \
1091 brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_UW); \
1093 ERROR_IF(src ## n ## _regs == 1 && \
1094 !src ## n ## _has_scalar_region(devinfo, inst) && \
1095 !(dst_is_packed_dword && src ## n ## _is_packed_word), \
1096 "When the destination spans two registers, the source must " \
1097 "span two registers\n" ERROR_INDENT "(exceptions for scalar " \
1098 "source and packed-word to packed-dword expansion)")
1112 static struct string
1113 vector_immediate_restrictions(const struct gen_device_info
*devinfo
,
1114 const brw_inst
*inst
)
1116 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1117 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1119 if (num_sources
== 3 || num_sources
== 0)
1120 return (struct string
){};
1122 unsigned file
= num_sources
== 1 ?
1123 brw_inst_src0_reg_file(devinfo
, inst
) :
1124 brw_inst_src1_reg_file(devinfo
, inst
);
1125 if (file
!= BRW_IMMEDIATE_VALUE
)
1126 return (struct string
){};
1128 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1129 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1130 unsigned dst_subreg
= brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
?
1131 brw_inst_dst_da1_subreg_nr(devinfo
, inst
) : 0;
1132 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1133 enum brw_reg_type type
= num_sources
== 1 ?
1134 brw_inst_src0_type(devinfo
, inst
) :
1135 brw_inst_src1_type(devinfo
, inst
);
1139 * When an immediate vector is used in an instruction, the destination
1140 * must be 128-bit aligned with destination horizontal stride equivalent
1141 * to a word for an immediate integer vector (v) and equivalent to a
1142 * DWord for an immediate float vector (vf).
1144 * The text has not been updated for the addition of the immediate unsigned
1145 * integer vector type (uv) on SNB, but presumably the same restriction
1149 case BRW_REGISTER_TYPE_V
:
1150 case BRW_REGISTER_TYPE_UV
:
1151 case BRW_REGISTER_TYPE_VF
:
1152 ERROR_IF(dst_subreg
% (128 / 8) != 0,
1153 "Destination must be 128-bit aligned in order to use immediate "
1156 if (type
== BRW_REGISTER_TYPE_VF
) {
1157 ERROR_IF(dst_type_size
* dst_stride
!= 4,
1158 "Destination must have stride equivalent to dword in order "
1159 "to use the VF type");
1161 ERROR_IF(dst_type_size
* dst_stride
!= 2,
1162 "Destination must have stride equivalent to word in order "
1163 "to use the V or UV type");
1173 static struct string
1174 special_requirements_for_handling_double_precision_data_types(
1175 const struct gen_device_info
*devinfo
,
1176 const brw_inst
*inst
)
1178 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1179 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1181 if (num_sources
== 3 || num_sources
== 0)
1182 return (struct string
){};
1184 /* Split sends don't have types so there's no doubles there. */
1185 if (inst_is_split_send(devinfo
, inst
))
1186 return (struct string
){};
1188 enum brw_reg_type exec_type
= execution_type(devinfo
, inst
);
1189 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
1191 enum brw_reg_file dst_file
= brw_inst_dst_reg_file(devinfo
, inst
);
1192 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1193 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1194 unsigned dst_hstride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1195 unsigned dst_reg
= brw_inst_dst_da_reg_nr(devinfo
, inst
);
1196 unsigned dst_subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
1197 unsigned dst_address_mode
= brw_inst_dst_address_mode(devinfo
, inst
);
1199 bool is_integer_dword_multiply
=
1200 devinfo
->gen
>= 8 &&
1201 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MUL
&&
1202 (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1203 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
) &&
1204 (brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1205 brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
);
1207 if (dst_type_size
!= 8 && exec_type_size
!= 8 && !is_integer_dword_multiply
)
1208 return (struct string
){};
1210 for (unsigned i
= 0; i
< num_sources
; i
++) {
1211 unsigned vstride
, width
, hstride
, type_size
, reg
, subreg
, address_mode
;
1212 bool is_scalar_region
;
1213 enum brw_reg_file file
;
1214 enum brw_reg_type type
;
1217 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
1218 BRW_IMMEDIATE_VALUE) \
1221 is_scalar_region = src ## n ## _has_scalar_region(devinfo, inst); \
1222 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1223 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1224 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1225 file = brw_inst_src ## n ## _reg_file(devinfo, inst); \
1226 type = brw_inst_src ## n ## _type(devinfo, inst); \
1227 type_size = brw_reg_type_to_size(type); \
1228 reg = brw_inst_src ## n ## _da_reg_nr(devinfo, inst); \
1229 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1230 address_mode = brw_inst_src ## n ## _address_mode(devinfo, inst)
1239 /* The PRMs say that for CHV, BXT:
1241 * When source or destination datatype is 64b or operation is integer
1242 * DWord multiply, regioning in Align1 must follow these rules:
1244 * 1. Source and Destination horizontal stride must be aligned to the
1246 * 2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
1247 * 3. Source and Destination offset must be the same, except the case
1250 * We assume that the restriction applies to GLK as well.
1252 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
1253 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
1254 unsigned src_stride
= hstride
* type_size
;
1255 unsigned dst_stride
= dst_hstride
* dst_type_size
;
1257 ERROR_IF(!is_scalar_region
&&
1258 (src_stride
% 8 != 0 ||
1259 dst_stride
% 8 != 0 ||
1260 src_stride
!= dst_stride
),
1261 "Source and destination horizontal stride must equal and a "
1262 "multiple of a qword when the execution type is 64-bit");
1264 ERROR_IF(vstride
!= width
* hstride
,
1265 "Vstride must be Width * Hstride when the execution type is "
1268 ERROR_IF(!is_scalar_region
&& dst_subreg
!= subreg
,
1269 "Source and destination offset must be the same when the "
1270 "execution type is 64-bit");
1273 /* The PRMs say that for CHV, BXT:
1275 * When source or destination datatype is 64b or operation is integer
1276 * DWord multiply, indirect addressing must not be used.
1278 * We assume that the restriction applies to GLK as well.
1280 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1281 ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== address_mode
||
1282 BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== dst_address_mode
,
1283 "Indirect addressing is not allowed when the execution type "
1287 /* The PRMs say that for CHV, BXT:
1289 * ARF registers must never be used with 64b datatype or when
1290 * operation is integer DWord multiply.
1292 * We assume that the restriction applies to GLK as well.
1294 * We assume that the restriction does not apply to the null register.
1296 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1297 ERROR_IF(brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MAC
||
1298 brw_inst_acc_wr_control(devinfo
, inst
) ||
1299 (BRW_ARCHITECTURE_REGISTER_FILE
== file
&&
1300 reg
!= BRW_ARF_NULL
) ||
1301 (BRW_ARCHITECTURE_REGISTER_FILE
== dst_file
&&
1302 dst_reg
!= BRW_ARF_NULL
),
1303 "Architecture registers cannot be used when the execution "
1308 /* The PRMs say that for BDW, SKL:
1310 * If Align16 is required for an operation with QW destination and non-QW
1311 * source datatypes, the execution size cannot exceed 2.
1313 * We assume that the restriction applies to all Gen8+ parts.
1315 if (devinfo
->gen
>= 8) {
1316 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
1317 enum brw_reg_type src1_type
=
1318 num_sources
> 1 ? brw_inst_src1_type(devinfo
, inst
) : src0_type
;
1319 unsigned src0_type_size
= brw_reg_type_to_size(src0_type
);
1320 unsigned src1_type_size
= brw_reg_type_to_size(src1_type
);
1322 ERROR_IF(brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
&&
1323 dst_type_size
== 8 &&
1324 (src0_type_size
!= 8 || src1_type_size
!= 8) &&
1325 brw_inst_exec_size(devinfo
, inst
) > BRW_EXECUTE_2
,
1326 "In Align16 exec size cannot exceed 2 with a QWord destination "
1327 "and a non-QWord source");
1330 /* The PRMs say that for CHV, BXT:
1332 * When source or destination datatype is 64b or operation is integer
1333 * DWord multiply, DepCtrl must not be used.
1335 * We assume that the restriction applies to GLK as well.
1337 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1338 ERROR_IF(brw_inst_no_dd_check(devinfo
, inst
) ||
1339 brw_inst_no_dd_clear(devinfo
, inst
),
1340 "DepCtrl is not allowed when the execution type is 64-bit");
1347 brw_validate_instructions(const struct gen_device_info
*devinfo
,
1348 const void *assembly
, int start_offset
, int end_offset
,
1349 struct disasm_info
*disasm
)
1353 for (int src_offset
= start_offset
; src_offset
< end_offset
;) {
1354 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1355 const brw_inst
*inst
= assembly
+ src_offset
;
1356 bool is_compact
= brw_inst_cmpt_control(devinfo
, inst
);
1357 brw_inst uncompacted
;
1360 brw_compact_inst
*compacted
= (void *)inst
;
1361 brw_uncompact_instruction(devinfo
, &uncompacted
, compacted
);
1362 inst
= &uncompacted
;
1365 if (is_unsupported_inst(devinfo
, inst
)) {
1366 ERROR("Instruction not supported on this Gen");
1368 CHECK(sources_not_null
);
1369 CHECK(send_restrictions
);
1370 CHECK(general_restrictions_based_on_operand_types
);
1371 CHECK(general_restrictions_on_region_parameters
);
1372 CHECK(region_alignment_rules
);
1373 CHECK(vector_immediate_restrictions
);
1374 CHECK(special_requirements_for_handling_double_precision_data_types
);
1377 if (error_msg
.str
&& disasm
) {
1378 disasm_insert_error(disasm
, src_offset
, error_msg
.str
);
1380 valid
= valid
&& error_msg
.len
== 0;
1381 free(error_msg
.str
);
1384 src_offset
+= sizeof(brw_compact_inst
);
1386 src_offset
+= sizeof(brw_inst
);