2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_validate.c
26 * This file implements a pass that validates shader assembly.
31 /* We're going to do lots of string concatenation, so this should help. */
38 cat(struct string
*dest
, const struct string src
)
40 dest
->str
= realloc(dest
->str
, dest
->len
+ src
.len
+ 1);
41 memcpy(dest
->str
+ dest
->len
, src
.str
, src
.len
);
42 dest
->str
[dest
->len
+ src
.len
] = '\0';
43 dest
->len
= dest
->len
+ src
.len
;
45 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
47 #define error(str) "\tERROR: " str "\n"
48 #define ERROR_INDENT "\t "
50 #define ERROR(msg) ERROR_IF(true, msg)
51 #define ERROR_IF(cond, msg) \
54 CAT(error_msg, error(msg)); \
58 #define CHECK(func, args...) \
60 struct string __msg = func(devinfo, inst, ##args); \
62 cat(&error_msg, __msg); \
68 inst_is_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
70 switch (brw_inst_opcode(devinfo
, inst
)) {
72 case BRW_OPCODE_SENDC
:
73 case BRW_OPCODE_SENDS
:
74 case BRW_OPCODE_SENDSC
:
82 signed_type(unsigned type
)
85 case BRW_REGISTER_TYPE_UD
: return BRW_REGISTER_TYPE_D
;
86 case BRW_REGISTER_TYPE_UW
: return BRW_REGISTER_TYPE_W
;
87 case BRW_REGISTER_TYPE_UB
: return BRW_REGISTER_TYPE_B
;
88 case BRW_REGISTER_TYPE_UQ
: return BRW_REGISTER_TYPE_Q
;
94 inst_is_raw_move(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
96 unsigned dst_type
= signed_type(brw_inst_dst_type(devinfo
, inst
));
97 unsigned src_type
= signed_type(brw_inst_src0_type(devinfo
, inst
));
99 if (brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
) {
100 /* FIXME: not strictly true */
101 if (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_VF
||
102 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UV
||
103 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_V
) {
106 } else if (brw_inst_src0_negate(devinfo
, inst
) ||
107 brw_inst_src0_abs(devinfo
, inst
)) {
111 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MOV
&&
112 brw_inst_saturate(devinfo
, inst
) == 0 &&
113 dst_type
== src_type
;
117 dst_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
119 return brw_inst_dst_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
120 brw_inst_dst_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
124 src0_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
126 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
127 brw_inst_src0_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
131 src1_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
133 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
134 brw_inst_src1_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
138 src0_is_grf(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
140 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
;
144 src0_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
146 return brw_inst_src0_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
147 brw_inst_src0_width(devinfo
, inst
) == BRW_WIDTH_1
&&
148 brw_inst_src0_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
152 src1_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
154 return brw_inst_src1_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
155 brw_inst_src1_width(devinfo
, inst
) == BRW_WIDTH_1
&&
156 brw_inst_src1_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
160 num_sources_from_inst(const struct gen_device_info
*devinfo
,
161 const brw_inst
*inst
)
163 const struct opcode_desc
*desc
=
164 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
165 unsigned math_function
;
167 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
168 math_function
= brw_inst_math_function(devinfo
, inst
);
169 } else if (devinfo
->gen
< 6 &&
170 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
171 if (brw_inst_sfid(devinfo
, inst
) == BRW_SFID_MATH
) {
172 /* src1 must be a descriptor (including the information to determine
173 * that the SEND is doing an extended math operation), but src0 can
174 * actually be null since it serves as the source of the implicit GRF
177 * If we stop using that functionality, we'll have to revisit this.
181 /* Send instructions are allowed to have null sources since they use
182 * the base_mrf field to specify which message register source.
187 assert(desc
->nsrc
< 4);
191 switch (math_function
) {
192 case BRW_MATH_FUNCTION_INV
:
193 case BRW_MATH_FUNCTION_LOG
:
194 case BRW_MATH_FUNCTION_EXP
:
195 case BRW_MATH_FUNCTION_SQRT
:
196 case BRW_MATH_FUNCTION_RSQ
:
197 case BRW_MATH_FUNCTION_SIN
:
198 case BRW_MATH_FUNCTION_COS
:
199 case BRW_MATH_FUNCTION_SINCOS
:
200 case GEN8_MATH_FUNCTION_INVM
:
201 case GEN8_MATH_FUNCTION_RSQRTM
:
203 case BRW_MATH_FUNCTION_FDIV
:
204 case BRW_MATH_FUNCTION_POW
:
205 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
206 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
207 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
210 unreachable("not reached");
215 sources_not_null(const struct gen_device_info
*devinfo
,
216 const brw_inst
*inst
)
218 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
219 struct string error_msg
= { .str
= NULL
, .len
= 0 };
221 /* Nothing to test. 3-src instructions can only have GRF sources, and
222 * there's no bit to control the file.
224 if (num_sources
== 3)
225 return (struct string
){};
227 if (num_sources
>= 1)
228 ERROR_IF(src0_is_null(devinfo
, inst
), "src0 is null");
230 if (num_sources
== 2)
231 ERROR_IF(src1_is_null(devinfo
, inst
), "src1 is null");
237 send_restrictions(const struct gen_device_info
*devinfo
,
238 const brw_inst
*inst
)
240 struct string error_msg
= { .str
= NULL
, .len
= 0 };
242 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
243 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
,
244 "send must use direct addressing");
246 if (devinfo
->gen
>= 7) {
247 ERROR_IF(!src0_is_grf(devinfo
, inst
), "send from non-GRF");
248 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
249 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
250 "send with EOT must use g112-g127");
258 is_unsupported_inst(const struct gen_device_info
*devinfo
,
259 const brw_inst
*inst
)
261 return brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
)) == NULL
;
264 static enum brw_reg_type
265 execution_type_for_type(enum brw_reg_type type
)
268 case BRW_REGISTER_TYPE_DF
:
269 case BRW_REGISTER_TYPE_F
:
270 case BRW_REGISTER_TYPE_HF
:
273 case BRW_REGISTER_TYPE_VF
:
274 return BRW_REGISTER_TYPE_F
;
276 case BRW_REGISTER_TYPE_Q
:
277 case BRW_REGISTER_TYPE_UQ
:
278 return BRW_REGISTER_TYPE_Q
;
280 case BRW_REGISTER_TYPE_D
:
281 case BRW_REGISTER_TYPE_UD
:
282 return BRW_REGISTER_TYPE_D
;
284 case BRW_REGISTER_TYPE_W
:
285 case BRW_REGISTER_TYPE_UW
:
286 case BRW_REGISTER_TYPE_B
:
287 case BRW_REGISTER_TYPE_UB
:
288 case BRW_REGISTER_TYPE_V
:
289 case BRW_REGISTER_TYPE_UV
:
290 return BRW_REGISTER_TYPE_W
;
292 unreachable("not reached");
296 * Returns the execution type of an instruction \p inst
298 static enum brw_reg_type
299 execution_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
301 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
302 enum brw_reg_type src0_exec_type
, src1_exec_type
;
304 /* Execution data type is independent of destination data type, except in
305 * mixed F/HF instructions on CHV and SKL+.
307 enum brw_reg_type dst_exec_type
= brw_inst_dst_type(devinfo
, inst
);
309 src0_exec_type
= execution_type_for_type(brw_inst_src0_type(devinfo
, inst
));
310 if (num_sources
== 1) {
311 if ((devinfo
->gen
>= 9 || devinfo
->is_cherryview
) &&
312 src0_exec_type
== BRW_REGISTER_TYPE_HF
) {
313 return dst_exec_type
;
315 return src0_exec_type
;
318 src1_exec_type
= execution_type_for_type(brw_inst_src1_type(devinfo
, inst
));
319 if (src0_exec_type
== src1_exec_type
)
320 return src0_exec_type
;
322 /* Mixed operand types where one is float is float on Gen < 6
323 * (and not allowed on later platforms)
325 if (devinfo
->gen
< 6 &&
326 (src0_exec_type
== BRW_REGISTER_TYPE_F
||
327 src1_exec_type
== BRW_REGISTER_TYPE_F
))
328 return BRW_REGISTER_TYPE_F
;
330 if (src0_exec_type
== BRW_REGISTER_TYPE_Q
||
331 src1_exec_type
== BRW_REGISTER_TYPE_Q
)
332 return BRW_REGISTER_TYPE_Q
;
334 if (src0_exec_type
== BRW_REGISTER_TYPE_D
||
335 src1_exec_type
== BRW_REGISTER_TYPE_D
)
336 return BRW_REGISTER_TYPE_D
;
338 if (src0_exec_type
== BRW_REGISTER_TYPE_W
||
339 src1_exec_type
== BRW_REGISTER_TYPE_W
)
340 return BRW_REGISTER_TYPE_W
;
342 if (src0_exec_type
== BRW_REGISTER_TYPE_DF
||
343 src1_exec_type
== BRW_REGISTER_TYPE_DF
)
344 return BRW_REGISTER_TYPE_DF
;
346 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
347 if (dst_exec_type
== BRW_REGISTER_TYPE_F
||
348 src0_exec_type
== BRW_REGISTER_TYPE_F
||
349 src1_exec_type
== BRW_REGISTER_TYPE_F
) {
350 return BRW_REGISTER_TYPE_F
;
352 return BRW_REGISTER_TYPE_HF
;
356 assert(src0_exec_type
== BRW_REGISTER_TYPE_F
);
357 return BRW_REGISTER_TYPE_F
;
361 * Returns whether a region is packed
363 * A region is packed if its elements are adjacent in memory, with no
364 * intervening space, no overlap, and no replicated values.
367 is_packed(unsigned vstride
, unsigned width
, unsigned hstride
)
369 if (vstride
== width
) {
381 * Checks restrictions listed in "General Restrictions Based on Operand Types"
382 * in the "Register Region Restrictions" section.
385 general_restrictions_based_on_operand_types(const struct gen_device_info
*devinfo
,
386 const brw_inst
*inst
)
388 const struct opcode_desc
*desc
=
389 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
390 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
391 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
392 struct string error_msg
= { .str
= NULL
, .len
= 0 };
394 if (num_sources
== 3)
395 return (struct string
){};
397 if (inst_is_send(devinfo
, inst
))
398 return (struct string
){};
401 return (struct string
){};
404 return (struct string
){};
408 * Where n is the largest element size in bytes for any source or
409 * destination operand type, ExecSize * n must be <= 64.
411 * But we do not attempt to enforce it, because it is implied by other
414 * - that the destination stride must match the execution data type
415 * - sources may not span more than two adjacent GRF registers
416 * - destination may not span more than two adjacent GRF registers
418 * In fact, checking it would weaken testing of the other rules.
421 unsigned dst_stride
= 1 << (brw_inst_dst_hstride(devinfo
, inst
) - 1);
422 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
423 bool dst_type_is_byte
=
424 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_B
||
425 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UB
;
427 if (dst_type_is_byte
) {
428 if (is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
)) {
429 if (!inst_is_raw_move(devinfo
, inst
)) {
430 ERROR("Only raw MOV supports a packed-byte destination");
433 return (struct string
){};
438 unsigned exec_type
= execution_type(devinfo
, inst
);
439 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
440 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
442 /* On IVB/BYT, region parameters and execution size for DF are in terms of
443 * 32-bit elements, so they are doubled. For evaluating the validity of an
444 * instruction, we halve them.
446 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
447 exec_type_size
== 8 && dst_type_size
== 4)
450 if (exec_type_size
> dst_type_size
) {
451 ERROR_IF(dst_stride
* dst_type_size
!= exec_type_size
,
452 "Destination stride must be equal to the ratio of the sizes of "
453 "the execution data type to the destination type");
455 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
457 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
458 brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
) {
459 /* The i965 PRM says:
461 * Implementation Restriction: The relaxed alignment rule for byte
462 * destination (#10.5) is not supported.
464 if ((devinfo
->gen
> 4 || devinfo
->is_g4x
) && dst_type_is_byte
) {
465 ERROR_IF(subreg
% exec_type_size
!= 0 &&
466 subreg
% exec_type_size
!= 1,
467 "Destination subreg must be aligned to the size of the "
468 "execution data type (or to the next lowest byte for byte "
471 ERROR_IF(subreg
% exec_type_size
!= 0,
472 "Destination subreg must be aligned to the size of the "
473 "execution data type");
482 * Checks restrictions listed in "General Restrictions on Regioning Parameters"
483 * in the "Register Region Restrictions" section.
486 general_restrictions_on_region_parameters(const struct gen_device_info
*devinfo
,
487 const brw_inst
*inst
)
489 const struct opcode_desc
*desc
=
490 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
491 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
492 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
493 struct string error_msg
= { .str
= NULL
, .len
= 0 };
495 if (num_sources
== 3)
496 return (struct string
){};
498 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
) {
499 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
))
500 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) != BRW_HORIZONTAL_STRIDE_1
,
501 "Destination Horizontal Stride must be 1");
503 if (num_sources
>= 1) {
504 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
505 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
506 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
507 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
508 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
509 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
511 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
512 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
513 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
514 "In Align16 mode, only VertStride of 0 or 4 is allowed");
518 if (num_sources
== 2) {
519 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
520 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
521 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
522 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
523 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
524 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
526 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
527 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
528 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
529 "In Align16 mode, only VertStride of 0 or 4 is allowed");
536 for (unsigned i
= 0; i
< num_sources
; i
++) {
537 unsigned vstride
, width
, hstride
, element_size
, subreg
;
538 enum brw_reg_type type
;
541 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
542 BRW_IMMEDIATE_VALUE) \
545 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
546 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
547 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
548 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
549 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
550 type = brw_inst_src ## n ## _type(devinfo, inst); \
551 element_size = brw_reg_type_to_size(type); \
552 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
561 /* On IVB/BYT, region parameters and execution size for DF are in terms of
562 * 32-bit elements, so they are doubled. For evaluating the validity of an
563 * instruction, we halve them.
565 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
569 /* ExecSize must be greater than or equal to Width. */
570 ERROR_IF(exec_size
< width
, "ExecSize must be greater than or equal "
573 /* If ExecSize = Width and HorzStride ≠ 0,
574 * VertStride must be set to Width * HorzStride.
576 if (exec_size
== width
&& hstride
!= 0) {
577 ERROR_IF(vstride
!= width
* hstride
,
578 "If ExecSize = Width and HorzStride ≠ 0, "
579 "VertStride must be set to Width * HorzStride");
582 /* If Width = 1, HorzStride must be 0 regardless of the values of
583 * ExecSize and VertStride.
586 ERROR_IF(hstride
!= 0,
587 "If Width = 1, HorzStride must be 0 regardless "
588 "of the values of ExecSize and VertStride");
591 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
592 if (exec_size
== 1 && width
== 1) {
593 ERROR_IF(vstride
!= 0 || hstride
!= 0,
594 "If ExecSize = Width = 1, both VertStride "
595 "and HorzStride must be 0");
598 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the
601 if (vstride
== 0 && hstride
== 0) {
603 "If VertStride = HorzStride = 0, Width must be "
604 "1 regardless of the value of ExecSize");
607 /* VertStride must be used to cross GRF register boundaries. This rule
608 * implies that elements within a 'Width' cannot cross GRF boundaries.
610 const uint64_t mask
= (1ULL << element_size
) - 1;
611 unsigned rowbase
= subreg
;
613 for (int y
= 0; y
< exec_size
/ width
; y
++) {
614 uint64_t access_mask
= 0;
615 unsigned offset
= rowbase
;
617 for (int x
= 0; x
< width
; x
++) {
618 access_mask
|= mask
<< offset
;
619 offset
+= hstride
* element_size
;
622 rowbase
+= vstride
* element_size
;
624 if ((uint32_t)access_mask
!= 0 && (access_mask
>> 32) != 0) {
625 ERROR("VertStride must be used to cross GRF register boundaries");
631 /* Dst.HorzStride must not be 0. */
632 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
)) {
633 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
,
634 "Destination Horizontal Stride must not be 0");
641 * Creates an \p access_mask for an \p exec_size, \p element_size, and a region
643 * An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
644 * a bitmask of bytes accessed by the region.
646 * For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
647 * instruction would be
649 * access_mask[0] = 0x00000000000000F0
650 * access_mask[1] = 0x000000000000F000
651 * access_mask[2] = 0x0000000000F00000
652 * access_mask[3] = 0x00000000F0000000
653 * access_mask[4-31] = 0
655 * because the first execution channel accesses bytes 7-4 and the second
656 * execution channel accesses bytes 15-12, etc.
659 align1_access_mask(uint64_t access_mask
[static 32],
660 unsigned exec_size
, unsigned element_size
, unsigned subreg
,
661 unsigned vstride
, unsigned width
, unsigned hstride
)
663 const uint64_t mask
= (1ULL << element_size
) - 1;
664 unsigned rowbase
= subreg
;
665 unsigned element
= 0;
667 for (int y
= 0; y
< exec_size
/ width
; y
++) {
668 unsigned offset
= rowbase
;
670 for (int x
= 0; x
< width
; x
++) {
671 access_mask
[element
++] = mask
<< offset
;
672 offset
+= hstride
* element_size
;
675 rowbase
+= vstride
* element_size
;
678 assert(element
== 0 || element
== exec_size
);
682 * Returns the number of registers accessed according to the \p access_mask
685 registers_read(const uint64_t access_mask
[static 32])
689 for (unsigned i
= 0; i
< 32; i
++) {
690 if (access_mask
[i
] > 0xFFFFFFFF) {
692 } else if (access_mask
[i
]) {
701 * Checks restrictions listed in "Region Alignment Rules" in the "Register
702 * Region Restrictions" section.
705 region_alignment_rules(const struct gen_device_info
*devinfo
,
706 const brw_inst
*inst
)
708 const struct opcode_desc
*desc
=
709 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
710 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
711 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
712 uint64_t dst_access_mask
[32], src0_access_mask
[32], src1_access_mask
[32];
713 struct string error_msg
= { .str
= NULL
, .len
= 0 };
715 if (num_sources
== 3)
716 return (struct string
){};
718 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
)
719 return (struct string
){};
721 if (inst_is_send(devinfo
, inst
))
722 return (struct string
){};
724 memset(dst_access_mask
, 0, sizeof(dst_access_mask
));
725 memset(src0_access_mask
, 0, sizeof(src0_access_mask
));
726 memset(src1_access_mask
, 0, sizeof(src1_access_mask
));
728 for (unsigned i
= 0; i
< num_sources
; i
++) {
729 unsigned vstride
, width
, hstride
, element_size
, subreg
;
730 enum brw_reg_type type
;
732 /* In Direct Addressing mode, a source cannot span more than 2 adjacent
737 if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
738 BRW_ADDRESS_DIRECT) \
741 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
742 BRW_IMMEDIATE_VALUE) \
745 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
746 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
747 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
748 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
749 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
750 type = brw_inst_src ## n ## _type(devinfo, inst); \
751 element_size = brw_reg_type_to_size(type); \
752 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
753 align1_access_mask(src ## n ## _access_mask, \
754 exec_size, element_size, subreg, \
755 vstride, width, hstride)
764 unsigned num_vstride
= exec_size
/ width
;
765 unsigned num_hstride
= width
;
766 unsigned vstride_elements
= (num_vstride
- 1) * vstride
;
767 unsigned hstride_elements
= (num_hstride
- 1) * hstride
;
768 unsigned offset
= (vstride_elements
+ hstride_elements
) * element_size
+
770 ERROR_IF(offset
>= 64,
771 "A source cannot span more than 2 adjacent GRF registers");
774 if (desc
->ndst
== 0 || dst_is_null(devinfo
, inst
))
777 unsigned stride
= 1 << (brw_inst_dst_hstride(devinfo
, inst
) - 1);
778 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
779 unsigned element_size
= brw_reg_type_to_size(dst_type
);
780 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
781 unsigned offset
= ((exec_size
- 1) * stride
* element_size
) + subreg
;
782 ERROR_IF(offset
>= 64,
783 "A destination cannot span more than 2 adjacent GRF registers");
788 /* On IVB/BYT, region parameters and execution size for DF are in terms of
789 * 32-bit elements, so they are doubled. For evaluating the validity of an
790 * instruction, we halve them.
792 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
796 align1_access_mask(dst_access_mask
, exec_size
, element_size
, subreg
,
797 exec_size
== 1 ? 0 : exec_size
* stride
,
798 exec_size
== 1 ? 1 : exec_size
,
799 exec_size
== 1 ? 0 : stride
);
801 unsigned dst_regs
= registers_read(dst_access_mask
);
802 unsigned src0_regs
= registers_read(src0_access_mask
);
803 unsigned src1_regs
= registers_read(src1_access_mask
);
805 /* The SNB, IVB, HSW, BDW, and CHV PRMs say:
807 * When an instruction has a source region spanning two registers and a
808 * destination region contained in one register, the number of elements
809 * must be the same between two sources and one of the following must be
812 * 1. The destination region is entirely contained in the lower OWord
814 * 2. The destination region is entirely contained in the upper OWord
816 * 3. The destination elements are evenly split between the two OWords
819 if (devinfo
->gen
<= 8) {
820 if (dst_regs
== 1 && (src0_regs
== 2 || src1_regs
== 2)) {
821 unsigned upper_oword_writes
= 0, lower_oword_writes
= 0;
823 for (unsigned i
= 0; i
< exec_size
; i
++) {
824 if (dst_access_mask
[i
] > 0x0000FFFF) {
825 upper_oword_writes
++;
827 assert(dst_access_mask
[i
] != 0);
828 lower_oword_writes
++;
832 ERROR_IF(lower_oword_writes
!= 0 &&
833 upper_oword_writes
!= 0 &&
834 upper_oword_writes
!= lower_oword_writes
,
835 "Writes must be to only one OWord or "
836 "evenly split between OWords");
840 /* The IVB and HSW PRMs say:
842 * When an instruction has a source region that spans two registers and
843 * the destination spans two registers, the destination elements must be
844 * evenly split between the two registers [...]
846 * The SNB PRM contains similar wording (but written in a much more
851 * When destination spans two registers, the source may be one or two
852 * registers. The destination elements must be evenly split between the
857 * When destination of MATH instruction spans two registers, the
858 * destination elements must be evenly split between the two registers.
860 * It is not known whether this restriction applies to KBL other Gens after
863 if (devinfo
->gen
<= 8 ||
864 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
866 /* Nothing explicitly states that on Gen < 8 elements must be evenly
867 * split between two destination registers in the two exceptional
868 * source-region-spans-one-register cases, but since Broadwell requires
869 * evenly split writes regardless of source region, we assume that it was
870 * an oversight and require it.
873 unsigned upper_reg_writes
= 0, lower_reg_writes
= 0;
875 for (unsigned i
= 0; i
< exec_size
; i
++) {
876 if (dst_access_mask
[i
] > 0xFFFFFFFF) {
879 assert(dst_access_mask
[i
] != 0);
884 ERROR_IF(upper_reg_writes
!= lower_reg_writes
,
885 "Writes must be evenly split between the two "
886 "destination registers");
890 /* The IVB and HSW PRMs say:
892 * When an instruction has a source region that spans two registers and
893 * the destination spans two registers, the destination elements must be
894 * evenly split between the two registers and each destination register
895 * must be entirely derived from one source register.
897 * Note: In such cases, the regioning parameters must ensure that the
898 * offset from the two source registers is the same.
900 * The SNB PRM contains similar wording (but written in a much more
903 * There are effectively three rules stated here:
905 * For an instruction with a source and a destination spanning two
908 * (1) destination elements must be evenly split between the two
910 * (2) all destination elements in a register must be derived
911 * from one source register
912 * (3) the offset (i.e. the starting location in each of the two
913 * registers spanned by a region) must be the same in the two
914 * registers spanned by a region
916 * It is impossible to violate rule (1) without violating (2) or (3), so we
917 * do not attempt to validate it.
919 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
920 for (unsigned i
= 0; i
< num_sources
; i
++) {
922 if (src ## n ## _regs <= 1) \
925 for (unsigned i = 0; i < exec_size; i++) { \
926 if ((dst_access_mask[i] > 0xFFFFFFFF) != \
927 (src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
928 ERROR("Each destination register must be entirely derived " \
929 "from one source register"); \
934 unsigned offset_0 = \
935 brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
936 unsigned offset_1 = offset_0; \
938 for (unsigned i = 0; i < exec_size; i++) { \
939 if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
940 offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
945 ERROR_IF(offset_0 != offset_1, \
946 "The offset from the two source registers " \
958 /* The IVB and HSW PRMs say:
960 * When destination spans two registers, the source MUST span two
961 * registers. The exception to the above rule:
962 * 1. When source is scalar, the source registers are not
964 * 2. When source is packed integer Word and destination is packed
965 * integer DWord, the source register is not incremented by the
966 * source sub register is incremented.
968 * The SNB PRM does not contain this rule, but the internal documentation
969 * indicates that it applies to SNB as well. We assume that the rule applies
970 * to Gen <= 5 although their PRMs do not state it.
972 * While the documentation explicitly says in exception (2) that the
973 * destination must be an integer DWord, the hardware allows at least a
974 * float destination type as well. We emit such instructions from
976 * fs_visitor::emit_interpolation_setup_gen6
977 * fs_visitor::emit_fragcoord_interpolation
979 * and have for years with no ill effects.
981 * Additionally the simulator source code indicates that the real condition
982 * is that the size of the destination type is 4 bytes.
984 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
985 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
986 bool dst_is_packed_dword
=
987 is_packed(exec_size
* stride
, exec_size
, stride
) &&
988 brw_reg_type_to_size(dst_type
) == 4;
990 for (unsigned i
= 0; i
< num_sources
; i
++) {
992 unsigned vstride, width, hstride; \
993 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
994 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
995 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
996 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
997 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
998 bool src ## n ## _is_packed_word = \
999 is_packed(vstride, width, hstride) && \
1000 (brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_W || \
1001 brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_UW); \
1003 ERROR_IF(src ## n ## _regs == 1 && \
1004 !src ## n ## _has_scalar_region(devinfo, inst) && \
1005 !(dst_is_packed_dword && src ## n ## _is_packed_word), \
1006 "When the destination spans two registers, the source must " \
1007 "span two registers\n" ERROR_INDENT "(exceptions for scalar " \
1008 "source and packed-word to packed-dword expansion)")
1022 static struct string
1023 vector_immediate_restrictions(const struct gen_device_info
*devinfo
,
1024 const brw_inst
*inst
)
1026 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1027 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1029 if (num_sources
== 3 || num_sources
== 0)
1030 return (struct string
){};
1032 unsigned file
= num_sources
== 1 ?
1033 brw_inst_src0_reg_file(devinfo
, inst
) :
1034 brw_inst_src1_reg_file(devinfo
, inst
);
1035 if (file
!= BRW_IMMEDIATE_VALUE
)
1036 return (struct string
){};
1038 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1039 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1040 unsigned dst_subreg
= brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
?
1041 brw_inst_dst_da1_subreg_nr(devinfo
, inst
) : 0;
1042 unsigned dst_stride
= 1 << (brw_inst_dst_hstride(devinfo
, inst
) - 1);
1043 enum brw_reg_type type
= num_sources
== 1 ?
1044 brw_inst_src0_type(devinfo
, inst
) :
1045 brw_inst_src1_type(devinfo
, inst
);
1049 * When an immediate vector is used in an instruction, the destination
1050 * must be 128-bit aligned with destination horizontal stride equivalent
1051 * to a word for an immediate integer vector (v) and equivalent to a
1052 * DWord for an immediate float vector (vf).
1054 * The text has not been updated for the addition of the immediate unsigned
1055 * integer vector type (uv) on SNB, but presumably the same restriction
1059 case BRW_REGISTER_TYPE_V
:
1060 case BRW_REGISTER_TYPE_UV
:
1061 case BRW_REGISTER_TYPE_VF
:
1062 ERROR_IF(dst_subreg
% (128 / 8) != 0,
1063 "Destination must be 128-bit aligned in order to use immediate "
1066 if (type
== BRW_REGISTER_TYPE_VF
) {
1067 ERROR_IF(dst_type_size
* dst_stride
!= 4,
1068 "Destination must have stride equivalent to dword in order "
1069 "to use the VF type");
1071 ERROR_IF(dst_type_size
* dst_stride
!= 2,
1072 "Destination must have stride equivalent to word in order "
1073 "to use the V or UV type");
1084 brw_validate_instructions(const struct gen_device_info
*devinfo
,
1085 void *assembly
, int start_offset
, int end_offset
,
1086 struct annotation_info
*annotation
)
1090 for (int src_offset
= start_offset
; src_offset
< end_offset
;) {
1091 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1092 const brw_inst
*inst
= assembly
+ src_offset
;
1093 bool is_compact
= brw_inst_cmpt_control(devinfo
, inst
);
1094 brw_inst uncompacted
;
1097 brw_compact_inst
*compacted
= (void *)inst
;
1098 brw_uncompact_instruction(devinfo
, &uncompacted
, compacted
);
1099 inst
= &uncompacted
;
1102 if (is_unsupported_inst(devinfo
, inst
)) {
1103 ERROR("Instruction not supported on this Gen");
1105 CHECK(sources_not_null
);
1106 CHECK(send_restrictions
);
1107 CHECK(general_restrictions_based_on_operand_types
);
1108 CHECK(general_restrictions_on_region_parameters
);
1109 CHECK(region_alignment_rules
);
1110 CHECK(vector_immediate_restrictions
);
1113 if (error_msg
.str
&& annotation
) {
1114 annotation_insert_error(annotation
, src_offset
, error_msg
.str
);
1116 valid
= valid
&& error_msg
.len
== 0;
1117 free(error_msg
.str
);
1120 src_offset
+= sizeof(brw_compact_inst
);
1122 src_offset
+= sizeof(brw_inst
);