2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_validate.c
26 * This file implements a pass that validates shader assembly.
31 /* We're going to do lots of string concatenation, so this should help. */
38 cat(struct string
*dest
, const struct string src
)
40 dest
->str
= realloc(dest
->str
, dest
->len
+ src
.len
+ 1);
41 memcpy(dest
->str
+ dest
->len
, src
.str
, src
.len
);
42 dest
->str
[dest
->len
+ src
.len
] = '\0';
43 dest
->len
= dest
->len
+ src
.len
;
45 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
47 #define error(str) "\tERROR: " str "\n"
48 #define ERROR_INDENT "\t "
50 #define ERROR(msg) ERROR_IF(true, msg)
51 #define ERROR_IF(cond, msg) \
54 CAT(error_msg, error(msg)); \
58 #define CHECK(func, args...) \
60 struct string __msg = func(devinfo, inst, ##args); \
62 cat(&error_msg, __msg); \
68 inst_is_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
70 switch (brw_inst_opcode(devinfo
, inst
)) {
72 case BRW_OPCODE_SENDC
:
73 case BRW_OPCODE_SENDS
:
74 case BRW_OPCODE_SENDSC
:
82 signed_type(unsigned type
)
85 case BRW_HW_REG_TYPE_UD
: return BRW_HW_REG_TYPE_D
;
86 case BRW_HW_REG_TYPE_UW
: return BRW_HW_REG_TYPE_W
;
87 case BRW_HW_REG_TYPE_UB
: return BRW_HW_REG_TYPE_B
;
88 case GEN8_HW_REG_TYPE_UQ
: return GEN8_HW_REG_TYPE_Q
;
94 inst_is_raw_move(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
96 unsigned dst_type
= signed_type(brw_inst_dst_reg_type(devinfo
, inst
));
97 unsigned src_type
= signed_type(brw_inst_src0_reg_type(devinfo
, inst
));
99 if (brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
) {
100 /* FIXME: not strictly true */
101 if (brw_inst_src0_reg_type(devinfo
, inst
) == BRW_HW_IMM_TYPE_VF
||
102 brw_inst_src0_reg_type(devinfo
, inst
) == BRW_HW_IMM_TYPE_UV
||
103 brw_inst_src0_reg_type(devinfo
, inst
) == BRW_HW_IMM_TYPE_V
) {
106 } else if (brw_inst_src0_negate(devinfo
, inst
) ||
107 brw_inst_src0_abs(devinfo
, inst
)) {
111 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MOV
&&
112 brw_inst_saturate(devinfo
, inst
) == 0 &&
113 dst_type
== src_type
;
117 dst_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
119 return brw_inst_dst_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
120 brw_inst_dst_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
124 src0_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
126 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
127 brw_inst_src0_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
131 src1_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
133 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
134 brw_inst_src1_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
138 src0_is_grf(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
140 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
;
144 src0_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
146 return brw_inst_src0_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
147 brw_inst_src0_width(devinfo
, inst
) == BRW_WIDTH_1
&&
148 brw_inst_src0_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
152 src1_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
154 return brw_inst_src1_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
155 brw_inst_src1_width(devinfo
, inst
) == BRW_WIDTH_1
&&
156 brw_inst_src1_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
160 num_sources_from_inst(const struct gen_device_info
*devinfo
,
161 const brw_inst
*inst
)
163 const struct opcode_desc
*desc
=
164 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
165 unsigned math_function
;
167 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
168 math_function
= brw_inst_math_function(devinfo
, inst
);
169 } else if (devinfo
->gen
< 6 &&
170 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
171 if (brw_inst_sfid(devinfo
, inst
) == BRW_SFID_MATH
) {
172 /* src1 must be a descriptor (including the information to determine
173 * that the SEND is doing an extended math operation), but src0 can
174 * actually be null since it serves as the source of the implicit GRF
177 * If we stop using that functionality, we'll have to revisit this.
181 /* Send instructions are allowed to have null sources since they use
182 * the base_mrf field to specify which message register source.
187 assert(desc
->nsrc
< 4);
191 switch (math_function
) {
192 case BRW_MATH_FUNCTION_INV
:
193 case BRW_MATH_FUNCTION_LOG
:
194 case BRW_MATH_FUNCTION_EXP
:
195 case BRW_MATH_FUNCTION_SQRT
:
196 case BRW_MATH_FUNCTION_RSQ
:
197 case BRW_MATH_FUNCTION_SIN
:
198 case BRW_MATH_FUNCTION_COS
:
199 case BRW_MATH_FUNCTION_SINCOS
:
200 case GEN8_MATH_FUNCTION_INVM
:
201 case GEN8_MATH_FUNCTION_RSQRTM
:
203 case BRW_MATH_FUNCTION_FDIV
:
204 case BRW_MATH_FUNCTION_POW
:
205 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
206 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
207 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
210 unreachable("not reached");
215 sources_not_null(const struct gen_device_info
*devinfo
,
216 const brw_inst
*inst
)
218 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
219 struct string error_msg
= { .str
= NULL
, .len
= 0 };
221 /* Nothing to test. 3-src instructions can only have GRF sources, and
222 * there's no bit to control the file.
224 if (num_sources
== 3)
225 return (struct string
){};
227 if (num_sources
>= 1)
228 ERROR_IF(src0_is_null(devinfo
, inst
), "src0 is null");
230 if (num_sources
== 2)
231 ERROR_IF(src1_is_null(devinfo
, inst
), "src1 is null");
237 send_restrictions(const struct gen_device_info
*devinfo
,
238 const brw_inst
*inst
)
240 struct string error_msg
= { .str
= NULL
, .len
= 0 };
242 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
243 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
,
244 "send must use direct addressing");
246 if (devinfo
->gen
>= 7) {
247 ERROR_IF(!src0_is_grf(devinfo
, inst
), "send from non-GRF");
248 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
249 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
250 "send with EOT must use g112-g127");
258 is_unsupported_inst(const struct gen_device_info
*devinfo
,
259 const brw_inst
*inst
)
261 return brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
)) == NULL
;
265 execution_type_for_type(unsigned type
, bool is_immediate
)
267 /* The meaning of the type bits is dependent on whether the operand is an
268 * immediate, so normalize them first.
272 case BRW_HW_IMM_TYPE_UV
:
273 case BRW_HW_IMM_TYPE_V
:
274 type
= BRW_HW_REG_TYPE_W
;
276 case BRW_HW_IMM_TYPE_VF
:
277 type
= BRW_HW_REG_TYPE_F
;
279 case GEN8_HW_IMM_TYPE_DF
:
280 type
= GEN7_HW_REG_TYPE_DF
;
282 case GEN8_HW_IMM_TYPE_HF
:
283 type
= GEN8_HW_IMM_TYPE_HF
;
291 case BRW_HW_REG_TYPE_UD
:
292 case BRW_HW_REG_TYPE_D
:
293 return BRW_HW_REG_TYPE_D
;
294 case BRW_HW_REG_TYPE_UW
:
295 case BRW_HW_REG_TYPE_W
:
296 case BRW_HW_REG_TYPE_UB
:
297 case BRW_HW_REG_TYPE_B
:
298 return BRW_HW_REG_TYPE_W
;
299 case GEN8_HW_REG_TYPE_UQ
:
300 case GEN8_HW_REG_TYPE_Q
:
301 return GEN8_HW_REG_TYPE_Q
;
302 case BRW_HW_REG_TYPE_F
:
303 case GEN7_HW_REG_TYPE_DF
:
304 case GEN8_HW_REG_TYPE_HF
:
307 unreachable("not reached");
312 * Returns the execution type of an instruction \p inst
315 execution_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
317 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
318 unsigned src0_exec_type
, src1_exec_type
;
319 unsigned src0_type
= brw_inst_src0_reg_type(devinfo
, inst
);
320 unsigned src1_type
= brw_inst_src1_reg_type(devinfo
, inst
);
322 bool src0_is_immediate
=
323 brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
;
324 bool src1_is_immediate
=
325 brw_inst_src1_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
;
327 /* Execution data type is independent of destination data type, except in
328 * mixed F/HF instructions on CHV and SKL+.
330 unsigned dst_exec_type
= brw_inst_dst_reg_type(devinfo
, inst
);
332 src0_exec_type
= execution_type_for_type(src0_type
, src0_is_immediate
);
333 if (num_sources
== 1) {
334 if ((devinfo
->gen
>= 9 || devinfo
->is_cherryview
) &&
335 src0_exec_type
== GEN8_HW_REG_TYPE_HF
) {
336 return dst_exec_type
;
338 return src0_exec_type
;
341 src1_exec_type
= execution_type_for_type(src1_type
, src1_is_immediate
);
342 if (src0_exec_type
== src1_exec_type
)
343 return src0_exec_type
;
345 /* Mixed operand types where one is float is float on Gen < 6
346 * (and not allowed on later platforms)
348 if (devinfo
->gen
< 6 &&
349 (src0_exec_type
== BRW_HW_REG_TYPE_F
||
350 src1_exec_type
== BRW_HW_REG_TYPE_F
))
351 return BRW_HW_REG_TYPE_F
;
353 if (src0_exec_type
== GEN8_HW_REG_TYPE_Q
||
354 src1_exec_type
== GEN8_HW_REG_TYPE_Q
)
355 return GEN8_HW_REG_TYPE_Q
;
357 if (src0_exec_type
== BRW_HW_REG_TYPE_D
||
358 src1_exec_type
== BRW_HW_REG_TYPE_D
)
359 return BRW_HW_REG_TYPE_D
;
361 if (src0_exec_type
== BRW_HW_REG_TYPE_W
||
362 src1_exec_type
== BRW_HW_REG_TYPE_W
)
363 return BRW_HW_REG_TYPE_W
;
365 if (src0_exec_type
== GEN7_HW_REG_TYPE_DF
||
366 src1_exec_type
== GEN7_HW_REG_TYPE_DF
)
367 return GEN7_HW_REG_TYPE_DF
;
369 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
370 if (dst_exec_type
== BRW_HW_REG_TYPE_F
||
371 src0_exec_type
== BRW_HW_REG_TYPE_F
||
372 src1_exec_type
== BRW_HW_REG_TYPE_F
) {
373 return BRW_HW_REG_TYPE_F
;
375 return GEN8_HW_REG_TYPE_HF
;
379 assert(src0_exec_type
== BRW_HW_REG_TYPE_F
);
380 return BRW_HW_REG_TYPE_F
;
384 * Returns whether a region is packed
386 * A region is packed if its elements are adjacent in memory, with no
387 * intervening space, no overlap, and no replicated values.
390 is_packed(unsigned vstride
, unsigned width
, unsigned hstride
)
392 if (vstride
== width
) {
404 * Checks restrictions listed in "General Restrictions Based on Operand Types"
405 * in the "Register Region Restrictions" section.
408 general_restrictions_based_on_operand_types(const struct gen_device_info
*devinfo
,
409 const brw_inst
*inst
)
411 const struct opcode_desc
*desc
=
412 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
413 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
414 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
415 struct string error_msg
= { .str
= NULL
, .len
= 0 };
417 if (num_sources
== 3)
418 return (struct string
){};
420 if (inst_is_send(devinfo
, inst
))
421 return (struct string
){};
424 return (struct string
){};
427 return (struct string
){};
431 * Where n is the largest element size in bytes for any source or
432 * destination operand type, ExecSize * n must be <= 64.
434 * But we do not attempt to enforce it, because it is implied by other
437 * - that the destination stride must match the execution data type
438 * - sources may not span more than two adjacent GRF registers
439 * - destination may not span more than two adjacent GRF registers
441 * In fact, checking it would weaken testing of the other rules.
444 unsigned dst_stride
= 1 << (brw_inst_dst_hstride(devinfo
, inst
) - 1);
445 bool dst_type_is_byte
=
446 brw_inst_dst_reg_type(devinfo
, inst
) == BRW_HW_REG_TYPE_B
||
447 brw_inst_dst_reg_type(devinfo
, inst
) == BRW_HW_REG_TYPE_UB
;
449 if (dst_type_is_byte
) {
450 if (is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
)) {
451 if (!inst_is_raw_move(devinfo
, inst
)) {
452 ERROR("Only raw MOV supports a packed-byte destination");
455 return (struct string
){};
460 unsigned exec_type
= execution_type(devinfo
, inst
);
461 unsigned exec_type_size
=
462 brw_hw_reg_type_to_size(devinfo
, exec_type
, BRW_GENERAL_REGISTER_FILE
);
463 unsigned dst_type_size
= brw_element_size(devinfo
, inst
, dst
);
465 /* On IVB/BYT, region parameters and execution size for DF are in terms of
466 * 32-bit elements, so they are doubled. For evaluating the validity of an
467 * instruction, we halve them.
469 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
470 exec_type_size
== 8 && dst_type_size
== 4)
473 if (exec_type_size
> dst_type_size
) {
474 ERROR_IF(dst_stride
* dst_type_size
!= exec_type_size
,
475 "Destination stride must be equal to the ratio of the sizes of "
476 "the execution data type to the destination type");
478 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
480 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
481 brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
) {
482 /* The i965 PRM says:
484 * Implementation Restriction: The relaxed alignment rule for byte
485 * destination (#10.5) is not supported.
487 if ((devinfo
->gen
> 4 || devinfo
->is_g4x
) && dst_type_is_byte
) {
488 ERROR_IF(subreg
% exec_type_size
!= 0 &&
489 subreg
% exec_type_size
!= 1,
490 "Destination subreg must be aligned to the size of the "
491 "execution data type (or to the next lowest byte for byte "
494 ERROR_IF(subreg
% exec_type_size
!= 0,
495 "Destination subreg must be aligned to the size of the "
496 "execution data type");
505 * Checks restrictions listed in "General Restrictions on Regioning Parameters"
506 * in the "Register Region Restrictions" section.
509 general_restrictions_on_region_parameters(const struct gen_device_info
*devinfo
,
510 const brw_inst
*inst
)
512 const struct opcode_desc
*desc
=
513 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
514 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
515 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
516 struct string error_msg
= { .str
= NULL
, .len
= 0 };
518 if (num_sources
== 3)
519 return (struct string
){};
521 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
) {
522 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
))
523 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) != BRW_HORIZONTAL_STRIDE_1
,
524 "Destination Horizontal Stride must be 1");
526 if (num_sources
>= 1) {
527 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
528 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
529 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
530 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
531 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
532 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
534 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
535 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
536 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
537 "In Align16 mode, only VertStride of 0 or 4 is allowed");
541 if (num_sources
== 2) {
542 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
543 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
544 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
545 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
546 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
547 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
549 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
550 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
551 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
552 "In Align16 mode, only VertStride of 0 or 4 is allowed");
559 for (unsigned i
= 0; i
< num_sources
; i
++) {
560 unsigned vstride
, width
, hstride
, element_size
, subreg
;
563 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
564 BRW_IMMEDIATE_VALUE) \
567 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
568 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
569 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
570 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
571 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
572 element_size = brw_element_size(devinfo, inst, src ## n); \
573 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
582 /* On IVB/BYT, region parameters and execution size for DF are in terms of
583 * 32-bit elements, so they are doubled. For evaluating the validity of an
584 * instruction, we halve them.
586 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
590 /* ExecSize must be greater than or equal to Width. */
591 ERROR_IF(exec_size
< width
, "ExecSize must be greater than or equal "
594 /* If ExecSize = Width and HorzStride ≠ 0,
595 * VertStride must be set to Width * HorzStride.
597 if (exec_size
== width
&& hstride
!= 0) {
598 ERROR_IF(vstride
!= width
* hstride
,
599 "If ExecSize = Width and HorzStride ≠ 0, "
600 "VertStride must be set to Width * HorzStride");
603 /* If Width = 1, HorzStride must be 0 regardless of the values of
604 * ExecSize and VertStride.
607 ERROR_IF(hstride
!= 0,
608 "If Width = 1, HorzStride must be 0 regardless "
609 "of the values of ExecSize and VertStride");
612 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
613 if (exec_size
== 1 && width
== 1) {
614 ERROR_IF(vstride
!= 0 || hstride
!= 0,
615 "If ExecSize = Width = 1, both VertStride "
616 "and HorzStride must be 0");
619 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the
622 if (vstride
== 0 && hstride
== 0) {
624 "If VertStride = HorzStride = 0, Width must be "
625 "1 regardless of the value of ExecSize");
628 /* VertStride must be used to cross GRF register boundaries. This rule
629 * implies that elements within a 'Width' cannot cross GRF boundaries.
631 const uint64_t mask
= (1ULL << element_size
) - 1;
632 unsigned rowbase
= subreg
;
634 for (int y
= 0; y
< exec_size
/ width
; y
++) {
635 uint64_t access_mask
= 0;
636 unsigned offset
= rowbase
;
638 for (int x
= 0; x
< width
; x
++) {
639 access_mask
|= mask
<< offset
;
640 offset
+= hstride
* element_size
;
643 rowbase
+= vstride
* element_size
;
645 if ((uint32_t)access_mask
!= 0 && (access_mask
>> 32) != 0) {
646 ERROR("VertStride must be used to cross GRF register boundaries");
652 /* Dst.HorzStride must not be 0. */
653 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
)) {
654 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
,
655 "Destination Horizontal Stride must not be 0");
662 * Creates an \p access_mask for an \p exec_size, \p element_size, and a region
664 * An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
665 * a bitmask of bytes accessed by the region.
667 * For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
668 * instruction would be
670 * access_mask[0] = 0x00000000000000F0
671 * access_mask[1] = 0x000000000000F000
672 * access_mask[2] = 0x0000000000F00000
673 * access_mask[3] = 0x00000000F0000000
674 * access_mask[4-31] = 0
676 * because the first execution channel accesses bytes 7-4 and the second
677 * execution channel accesses bytes 15-12, etc.
680 align1_access_mask(uint64_t access_mask
[static 32],
681 unsigned exec_size
, unsigned element_size
, unsigned subreg
,
682 unsigned vstride
, unsigned width
, unsigned hstride
)
684 const uint64_t mask
= (1ULL << element_size
) - 1;
685 unsigned rowbase
= subreg
;
686 unsigned element
= 0;
688 for (int y
= 0; y
< exec_size
/ width
; y
++) {
689 unsigned offset
= rowbase
;
691 for (int x
= 0; x
< width
; x
++) {
692 access_mask
[element
++] = mask
<< offset
;
693 offset
+= hstride
* element_size
;
696 rowbase
+= vstride
* element_size
;
699 assert(element
== 0 || element
== exec_size
);
703 * Returns the number of registers accessed according to the \p access_mask
706 registers_read(const uint64_t access_mask
[static 32])
710 for (unsigned i
= 0; i
< 32; i
++) {
711 if (access_mask
[i
] > 0xFFFFFFFF) {
713 } else if (access_mask
[i
]) {
722 * Checks restrictions listed in "Region Alignment Rules" in the "Register
723 * Region Restrictions" section.
726 region_alignment_rules(const struct gen_device_info
*devinfo
,
727 const brw_inst
*inst
)
729 const struct opcode_desc
*desc
=
730 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
731 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
732 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
733 uint64_t dst_access_mask
[32], src0_access_mask
[32], src1_access_mask
[32];
734 struct string error_msg
= { .str
= NULL
, .len
= 0 };
736 if (num_sources
== 3)
737 return (struct string
){};
739 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
)
740 return (struct string
){};
742 if (inst_is_send(devinfo
, inst
))
743 return (struct string
){};
745 memset(dst_access_mask
, 0, sizeof(dst_access_mask
));
746 memset(src0_access_mask
, 0, sizeof(src0_access_mask
));
747 memset(src1_access_mask
, 0, sizeof(src1_access_mask
));
749 for (unsigned i
= 0; i
< num_sources
; i
++) {
750 unsigned vstride
, width
, hstride
, element_size
, subreg
;
752 /* In Direct Addressing mode, a source cannot span more than 2 adjacent
757 if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
758 BRW_ADDRESS_DIRECT) \
761 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
762 BRW_IMMEDIATE_VALUE) \
765 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
766 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
767 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
768 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
769 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
770 element_size = brw_element_size(devinfo, inst, src ## n); \
771 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
772 align1_access_mask(src ## n ## _access_mask, \
773 exec_size, element_size, subreg, \
774 vstride, width, hstride)
783 unsigned num_vstride
= exec_size
/ width
;
784 unsigned num_hstride
= width
;
785 unsigned vstride_elements
= (num_vstride
- 1) * vstride
;
786 unsigned hstride_elements
= (num_hstride
- 1) * hstride
;
787 unsigned offset
= (vstride_elements
+ hstride_elements
) * element_size
+
789 ERROR_IF(offset
>= 64,
790 "A source cannot span more than 2 adjacent GRF registers");
793 if (desc
->ndst
== 0 || dst_is_null(devinfo
, inst
))
796 unsigned stride
= 1 << (brw_inst_dst_hstride(devinfo
, inst
) - 1);
797 unsigned element_size
= brw_element_size(devinfo
, inst
, dst
);
798 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
799 unsigned offset
= ((exec_size
- 1) * stride
* element_size
) + subreg
;
800 ERROR_IF(offset
>= 64,
801 "A destination cannot span more than 2 adjacent GRF registers");
806 /* On IVB/BYT, region parameters and execution size for DF are in terms of
807 * 32-bit elements, so they are doubled. For evaluating the validity of an
808 * instruction, we halve them.
810 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
814 align1_access_mask(dst_access_mask
, exec_size
, element_size
, subreg
,
815 exec_size
== 1 ? 0 : exec_size
* stride
,
816 exec_size
== 1 ? 1 : exec_size
,
817 exec_size
== 1 ? 0 : stride
);
819 unsigned dst_regs
= registers_read(dst_access_mask
);
820 unsigned src0_regs
= registers_read(src0_access_mask
);
821 unsigned src1_regs
= registers_read(src1_access_mask
);
823 /* The SNB, IVB, HSW, BDW, and CHV PRMs say:
825 * When an instruction has a source region spanning two registers and a
826 * destination region contained in one register, the number of elements
827 * must be the same between two sources and one of the following must be
830 * 1. The destination region is entirely contained in the lower OWord
832 * 2. The destination region is entirely contained in the upper OWord
834 * 3. The destination elements are evenly split between the two OWords
837 if (devinfo
->gen
<= 8) {
838 if (dst_regs
== 1 && (src0_regs
== 2 || src1_regs
== 2)) {
839 unsigned upper_oword_writes
= 0, lower_oword_writes
= 0;
841 for (unsigned i
= 0; i
< exec_size
; i
++) {
842 if (dst_access_mask
[i
] > 0x0000FFFF) {
843 upper_oword_writes
++;
845 assert(dst_access_mask
[i
] != 0);
846 lower_oword_writes
++;
850 ERROR_IF(lower_oword_writes
!= 0 &&
851 upper_oword_writes
!= 0 &&
852 upper_oword_writes
!= lower_oword_writes
,
853 "Writes must be to only one OWord or "
854 "evenly split between OWords");
858 /* The IVB and HSW PRMs say:
860 * When an instruction has a source region that spans two registers and
861 * the destination spans two registers, the destination elements must be
862 * evenly split between the two registers [...]
864 * The SNB PRM contains similar wording (but written in a much more
869 * When destination spans two registers, the source may be one or two
870 * registers. The destination elements must be evenly split between the
875 * When destination of MATH instruction spans two registers, the
876 * destination elements must be evenly split between the two registers.
878 * It is not known whether this restriction applies to KBL other Gens after
881 if (devinfo
->gen
<= 8 ||
882 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
884 /* Nothing explicitly states that on Gen < 8 elements must be evenly
885 * split between two destination registers in the two exceptional
886 * source-region-spans-one-register cases, but since Broadwell requires
887 * evenly split writes regardless of source region, we assume that it was
888 * an oversight and require it.
891 unsigned upper_reg_writes
= 0, lower_reg_writes
= 0;
893 for (unsigned i
= 0; i
< exec_size
; i
++) {
894 if (dst_access_mask
[i
] > 0xFFFFFFFF) {
897 assert(dst_access_mask
[i
] != 0);
902 ERROR_IF(upper_reg_writes
!= lower_reg_writes
,
903 "Writes must be evenly split between the two "
904 "destination registers");
908 /* The IVB and HSW PRMs say:
910 * When an instruction has a source region that spans two registers and
911 * the destination spans two registers, the destination elements must be
912 * evenly split between the two registers and each destination register
913 * must be entirely derived from one source register.
915 * Note: In such cases, the regioning parameters must ensure that the
916 * offset from the two source registers is the same.
918 * The SNB PRM contains similar wording (but written in a much more
921 * There are effectively three rules stated here:
923 * For an instruction with a source and a destination spanning two
926 * (1) destination elements must be evenly split between the two
928 * (2) all destination elements in a register must be derived
929 * from one source register
930 * (3) the offset (i.e. the starting location in each of the two
931 * registers spanned by a region) must be the same in the two
932 * registers spanned by a region
934 * It is impossible to violate rule (1) without violating (2) or (3), so we
935 * do not attempt to validate it.
937 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
938 for (unsigned i
= 0; i
< num_sources
; i
++) {
940 if (src ## n ## _regs <= 1) \
943 for (unsigned i = 0; i < exec_size; i++) { \
944 if ((dst_access_mask[i] > 0xFFFFFFFF) != \
945 (src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
946 ERROR("Each destination register must be entirely derived " \
947 "from one source register"); \
952 unsigned offset_0 = \
953 brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
954 unsigned offset_1 = offset_0; \
956 for (unsigned i = 0; i < exec_size; i++) { \
957 if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
958 offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
963 ERROR_IF(offset_0 != offset_1, \
964 "The offset from the two source registers " \
976 /* The IVB and HSW PRMs say:
978 * When destination spans two registers, the source MUST span two
979 * registers. The exception to the above rule:
980 * 1. When source is scalar, the source registers are not
982 * 2. When source is packed integer Word and destination is packed
983 * integer DWord, the source register is not incremented by the
984 * source sub register is incremented.
986 * The SNB PRM does not contain this rule, but the internal documentation
987 * indicates that it applies to SNB as well. We assume that the rule applies
988 * to Gen <= 5 although their PRMs do not state it.
990 * While the documentation explicitly says in exception (2) that the
991 * destination must be an integer DWord, the hardware allows at least a
992 * float destination type as well. We emit such instructions from
994 * fs_visitor::emit_interpolation_setup_gen6
995 * fs_visitor::emit_fragcoord_interpolation
997 * and have for years with no ill effects.
999 * Additionally the simulator source code indicates that the real condition
1000 * is that the size of the destination type is 4 bytes.
1002 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
1003 bool dst_is_packed_dword
=
1004 is_packed(exec_size
* stride
, exec_size
, stride
) &&
1005 brw_element_size(devinfo
, inst
, dst
) == 4;
1007 for (unsigned i
= 0; i
< num_sources
; i
++) {
1009 unsigned vstride, width, hstride; \
1010 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
1011 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
1012 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
1013 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
1014 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
1015 bool src ## n ## _is_packed_word = \
1016 is_packed(vstride, width, hstride) && \
1017 (brw_inst_src ## n ## _reg_type(devinfo, inst) == BRW_HW_REG_TYPE_W || \
1018 brw_inst_src ## n ## _reg_type(devinfo, inst) == BRW_HW_REG_TYPE_UW); \
1020 ERROR_IF(src ## n ## _regs == 1 && \
1021 !src ## n ## _has_scalar_region(devinfo, inst) && \
1022 !(dst_is_packed_dword && src ## n ## _is_packed_word), \
1023 "When the destination spans two registers, the source must " \
1024 "span two registers\n" ERROR_INDENT "(exceptions for scalar " \
1025 "source and packed-word to packed-dword expansion)")
1029 } else if (i
== 1) {
1039 static struct string
1040 vector_immediate_restrictions(const struct gen_device_info
*devinfo
,
1041 const brw_inst
*inst
)
1043 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1044 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1046 if (num_sources
== 3 || num_sources
== 0)
1047 return (struct string
){};
1049 unsigned file
= num_sources
== 1 ?
1050 brw_inst_src0_reg_file(devinfo
, inst
) :
1051 brw_inst_src1_reg_file(devinfo
, inst
);
1052 if (file
!= BRW_IMMEDIATE_VALUE
)
1053 return (struct string
){};
1055 unsigned dst_type_size
= brw_element_size(devinfo
, inst
, dst
);
1056 unsigned dst_subreg
= brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
?
1057 brw_inst_dst_da1_subreg_nr(devinfo
, inst
) : 0;
1058 unsigned dst_stride
= 1 << (brw_inst_dst_hstride(devinfo
, inst
) - 1);
1059 unsigned type
= num_sources
== 1 ?
1060 brw_inst_src0_reg_type(devinfo
, inst
) :
1061 brw_inst_src1_reg_type(devinfo
, inst
);
1065 * When an immediate vector is used in an instruction, the destination
1066 * must be 128-bit aligned with destination horizontal stride equivalent
1067 * to a word for an immediate integer vector (v) and equivalent to a
1068 * DWord for an immediate float vector (vf).
1070 * The text has not been updated for the addition of the immediate unsigned
1071 * integer vector type (uv) on SNB, but presumably the same restriction
1075 case BRW_HW_IMM_TYPE_V
:
1076 case BRW_HW_IMM_TYPE_UV
:
1077 case BRW_HW_IMM_TYPE_VF
:
1078 ERROR_IF(dst_subreg
% (128 / 8) != 0,
1079 "Destination must be 128-bit aligned in order to use immediate "
1082 if (type
== BRW_HW_IMM_TYPE_VF
) {
1083 ERROR_IF(dst_type_size
* dst_stride
!= 4,
1084 "Destination must have stride equivalent to dword in order "
1085 "to use the VF type");
1087 ERROR_IF(dst_type_size
* dst_stride
!= 2,
1088 "Destination must have stride equivalent to word in order "
1089 "to use the V or UV type");
1100 brw_validate_instructions(const struct gen_device_info
*devinfo
,
1101 void *assembly
, int start_offset
, int end_offset
,
1102 struct annotation_info
*annotation
)
1106 for (int src_offset
= start_offset
; src_offset
< end_offset
;) {
1107 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1108 const brw_inst
*inst
= assembly
+ src_offset
;
1109 bool is_compact
= brw_inst_cmpt_control(devinfo
, inst
);
1110 brw_inst uncompacted
;
1113 brw_compact_inst
*compacted
= (void *)inst
;
1114 brw_uncompact_instruction(devinfo
, &uncompacted
, compacted
);
1115 inst
= &uncompacted
;
1118 if (is_unsupported_inst(devinfo
, inst
)) {
1119 ERROR("Instruction not supported on this Gen");
1121 CHECK(sources_not_null
);
1122 CHECK(send_restrictions
);
1123 CHECK(general_restrictions_based_on_operand_types
);
1124 CHECK(general_restrictions_on_region_parameters
);
1125 CHECK(region_alignment_rules
);
1126 CHECK(vector_immediate_restrictions
);
1129 if (error_msg
.str
&& annotation
) {
1130 annotation_insert_error(annotation
, src_offset
, error_msg
.str
);
1132 valid
= valid
&& error_msg
.len
== 0;
1133 free(error_msg
.str
);
1136 src_offset
+= sizeof(brw_compact_inst
);
1138 src_offset
+= sizeof(brw_inst
);