2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_validate.c
26 * This file implements a pass that validates shader assembly.
31 /* We're going to do lots of string concatenation, so this should help. */
38 cat(struct string
*dest
, const struct string src
)
40 dest
->str
= realloc(dest
->str
, dest
->len
+ src
.len
+ 1);
41 memcpy(dest
->str
+ dest
->len
, src
.str
, src
.len
);
42 dest
->str
[dest
->len
+ src
.len
] = '\0';
43 dest
->len
= dest
->len
+ src
.len
;
45 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
47 #define error(str) "\tERROR: " str "\n"
48 #define ERROR_INDENT "\t "
50 #define ERROR(msg) ERROR_IF(true, msg)
51 #define ERROR_IF(cond, msg) \
54 CAT(error_msg, error(msg)); \
58 #define CHECK(func, args...) \
60 struct string __msg = func(devinfo, inst, ##args); \
62 cat(&error_msg, __msg); \
68 inst_is_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
70 switch (brw_inst_opcode(devinfo
, inst
)) {
72 case BRW_OPCODE_SENDC
:
73 case BRW_OPCODE_SENDS
:
74 case BRW_OPCODE_SENDSC
:
82 signed_type(unsigned type
)
85 case BRW_HW_REG_TYPE_UD
: return BRW_HW_REG_TYPE_D
;
86 case BRW_HW_REG_TYPE_UW
: return BRW_HW_REG_TYPE_W
;
87 case BRW_HW_REG_NON_IMM_TYPE_UB
: return BRW_HW_REG_NON_IMM_TYPE_B
;
88 case GEN8_HW_REG_TYPE_UQ
: return GEN8_HW_REG_TYPE_Q
;
94 inst_is_raw_move(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
96 unsigned dst_type
= signed_type(brw_inst_dst_reg_type(devinfo
, inst
));
97 unsigned src_type
= signed_type(brw_inst_src0_reg_type(devinfo
, inst
));
99 if (brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
100 (brw_inst_src0_negate(devinfo
, inst
) ||
101 brw_inst_src0_abs(devinfo
, inst
)))
104 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MOV
&&
105 brw_inst_saturate(devinfo
, inst
) == 0 &&
106 dst_type
== src_type
;
110 dst_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
112 return brw_inst_dst_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
113 brw_inst_dst_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
117 src0_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
119 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
120 brw_inst_src0_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
124 src1_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
126 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
127 brw_inst_src1_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
131 src0_is_grf(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
133 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
;
137 src0_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
139 return brw_inst_src0_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
140 brw_inst_src0_width(devinfo
, inst
) == BRW_WIDTH_1
&&
141 brw_inst_src0_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
145 src1_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
147 return brw_inst_src1_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
148 brw_inst_src1_width(devinfo
, inst
) == BRW_WIDTH_1
&&
149 brw_inst_src1_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
153 num_sources_from_inst(const struct gen_device_info
*devinfo
,
154 const brw_inst
*inst
)
156 const struct opcode_desc
*desc
=
157 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
158 unsigned math_function
;
160 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
161 math_function
= brw_inst_math_function(devinfo
, inst
);
162 } else if (devinfo
->gen
< 6 &&
163 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
164 if (brw_inst_sfid(devinfo
, inst
) == BRW_SFID_MATH
) {
165 /* src1 must be a descriptor (including the information to determine
166 * that the SEND is doing an extended math operation), but src0 can
167 * actually be null since it serves as the source of the implicit GRF
170 * If we stop using that functionality, we'll have to revisit this.
174 /* Send instructions are allowed to have null sources since they use
175 * the base_mrf field to specify which message register source.
180 assert(desc
->nsrc
< 4);
184 switch (math_function
) {
185 case BRW_MATH_FUNCTION_INV
:
186 case BRW_MATH_FUNCTION_LOG
:
187 case BRW_MATH_FUNCTION_EXP
:
188 case BRW_MATH_FUNCTION_SQRT
:
189 case BRW_MATH_FUNCTION_RSQ
:
190 case BRW_MATH_FUNCTION_SIN
:
191 case BRW_MATH_FUNCTION_COS
:
192 case BRW_MATH_FUNCTION_SINCOS
:
193 case GEN8_MATH_FUNCTION_INVM
:
194 case GEN8_MATH_FUNCTION_RSQRTM
:
196 case BRW_MATH_FUNCTION_FDIV
:
197 case BRW_MATH_FUNCTION_POW
:
198 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
199 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
200 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
203 unreachable("not reached");
208 sources_not_null(const struct gen_device_info
*devinfo
,
209 const brw_inst
*inst
)
211 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
212 struct string error_msg
= { .str
= NULL
, .len
= 0 };
214 /* Nothing to test. 3-src instructions can only have GRF sources, and
215 * there's no bit to control the file.
217 if (num_sources
== 3)
218 return (struct string
){};
220 if (num_sources
>= 1)
221 ERROR_IF(src0_is_null(devinfo
, inst
), "src0 is null");
223 if (num_sources
== 2)
224 ERROR_IF(src1_is_null(devinfo
, inst
), "src1 is null");
230 send_restrictions(const struct gen_device_info
*devinfo
,
231 const brw_inst
*inst
)
233 struct string error_msg
= { .str
= NULL
, .len
= 0 };
235 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
236 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
,
237 "send must use direct addressing");
239 if (devinfo
->gen
>= 7) {
240 ERROR_IF(!src0_is_grf(devinfo
, inst
), "send from non-GRF");
241 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
242 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
243 "send with EOT must use g112-g127");
251 is_unsupported_inst(const struct gen_device_info
*devinfo
,
252 const brw_inst
*inst
)
254 return brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
)) == NULL
;
258 execution_type_for_type(unsigned type
, bool is_immediate
)
260 /* The meaning of the type bits is dependent on whether the operand is an
261 * immediate, so normalize them first.
265 case BRW_HW_REG_IMM_TYPE_UV
:
266 case BRW_HW_REG_IMM_TYPE_V
:
267 type
= BRW_HW_REG_TYPE_W
;
269 case BRW_HW_REG_IMM_TYPE_VF
:
270 type
= BRW_HW_REG_TYPE_F
;
272 case GEN8_HW_REG_IMM_TYPE_DF
:
273 type
= GEN7_HW_REG_NON_IMM_TYPE_DF
;
275 case GEN8_HW_REG_IMM_TYPE_HF
:
276 type
= GEN8_HW_REG_NON_IMM_TYPE_HF
;
284 case BRW_HW_REG_TYPE_UD
:
285 case BRW_HW_REG_TYPE_D
:
286 return BRW_HW_REG_TYPE_D
;
287 case BRW_HW_REG_TYPE_UW
:
288 case BRW_HW_REG_TYPE_W
:
289 case BRW_HW_REG_NON_IMM_TYPE_UB
:
290 case BRW_HW_REG_NON_IMM_TYPE_B
:
291 return BRW_HW_REG_TYPE_W
;
292 case GEN8_HW_REG_TYPE_UQ
:
293 case GEN8_HW_REG_TYPE_Q
:
294 return GEN8_HW_REG_TYPE_Q
;
295 case BRW_HW_REG_TYPE_F
:
296 case GEN7_HW_REG_NON_IMM_TYPE_DF
:
297 case GEN8_HW_REG_NON_IMM_TYPE_HF
:
300 unreachable("not reached");
305 * Returns the execution type of an instruction \p inst
308 execution_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
310 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
311 unsigned src0_exec_type
, src1_exec_type
;
312 unsigned src0_type
= brw_inst_src0_reg_type(devinfo
, inst
);
313 unsigned src1_type
= brw_inst_src1_reg_type(devinfo
, inst
);
315 bool src0_is_immediate
=
316 brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
;
317 bool src1_is_immediate
=
318 brw_inst_src1_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
;
320 /* Execution data type is independent of destination data type, except in
321 * mixed F/HF instructions on CHV and SKL+.
323 unsigned dst_exec_type
= brw_inst_dst_reg_type(devinfo
, inst
);
325 src0_exec_type
= execution_type_for_type(src0_type
, src0_is_immediate
);
326 if (num_sources
== 1) {
327 if ((devinfo
->gen
>= 9 || devinfo
->is_cherryview
) &&
328 src0_exec_type
== GEN8_HW_REG_NON_IMM_TYPE_HF
) {
329 return dst_exec_type
;
331 return src0_exec_type
;
334 src1_exec_type
= execution_type_for_type(src1_type
, src1_is_immediate
);
335 if (src0_exec_type
== src1_exec_type
)
336 return src0_exec_type
;
338 /* Mixed operand types where one is float is float on Gen < 6
339 * (and not allowed on later platforms)
341 if (devinfo
->gen
< 6 &&
342 (src0_exec_type
== BRW_HW_REG_TYPE_F
||
343 src1_exec_type
== BRW_HW_REG_TYPE_F
))
344 return BRW_HW_REG_TYPE_F
;
346 if (src0_exec_type
== GEN8_HW_REG_TYPE_Q
||
347 src1_exec_type
== GEN8_HW_REG_TYPE_Q
)
348 return GEN8_HW_REG_TYPE_Q
;
350 if (src0_exec_type
== BRW_HW_REG_TYPE_D
||
351 src1_exec_type
== BRW_HW_REG_TYPE_D
)
352 return BRW_HW_REG_TYPE_D
;
354 if (src0_exec_type
== BRW_HW_REG_TYPE_W
||
355 src1_exec_type
== BRW_HW_REG_TYPE_W
)
356 return BRW_HW_REG_TYPE_W
;
358 if (src0_exec_type
== GEN7_HW_REG_NON_IMM_TYPE_DF
||
359 src1_exec_type
== GEN7_HW_REG_NON_IMM_TYPE_DF
)
360 return GEN7_HW_REG_NON_IMM_TYPE_DF
;
362 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
363 if (dst_exec_type
== BRW_HW_REG_TYPE_F
||
364 src0_exec_type
== BRW_HW_REG_TYPE_F
||
365 src1_exec_type
== BRW_HW_REG_TYPE_F
) {
366 return BRW_HW_REG_TYPE_F
;
368 return GEN8_HW_REG_NON_IMM_TYPE_HF
;
372 assert(src0_exec_type
== BRW_HW_REG_TYPE_F
);
373 return BRW_HW_REG_TYPE_F
;
377 * Returns whether a region is packed
379 * A region is packed if its elements are adjacent in memory, with no
380 * intervening space, no overlap, and no replicated values.
383 is_packed(unsigned vstride
, unsigned width
, unsigned hstride
)
385 if (vstride
== width
) {
397 * Checks restrictions listed in "General Restrictions Based on Operand Types"
398 * in the "Register Region Restrictions" section.
401 general_restrictions_based_on_operand_types(const struct gen_device_info
*devinfo
,
402 const brw_inst
*inst
)
404 const struct opcode_desc
*desc
=
405 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
406 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
407 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
408 struct string error_msg
= { .str
= NULL
, .len
= 0 };
410 if (num_sources
== 3)
411 return (struct string
){};
413 if (inst_is_send(devinfo
, inst
))
414 return (struct string
){};
417 return (struct string
){};
420 return (struct string
){};
424 * Where n is the largest element size in bytes for any source or
425 * destination operand type, ExecSize * n must be <= 64.
427 * But we do not attempt to enforce it, because it is implied by other
430 * - that the destination stride must match the execution data type
431 * - sources may not span more than two adjacent GRF registers
432 * - destination may not span more than two adjacent GRF registers
434 * In fact, checking it would weaken testing of the other rules.
437 if (num_sources
== 3)
438 return (struct string
){};
441 return (struct string
){};
443 if (inst_is_send(devinfo
, inst
))
444 return (struct string
){};
447 return (struct string
){};
449 unsigned dst_stride
= 1 << (brw_inst_dst_hstride(devinfo
, inst
) - 1);
450 bool dst_type_is_byte
=
451 brw_inst_dst_reg_type(devinfo
, inst
) == BRW_HW_REG_NON_IMM_TYPE_B
||
452 brw_inst_dst_reg_type(devinfo
, inst
) == BRW_HW_REG_NON_IMM_TYPE_UB
;
454 if (dst_type_is_byte
) {
455 if (is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
)) {
456 if (!inst_is_raw_move(devinfo
, inst
)) {
457 ERROR("Only raw MOV supports a packed-byte destination");
460 return (struct string
){};
465 unsigned exec_type
= execution_type(devinfo
, inst
);
466 unsigned exec_type_size
=
467 brw_hw_reg_type_to_size(devinfo
, exec_type
, BRW_GENERAL_REGISTER_FILE
);
468 unsigned dst_type_size
= brw_element_size(devinfo
, inst
, dst
);
470 /* On IVB/BYT, region parameters and execution size for DF are in terms of
471 * 32-bit elements, so they are doubled. For evaluating the validity of an
472 * instruction, we halve them.
474 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
475 exec_type_size
== 8 && dst_type_size
== 4)
478 if (exec_type_size
> dst_type_size
) {
479 ERROR_IF(dst_stride
* dst_type_size
!= exec_type_size
,
480 "Destination stride must be equal to the ratio of the sizes of "
481 "the execution data type to the destination type");
483 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
485 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
486 brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
) {
487 /* The i965 PRM says:
489 * Implementation Restriction: The relaxed alignment rule for byte
490 * destination (#10.5) is not supported.
492 if ((devinfo
->gen
> 4 || devinfo
->is_g4x
) && dst_type_is_byte
) {
493 ERROR_IF(subreg
% exec_type_size
!= 0 &&
494 subreg
% exec_type_size
!= 1,
495 "Destination subreg must be aligned to the size of the "
496 "execution data type (or to the next lowest byte for byte "
499 ERROR_IF(subreg
% exec_type_size
!= 0,
500 "Destination subreg must be aligned to the size of the "
501 "execution data type");
510 * Checks restrictions listed in "General Restrictions on Regioning Parameters"
511 * in the "Register Region Restrictions" section.
514 general_restrictions_on_region_parameters(const struct gen_device_info
*devinfo
,
515 const brw_inst
*inst
)
517 const struct opcode_desc
*desc
=
518 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
519 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
520 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
521 struct string error_msg
= { .str
= NULL
, .len
= 0 };
523 if (num_sources
== 3)
524 return (struct string
){};
526 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
) {
527 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
))
528 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) != BRW_HORIZONTAL_STRIDE_1
,
529 "Destination Horizontal Stride must be 1");
531 if (num_sources
>= 1) {
532 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
533 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
534 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
535 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
536 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
537 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
539 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
540 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
541 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
542 "In Align16 mode, only VertStride of 0 or 4 is allowed");
546 if (num_sources
== 2) {
547 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
548 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
549 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
550 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
551 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
552 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
554 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
555 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
556 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
557 "In Align16 mode, only VertStride of 0 or 4 is allowed");
564 for (unsigned i
= 0; i
< num_sources
; i
++) {
565 unsigned vstride
, width
, hstride
, element_size
, subreg
;
568 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
569 BRW_IMMEDIATE_VALUE) \
572 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
573 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
574 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
575 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
576 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
577 element_size = brw_element_size(devinfo, inst, src ## n); \
578 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
587 /* On IVB/BYT, region parameters and execution size for DF are in terms of
588 * 32-bit elements, so they are doubled. For evaluating the validity of an
589 * instruction, we halve them.
591 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
595 /* ExecSize must be greater than or equal to Width. */
596 ERROR_IF(exec_size
< width
, "ExecSize must be greater than or equal "
599 /* If ExecSize = Width and HorzStride ≠ 0,
600 * VertStride must be set to Width * HorzStride.
602 if (exec_size
== width
&& hstride
!= 0) {
603 ERROR_IF(vstride
!= width
* hstride
,
604 "If ExecSize = Width and HorzStride ≠ 0, "
605 "VertStride must be set to Width * HorzStride");
608 /* If Width = 1, HorzStride must be 0 regardless of the values of
609 * ExecSize and VertStride.
612 ERROR_IF(hstride
!= 0,
613 "If Width = 1, HorzStride must be 0 regardless "
614 "of the values of ExecSize and VertStride");
617 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
618 if (exec_size
== 1 && width
== 1) {
619 ERROR_IF(vstride
!= 0 || hstride
!= 0,
620 "If ExecSize = Width = 1, both VertStride "
621 "and HorzStride must be 0");
624 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the
627 if (vstride
== 0 && hstride
== 0) {
629 "If VertStride = HorzStride = 0, Width must be "
630 "1 regardless of the value of ExecSize");
633 /* VertStride must be used to cross GRF register boundaries. This rule
634 * implies that elements within a 'Width' cannot cross GRF boundaries.
636 const uint64_t mask
= (1 << element_size
) - 1;
637 unsigned rowbase
= subreg
;
639 for (int y
= 0; y
< exec_size
/ width
; y
++) {
640 uint64_t access_mask
= 0;
641 unsigned offset
= rowbase
;
643 for (int x
= 0; x
< width
; x
++) {
644 access_mask
|= mask
<< offset
;
645 offset
+= hstride
* element_size
;
648 rowbase
+= vstride
* element_size
;
650 if ((uint32_t)access_mask
!= 0 && (access_mask
>> 32) != 0) {
651 ERROR("VertStride must be used to cross GRF register boundaries");
657 /* Dst.HorzStride must not be 0. */
658 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
)) {
659 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
,
660 "Destination Horizontal Stride must not be 0");
667 * Creates an \p access_mask for an \p exec_size, \p element_size, and a region
669 * An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
670 * a bitmask of bytes accessed by the region.
672 * For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
673 * instruction would be
675 * access_mask[0] = 0x00000000000000F0
676 * access_mask[1] = 0x000000000000F000
677 * access_mask[2] = 0x0000000000F00000
678 * access_mask[3] = 0x00000000F0000000
679 * access_mask[4-31] = 0
681 * because the first execution channel accesses bytes 7-4 and the second
682 * execution channel accesses bytes 15-12, etc.
685 align1_access_mask(uint64_t access_mask
[static 32],
686 unsigned exec_size
, unsigned element_size
, unsigned subreg
,
687 unsigned vstride
, unsigned width
, unsigned hstride
)
689 const uint64_t mask
= (1 << element_size
) - 1;
690 unsigned rowbase
= subreg
;
691 unsigned element
= 0;
693 for (int y
= 0; y
< exec_size
/ width
; y
++) {
694 unsigned offset
= rowbase
;
696 for (int x
= 0; x
< width
; x
++) {
697 access_mask
[element
++] = mask
<< offset
;
698 offset
+= hstride
* element_size
;
701 rowbase
+= vstride
* element_size
;
704 assert(element
== 0 || element
== exec_size
);
708 * Returns the number of registers accessed according to the \p access_mask
711 registers_read(const uint64_t access_mask
[static 32])
715 for (unsigned i
= 0; i
< 32; i
++) {
716 if (access_mask
[i
] > 0xFFFFFFFF) {
718 } else if (access_mask
[i
]) {
727 * Checks restrictions listed in "Region Alignment Rules" in the "Register
728 * Region Restrictions" section.
731 region_alignment_rules(const struct gen_device_info
*devinfo
,
732 const brw_inst
*inst
)
734 const struct opcode_desc
*desc
=
735 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
736 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
737 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
738 uint64_t dst_access_mask
[32], src0_access_mask
[32], src1_access_mask
[32];
739 struct string error_msg
= { .str
= NULL
, .len
= 0 };
741 if (num_sources
== 3)
742 return (struct string
){};
744 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
)
745 return (struct string
){};
747 if (inst_is_send(devinfo
, inst
))
748 return (struct string
){};
750 memset(dst_access_mask
, 0, sizeof(dst_access_mask
));
751 memset(src0_access_mask
, 0, sizeof(src0_access_mask
));
752 memset(src1_access_mask
, 0, sizeof(src1_access_mask
));
754 for (unsigned i
= 0; i
< num_sources
; i
++) {
755 unsigned vstride
, width
, hstride
, element_size
, subreg
;
757 /* In Direct Addressing mode, a source cannot span more than 2 adjacent
762 if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
763 BRW_ADDRESS_DIRECT) \
766 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
767 BRW_IMMEDIATE_VALUE) \
770 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
771 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
772 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
773 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
774 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
775 element_size = brw_element_size(devinfo, inst, src ## n); \
776 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
777 align1_access_mask(src ## n ## _access_mask, \
778 exec_size, element_size, subreg, \
779 vstride, width, hstride)
788 unsigned num_vstride
= exec_size
/ width
;
789 unsigned num_hstride
= width
;
790 unsigned vstride_elements
= (num_vstride
- 1) * vstride
;
791 unsigned hstride_elements
= (num_hstride
- 1) * hstride
;
792 unsigned offset
= (vstride_elements
+ hstride_elements
) * element_size
+
794 ERROR_IF(offset
>= 64,
795 "A source cannot span more than 2 adjacent GRF registers");
798 if (desc
->ndst
== 0 || dst_is_null(devinfo
, inst
))
801 unsigned stride
= 1 << (brw_inst_dst_hstride(devinfo
, inst
) - 1);
802 unsigned element_size
= brw_element_size(devinfo
, inst
, dst
);
803 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
804 unsigned offset
= ((exec_size
- 1) * stride
* element_size
) + subreg
;
805 ERROR_IF(offset
>= 64,
806 "A destination cannot span more than 2 adjacent GRF registers");
811 /* On IVB/BYT, region parameters and execution size for DF are in terms of
812 * 32-bit elements, so they are doubled. For evaluating the validity of an
813 * instruction, we halve them.
815 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
819 align1_access_mask(dst_access_mask
, exec_size
, element_size
, subreg
,
820 exec_size
== 1 ? 0 : exec_size
* stride
,
821 exec_size
== 1 ? 1 : exec_size
,
822 exec_size
== 1 ? 0 : stride
);
824 unsigned dst_regs
= registers_read(dst_access_mask
);
825 unsigned src0_regs
= registers_read(src0_access_mask
);
826 unsigned src1_regs
= registers_read(src1_access_mask
);
828 /* The SNB, IVB, HSW, BDW, and CHV PRMs say:
830 * When an instruction has a source region spanning two registers and a
831 * destination region contained in one register, the number of elements
832 * must be the same between two sources and one of the following must be
835 * 1. The destination region is entirely contained in the lower OWord
837 * 2. The destination region is entirely contained in the upper OWord
839 * 3. The destination elements are evenly split between the two OWords
842 if (devinfo
->gen
<= 8) {
843 if (dst_regs
== 1 && (src0_regs
== 2 || src1_regs
== 2)) {
844 unsigned upper_oword_writes
= 0, lower_oword_writes
= 0;
846 for (unsigned i
= 0; i
< exec_size
; i
++) {
847 if (dst_access_mask
[i
] > 0x0000FFFF) {
848 upper_oword_writes
++;
850 assert(dst_access_mask
[i
] != 0);
851 lower_oword_writes
++;
855 ERROR_IF(lower_oword_writes
!= 0 &&
856 upper_oword_writes
!= 0 &&
857 upper_oword_writes
!= lower_oword_writes
,
858 "Writes must be to only one OWord or "
859 "evenly split between OWords");
863 /* The IVB and HSW PRMs say:
865 * When an instruction has a source region that spans two registers and
866 * the destination spans two registers, the destination elements must be
867 * evenly split between the two registers [...]
869 * The SNB PRM contains similar wording (but written in a much more
874 * When destination spans two registers, the source may be one or two
875 * registers. The destination elements must be evenly split between the
880 * When destination of MATH instruction spans two registers, the
881 * destination elements must be evenly split between the two registers.
883 * It is not known whether this restriction applies to KBL other Gens after
886 if (devinfo
->gen
<= 8 ||
887 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
889 /* Nothing explicitly states that on Gen < 8 elements must be evenly
890 * split between two destination registers in the two exceptional
891 * source-region-spans-one-register cases, but since Broadwell requires
892 * evenly split writes regardless of source region, we assume that it was
893 * an oversight and require it.
896 unsigned upper_reg_writes
= 0, lower_reg_writes
= 0;
898 for (unsigned i
= 0; i
< exec_size
; i
++) {
899 if (dst_access_mask
[i
] > 0xFFFFFFFF) {
902 assert(dst_access_mask
[i
] != 0);
907 ERROR_IF(upper_reg_writes
!= lower_reg_writes
,
908 "Writes must be evenly split between the two "
909 "destination registers");
913 /* The IVB and HSW PRMs say:
915 * When an instruction has a source region that spans two registers and
916 * the destination spans two registers, the destination elements must be
917 * evenly split between the two registers and each destination register
918 * must be entirely derived from one source register.
920 * Note: In such cases, the regioning parameters must ensure that the
921 * offset from the two source registers is the same.
923 * The SNB PRM contains similar wording (but written in a much more
926 * There are effectively three rules stated here:
928 * For an instruction with a source and a destination spanning two
931 * (1) destination elements must be evenly split between the two
933 * (2) all destination elements in a register must be derived
934 * from one source register
935 * (3) the offset (i.e. the starting location in each of the two
936 * registers spanned by a region) must be the same in the two
937 * registers spanned by a region
939 * It is impossible to violate rule (1) without violating (2) or (3), so we
940 * do not attempt to validate it.
942 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
943 for (unsigned i
= 0; i
< num_sources
; i
++) {
945 if (src ## n ## _regs <= 1) \
948 for (unsigned i = 0; i < exec_size; i++) { \
949 if ((dst_access_mask[i] > 0xFFFFFFFF) != \
950 (src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
951 ERROR("Each destination register must be entirely derived " \
952 "from one source register"); \
957 unsigned offset_0 = \
958 brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
959 unsigned offset_1 = offset_0; \
961 for (unsigned i = 0; i < exec_size; i++) { \
962 if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
963 offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
968 ERROR_IF(offset_0 != offset_1, \
969 "The offset from the two source registers " \
981 /* The IVB and HSW PRMs say:
983 * When destination spans two registers, the source MUST span two
984 * registers. The exception to the above rule:
985 * 1. When source is scalar, the source registers are not
987 * 2. When source is packed integer Word and destination is packed
988 * integer DWord, the source register is not incremented by the
989 * source sub register is incremented.
991 * The SNB PRM does not contain this rule, but the internal documentation
992 * indicates that it applies to SNB as well. We assume that the rule applies
993 * to Gen <= 5 although their PRMs do not state it.
995 * While the documentation explicitly says in exception (2) that the
996 * destination must be an integer DWord, the hardware allows at least a
997 * float destination type as well. We emit such instructions from
999 * fs_visitor::emit_interpolation_setup_gen6
1000 * fs_visitor::emit_fragcoord_interpolation
1002 * and have for years with no ill effects.
1004 * Additionally the simulator source code indicates that the real condition
1005 * is that the size of the destination type is 4 bytes.
1007 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
1008 bool dst_is_packed_dword
=
1009 is_packed(exec_size
* stride
, exec_size
, stride
) &&
1010 brw_element_size(devinfo
, inst
, dst
) == 4;
1012 for (unsigned i
= 0; i
< num_sources
; i
++) {
1014 unsigned vstride, width, hstride; \
1015 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
1016 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
1017 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
1018 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
1019 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
1020 bool src ## n ## _is_packed_word = \
1021 is_packed(vstride, width, hstride) && \
1022 (brw_inst_src ## n ## _reg_type(devinfo, inst) == BRW_HW_REG_TYPE_W || \
1023 brw_inst_src ## n ## _reg_type(devinfo, inst) == BRW_HW_REG_TYPE_UW); \
1025 ERROR_IF(src ## n ## _regs == 1 && \
1026 !src ## n ## _has_scalar_region(devinfo, inst) && \
1027 !(dst_is_packed_dword && src ## n ## _is_packed_word), \
1028 "When the destination spans two registers, the source must " \
1029 "span two registers\n" ERROR_INDENT "(exceptions for scalar " \
1030 "source and packed-word to packed-dword expansion)")
1034 } else if (i
== 1) {
1045 brw_validate_instructions(const struct brw_codegen
*p
, int start_offset
,
1046 struct annotation_info
*annotation
)
1048 const struct gen_device_info
*devinfo
= p
->devinfo
;
1049 const void *store
= p
->store
;
1052 for (int src_offset
= start_offset
; src_offset
< p
->next_insn_offset
;
1053 src_offset
+= sizeof(brw_inst
)) {
1054 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1055 const brw_inst
*inst
= store
+ src_offset
;
1057 if (is_unsupported_inst(devinfo
, inst
)) {
1058 ERROR("Instruction not supported on this Gen");
1060 CHECK(sources_not_null
);
1061 CHECK(send_restrictions
);
1062 CHECK(general_restrictions_based_on_operand_types
);
1063 CHECK(general_restrictions_on_region_parameters
);
1064 CHECK(region_alignment_rules
);
1067 if (error_msg
.str
&& annotation
) {
1068 annotation_insert_error(annotation
, src_offset
, error_msg
.str
);
1070 valid
= valid
&& error_msg
.len
== 0;
1071 free(error_msg
.str
);