i965/fs: rename lower_d2x to lower_conversions
[mesa.git] / src / intel / compiler / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #ifndef BRW_FS_H
29 #define BRW_FS_H
30
31 #include "brw_shader.h"
32 #include "brw_ir_fs.h"
33 #include "brw_fs_builder.h"
34 #include "compiler/nir/nir.h"
35
36 struct bblock_t;
37 namespace {
38 struct acp_entry;
39 }
40
41 namespace brw {
42 class fs_live_variables;
43 }
44
45 struct brw_gs_compile;
46
47 static inline fs_reg
48 offset(const fs_reg &reg, const brw::fs_builder &bld, unsigned delta)
49 {
50 return offset(reg, bld.dispatch_width(), delta);
51 }
52
53 /**
54 * The fragment shader front-end.
55 *
56 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
57 */
58 class fs_visitor : public backend_shader
59 {
60 public:
61 fs_visitor(const struct brw_compiler *compiler, void *log_data,
62 void *mem_ctx,
63 const void *key,
64 struct brw_stage_prog_data *prog_data,
65 struct gl_program *prog,
66 const nir_shader *shader,
67 unsigned dispatch_width,
68 int shader_time_index,
69 const struct brw_vue_map *input_vue_map = NULL);
70 fs_visitor(const struct brw_compiler *compiler, void *log_data,
71 void *mem_ctx,
72 struct brw_gs_compile *gs_compile,
73 struct brw_gs_prog_data *prog_data,
74 const nir_shader *shader,
75 int shader_time_index);
76 void init();
77 ~fs_visitor();
78
79 fs_reg vgrf(const glsl_type *const type);
80 void import_uniforms(fs_visitor *v);
81 void setup_uniform_clipplane_values(gl_clip_plane *clip_planes);
82 void compute_clip_distance(gl_clip_plane *clip_planes);
83
84 fs_inst *get_instruction_generating_reg(fs_inst *start,
85 fs_inst *end,
86 const fs_reg &reg);
87
88 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
89 const fs_reg &dst,
90 const fs_reg &surf_index,
91 const fs_reg &varying_offset,
92 uint32_t const_offset);
93 void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
94
95 bool run_fs(bool allow_spilling, bool do_rep_send);
96 bool run_vs(gl_clip_plane *clip_planes);
97 bool run_tcs_single_patch();
98 bool run_tes();
99 bool run_gs();
100 bool run_cs();
101 void optimize();
102 void allocate_registers(bool allow_spilling);
103 void setup_fs_payload_gen4();
104 void setup_fs_payload_gen6();
105 void setup_vs_payload();
106 void setup_gs_payload();
107 void setup_cs_payload();
108 void fixup_3src_null_dest();
109 void assign_curb_setup();
110 void calculate_urb_setup();
111 void assign_urb_setup();
112 void convert_attr_sources_to_hw_regs(fs_inst *inst);
113 void assign_vs_urb_setup();
114 void assign_tcs_single_patch_urb_setup();
115 void assign_tes_urb_setup();
116 void assign_gs_urb_setup();
117 bool assign_regs(bool allow_spilling, bool spill_all);
118 void assign_regs_trivial();
119 void calculate_payload_ranges(int payload_node_count,
120 int *payload_last_use_ip);
121 void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
122 int first_payload_node);
123 int choose_spill_reg(struct ra_graph *g);
124 void spill_reg(int spill_reg);
125 void split_virtual_grfs();
126 bool compact_virtual_grfs();
127 void assign_constant_locations();
128 void lower_constant_loads();
129 void invalidate_live_intervals();
130 void calculate_live_intervals();
131 void calculate_register_pressure();
132 void validate();
133 bool opt_algebraic();
134 bool opt_redundant_discard_jumps();
135 bool opt_cse();
136 bool opt_cse_local(bblock_t *block);
137 bool opt_copy_propagation();
138 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
139 bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
140 bool opt_copy_propagation_local(void *mem_ctx, bblock_t *block,
141 exec_list *acp);
142 bool opt_drop_redundant_mov_to_flags();
143 bool opt_register_renaming();
144 bool register_coalesce();
145 bool compute_to_mrf();
146 bool eliminate_find_live_channel();
147 bool dead_code_eliminate();
148 bool remove_duplicate_mrf_writes();
149
150 bool opt_sampler_eot();
151 bool virtual_grf_interferes(int a, int b);
152 void schedule_instructions(instruction_scheduler_mode mode);
153 void insert_gen4_send_dependency_workarounds();
154 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
155 fs_inst *inst);
156 void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
157 fs_inst *inst);
158 void vfail(const char *msg, va_list args);
159 void fail(const char *msg, ...);
160 void limit_dispatch_width(unsigned n, const char *msg);
161 void lower_uniform_pull_constant_loads();
162 bool lower_load_payload();
163 bool lower_pack();
164 bool lower_conversions();
165 bool lower_logical_sends();
166 bool lower_integer_multiplication();
167 bool lower_minmax();
168 bool lower_simd_width();
169 bool opt_combine_constants();
170
171 void emit_dummy_fs();
172 void emit_repclear_shader();
173 void emit_fragcoord_interpolation(fs_reg wpos);
174 fs_reg *emit_frontfacing_interpolation();
175 fs_reg *emit_samplepos_setup();
176 fs_reg *emit_sampleid_setup();
177 fs_reg *emit_samplemaskin_setup();
178 fs_reg *emit_vs_system_value(int location);
179 void emit_interpolation_setup_gen4();
180 void emit_interpolation_setup_gen6();
181 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
182 fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
183 const fs_reg &sampler);
184 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
185 fs_reg resolve_source_modifiers(const fs_reg &src);
186 void emit_discard_jump();
187 bool opt_peephole_sel();
188 bool opt_peephole_predicated_break();
189 bool opt_saturate_propagation();
190 bool opt_cmod_propagation();
191 bool opt_zero_samples();
192
193 void emit_nir_code();
194 void nir_setup_outputs();
195 void nir_setup_uniforms();
196 void nir_emit_system_values();
197 void nir_emit_impl(nir_function_impl *impl);
198 void nir_emit_cf_list(exec_list *list);
199 void nir_emit_if(nir_if *if_stmt);
200 void nir_emit_loop(nir_loop *loop);
201 void nir_emit_block(nir_block *block);
202 void nir_emit_instr(nir_instr *instr);
203 void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
204 void nir_emit_load_const(const brw::fs_builder &bld,
205 nir_load_const_instr *instr);
206 void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
207 nir_intrinsic_instr *instr);
208 void nir_emit_tcs_intrinsic(const brw::fs_builder &bld,
209 nir_intrinsic_instr *instr);
210 void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
211 nir_intrinsic_instr *instr);
212 void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
213 nir_intrinsic_instr *instr);
214 void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
215 nir_intrinsic_instr *instr);
216 void nir_emit_intrinsic(const brw::fs_builder &bld,
217 nir_intrinsic_instr *instr);
218 void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
219 nir_intrinsic_instr *instr);
220 void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
221 int op, nir_intrinsic_instr *instr);
222 void nir_emit_shared_atomic(const brw::fs_builder &bld,
223 int op, nir_intrinsic_instr *instr);
224 void nir_emit_texture(const brw::fs_builder &bld,
225 nir_tex_instr *instr);
226 void nir_emit_jump(const brw::fs_builder &bld,
227 nir_jump_instr *instr);
228 fs_reg get_nir_src(const nir_src &src);
229 fs_reg get_nir_src_imm(const nir_src &src);
230 fs_reg get_nir_dest(const nir_dest &dest);
231 fs_reg get_nir_image_deref(const nir_deref_var *deref);
232 fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
233 void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
234 unsigned wr_mask);
235
236 bool optimize_extract_to_float(nir_alu_instr *instr,
237 const fs_reg &result);
238 bool optimize_frontfacing_ternary(nir_alu_instr *instr,
239 const fs_reg &result);
240
241 void emit_alpha_test();
242 fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
243 fs_reg color1, fs_reg color2,
244 fs_reg src0_alpha, unsigned components);
245 void emit_fb_writes();
246 fs_inst *emit_non_coherent_fb_read(const brw::fs_builder &bld,
247 const fs_reg &dst, unsigned target);
248 void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
249 void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
250 unsigned stream_id);
251 void emit_gs_control_data_bits(const fs_reg &vertex_count);
252 void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
253 void emit_gs_vertex(const nir_src &vertex_count_nir_src,
254 unsigned stream_id);
255 void emit_gs_thread_end();
256 void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
257 unsigned base_offset, const nir_src &offset_src,
258 unsigned num_components, unsigned first_component);
259 void emit_cs_terminate();
260 fs_reg *emit_cs_work_group_id_setup();
261
262 void emit_barrier();
263
264 void emit_shader_time_begin();
265 void emit_shader_time_end();
266 void SHADER_TIME_ADD(const brw::fs_builder &bld,
267 int shader_time_subindex,
268 fs_reg value);
269
270 fs_reg get_timestamp(const brw::fs_builder &bld);
271
272 struct brw_reg interp_reg(int location, int channel);
273
274 int implied_mrf_writes(fs_inst *inst);
275
276 virtual void dump_instructions();
277 virtual void dump_instructions(const char *name);
278 void dump_instruction(backend_instruction *inst);
279 void dump_instruction(backend_instruction *inst, FILE *file);
280
281 const void *const key;
282 const struct brw_sampler_prog_key_data *key_tex;
283
284 struct brw_gs_compile *gs_compile;
285
286 struct brw_stage_prog_data *prog_data;
287 struct gl_program *prog;
288
289 const struct brw_vue_map *input_vue_map;
290
291 int *virtual_grf_start;
292 int *virtual_grf_end;
293 brw::fs_live_variables *live_intervals;
294
295 int *regs_live_at_ip;
296
297 /** Number of uniform variable components visited. */
298 unsigned uniforms;
299
300 /** Byte-offset for the next available spot in the scratch space buffer. */
301 unsigned last_scratch;
302
303 /**
304 * Array mapping UNIFORM register numbers to the pull parameter index,
305 * or -1 if this uniform register isn't being uploaded as a pull constant.
306 */
307 int *pull_constant_loc;
308
309 /**
310 * Array mapping UNIFORM register numbers to the push parameter index,
311 * or -1 if this uniform register isn't being uploaded as a push constant.
312 */
313 int *push_constant_loc;
314
315 fs_reg frag_depth;
316 fs_reg frag_stencil;
317 fs_reg sample_mask;
318 fs_reg outputs[VARYING_SLOT_MAX];
319 fs_reg dual_src_output;
320 int first_non_payload_grf;
321 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
322 unsigned max_grf;
323
324 fs_reg *nir_locals;
325 fs_reg *nir_ssa_values;
326 fs_reg *nir_system_values;
327
328 bool failed;
329 char *fail_msg;
330
331 /** Register numbers for thread payload fields. */
332 struct thread_payload {
333 uint8_t source_depth_reg;
334 uint8_t source_w_reg;
335 uint8_t aa_dest_stencil_reg;
336 uint8_t dest_depth_reg;
337 uint8_t sample_pos_reg;
338 uint8_t sample_mask_in_reg;
339 uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT];
340 uint8_t local_invocation_id_reg;
341
342 /** The number of thread payload registers the hardware will supply. */
343 uint8_t num_regs;
344 } payload;
345
346 bool source_depth_to_render_target;
347 bool runtime_check_aads_emit;
348
349 fs_reg pixel_x;
350 fs_reg pixel_y;
351 fs_reg wpos_w;
352 fs_reg pixel_w;
353 fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT];
354 fs_reg shader_start_time;
355 fs_reg userplane[MAX_CLIP_PLANES];
356 fs_reg final_gs_vertex_count;
357 fs_reg control_data_bits;
358 fs_reg invocation_id;
359
360 unsigned grf_used;
361 bool spilled_any_registers;
362
363 const unsigned dispatch_width; /**< 8, 16 or 32 */
364 unsigned min_dispatch_width;
365 unsigned max_dispatch_width;
366
367 int shader_time_index;
368
369 unsigned promoted_constants;
370 brw::fs_builder bld;
371 };
372
373 /**
374 * The fragment shader code generator.
375 *
376 * Translates FS IR to actual i965 assembly code.
377 */
378 class fs_generator
379 {
380 public:
381 fs_generator(const struct brw_compiler *compiler, void *log_data,
382 void *mem_ctx,
383 const void *key,
384 struct brw_stage_prog_data *prog_data,
385 unsigned promoted_constants,
386 bool runtime_check_aads_emit,
387 gl_shader_stage stage);
388 ~fs_generator();
389
390 void enable_debug(const char *shader_name);
391 int generate_code(const cfg_t *cfg, int dispatch_width);
392 const unsigned *get_assembly(unsigned int *assembly_size);
393
394 private:
395 void fire_fb_write(fs_inst *inst,
396 struct brw_reg payload,
397 struct brw_reg implied_header,
398 GLuint nr);
399 void generate_fb_write(fs_inst *inst, struct brw_reg payload);
400 void generate_fb_read(fs_inst *inst, struct brw_reg dst,
401 struct brw_reg payload);
402 void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
403 void generate_urb_write(fs_inst *inst, struct brw_reg payload);
404 void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
405 void generate_barrier(fs_inst *inst, struct brw_reg src);
406 void generate_linterp(fs_inst *inst, struct brw_reg dst,
407 struct brw_reg *src);
408 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
409 struct brw_reg surface_index,
410 struct brw_reg sampler_index);
411 void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
412 struct brw_reg src,
413 struct brw_reg surf_index);
414 void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
415 void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src);
416 void generate_scratch_write(fs_inst *inst, struct brw_reg src);
417 void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
418 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
419 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
420 struct brw_reg index,
421 struct brw_reg offset);
422 void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
423 struct brw_reg dst,
424 struct brw_reg surf_index,
425 struct brw_reg payload);
426 void generate_varying_pull_constant_load_gen4(fs_inst *inst,
427 struct brw_reg dst,
428 struct brw_reg index);
429 void generate_varying_pull_constant_load_gen7(fs_inst *inst,
430 struct brw_reg dst,
431 struct brw_reg index,
432 struct brw_reg offset);
433 void generate_mov_dispatch_to_flags(fs_inst *inst);
434
435 void generate_pixel_interpolator_query(fs_inst *inst,
436 struct brw_reg dst,
437 struct brw_reg src,
438 struct brw_reg msg_data,
439 unsigned msg_type);
440
441 void generate_set_sample_id(fs_inst *inst,
442 struct brw_reg dst,
443 struct brw_reg src0,
444 struct brw_reg src1);
445
446 void generate_discard_jump(fs_inst *inst);
447
448 void generate_pack_half_2x16_split(fs_inst *inst,
449 struct brw_reg dst,
450 struct brw_reg x,
451 struct brw_reg y);
452 void generate_unpack_half_2x16_split(fs_inst *inst,
453 struct brw_reg dst,
454 struct brw_reg src);
455
456 void generate_shader_time_add(fs_inst *inst,
457 struct brw_reg payload,
458 struct brw_reg offset,
459 struct brw_reg value);
460
461 void generate_mov_indirect(fs_inst *inst,
462 struct brw_reg dst,
463 struct brw_reg reg,
464 struct brw_reg indirect_byte_offset);
465
466 bool patch_discard_jumps_to_fb_writes();
467
468 const struct brw_compiler *compiler;
469 void *log_data; /* Passed to compiler->*_log functions */
470
471 const struct gen_device_info *devinfo;
472
473 struct brw_codegen *p;
474 const void * const key;
475 struct brw_stage_prog_data * const prog_data;
476
477 unsigned dispatch_width; /**< 8, 16 or 32 */
478
479 exec_list discard_halt_patches;
480 unsigned promoted_constants;
481 bool runtime_check_aads_emit;
482 bool debug_flag;
483 const char *shader_name;
484 gl_shader_stage stage;
485 void *mem_ctx;
486 };
487
488 void shuffle_32bit_load_result_to_64bit_data(const brw::fs_builder &bld,
489 const fs_reg &dst,
490 const fs_reg &src,
491 uint32_t components);
492
493 void shuffle_64bit_data_for_32bit_write(const brw::fs_builder &bld,
494 const fs_reg &dst,
495 const fs_reg &src,
496 uint32_t components);
497 fs_reg setup_imm_df(const brw::fs_builder &bld,
498 double v);
499
500 enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode,
501 nir_intrinsic_op op);
502
503 #endif /* BRW_FS_H */