2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
33 #include "util/mesa-sha1.h"
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg
*reg
)
40 return BRW_ARCHITECTURE_REGISTER_FILE
;
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
51 unreachable("not reached");
53 return BRW_ARCHITECTURE_REGISTER_FILE
;
57 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
58 fs_reg
*reg
, bool compressed
)
60 struct brw_reg brw_reg
;
64 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
67 if (reg
->stride
== 0) {
68 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
70 /* From the Haswell PRM:
72 * "VertStride must be used to cross GRF register boundaries. This
73 * rule implies that elements within a 'Width' cannot cross GRF
76 * The maximum width value that could satisfy this restriction is:
78 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
80 /* Because the hardware can only split source regions at a whole
81 * multiple of width during decompression (i.e. vertically), clamp
82 * the value obtained above to the physical execution size of a
83 * single decompressed chunk of the instruction:
85 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
88 const unsigned max_hw_width
= 16;
90 /* XXX - The equation above is strictly speaking not correct on
91 * hardware that supports unbalanced GRF writes -- On Gen9+
92 * each decompressed chunk of the instruction may have a
93 * different execution size when the number of components
94 * written to each destination GRF is not the same.
96 if (reg
->stride
> 4) {
97 assert(reg
!= &inst
->dst
);
98 assert(reg
->stride
* type_sz(reg
->type
) <= REG_SIZE
);
99 brw_reg
= brw_vecn_reg(1, brw_file_from_reg(reg
), reg
->nr
, 0);
100 brw_reg
= stride(brw_reg
, reg
->stride
, 1, 0);
102 const unsigned width
= MIN3(reg_width
, phys_width
, max_hw_width
);
103 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
104 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
107 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
108 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
109 * "Each DF (Double Float) operand uses an element size of 4 rather
110 * than 8 and all regioning parameters are twice what the values
111 * would be based on the true element size: ExecSize, Width,
112 * HorzStride, and VertStride. Each DF operand uses a pair of
113 * channels and all masking and swizzing should be adjusted
116 * From the IvyBridge PRM (Special Requirements for Handling Double
117 * Precision Data Types, page 71):
118 * "In Align1 mode, all regioning parameters like stride, execution
119 * size, and width must use the syntax of a pair of packed
120 * floats. The offsets for these data types must be 64-bit
121 * aligned. The execution size and regioning parameters are in terms
124 * Summarized: when handling DF-typed arguments, ExecSize,
125 * VertStride, and Width must be doubled.
127 * It applies to BayTrail too.
129 if (type_sz(reg
->type
) == 8) {
131 if (brw_reg
.vstride
> 0)
133 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
136 /* When converting from DF->F, we set the destination stride to 2
137 * because each d2f conversion implicitly writes 2 floats, being
138 * the first one the converted value. IVB/BYT actually writes two
139 * F components per SIMD channel, and every other component is
140 * filled with garbage.
142 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
143 type_sz(inst
->dst
.type
) < 8) {
144 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
150 brw_reg
= retype(brw_reg
, reg
->type
);
151 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
152 brw_reg
.abs
= reg
->abs
;
153 brw_reg
.negate
= reg
->negate
;
158 assert(reg
->offset
== 0);
159 brw_reg
= reg
->as_brw_reg();
162 /* Probably unused. */
163 brw_reg
= brw_null_reg();
167 unreachable("not reached");
170 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
171 * region, but on IVB and BYT DF regions must be programmed in terms of
172 * floats. A <0,2,1> region accomplishes this.
174 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
175 type_sz(reg
->type
) == 8 &&
176 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
177 brw_reg
.width
== BRW_WIDTH_1
&&
178 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
179 brw_reg
.width
= BRW_WIDTH_2
;
180 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
186 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
188 struct brw_stage_prog_data
*prog_data
,
189 struct shader_stats shader_stats
,
190 bool runtime_check_aads_emit
,
191 gl_shader_stage stage
)
193 : compiler(compiler
), log_data(log_data
),
194 devinfo(compiler
->devinfo
),
195 prog_data(prog_data
),
196 shader_stats(shader_stats
),
197 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
198 stage(stage
), mem_ctx(mem_ctx
)
200 p
= rzalloc(mem_ctx
, struct brw_codegen
);
201 brw_init_codegen(devinfo
, p
, mem_ctx
);
203 /* In the FS code generator, we are very careful to ensure that we always
204 * set the right execution size so we don't need the EU code to "help" us
205 * by trying to infer it. Sometimes, it infers the wrong thing.
207 p
->automatic_exec_sizes
= false;
210 fs_generator::~fs_generator()
214 class ip_record
: public exec_node
{
216 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
227 fs_generator::patch_discard_jumps_to_fb_writes()
229 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
232 int scale
= brw_jump_scale(p
->devinfo
);
234 /* There is a somewhat strange undocumented requirement of using
235 * HALT, according to the simulator. If some channel has HALTed to
236 * a particular UIP, then by the end of the program, every channel
237 * must have HALTed to that UIP. Furthermore, the tracking is a
238 * stack, so you can't do the final halt of a UIP after starting
239 * halting to a new UIP.
241 * Symptoms of not emitting this instruction on actual hardware
242 * included GPU hangs and sparkly rendering on the piglit discard
245 brw_inst
*last_halt
= gen6_HALT(p
);
246 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
247 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
251 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
252 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
254 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
255 /* HALT takes a half-instruction distance from the pre-incremented IP. */
256 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
259 this->discard_halt_patches
.make_empty();
264 fs_generator::generate_send(fs_inst
*inst
,
267 struct brw_reg ex_desc
,
268 struct brw_reg payload
,
269 struct brw_reg payload2
)
271 const bool dst_is_null
= dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
272 dst
.nr
== BRW_ARF_NULL
;
273 const unsigned rlen
= dst_is_null
? 0 : inst
->size_written
/ REG_SIZE
;
275 uint32_t desc_imm
= inst
->desc
|
276 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
);
278 uint32_t ex_desc_imm
= brw_message_ex_desc(devinfo
, inst
->ex_mlen
);
280 if (ex_desc
.file
!= BRW_IMMEDIATE_VALUE
|| ex_desc
.ud
|| ex_desc_imm
) {
281 /* If we have any sort of extended descriptor, then we need SENDS. This
282 * also covers the dual-payload case because ex_mlen goes in ex_desc.
284 brw_send_indirect_split_message(p
, inst
->sfid
, dst
, payload
, payload2
,
285 desc
, desc_imm
, ex_desc
, ex_desc_imm
,
288 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDSC
);
290 brw_send_indirect_message(p
, inst
->sfid
, dst
, payload
, desc
, desc_imm
,
293 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
298 fs_generator::fire_fb_write(fs_inst
*inst
,
299 struct brw_reg payload
,
300 struct brw_reg implied_header
,
303 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
305 if (devinfo
->gen
< 6) {
306 brw_push_insn_state(p
);
307 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
308 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
309 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
310 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
311 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
312 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
313 brw_pop_insn_state(p
);
316 uint32_t msg_control
= brw_fb_write_msg_control(inst
, prog_data
);
318 /* We assume render targets start at 0, because headerless FB write
319 * messages set "Render Target Index" to 0. Using a different binding
320 * table index would make it impossible to use headerless messages.
322 const uint32_t surf_index
= inst
->target
;
324 brw_inst
*insn
= brw_fb_WRITE(p
,
326 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
333 inst
->header_size
!= 0);
335 if (devinfo
->gen
>= 6)
336 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
340 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
342 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
343 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
344 brw_set_default_flag_reg(p
, 0, 0);
347 const struct brw_reg implied_header
=
348 devinfo
->gen
< 6 ? payload
: brw_null_reg();
350 if (inst
->base_mrf
>= 0)
351 payload
= brw_message_reg(inst
->base_mrf
);
353 if (!runtime_check_aads_emit
) {
354 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
356 /* This can only happen in gen < 6 */
357 assert(devinfo
->gen
< 6);
359 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
361 /* Check runtime bit to detect if we have to send AA data or not */
362 brw_push_insn_state(p
);
363 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
364 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
367 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
369 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
371 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
372 brw_pop_insn_state(p
);
374 /* Don't send AA data */
375 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
377 brw_land_fwd_jump(p
, jmp
);
378 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
383 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
384 struct brw_reg payload
)
386 assert(inst
->size_written
% REG_SIZE
== 0);
387 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
388 /* We assume that render targets start at binding table index 0. */
389 const unsigned surf_index
= inst
->target
;
391 gen9_fb_READ(p
, dst
, payload
, surf_index
,
392 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
393 prog_data
->persample_dispatch
);
397 fs_generator::generate_mov_indirect(fs_inst
*inst
,
400 struct brw_reg indirect_byte_offset
)
402 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
403 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
404 assert(!reg
.abs
&& !reg
.negate
);
405 assert(reg
.type
== dst
.type
);
407 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
409 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
410 imm_byte_offset
+= indirect_byte_offset
.ud
;
412 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
413 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
414 brw_MOV(p
, dst
, reg
);
416 /* Prior to Broadwell, there are only 8 address registers. */
417 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
419 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
420 struct brw_reg addr
= vec8(brw_address_reg(0));
422 /* The destination stride of an instruction (in bytes) must be greater
423 * than or equal to the size of the rest of the instruction. Since the
424 * address register is of type UW, we can't use a D-type instruction.
425 * In order to get around this, re retype to UW and use a stride.
427 indirect_byte_offset
=
428 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
430 /* There are a number of reasons why we don't use the base offset here.
431 * One reason is that the field is only 9 bits which means we can only
432 * use it to access the first 16 GRFs. Also, from the Haswell PRM
433 * section "Register Region Restrictions":
435 * "The lower bits of the AddressImmediate must not overflow to
436 * change the register address. The lower 5 bits of Address
437 * Immediate when added to lower 5 bits of address register gives
438 * the sub-register offset. The upper bits of Address Immediate
439 * when added to upper bits of address register gives the register
440 * address. Any overflow from sub-register offset is dropped."
442 * Since the indirect may cause us to cross a register boundary, this
443 * makes the base offset almost useless. We could try and do something
444 * clever where we use a actual base offset if base_offset % 32 == 0 but
445 * that would mean we were generating different code depending on the
446 * base offset. Instead, for the sake of consistency, we'll just do the
447 * add ourselves. This restriction is only listed in the Haswell PRM
448 * but empirical testing indicates that it applies on all older
449 * generations and is lifted on Broadwell.
451 * In the end, while base_offset is nice to look at in the generated
452 * code, using it saves us 0 instructions and would require quite a bit
453 * of case-by-case work. It's just not worth it.
455 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
457 if (type_sz(reg
.type
) > 4 &&
458 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
459 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
) ||
460 !devinfo
->has_64bit_types
)) {
461 /* IVB has an issue (which we found empirically) where it reads two
462 * address register components per channel for indirectly addressed
465 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
467 * "When source or destination datatype is 64b or operation is
468 * integer DWord multiply, indirect addressing must not be used."
470 * To work around both of these, we do two integer MOVs insead of one
471 * 64-bit MOV. Because no double value should ever cross a register
472 * boundary, it's safe to use the immediate offset in the indirect
473 * here to handle adding 4 bytes to the offset and avoid the extra
474 * ADD to the register file.
476 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
477 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
478 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
479 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
481 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
483 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
485 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
486 !inst
->get_next()->is_tail_sentinel() &&
487 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
488 /* From the Sandybridge PRM:
490 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
491 * instruction that “indexed/indirect” source AND is followed
492 * by a send, the instruction requires a “Switch”. This is to
493 * avoid race condition where send may dispatch before MRF is
496 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
503 fs_generator::generate_shuffle(fs_inst
*inst
,
508 /* Ivy bridge has some strange behavior that makes this a real pain to
509 * implement for 64-bit values so we just don't bother.
511 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
513 /* Because we're using the address register, we're limited to 8-wide
514 * execution on gen7. On gen8, we're limited to 16-wide by the address
515 * register file and 8-wide for 64-bit types. We could try and make this
516 * instruction splittable higher up in the compiler but that gets weird
517 * because it reads all of the channels regardless of execution size. It's
518 * easier just to split it here.
520 const unsigned lower_width
=
521 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
522 8 : MIN2(16, inst
->exec_size
);
524 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
525 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
526 brw_set_default_group(p
, group
);
528 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
529 idx
.file
== BRW_IMMEDIATE_VALUE
) {
530 /* Trivial, the source is already uniform or the index is a constant.
531 * We will typically not get here if the optimizer is doing its job,
532 * but asserting would be mean.
534 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
535 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
537 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
538 struct brw_reg addr
= vec8(brw_address_reg(0));
540 struct brw_reg group_idx
= suboffset(idx
, group
);
542 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
543 /* Things get grumpy if the register is too wide. */
548 assert(type_sz(group_idx
.type
) <= 4);
549 if (type_sz(group_idx
.type
) == 4) {
550 /* The destination stride of an instruction (in bytes) must be
551 * greater than or equal to the size of the rest of the
552 * instruction. Since the address register is of type UW, we
553 * can't use a D-type instruction. In order to get around this,
554 * re retype to UW and use a stride.
556 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
559 /* Take into account the component size and horizontal stride. */
560 assert(src
.vstride
== src
.hstride
+ src
.width
);
561 brw_SHL(p
, addr
, group_idx
,
562 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
565 /* Add on the register start offset */
566 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
568 if (type_sz(src
.type
) > 4 &&
569 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
570 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
571 /* IVB has an issue (which we found empirically) where it reads
572 * two address register components per channel for indirectly
573 * addressed 64-bit sources.
575 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
577 * "When source or destination datatype is 64b or operation is
578 * integer DWord multiply, indirect addressing must not be
581 * To work around both of these, we do two integer MOVs insead of
582 * one 64-bit MOV. Because no double value should ever cross a
583 * register boundary, it's safe to use the immediate offset in the
584 * indirect here to handle adding 4 bytes to the offset and avoid
585 * the extra ADD to the register file.
587 struct brw_reg gdst
= suboffset(dst
, group
);
588 struct brw_reg dst_d
= retype(spread(gdst
, 2),
589 BRW_REGISTER_TYPE_D
);
590 assert(dst
.hstride
== 1);
592 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
593 brw_MOV(p
, byte_offset(dst_d
, 4),
594 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
596 brw_MOV(p
, suboffset(dst
, group
* dst
.hstride
),
597 retype(brw_VxH_indirect(0, 0), src
.type
));
604 fs_generator::generate_quad_swizzle(const fs_inst
*inst
,
605 struct brw_reg dst
, struct brw_reg src
,
608 /* Requires a quad. */
609 assert(inst
->exec_size
>= 4);
611 if (src
.file
== BRW_IMMEDIATE_VALUE
||
612 has_scalar_region(src
)) {
613 /* The value is uniform across all channels */
614 brw_MOV(p
, dst
, src
);
616 } else if (devinfo
->gen
< 11 && type_sz(src
.type
) == 4) {
617 /* This only works on 8-wide 32-bit values */
618 assert(inst
->exec_size
== 8);
619 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
620 assert(src
.vstride
== src
.width
+ 1);
621 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
622 struct brw_reg swiz_src
= stride(src
, 4, 4, 1);
623 swiz_src
.swizzle
= swiz
;
624 brw_MOV(p
, dst
, swiz_src
);
627 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
628 assert(src
.vstride
== src
.width
+ 1);
629 const struct brw_reg src_0
= suboffset(src
, BRW_GET_SWZ(swiz
, 0));
632 case BRW_SWIZZLE_XXXX
:
633 case BRW_SWIZZLE_YYYY
:
634 case BRW_SWIZZLE_ZZZZ
:
635 case BRW_SWIZZLE_WWWW
:
636 brw_MOV(p
, dst
, stride(src_0
, 4, 4, 0));
639 case BRW_SWIZZLE_XXZZ
:
640 case BRW_SWIZZLE_YYWW
:
641 brw_MOV(p
, dst
, stride(src_0
, 2, 2, 0));
644 case BRW_SWIZZLE_XYXY
:
645 case BRW_SWIZZLE_ZWZW
:
646 assert(inst
->exec_size
== 4);
647 brw_MOV(p
, dst
, stride(src_0
, 0, 2, 1));
651 assert(inst
->force_writemask_all
);
652 brw_set_default_exec_size(p
, cvt(inst
->exec_size
/ 4) - 1);
654 for (unsigned c
= 0; c
< 4; c
++) {
655 brw_inst
*insn
= brw_MOV(
656 p
, stride(suboffset(dst
, c
),
657 4 * inst
->dst
.stride
, 1, 4 * inst
->dst
.stride
),
658 stride(suboffset(src
, BRW_GET_SWZ(swiz
, c
)), 4, 1, 0));
660 brw_inst_set_no_dd_clear(devinfo
, insn
, c
< 3);
661 brw_inst_set_no_dd_check(devinfo
, insn
, c
> 0);
670 fs_generator::generate_urb_read(fs_inst
*inst
,
672 struct brw_reg header
)
674 assert(inst
->size_written
% REG_SIZE
== 0);
675 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
676 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
678 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
679 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
680 brw_set_src0(p
, send
, header
);
681 brw_set_src1(p
, send
, brw_imm_ud(0u));
683 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
684 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
686 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
687 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
689 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
690 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
691 brw_inst_set_header_present(p
->devinfo
, send
, true);
692 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
696 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
700 /* WaClearTDRRegBeforeEOTForNonPS.
702 * WA: Clear tdr register before send EOT in all non-PS shader kernels
704 * mov(8) tdr0:ud 0x0:ud {NoMask}"
706 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
707 brw_push_insn_state(p
);
708 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
709 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
710 brw_pop_insn_state(p
);
713 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
715 brw_set_dest(p
, insn
, brw_null_reg());
716 brw_set_src0(p
, insn
, payload
);
717 brw_set_src1(p
, insn
, brw_imm_ud(0u));
719 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
720 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
722 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
723 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
724 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
726 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
727 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
728 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
730 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
731 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
732 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
733 brw_inst_set_header_present(p
->devinfo
, insn
, true);
734 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
738 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
740 struct brw_inst
*insn
;
742 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
744 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
745 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
746 brw_set_src1(p
, insn
, brw_imm_ud(0u));
748 /* Terminate a compute shader by sending a message to the thread spawner.
750 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
751 brw_inst_set_mlen(devinfo
, insn
, 1);
752 brw_inst_set_rlen(devinfo
, insn
, 0);
753 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
754 brw_inst_set_header_present(devinfo
, insn
, false);
756 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
757 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
759 /* Note that even though the thread has a URB resource associated with it,
760 * we set the "do not dereference URB" bit, because the URB resource is
761 * managed by the fixed-function unit, so it will free it automatically.
763 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
765 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
769 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
776 fs_generator::generate_linterp(fs_inst
*inst
,
777 struct brw_reg dst
, struct brw_reg
*src
)
781 * -----------------------------------
782 * | src1+0 | src1+1 | src1+2 | src1+3 |
783 * |-----------------------------------|
784 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
785 * -----------------------------------
787 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
789 * -----------------------------------
790 * | src1+0 | src1+1 | src1+2 | src1+3 |
791 * |-----------------------------------|
792 * |(x0, x1)|(y0, y1)| | | in SIMD8
793 * |-----------------------------------|
794 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
795 * -----------------------------------
797 * See also: emit_interpolation_setup_gen4().
799 struct brw_reg delta_x
= src
[0];
800 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
801 struct brw_reg interp
= src
[1];
804 /* nir_lower_interpolation() will do the lowering to MAD instructions for
807 assert(devinfo
->gen
< 11);
809 if (devinfo
->has_pln
) {
810 if (devinfo
->gen
<= 6 && (delta_x
.nr
& 1) != 0) {
811 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
813 * "[DevSNB]:<src1> must be even register aligned.
815 * This restriction is lifted on Ivy Bridge.
817 * This means that we need to split PLN into LINE+MAC on-the-fly.
818 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
819 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
820 * coordinate registers are laid out differently so we leave it as a
821 * SIMD16 instruction.
823 assert(inst
->exec_size
== 8 || inst
->exec_size
== 16);
824 assert(inst
->group
% 16 == 0);
826 brw_push_insn_state(p
);
827 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
829 /* Thanks to two accumulators, we can emit all the LINEs and then all
830 * the MACs. This improves parallelism a bit.
832 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
833 brw_inst
*line
= brw_LINE(p
, brw_null_reg(), interp
,
834 offset(delta_x
, g
* 2));
835 brw_inst_set_group(devinfo
, line
, inst
->group
+ g
* 8);
837 /* LINE writes the accumulator automatically on gen4-5. On Sandy
838 * Bridge and later, we have to explicitly enable it.
840 if (devinfo
->gen
>= 6)
841 brw_inst_set_acc_wr_control(p
->devinfo
, line
, true);
843 /* brw_set_default_saturate() is called before emitting
844 * instructions, so the saturate bit is set in each instruction,
845 * so we need to unset it on the LINE instructions.
847 brw_inst_set_saturate(p
->devinfo
, line
, false);
850 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
851 brw_inst
*mac
= brw_MAC(p
, offset(dst
, g
), suboffset(interp
, 1),
852 offset(delta_x
, g
* 2 + 1));
853 brw_inst_set_group(devinfo
, mac
, inst
->group
+ g
* 8);
854 brw_inst_set_cond_modifier(p
->devinfo
, mac
, inst
->conditional_mod
);
857 brw_pop_insn_state(p
);
861 brw_PLN(p
, dst
, interp
, delta_x
);
866 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
867 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
869 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
871 /* brw_set_default_saturate() is called before emitting instructions, so
872 * the saturate bit is set in each instruction, so we need to unset it on
873 * the first instruction.
875 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
882 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
885 struct brw_reg surf_index
)
887 assert(devinfo
->gen
>= 7);
888 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
893 switch (inst
->exec_size
) {
895 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
898 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
901 unreachable("Invalid width for texture instruction");
904 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
910 retype(dst
, BRW_REGISTER_TYPE_UW
),
915 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
916 rlen
, /* response length */
918 inst
->header_size
> 0,
920 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
924 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
,
925 struct brw_reg surface_index
,
926 struct brw_reg sampler_index
)
928 assert(devinfo
->gen
< 7);
929 assert(inst
->size_written
% REG_SIZE
== 0);
932 uint32_t return_format
;
934 /* Sampler EOT message of less than the dispatch width would kill the
935 * thread prematurely.
937 assert(!inst
->eot
|| inst
->exec_size
== dispatch_width
);
940 case BRW_REGISTER_TYPE_D
:
941 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
943 case BRW_REGISTER_TYPE_UD
:
944 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
947 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
951 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
952 * is set as part of the message descriptor. On gen4, the PRM seems to
953 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
954 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
955 * gone from the message descriptor entirely and you just get UINT32 all
956 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
957 * just stomp it to UINT32 all the time.
959 if (inst
->opcode
== SHADER_OPCODE_TXS
)
960 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
962 switch (inst
->exec_size
) {
964 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
967 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
970 unreachable("Invalid width for texture instruction");
973 if (devinfo
->gen
>= 5) {
974 switch (inst
->opcode
) {
975 case SHADER_OPCODE_TEX
:
976 if (inst
->shadow_compare
) {
977 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
979 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
983 if (inst
->shadow_compare
) {
984 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
986 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
989 case SHADER_OPCODE_TXL
:
990 if (inst
->shadow_compare
) {
991 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
993 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
996 case SHADER_OPCODE_TXS
:
997 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
999 case SHADER_OPCODE_TXD
:
1000 assert(!inst
->shadow_compare
);
1001 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
1003 case SHADER_OPCODE_TXF
:
1004 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1006 case SHADER_OPCODE_TXF_CMS
:
1007 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1009 case SHADER_OPCODE_LOD
:
1010 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1012 case SHADER_OPCODE_TG4
:
1013 assert(devinfo
->gen
== 6);
1014 assert(!inst
->shadow_compare
);
1015 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1017 case SHADER_OPCODE_SAMPLEINFO
:
1018 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1021 unreachable("not reached");
1024 switch (inst
->opcode
) {
1025 case SHADER_OPCODE_TEX
:
1026 /* Note that G45 and older determines shadow compare and dispatch width
1027 * from message length for most messages.
1029 if (inst
->exec_size
== 8) {
1030 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1031 if (inst
->shadow_compare
) {
1032 assert(inst
->mlen
== 6);
1034 assert(inst
->mlen
<= 4);
1037 if (inst
->shadow_compare
) {
1038 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1039 assert(inst
->mlen
== 9);
1041 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1042 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1047 if (inst
->shadow_compare
) {
1048 assert(inst
->exec_size
== 8);
1049 assert(inst
->mlen
== 6);
1050 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1052 assert(inst
->mlen
== 9);
1053 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1054 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1057 case SHADER_OPCODE_TXL
:
1058 if (inst
->shadow_compare
) {
1059 assert(inst
->exec_size
== 8);
1060 assert(inst
->mlen
== 6);
1061 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1063 assert(inst
->mlen
== 9);
1064 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1065 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1068 case SHADER_OPCODE_TXD
:
1069 /* There is no sample_d_c message; comparisons are done manually */
1070 assert(inst
->exec_size
== 8);
1071 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1072 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1074 case SHADER_OPCODE_TXF
:
1075 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1076 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1077 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1079 case SHADER_OPCODE_TXS
:
1080 assert(inst
->mlen
== 3);
1081 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1082 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1085 unreachable("not reached");
1088 assert(msg_type
!= -1);
1090 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1094 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1096 /* Load the message header if present. If there's a texture offset,
1097 * we need to set it up explicitly and load the offset bitfield.
1098 * Otherwise, we can use an implied move from g0 to the first message reg.
1100 struct brw_reg src
= brw_null_reg();
1101 if (inst
->header_size
!= 0) {
1102 if (devinfo
->gen
< 6 && !inst
->offset
) {
1103 /* Set up an implied move from g0 to the MRF. */
1104 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1106 assert(inst
->base_mrf
!= -1);
1107 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1109 brw_push_insn_state(p
);
1110 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1111 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1112 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1113 /* Explicitly set up the message header by copying g0 to the MRF. */
1114 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1116 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1118 /* Set the offset bits in DWord 2. */
1119 brw_MOV(p
, get_element_ud(header_reg
, 2),
1120 brw_imm_ud(inst
->offset
));
1123 brw_pop_insn_state(p
);
1127 uint32_t base_binding_table_index
;
1128 switch (inst
->opcode
) {
1129 case SHADER_OPCODE_TG4
:
1130 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
1133 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
1137 assert(surface_index
.file
== BRW_IMMEDIATE_VALUE
);
1138 assert(sampler_index
.file
== BRW_IMMEDIATE_VALUE
);
1141 retype(dst
, BRW_REGISTER_TYPE_UW
),
1144 surface_index
.ud
+ base_binding_table_index
,
1145 sampler_index
.ud
% 16,
1147 inst
->size_written
/ REG_SIZE
,
1149 inst
->header_size
!= 0,
1155 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1158 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1160 * Ideally, we want to produce:
1163 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1164 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1165 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1166 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1167 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1168 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1169 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1170 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1172 * and add another set of two more subspans if in 16-pixel dispatch mode.
1174 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1175 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1176 * pair. But the ideal approximation may impose a huge performance cost on
1177 * sample_d. On at least Haswell, sample_d instruction does some
1178 * optimizations if the same LOD is used for all pixels in the subspan.
1180 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1181 * appropriate swizzling.
1184 fs_generator::generate_ddx(const fs_inst
*inst
,
1185 struct brw_reg dst
, struct brw_reg src
)
1187 unsigned vstride
, width
;
1189 if (devinfo
->gen
>= 8) {
1190 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1191 /* produce accurate derivatives */
1192 vstride
= BRW_VERTICAL_STRIDE_2
;
1193 width
= BRW_WIDTH_2
;
1195 /* replicate the derivative at the top-left pixel to other pixels */
1196 vstride
= BRW_VERTICAL_STRIDE_4
;
1197 width
= BRW_WIDTH_4
;
1200 struct brw_reg src0
= byte_offset(src
, type_sz(src
.type
));;
1201 struct brw_reg src1
= src
;
1203 src0
.vstride
= vstride
;
1205 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1206 src1
.vstride
= vstride
;
1208 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1210 brw_ADD(p
, dst
, src0
, negate(src1
));
1212 /* On Haswell and earlier, the region used above appears to not work
1213 * correctly for compressed instructions. At least on Haswell and
1214 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1215 * would have to split to SIMD8 no matter which method we choose, we
1216 * may as well use ALIGN16 on all platforms gen7 and earlier.
1218 struct brw_reg src0
= stride(src
, 4, 4, 1);
1219 struct brw_reg src1
= stride(src
, 4, 4, 1);
1220 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1221 src0
.swizzle
= BRW_SWIZZLE_XXZZ
;
1222 src1
.swizzle
= BRW_SWIZZLE_YYWW
;
1224 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1225 src1
.swizzle
= BRW_SWIZZLE_YYYY
;
1228 brw_push_insn_state(p
);
1229 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1230 brw_ADD(p
, dst
, negate(src0
), src1
);
1231 brw_pop_insn_state(p
);
1235 /* The negate_value boolean is used to negate the derivative computation for
1236 * FBOs, since they place the origin at the upper left instead of the lower
1240 fs_generator::generate_ddy(const fs_inst
*inst
,
1241 struct brw_reg dst
, struct brw_reg src
)
1243 const uint32_t type_size
= type_sz(src
.type
);
1245 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1246 /* produce accurate derivatives.
1248 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
1249 * "Register Region Restrictions", Section "1. Special Restrictions":
1251 * "In Align16 mode, the channel selects and channel enables apply to
1252 * a pair of half-floats, because these parameters are defined for
1253 * DWord elements ONLY. This is applicable when both source and
1254 * destination are half-floats."
1256 * So for half-float operations we use the Gen11+ Align1 path. CHV
1257 * inherits its FP16 hardware from SKL, so it is not affected.
1259 if (devinfo
->gen
>= 11 ||
1260 (devinfo
->is_broadwell
&& src
.type
== BRW_REGISTER_TYPE_HF
)) {
1261 src
= stride(src
, 0, 2, 1);
1263 brw_push_insn_state(p
);
1264 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1265 for (uint32_t g
= 0; g
< inst
->exec_size
; g
+= 4) {
1266 brw_set_default_group(p
, inst
->group
+ g
);
1267 brw_ADD(p
, byte_offset(dst
, g
* type_size
),
1268 negate(byte_offset(src
, g
* type_size
)),
1269 byte_offset(src
, (g
+ 2) * type_size
));
1271 brw_pop_insn_state(p
);
1273 struct brw_reg src0
= stride(src
, 4, 4, 1);
1274 struct brw_reg src1
= stride(src
, 4, 4, 1);
1275 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1276 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1278 brw_push_insn_state(p
);
1279 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1280 brw_ADD(p
, dst
, negate(src0
), src1
);
1281 brw_pop_insn_state(p
);
1284 /* replicate the derivative at the top-left pixel to other pixels */
1285 if (devinfo
->gen
>= 8) {
1286 struct brw_reg src0
= byte_offset(stride(src
, 4, 4, 0), 0 * type_size
);
1287 struct brw_reg src1
= byte_offset(stride(src
, 4, 4, 0), 2 * type_size
);
1289 brw_ADD(p
, dst
, negate(src0
), src1
);
1291 /* On Haswell and earlier, the region used above appears to not work
1292 * correctly for compressed instructions. At least on Haswell and
1293 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1294 * would have to split to SIMD8 no matter which method we choose, we
1295 * may as well use ALIGN16 on all platforms gen7 and earlier.
1297 struct brw_reg src0
= stride(src
, 4, 4, 1);
1298 struct brw_reg src1
= stride(src
, 4, 4, 1);
1299 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1300 src1
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1302 brw_push_insn_state(p
);
1303 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1304 brw_ADD(p
, dst
, negate(src0
), src1
);
1305 brw_pop_insn_state(p
);
1311 fs_generator::generate_discard_jump(fs_inst
*)
1313 assert(devinfo
->gen
>= 6);
1315 /* This HALT will be patched up at FB write time to point UIP at the end of
1316 * the program, and at brw_uip_jip() JIP will be set to the end of the
1317 * current block (or the program).
1319 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1324 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1326 /* The 32-wide messages only respect the first 16-wide half of the channel
1327 * enable signals which are replicated identically for the second group of
1328 * 16 channels, so we cannot use them unless the write is marked
1329 * force_writemask_all.
1331 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1332 MIN2(16, inst
->exec_size
);
1333 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1334 assert(inst
->mlen
!= 0);
1336 brw_push_insn_state(p
);
1337 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1338 brw_set_default_compression(p
, lower_size
> 8);
1340 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1341 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1343 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1344 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1346 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1348 inst
->offset
+ block_size
* REG_SIZE
* i
);
1351 brw_pop_insn_state(p
);
1355 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1357 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1358 assert(inst
->mlen
!= 0);
1360 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1361 inst
->exec_size
/ 8, inst
->offset
);
1365 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1367 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1369 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1373 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1375 struct brw_reg index
,
1376 struct brw_reg offset
)
1378 assert(type_sz(dst
.type
) == 4);
1379 assert(inst
->mlen
!= 0);
1381 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1382 index
.type
== BRW_REGISTER_TYPE_UD
);
1383 uint32_t surf_index
= index
.ud
;
1385 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1386 offset
.type
== BRW_REGISTER_TYPE_UD
);
1387 uint32_t read_offset
= offset
.ud
;
1389 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1390 read_offset
, surf_index
);
1394 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1396 struct brw_reg index
,
1397 struct brw_reg payload
)
1399 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1400 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1401 assert(type_sz(dst
.type
) == 4);
1403 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1404 const uint32_t surf_index
= index
.ud
;
1406 brw_push_insn_state(p
);
1407 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1408 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1409 brw_pop_insn_state(p
);
1411 brw_inst_set_sfid(devinfo
, send
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
);
1412 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1413 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1414 brw_set_desc(p
, send
,
1415 brw_message_desc(devinfo
, 1, DIV_ROUND_UP(inst
->size_written
,
1417 brw_dp_read_desc(devinfo
, surf_index
,
1418 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1419 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1420 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1423 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1425 brw_push_insn_state(p
);
1426 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1428 /* a0.0 = surf_index & 0xff */
1429 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1430 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1431 brw_set_dest(p
, insn_and
, addr
);
1432 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1433 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1435 /* dst = send(payload, a0.0 | <descriptor>) */
1436 brw_send_indirect_message(
1437 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1438 retype(dst
, BRW_REGISTER_TYPE_UD
),
1439 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
,
1440 brw_message_desc(devinfo
, 1,
1441 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
), true) |
1442 brw_dp_read_desc(devinfo
, 0 /* surface */,
1443 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1444 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1445 BRW_DATAPORT_READ_TARGET_DATA_CACHE
),
1448 brw_pop_insn_state(p
);
1453 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1455 struct brw_reg index
)
1457 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1458 assert(inst
->header_size
!= 0);
1461 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1462 index
.type
== BRW_REGISTER_TYPE_UD
);
1463 uint32_t surf_index
= index
.ud
;
1465 uint32_t simd_mode
, rlen
, msg_type
;
1466 if (inst
->exec_size
== 16) {
1467 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1470 assert(inst
->exec_size
== 8);
1471 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1475 if (devinfo
->gen
>= 5)
1476 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1478 /* We always use the SIMD16 message so that we only have to load U, and
1481 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1482 assert(inst
->mlen
== 3);
1483 assert(inst
->size_written
== 8 * REG_SIZE
);
1485 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1488 struct brw_reg header
= brw_vec8_grf(0, 0);
1489 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1491 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1492 brw_inst_set_compression(devinfo
, send
, false);
1493 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1494 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1495 brw_set_src0(p
, send
, header
);
1496 if (devinfo
->gen
< 6)
1497 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1499 /* Our surface is set up as floats, regardless of what actual data is
1502 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1503 brw_set_desc(p
, send
,
1504 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
) |
1505 brw_sampler_desc(devinfo
, surf_index
,
1506 0, /* sampler (unused) */
1507 msg_type
, simd_mode
, return_format
));
1511 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1514 struct brw_reg msg_data
,
1517 const bool has_payload
= inst
->src
[0].file
!= BAD_FILE
;
1518 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1519 assert(inst
->size_written
% REG_SIZE
== 0);
1521 brw_pixel_interpolator_query(p
,
1522 retype(dst
, BRW_REGISTER_TYPE_UW
),
1523 /* If we don't have a payload, what we send doesn't matter */
1524 has_payload
? src
: brw_vec8_grf(0, 0),
1525 inst
->pi_noperspective
,
1528 has_payload
? 2 * inst
->exec_size
/ 8 : 1,
1529 inst
->size_written
/ REG_SIZE
);
1532 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1533 * the ADD instruction.
1536 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1538 struct brw_reg src0
,
1539 struct brw_reg src1
)
1541 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1542 dst
.type
== BRW_REGISTER_TYPE_UD
);
1543 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1544 src0
.type
== BRW_REGISTER_TYPE_UD
);
1546 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1547 const unsigned lower_size
= MIN2(inst
->exec_size
,
1548 devinfo
->gen
>= 8 ? 16 : 8);
1550 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1551 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1552 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1553 (i
* lower_size
/ (1 << src0
.width
))) *
1554 type_sz(src0
.type
) / REG_SIZE
),
1555 suboffset(reg
, i
* lower_size
/ 4));
1556 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1557 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1558 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1563 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1568 assert(devinfo
->gen
>= 7);
1569 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1570 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1571 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1573 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1575 * Because this instruction does not have a 16-bit floating-point type,
1576 * the destination data type must be Word (W).
1578 * The destination must be DWord-aligned and specify a horizontal stride
1579 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1580 * each destination channel and the upper word is not modified.
1582 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1584 /* Give each 32-bit channel of dst the form below, where "." means
1588 brw_F32TO16(p
, dst_w
, y
);
1593 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1595 /* And, finally the form of packHalf2x16's output:
1598 brw_F32TO16(p
, dst_w
, x
);
1602 fs_generator::generate_shader_time_add(fs_inst
*,
1603 struct brw_reg payload
,
1604 struct brw_reg offset
,
1605 struct brw_reg value
)
1607 assert(devinfo
->gen
>= 7);
1608 brw_push_insn_state(p
);
1609 brw_set_default_mask_control(p
, true);
1611 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1612 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1614 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1617 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1618 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1619 value
.width
= BRW_WIDTH_1
;
1620 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1621 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1623 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1626 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1627 * case, and we don't really care about squeezing every bit of performance
1628 * out of this path, so we just emit the MOVs from here.
1630 brw_MOV(p
, payload_offset
, offset
);
1631 brw_MOV(p
, payload_value
, value
);
1632 brw_shader_time_add(p
, payload
,
1633 prog_data
->binding_table
.shader_time_start
);
1634 brw_pop_insn_state(p
);
1638 fs_generator::enable_debug(const char *shader_name
)
1641 this->shader_name
= shader_name
;
1645 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
,
1646 struct brw_compile_stats
*stats
)
1648 /* align to 64 byte boundary. */
1649 while (p
->next_insn_offset
% 64)
1652 this->dispatch_width
= dispatch_width
;
1654 int start_offset
= p
->next_insn_offset
;
1655 int spill_count
= 0, fill_count
= 0;
1658 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1660 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1661 if (inst
->opcode
== SHADER_OPCODE_UNDEF
)
1664 struct brw_reg src
[4], dst
;
1665 unsigned int last_insn_offset
= p
->next_insn_offset
;
1666 bool multiple_instructions_emitted
= false;
1668 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1669 * "Register Region Restrictions" section: for BDW, SKL:
1671 * "A POW/FDIV operation must not be followed by an instruction
1672 * that requires two destination registers."
1674 * The documentation is often lacking annotations for Atom parts,
1675 * and empirically this affects CHV as well.
1677 if (devinfo
->gen
>= 8 &&
1678 devinfo
->gen
<= 9 &&
1680 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1681 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1682 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1684 last_insn_offset
= p
->next_insn_offset
;
1687 if (unlikely(debug_flag
))
1688 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1690 /* If the instruction writes to more than one register, it needs to be
1691 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1692 * hardware figures out by itself what the right compression mode is,
1693 * but we still need to know whether the instruction is compressed to
1694 * set up the source register regions appropriately.
1696 * XXX - This is wrong for instructions that write a single register but
1697 * read more than one which should strictly speaking be treated as
1698 * compressed. For instructions that don't write any registers it
1699 * relies on the destination being a null register of the correct
1700 * type and regioning so the instruction is considered compressed
1701 * or not accordingly.
1703 const bool compressed
=
1704 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1705 brw_set_default_compression(p
, compressed
);
1706 brw_set_default_group(p
, inst
->group
);
1708 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1709 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1710 &inst
->src
[i
], compressed
);
1711 /* The accumulator result appears to get used for the
1712 * conditional modifier generation. When negating a UD
1713 * value, there is a 33rd bit generated for the sign in the
1714 * accumulator value, so now you can't check, for example,
1715 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1717 assert(!inst
->conditional_mod
||
1718 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1719 !inst
->src
[i
].negate
);
1721 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1722 &inst
->dst
, compressed
);
1724 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1725 brw_set_default_predicate_control(p
, inst
->predicate
);
1726 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1727 /* On gen7 and above, hardware automatically adds the group onto the
1728 * flag subregister number. On Sandy Bridge and older, we have to do it
1731 const unsigned flag_subreg
= inst
->flag_subreg
+
1732 (devinfo
->gen
>= 7 ? 0 : inst
->group
/ 16);
1733 brw_set_default_flag_reg(p
, flag_subreg
/ 2, flag_subreg
% 2);
1734 brw_set_default_saturate(p
, inst
->saturate
);
1735 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1736 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1738 unsigned exec_size
= inst
->exec_size
;
1739 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1740 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1744 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1746 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1747 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1748 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1749 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1751 switch (inst
->opcode
) {
1752 case BRW_OPCODE_MOV
:
1753 brw_MOV(p
, dst
, src
[0]);
1755 case BRW_OPCODE_ADD
:
1756 brw_ADD(p
, dst
, src
[0], src
[1]);
1758 case BRW_OPCODE_MUL
:
1759 brw_MUL(p
, dst
, src
[0], src
[1]);
1761 case BRW_OPCODE_AVG
:
1762 brw_AVG(p
, dst
, src
[0], src
[1]);
1764 case BRW_OPCODE_MACH
:
1765 brw_MACH(p
, dst
, src
[0], src
[1]);
1768 case BRW_OPCODE_LINE
:
1769 brw_LINE(p
, dst
, src
[0], src
[1]);
1772 case BRW_OPCODE_MAD
:
1773 assert(devinfo
->gen
>= 6);
1774 if (devinfo
->gen
< 10)
1775 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1776 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1779 case BRW_OPCODE_LRP
:
1780 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1781 if (devinfo
->gen
< 10)
1782 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1783 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1786 case BRW_OPCODE_FRC
:
1787 brw_FRC(p
, dst
, src
[0]);
1789 case BRW_OPCODE_RNDD
:
1790 brw_RNDD(p
, dst
, src
[0]);
1792 case BRW_OPCODE_RNDE
:
1793 brw_RNDE(p
, dst
, src
[0]);
1795 case BRW_OPCODE_RNDZ
:
1796 brw_RNDZ(p
, dst
, src
[0]);
1799 case BRW_OPCODE_AND
:
1800 brw_AND(p
, dst
, src
[0], src
[1]);
1803 brw_OR(p
, dst
, src
[0], src
[1]);
1805 case BRW_OPCODE_XOR
:
1806 brw_XOR(p
, dst
, src
[0], src
[1]);
1808 case BRW_OPCODE_NOT
:
1809 brw_NOT(p
, dst
, src
[0]);
1811 case BRW_OPCODE_ASR
:
1812 brw_ASR(p
, dst
, src
[0], src
[1]);
1814 case BRW_OPCODE_SHR
:
1815 brw_SHR(p
, dst
, src
[0], src
[1]);
1817 case BRW_OPCODE_SHL
:
1818 brw_SHL(p
, dst
, src
[0], src
[1]);
1820 case BRW_OPCODE_ROL
:
1821 assert(devinfo
->gen
>= 11);
1822 assert(src
[0].type
== dst
.type
);
1823 brw_ROL(p
, dst
, src
[0], src
[1]);
1825 case BRW_OPCODE_ROR
:
1826 assert(devinfo
->gen
>= 11);
1827 assert(src
[0].type
== dst
.type
);
1828 brw_ROR(p
, dst
, src
[0], src
[1]);
1830 case BRW_OPCODE_F32TO16
:
1831 assert(devinfo
->gen
>= 7);
1832 brw_F32TO16(p
, dst
, src
[0]);
1834 case BRW_OPCODE_F16TO32
:
1835 assert(devinfo
->gen
>= 7);
1836 brw_F16TO32(p
, dst
, src
[0]);
1838 case BRW_OPCODE_CMP
:
1839 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1840 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1841 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1842 * implemented in the compiler is not sufficient. Overriding the
1843 * type when the destination is the null register is necessary but
1844 * not sufficient by itself.
1846 assert(dst
.nr
== BRW_ARF_NULL
);
1847 dst
.type
= BRW_REGISTER_TYPE_D
;
1849 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1851 case BRW_OPCODE_SEL
:
1852 brw_SEL(p
, dst
, src
[0], src
[1]);
1854 case BRW_OPCODE_CSEL
:
1855 assert(devinfo
->gen
>= 8);
1856 if (devinfo
->gen
< 10)
1857 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1858 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
1860 case BRW_OPCODE_BFREV
:
1861 assert(devinfo
->gen
>= 7);
1862 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1863 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1865 case BRW_OPCODE_FBH
:
1866 assert(devinfo
->gen
>= 7);
1867 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1869 case BRW_OPCODE_FBL
:
1870 assert(devinfo
->gen
>= 7);
1871 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1872 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1874 case BRW_OPCODE_LZD
:
1875 brw_LZD(p
, dst
, src
[0]);
1877 case BRW_OPCODE_CBIT
:
1878 assert(devinfo
->gen
>= 7);
1879 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1880 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1882 case BRW_OPCODE_ADDC
:
1883 assert(devinfo
->gen
>= 7);
1884 brw_ADDC(p
, dst
, src
[0], src
[1]);
1886 case BRW_OPCODE_SUBB
:
1887 assert(devinfo
->gen
>= 7);
1888 brw_SUBB(p
, dst
, src
[0], src
[1]);
1890 case BRW_OPCODE_MAC
:
1891 brw_MAC(p
, dst
, src
[0], src
[1]);
1894 case BRW_OPCODE_BFE
:
1895 assert(devinfo
->gen
>= 7);
1896 if (devinfo
->gen
< 10)
1897 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1898 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1901 case BRW_OPCODE_BFI1
:
1902 assert(devinfo
->gen
>= 7);
1903 brw_BFI1(p
, dst
, src
[0], src
[1]);
1905 case BRW_OPCODE_BFI2
:
1906 assert(devinfo
->gen
>= 7);
1907 if (devinfo
->gen
< 10)
1908 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1909 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1913 if (inst
->src
[0].file
!= BAD_FILE
) {
1914 /* The instruction has an embedded compare (only allowed on gen6) */
1915 assert(devinfo
->gen
== 6);
1916 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1918 brw_IF(p
, brw_get_default_exec_size(p
));
1922 case BRW_OPCODE_ELSE
:
1925 case BRW_OPCODE_ENDIF
:
1930 brw_DO(p
, brw_get_default_exec_size(p
));
1933 case BRW_OPCODE_BREAK
:
1936 case BRW_OPCODE_CONTINUE
:
1940 case BRW_OPCODE_WHILE
:
1945 case SHADER_OPCODE_RCP
:
1946 case SHADER_OPCODE_RSQ
:
1947 case SHADER_OPCODE_SQRT
:
1948 case SHADER_OPCODE_EXP2
:
1949 case SHADER_OPCODE_LOG2
:
1950 case SHADER_OPCODE_SIN
:
1951 case SHADER_OPCODE_COS
:
1952 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1953 if (devinfo
->gen
>= 6) {
1954 assert(inst
->mlen
== 0);
1955 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
1956 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
1957 src
[0], brw_null_reg());
1959 assert(inst
->mlen
>= 1);
1960 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
1962 brw_math_function(inst
->opcode
),
1963 inst
->base_mrf
, src
[0],
1964 BRW_MATH_PRECISION_FULL
);
1967 case SHADER_OPCODE_INT_QUOTIENT
:
1968 case SHADER_OPCODE_INT_REMAINDER
:
1969 case SHADER_OPCODE_POW
:
1970 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1971 if (devinfo
->gen
>= 6) {
1972 assert(inst
->mlen
== 0);
1973 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
1974 inst
->exec_size
== 8);
1975 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1977 assert(inst
->mlen
>= 1);
1978 assert(inst
->exec_size
== 8);
1979 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
1980 inst
->base_mrf
, src
[0],
1981 BRW_MATH_PRECISION_FULL
);
1984 case FS_OPCODE_LINTERP
:
1985 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
1987 case FS_OPCODE_PIXEL_X
:
1988 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1989 src
[0].subnr
= 0 * type_sz(src
[0].type
);
1990 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1992 case FS_OPCODE_PIXEL_Y
:
1993 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1994 src
[0].subnr
= 4 * type_sz(src
[0].type
);
1995 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1998 case SHADER_OPCODE_SEND
:
1999 generate_send(inst
, dst
, src
[0], src
[1], src
[2],
2000 inst
->ex_mlen
> 0 ? src
[3] : brw_null_reg());
2003 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2004 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2006 case SHADER_OPCODE_TEX
:
2008 case SHADER_OPCODE_TXD
:
2009 case SHADER_OPCODE_TXF
:
2010 case SHADER_OPCODE_TXF_CMS
:
2011 case SHADER_OPCODE_TXL
:
2012 case SHADER_OPCODE_TXS
:
2013 case SHADER_OPCODE_LOD
:
2014 case SHADER_OPCODE_TG4
:
2015 case SHADER_OPCODE_SAMPLEINFO
:
2016 assert(inst
->src
[0].file
== BAD_FILE
);
2017 generate_tex(inst
, dst
, src
[1], src
[2]);
2020 case FS_OPCODE_DDX_COARSE
:
2021 case FS_OPCODE_DDX_FINE
:
2022 generate_ddx(inst
, dst
, src
[0]);
2024 case FS_OPCODE_DDY_COARSE
:
2025 case FS_OPCODE_DDY_FINE
:
2026 generate_ddy(inst
, dst
, src
[0]);
2029 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2030 generate_scratch_write(inst
, src
[0]);
2034 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2035 generate_scratch_read(inst
, dst
);
2039 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2040 generate_scratch_read_gen7(inst
, dst
);
2044 case SHADER_OPCODE_MOV_INDIRECT
:
2045 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2048 case SHADER_OPCODE_URB_READ_SIMD8
:
2049 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2050 generate_urb_read(inst
, dst
, src
[0]);
2053 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2054 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2055 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2056 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2057 generate_urb_write(inst
, src
[0]);
2060 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2061 assert(inst
->force_writemask_all
);
2062 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2065 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2066 assert(inst
->force_writemask_all
);
2067 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2070 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2071 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2074 case FS_OPCODE_REP_FB_WRITE
:
2075 case FS_OPCODE_FB_WRITE
:
2076 generate_fb_write(inst
, src
[0]);
2079 case FS_OPCODE_FB_READ
:
2080 generate_fb_read(inst
, dst
, src
[0]);
2083 case FS_OPCODE_DISCARD_JUMP
:
2084 generate_discard_jump(inst
);
2087 case SHADER_OPCODE_SHADER_TIME_ADD
:
2088 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2091 case SHADER_OPCODE_MEMORY_FENCE
:
2092 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2093 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2094 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SEND
, src
[1].ud
, src
[2].ud
);
2097 case SHADER_OPCODE_INTERLOCK
:
2098 assert(devinfo
->gen
>= 9);
2099 /* The interlock is basically a memory fence issued via sendc */
2100 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SENDC
, false, /* bti */ 0);
2103 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2104 const struct brw_reg mask
=
2105 brw_stage_has_packed_dispatch(devinfo
, stage
,
2106 prog_data
) ? brw_imm_ud(~0u) :
2107 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2109 brw_find_live_channel(p
, dst
, mask
);
2113 case SHADER_OPCODE_BROADCAST
:
2114 assert(inst
->force_writemask_all
);
2115 brw_broadcast(p
, dst
, src
[0], src
[1]);
2118 case SHADER_OPCODE_SHUFFLE
:
2119 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2122 case SHADER_OPCODE_SEL_EXEC
:
2123 assert(inst
->force_writemask_all
);
2124 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2125 brw_MOV(p
, dst
, src
[1]);
2126 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2127 brw_MOV(p
, dst
, src
[0]);
2130 case SHADER_OPCODE_QUAD_SWIZZLE
:
2131 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2132 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2133 generate_quad_swizzle(inst
, dst
, src
[0], src
[1].ud
);
2136 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2137 assert(!src
[0].negate
&& !src
[0].abs
);
2138 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2139 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2140 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2141 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2142 const unsigned component
= src
[1].ud
;
2143 const unsigned cluster_size
= src
[2].ud
;
2144 unsigned vstride
= cluster_size
;
2145 unsigned width
= cluster_size
;
2147 /* The maximum exec_size is 32, but the maximum width is only 16. */
2148 if (inst
->exec_size
== width
) {
2153 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2155 if (type_sz(src
[0].type
) > 4 &&
2156 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2157 /* IVB has an issue (which we found empirically) where it reads
2158 * two address register components per channel for indirectly
2159 * addressed 64-bit sources.
2161 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2163 * "When source or destination datatype is 64b or operation is
2164 * integer DWord multiply, indirect addressing must not be
2167 * To work around both of these, we do two integer MOVs insead of
2168 * one 64-bit MOV. Because no double value should ever cross a
2169 * register boundary, it's safe to use the immediate offset in the
2170 * indirect here to handle adding 4 bytes to the offset and avoid
2171 * the extra ADD to the register file.
2173 assert(src
[0].type
== dst
.type
);
2174 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2175 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2176 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2177 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2179 brw_MOV(p
, dst
, strided
);
2184 case FS_OPCODE_SET_SAMPLE_ID
:
2185 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2188 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2189 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2192 case FS_OPCODE_PLACEHOLDER_HALT
:
2193 /* This is the place where the final HALT needs to be inserted if
2194 * we've emitted any discards. If not, this will emit no code.
2196 if (!patch_discard_jumps_to_fb_writes()) {
2197 if (unlikely(debug_flag
)) {
2198 disasm_info
->use_tail
= true;
2203 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2204 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2205 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2208 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2209 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2210 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2213 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2214 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2215 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2218 case CS_OPCODE_CS_TERMINATE
:
2219 generate_cs_terminate(inst
, src
[0]);
2222 case SHADER_OPCODE_BARRIER
:
2223 generate_barrier(inst
, src
[0]);
2226 case BRW_OPCODE_DIM
:
2227 assert(devinfo
->is_haswell
);
2228 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2229 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2230 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2233 case SHADER_OPCODE_RND_MODE
: {
2234 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2236 * Changes the floating point rounding mode updating the control
2237 * register field defined at cr0.0[5-6] bits.
2239 enum brw_rnd_mode mode
=
2240 (enum brw_rnd_mode
) (src
[0].d
<< BRW_CR0_RND_MODE_SHIFT
);
2241 brw_float_controls_mode(p
, mode
, BRW_CR0_RND_MODE_MASK
);
2245 case SHADER_OPCODE_FLOAT_CONTROL_MODE
:
2246 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2247 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2248 brw_float_controls_mode(p
, src
[0].d
, src
[1].d
);
2252 unreachable("Unsupported opcode");
2254 case SHADER_OPCODE_LOAD_PAYLOAD
:
2255 unreachable("Should be lowered by lower_load_payload()");
2258 if (multiple_instructions_emitted
)
2261 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2262 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2263 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2264 "emitting more than 1 instruction");
2266 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2268 if (inst
->conditional_mod
)
2269 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2270 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2271 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2275 brw_set_uip_jip(p
, start_offset
);
2277 /* end of program sentinel */
2278 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2283 if (unlikely(debug_flag
))
2285 brw_validate_instructions(devinfo
, p
->store
,
2287 p
->next_insn_offset
,
2290 int before_size
= p
->next_insn_offset
- start_offset
;
2291 brw_compact_instructions(p
, start_offset
, disasm_info
);
2292 int after_size
= p
->next_insn_offset
- start_offset
;
2294 if (unlikely(debug_flag
)) {
2295 unsigned char sha1
[21];
2298 _mesa_sha1_compute(p
->store
+ start_offset
/ sizeof(brw_inst
),
2300 _mesa_sha1_format(sha1buf
, sha1
);
2302 fprintf(stderr
, "Native code for %s (sha1 %s)\n"
2303 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
2304 "%d:%d spills:fills. "
2305 "scheduled with mode %s. "
2306 "Promoted %u constants. "
2307 "Compacted %d to %d bytes (%.0f%%)\n",
2308 shader_name
, sha1buf
,
2309 dispatch_width
, before_size
/ 16,
2310 loop_count
, cfg
->cycle_count
,
2311 spill_count
, fill_count
,
2312 shader_stats
.scheduler_mode
,
2313 shader_stats
.promoted_constants
,
2314 before_size
, after_size
,
2315 100.0f
* (before_size
- after_size
) / before_size
);
2317 /* overriding the shader makes disasm_info invalid */
2318 if (!brw_try_override_assembly(p
, start_offset
, sha1buf
)) {
2319 dump_assembly(p
->store
, disasm_info
);
2321 fprintf(stderr
, "Successfully overrode shader with sha1 %s\n\n", sha1buf
);
2324 ralloc_free(disasm_info
);
2327 compiler
->shader_debug_log(log_data
,
2328 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2329 "%d:%d spills:fills, "
2330 "scheduled with mode %s, "
2331 "Promoted %u constants, "
2332 "compacted %d to %d bytes.",
2333 _mesa_shader_stage_to_abbrev(stage
),
2334 dispatch_width
, before_size
/ 16,
2335 loop_count
, cfg
->cycle_count
,
2336 spill_count
, fill_count
,
2337 shader_stats
.scheduler_mode
,
2338 shader_stats
.promoted_constants
,
2339 before_size
, after_size
);
2341 stats
->dispatch_width
= dispatch_width
;
2342 stats
->instructions
= before_size
/ 16;
2343 stats
->loops
= loop_count
;
2344 stats
->cycles
= cfg
->cycle_count
;
2345 stats
->spills
= spill_count
;
2346 stats
->fills
= fill_count
;
2349 return start_offset
;
2353 fs_generator::get_assembly()
2355 return brw_get_program(p
, &prog_data
->program_size
);