2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
33 #include "util/mesa-sha1.h"
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg
*reg
)
40 return BRW_ARCHITECTURE_REGISTER_FILE
;
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
51 unreachable("not reached");
53 return BRW_ARCHITECTURE_REGISTER_FILE
;
57 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
58 fs_reg
*reg
, bool compressed
)
60 struct brw_reg brw_reg
;
64 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
67 if (reg
->stride
== 0) {
68 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
70 /* From the Haswell PRM:
72 * "VertStride must be used to cross GRF register boundaries. This
73 * rule implies that elements within a 'Width' cannot cross GRF
76 * The maximum width value that could satisfy this restriction is:
78 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
80 /* Because the hardware can only split source regions at a whole
81 * multiple of width during decompression (i.e. vertically), clamp
82 * the value obtained above to the physical execution size of a
83 * single decompressed chunk of the instruction:
85 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
88 const unsigned max_hw_width
= 16;
90 /* XXX - The equation above is strictly speaking not correct on
91 * hardware that supports unbalanced GRF writes -- On Gen9+
92 * each decompressed chunk of the instruction may have a
93 * different execution size when the number of components
94 * written to each destination GRF is not the same.
96 if (reg
->stride
> 4) {
97 assert(reg
!= &inst
->dst
);
98 assert(reg
->stride
* type_sz(reg
->type
) <= REG_SIZE
);
99 brw_reg
= brw_vecn_reg(1, brw_file_from_reg(reg
), reg
->nr
, 0);
100 brw_reg
= stride(brw_reg
, reg
->stride
, 1, 0);
102 const unsigned width
= MIN3(reg_width
, phys_width
, max_hw_width
);
103 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
104 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
107 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
108 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
109 * "Each DF (Double Float) operand uses an element size of 4 rather
110 * than 8 and all regioning parameters are twice what the values
111 * would be based on the true element size: ExecSize, Width,
112 * HorzStride, and VertStride. Each DF operand uses a pair of
113 * channels and all masking and swizzing should be adjusted
116 * From the IvyBridge PRM (Special Requirements for Handling Double
117 * Precision Data Types, page 71):
118 * "In Align1 mode, all regioning parameters like stride, execution
119 * size, and width must use the syntax of a pair of packed
120 * floats. The offsets for these data types must be 64-bit
121 * aligned. The execution size and regioning parameters are in terms
124 * Summarized: when handling DF-typed arguments, ExecSize,
125 * VertStride, and Width must be doubled.
127 * It applies to BayTrail too.
129 if (type_sz(reg
->type
) == 8) {
131 if (brw_reg
.vstride
> 0)
133 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
136 /* When converting from DF->F, we set the destination stride to 2
137 * because each d2f conversion implicitly writes 2 floats, being
138 * the first one the converted value. IVB/BYT actually writes two
139 * F components per SIMD channel, and every other component is
140 * filled with garbage.
142 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
143 type_sz(inst
->dst
.type
) < 8) {
144 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
150 brw_reg
= retype(brw_reg
, reg
->type
);
151 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
152 brw_reg
.abs
= reg
->abs
;
153 brw_reg
.negate
= reg
->negate
;
158 assert(reg
->offset
== 0);
159 brw_reg
= reg
->as_brw_reg();
162 /* Probably unused. */
163 brw_reg
= brw_null_reg();
167 unreachable("not reached");
170 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
171 * region, but on IVB and BYT DF regions must be programmed in terms of
172 * floats. A <0,2,1> region accomplishes this.
174 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
175 type_sz(reg
->type
) == 8 &&
176 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
177 brw_reg
.width
== BRW_WIDTH_1
&&
178 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
179 brw_reg
.width
= BRW_WIDTH_2
;
180 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
186 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
188 struct brw_stage_prog_data
*prog_data
,
189 struct shader_stats shader_stats
,
190 bool runtime_check_aads_emit
,
191 gl_shader_stage stage
)
193 : compiler(compiler
), log_data(log_data
),
194 devinfo(compiler
->devinfo
),
195 prog_data(prog_data
),
196 shader_stats(shader_stats
),
197 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
198 stage(stage
), mem_ctx(mem_ctx
)
200 p
= rzalloc(mem_ctx
, struct brw_codegen
);
201 brw_init_codegen(devinfo
, p
, mem_ctx
);
203 /* In the FS code generator, we are very careful to ensure that we always
204 * set the right execution size so we don't need the EU code to "help" us
205 * by trying to infer it. Sometimes, it infers the wrong thing.
207 p
->automatic_exec_sizes
= false;
210 fs_generator::~fs_generator()
214 class ip_record
: public exec_node
{
216 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
227 fs_generator::patch_discard_jumps_to_fb_writes()
229 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
232 int scale
= brw_jump_scale(p
->devinfo
);
234 /* There is a somewhat strange undocumented requirement of using
235 * HALT, according to the simulator. If some channel has HALTed to
236 * a particular UIP, then by the end of the program, every channel
237 * must have HALTed to that UIP. Furthermore, the tracking is a
238 * stack, so you can't do the final halt of a UIP after starting
239 * halting to a new UIP.
241 * Symptoms of not emitting this instruction on actual hardware
242 * included GPU hangs and sparkly rendering on the piglit discard
245 brw_inst
*last_halt
= gen6_HALT(p
);
246 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
247 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
251 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
252 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
254 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
255 /* HALT takes a half-instruction distance from the pre-incremented IP. */
256 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
259 this->discard_halt_patches
.make_empty();
264 fs_generator::generate_send(fs_inst
*inst
,
267 struct brw_reg ex_desc
,
268 struct brw_reg payload
,
269 struct brw_reg payload2
)
271 const bool dst_is_null
= dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
272 dst
.nr
== BRW_ARF_NULL
;
273 const unsigned rlen
= dst_is_null
? 0 : inst
->size_written
/ REG_SIZE
;
275 uint32_t desc_imm
= inst
->desc
|
276 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
);
278 uint32_t ex_desc_imm
= brw_message_ex_desc(devinfo
, inst
->ex_mlen
);
280 if (ex_desc
.file
!= BRW_IMMEDIATE_VALUE
|| ex_desc
.ud
|| ex_desc_imm
) {
281 /* If we have any sort of extended descriptor, then we need SENDS. This
282 * also covers the dual-payload case because ex_mlen goes in ex_desc.
284 brw_send_indirect_split_message(p
, inst
->sfid
, dst
, payload
, payload2
,
285 desc
, desc_imm
, ex_desc
, ex_desc_imm
,
288 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
,
289 devinfo
->gen
>= 12 ? BRW_OPCODE_SENDC
: BRW_OPCODE_SENDSC
);
291 brw_send_indirect_message(p
, inst
->sfid
, dst
, payload
, desc
, desc_imm
,
294 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
299 fs_generator::fire_fb_write(fs_inst
*inst
,
300 struct brw_reg payload
,
301 struct brw_reg implied_header
,
304 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
306 if (devinfo
->gen
< 6) {
307 brw_push_insn_state(p
);
308 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
309 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
310 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
311 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
312 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
313 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
314 brw_pop_insn_state(p
);
317 uint32_t msg_control
= brw_fb_write_msg_control(inst
, prog_data
);
319 /* We assume render targets start at 0, because headerless FB write
320 * messages set "Render Target Index" to 0. Using a different binding
321 * table index would make it impossible to use headerless messages.
323 const uint32_t surf_index
= inst
->target
;
325 brw_inst
*insn
= brw_fb_WRITE(p
,
327 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
334 inst
->header_size
!= 0);
336 if (devinfo
->gen
>= 6)
337 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
341 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
343 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
344 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
345 brw_set_default_flag_reg(p
, 0, 0);
348 const struct brw_reg implied_header
=
349 devinfo
->gen
< 6 ? payload
: brw_null_reg();
351 if (inst
->base_mrf
>= 0)
352 payload
= brw_message_reg(inst
->base_mrf
);
354 if (!runtime_check_aads_emit
) {
355 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
357 /* This can only happen in gen < 6 */
358 assert(devinfo
->gen
< 6);
360 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
362 /* Check runtime bit to detect if we have to send AA data or not */
363 brw_push_insn_state(p
);
364 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
365 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
368 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
370 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
372 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
373 brw_pop_insn_state(p
);
375 /* Don't send AA data */
376 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
378 brw_land_fwd_jump(p
, jmp
);
379 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
384 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
385 struct brw_reg payload
)
387 assert(inst
->size_written
% REG_SIZE
== 0);
388 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
389 /* We assume that render targets start at binding table index 0. */
390 const unsigned surf_index
= inst
->target
;
392 gen9_fb_READ(p
, dst
, payload
, surf_index
,
393 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
394 prog_data
->persample_dispatch
);
398 fs_generator::generate_mov_indirect(fs_inst
*inst
,
401 struct brw_reg indirect_byte_offset
)
403 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
404 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
405 assert(!reg
.abs
&& !reg
.negate
);
406 assert(reg
.type
== dst
.type
);
408 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
410 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
411 imm_byte_offset
+= indirect_byte_offset
.ud
;
413 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
414 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
415 brw_MOV(p
, dst
, reg
);
417 /* Prior to Broadwell, there are only 8 address registers. */
418 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
420 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
421 struct brw_reg addr
= vec8(brw_address_reg(0));
423 /* The destination stride of an instruction (in bytes) must be greater
424 * than or equal to the size of the rest of the instruction. Since the
425 * address register is of type UW, we can't use a D-type instruction.
426 * In order to get around this, re retype to UW and use a stride.
428 indirect_byte_offset
=
429 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
431 /* There are a number of reasons why we don't use the base offset here.
432 * One reason is that the field is only 9 bits which means we can only
433 * use it to access the first 16 GRFs. Also, from the Haswell PRM
434 * section "Register Region Restrictions":
436 * "The lower bits of the AddressImmediate must not overflow to
437 * change the register address. The lower 5 bits of Address
438 * Immediate when added to lower 5 bits of address register gives
439 * the sub-register offset. The upper bits of Address Immediate
440 * when added to upper bits of address register gives the register
441 * address. Any overflow from sub-register offset is dropped."
443 * Since the indirect may cause us to cross a register boundary, this
444 * makes the base offset almost useless. We could try and do something
445 * clever where we use a actual base offset if base_offset % 32 == 0 but
446 * that would mean we were generating different code depending on the
447 * base offset. Instead, for the sake of consistency, we'll just do the
448 * add ourselves. This restriction is only listed in the Haswell PRM
449 * but empirical testing indicates that it applies on all older
450 * generations and is lifted on Broadwell.
452 * In the end, while base_offset is nice to look at in the generated
453 * code, using it saves us 0 instructions and would require quite a bit
454 * of case-by-case work. It's just not worth it.
456 * There's some sort of HW bug on Gen12 which causes issues if we write
457 * to the address register in control-flow. Since we only ever touch
458 * the address register from the generator, we can easily enough work
459 * around it by setting NoMask on the add.
461 brw_push_insn_state(p
);
462 if (devinfo
->gen
== 12)
463 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
464 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
465 brw_pop_insn_state(p
);
466 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
468 if (type_sz(reg
.type
) > 4 &&
469 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
470 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
) ||
471 !devinfo
->has_64bit_float
)) {
472 /* IVB has an issue (which we found empirically) where it reads two
473 * address register components per channel for indirectly addressed
476 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
478 * "When source or destination datatype is 64b or operation is
479 * integer DWord multiply, indirect addressing must not be used."
481 * To work around both of these, we do two integer MOVs insead of one
482 * 64-bit MOV. Because no double value should ever cross a register
483 * boundary, it's safe to use the immediate offset in the indirect
484 * here to handle adding 4 bytes to the offset and avoid the extra
485 * ADD to the register file.
487 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
488 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
489 brw_set_default_swsb(p
, tgl_swsb_null());
490 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
491 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
493 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
495 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
497 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
498 !inst
->get_next()->is_tail_sentinel() &&
499 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
500 /* From the Sandybridge PRM:
502 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
503 * instruction that “indexed/indirect” source AND is followed
504 * by a send, the instruction requires a “Switch”. This is to
505 * avoid race condition where send may dispatch before MRF is
508 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
515 fs_generator::generate_shuffle(fs_inst
*inst
,
520 /* Ivy bridge has some strange behavior that makes this a real pain to
521 * implement for 64-bit values so we just don't bother.
523 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
525 /* Because we're using the address register, we're limited to 8-wide
526 * execution on gen7. On gen8, we're limited to 16-wide by the address
527 * register file and 8-wide for 64-bit types. We could try and make this
528 * instruction splittable higher up in the compiler but that gets weird
529 * because it reads all of the channels regardless of execution size. It's
530 * easier just to split it here.
532 const unsigned lower_width
=
533 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
534 8 : MIN2(16, inst
->exec_size
);
536 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
537 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
538 brw_set_default_group(p
, group
);
540 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
541 idx
.file
== BRW_IMMEDIATE_VALUE
) {
542 /* Trivial, the source is already uniform or the index is a constant.
543 * We will typically not get here if the optimizer is doing its job,
544 * but asserting would be mean.
546 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
547 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
549 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
550 struct brw_reg addr
= vec8(brw_address_reg(0));
552 struct brw_reg group_idx
= suboffset(idx
, group
);
554 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
555 /* Things get grumpy if the register is too wide. */
560 assert(type_sz(group_idx
.type
) <= 4);
561 if (type_sz(group_idx
.type
) == 4) {
562 /* The destination stride of an instruction (in bytes) must be
563 * greater than or equal to the size of the rest of the
564 * instruction. Since the address register is of type UW, we
565 * can't use a D-type instruction. In order to get around this,
566 * re retype to UW and use a stride.
568 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
571 /* Take into account the component size and horizontal stride. */
572 assert(src
.vstride
== src
.hstride
+ src
.width
);
573 brw_SHL(p
, addr
, group_idx
,
574 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
577 /* Add on the register start offset */
578 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
579 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
581 if (type_sz(src
.type
) > 4 &&
582 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
583 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
584 /* IVB has an issue (which we found empirically) where it reads
585 * two address register components per channel for indirectly
586 * addressed 64-bit sources.
588 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
590 * "When source or destination datatype is 64b or operation is
591 * integer DWord multiply, indirect addressing must not be
594 * To work around both of these, we do two integer MOVs insead of
595 * one 64-bit MOV. Because no double value should ever cross a
596 * register boundary, it's safe to use the immediate offset in the
597 * indirect here to handle adding 4 bytes to the offset and avoid
598 * the extra ADD to the register file.
600 struct brw_reg gdst
= suboffset(dst
, group
);
601 struct brw_reg dst_d
= retype(spread(gdst
, 2),
602 BRW_REGISTER_TYPE_D
);
603 assert(dst
.hstride
== 1);
605 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
606 brw_set_default_swsb(p
, tgl_swsb_null());
607 brw_MOV(p
, byte_offset(dst_d
, 4),
608 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
610 brw_MOV(p
, suboffset(dst
, group
* dst
.hstride
),
611 retype(brw_VxH_indirect(0, 0), src
.type
));
615 brw_set_default_swsb(p
, tgl_swsb_null());
620 fs_generator::generate_quad_swizzle(const fs_inst
*inst
,
621 struct brw_reg dst
, struct brw_reg src
,
624 /* Requires a quad. */
625 assert(inst
->exec_size
>= 4);
627 if (src
.file
== BRW_IMMEDIATE_VALUE
||
628 has_scalar_region(src
)) {
629 /* The value is uniform across all channels */
630 brw_MOV(p
, dst
, src
);
632 } else if (devinfo
->gen
< 11 && type_sz(src
.type
) == 4) {
633 /* This only works on 8-wide 32-bit values */
634 assert(inst
->exec_size
== 8);
635 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
636 assert(src
.vstride
== src
.width
+ 1);
637 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
638 struct brw_reg swiz_src
= stride(src
, 4, 4, 1);
639 swiz_src
.swizzle
= swiz
;
640 brw_MOV(p
, dst
, swiz_src
);
643 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
644 assert(src
.vstride
== src
.width
+ 1);
645 const struct brw_reg src_0
= suboffset(src
, BRW_GET_SWZ(swiz
, 0));
648 case BRW_SWIZZLE_XXXX
:
649 case BRW_SWIZZLE_YYYY
:
650 case BRW_SWIZZLE_ZZZZ
:
651 case BRW_SWIZZLE_WWWW
:
652 brw_MOV(p
, dst
, stride(src_0
, 4, 4, 0));
655 case BRW_SWIZZLE_XXZZ
:
656 case BRW_SWIZZLE_YYWW
:
657 brw_MOV(p
, dst
, stride(src_0
, 2, 2, 0));
660 case BRW_SWIZZLE_XYXY
:
661 case BRW_SWIZZLE_ZWZW
:
662 assert(inst
->exec_size
== 4);
663 brw_MOV(p
, dst
, stride(src_0
, 0, 2, 1));
667 assert(inst
->force_writemask_all
);
668 brw_set_default_exec_size(p
, cvt(inst
->exec_size
/ 4) - 1);
670 for (unsigned c
= 0; c
< 4; c
++) {
671 brw_inst
*insn
= brw_MOV(
672 p
, stride(suboffset(dst
, c
),
673 4 * inst
->dst
.stride
, 1, 4 * inst
->dst
.stride
),
674 stride(suboffset(src
, BRW_GET_SWZ(swiz
, c
)), 4, 1, 0));
676 if (devinfo
->gen
< 12) {
677 brw_inst_set_no_dd_clear(devinfo
, insn
, c
< 3);
678 brw_inst_set_no_dd_check(devinfo
, insn
, c
> 0);
681 brw_set_default_swsb(p
, tgl_swsb_null());
690 fs_generator::generate_urb_read(fs_inst
*inst
,
692 struct brw_reg header
)
694 assert(inst
->size_written
% REG_SIZE
== 0);
695 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
696 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
698 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
699 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
700 brw_set_src0(p
, send
, header
);
701 if (devinfo
->gen
< 12)
702 brw_set_src1(p
, send
, brw_imm_ud(0u));
704 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
705 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
707 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
708 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
710 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
711 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
712 brw_inst_set_header_present(p
->devinfo
, send
, true);
713 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
717 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
721 /* WaClearTDRRegBeforeEOTForNonPS.
723 * WA: Clear tdr register before send EOT in all non-PS shader kernels
725 * mov(8) tdr0:ud 0x0:ud {NoMask}"
727 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
728 brw_push_insn_state(p
);
729 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
730 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
731 brw_pop_insn_state(p
);
734 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
736 brw_set_dest(p
, insn
, brw_null_reg());
737 brw_set_src0(p
, insn
, payload
);
738 if (devinfo
->gen
< 12)
739 brw_set_src1(p
, insn
, brw_imm_ud(0u));
741 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
742 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
744 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
745 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
746 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
748 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
749 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
750 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
752 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
753 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
754 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
755 brw_inst_set_header_present(p
->devinfo
, insn
, true);
756 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
760 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
762 struct brw_inst
*insn
;
764 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
766 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
767 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
768 if (devinfo
->gen
< 12)
769 brw_set_src1(p
, insn
, brw_imm_ud(0u));
771 /* Terminate a compute shader by sending a message to the thread spawner.
773 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
774 brw_inst_set_mlen(devinfo
, insn
, 1);
775 brw_inst_set_rlen(devinfo
, insn
, 0);
776 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
777 brw_inst_set_header_present(devinfo
, insn
, false);
779 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
781 if (devinfo
->gen
< 11) {
782 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
784 /* Note that even though the thread has a URB resource associated with it,
785 * we set the "do not dereference URB" bit, because the URB resource is
786 * managed by the fixed-function unit, so it will free it automatically.
788 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
791 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
795 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
798 if (devinfo
->gen
>= 12) {
799 brw_set_default_swsb(p
, tgl_swsb_null());
800 brw_SYNC(p
, TGL_SYNC_BAR
);
807 fs_generator::generate_linterp(fs_inst
*inst
,
808 struct brw_reg dst
, struct brw_reg
*src
)
812 * -----------------------------------
813 * | src1+0 | src1+1 | src1+2 | src1+3 |
814 * |-----------------------------------|
815 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
816 * -----------------------------------
818 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
820 * -----------------------------------
821 * | src1+0 | src1+1 | src1+2 | src1+3 |
822 * |-----------------------------------|
823 * |(x0, x1)|(y0, y1)| | | in SIMD8
824 * |-----------------------------------|
825 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
826 * -----------------------------------
828 * See also: emit_interpolation_setup_gen4().
830 struct brw_reg delta_x
= src
[0];
831 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
832 struct brw_reg interp
= src
[1];
835 /* nir_lower_interpolation() will do the lowering to MAD instructions for
838 assert(devinfo
->gen
< 11);
840 if (devinfo
->has_pln
) {
841 if (devinfo
->gen
<= 6 && (delta_x
.nr
& 1) != 0) {
842 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
844 * "[DevSNB]:<src1> must be even register aligned.
846 * This restriction is lifted on Ivy Bridge.
848 * This means that we need to split PLN into LINE+MAC on-the-fly.
849 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
850 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
851 * coordinate registers are laid out differently so we leave it as a
852 * SIMD16 instruction.
854 assert(inst
->exec_size
== 8 || inst
->exec_size
== 16);
855 assert(inst
->group
% 16 == 0);
857 brw_push_insn_state(p
);
858 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
860 /* Thanks to two accumulators, we can emit all the LINEs and then all
861 * the MACs. This improves parallelism a bit.
863 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
864 brw_inst
*line
= brw_LINE(p
, brw_null_reg(), interp
,
865 offset(delta_x
, g
* 2));
866 brw_inst_set_group(devinfo
, line
, inst
->group
+ g
* 8);
868 /* LINE writes the accumulator automatically on gen4-5. On Sandy
869 * Bridge and later, we have to explicitly enable it.
871 if (devinfo
->gen
>= 6)
872 brw_inst_set_acc_wr_control(p
->devinfo
, line
, true);
874 /* brw_set_default_saturate() is called before emitting
875 * instructions, so the saturate bit is set in each instruction,
876 * so we need to unset it on the LINE instructions.
878 brw_inst_set_saturate(p
->devinfo
, line
, false);
881 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
882 brw_inst
*mac
= brw_MAC(p
, offset(dst
, g
), suboffset(interp
, 1),
883 offset(delta_x
, g
* 2 + 1));
884 brw_inst_set_group(devinfo
, mac
, inst
->group
+ g
* 8);
885 brw_inst_set_cond_modifier(p
->devinfo
, mac
, inst
->conditional_mod
);
888 brw_pop_insn_state(p
);
892 brw_PLN(p
, dst
, interp
, delta_x
);
897 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
898 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
900 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
902 /* brw_set_default_saturate() is called before emitting instructions, so
903 * the saturate bit is set in each instruction, so we need to unset it on
904 * the first instruction.
906 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
913 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
916 struct brw_reg surf_index
)
918 assert(devinfo
->gen
>= 7);
919 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
924 switch (inst
->exec_size
) {
926 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
929 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
932 unreachable("Invalid width for texture instruction");
935 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
941 retype(dst
, BRW_REGISTER_TYPE_UW
),
946 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
947 rlen
, /* response length */
949 inst
->header_size
> 0,
951 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
955 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
,
956 struct brw_reg surface_index
,
957 struct brw_reg sampler_index
)
959 assert(devinfo
->gen
< 7);
960 assert(inst
->size_written
% REG_SIZE
== 0);
963 uint32_t return_format
;
965 /* Sampler EOT message of less than the dispatch width would kill the
966 * thread prematurely.
968 assert(!inst
->eot
|| inst
->exec_size
== dispatch_width
);
971 case BRW_REGISTER_TYPE_D
:
972 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
974 case BRW_REGISTER_TYPE_UD
:
975 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
978 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
982 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
983 * is set as part of the message descriptor. On gen4, the PRM seems to
984 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
985 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
986 * gone from the message descriptor entirely and you just get UINT32 all
987 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
988 * just stomp it to UINT32 all the time.
990 if (inst
->opcode
== SHADER_OPCODE_TXS
)
991 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
993 switch (inst
->exec_size
) {
995 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
998 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1001 unreachable("Invalid width for texture instruction");
1004 if (devinfo
->gen
>= 5) {
1005 switch (inst
->opcode
) {
1006 case SHADER_OPCODE_TEX
:
1007 if (inst
->shadow_compare
) {
1008 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
1010 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
1014 if (inst
->shadow_compare
) {
1015 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
1017 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
1020 case SHADER_OPCODE_TXL
:
1021 if (inst
->shadow_compare
) {
1022 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
1024 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
1027 case SHADER_OPCODE_TXS
:
1028 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
1030 case SHADER_OPCODE_TXD
:
1031 assert(!inst
->shadow_compare
);
1032 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
1034 case SHADER_OPCODE_TXF
:
1035 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1037 case SHADER_OPCODE_TXF_CMS
:
1038 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1040 case SHADER_OPCODE_LOD
:
1041 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1043 case SHADER_OPCODE_TG4
:
1044 assert(devinfo
->gen
== 6);
1045 assert(!inst
->shadow_compare
);
1046 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1048 case SHADER_OPCODE_SAMPLEINFO
:
1049 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1052 unreachable("not reached");
1055 switch (inst
->opcode
) {
1056 case SHADER_OPCODE_TEX
:
1057 /* Note that G45 and older determines shadow compare and dispatch width
1058 * from message length for most messages.
1060 if (inst
->exec_size
== 8) {
1061 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1062 if (inst
->shadow_compare
) {
1063 assert(inst
->mlen
== 6);
1065 assert(inst
->mlen
<= 4);
1068 if (inst
->shadow_compare
) {
1069 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1070 assert(inst
->mlen
== 9);
1072 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1073 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1078 if (inst
->shadow_compare
) {
1079 assert(inst
->exec_size
== 8);
1080 assert(inst
->mlen
== 6);
1081 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1083 assert(inst
->mlen
== 9);
1084 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1085 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1088 case SHADER_OPCODE_TXL
:
1089 if (inst
->shadow_compare
) {
1090 assert(inst
->exec_size
== 8);
1091 assert(inst
->mlen
== 6);
1092 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1094 assert(inst
->mlen
== 9);
1095 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1096 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1099 case SHADER_OPCODE_TXD
:
1100 /* There is no sample_d_c message; comparisons are done manually */
1101 assert(inst
->exec_size
== 8);
1102 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1103 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1105 case SHADER_OPCODE_TXF
:
1106 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1107 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1108 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1110 case SHADER_OPCODE_TXS
:
1111 assert(inst
->mlen
== 3);
1112 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1113 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1116 unreachable("not reached");
1119 assert(msg_type
!= -1);
1121 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1125 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1127 /* Load the message header if present. If there's a texture offset,
1128 * we need to set it up explicitly and load the offset bitfield.
1129 * Otherwise, we can use an implied move from g0 to the first message reg.
1131 struct brw_reg src
= brw_null_reg();
1132 if (inst
->header_size
!= 0) {
1133 if (devinfo
->gen
< 6 && !inst
->offset
) {
1134 /* Set up an implied move from g0 to the MRF. */
1135 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1137 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1138 assert(inst
->base_mrf
!= -1);
1139 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1141 brw_push_insn_state(p
);
1142 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1143 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1144 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1145 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1146 /* Explicitly set up the message header by copying g0 to the MRF. */
1147 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1148 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
1150 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1152 /* Set the offset bits in DWord 2. */
1153 brw_MOV(p
, get_element_ud(header_reg
, 2),
1154 brw_imm_ud(inst
->offset
));
1157 brw_pop_insn_state(p
);
1158 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1162 uint32_t base_binding_table_index
;
1163 switch (inst
->opcode
) {
1164 case SHADER_OPCODE_TG4
:
1165 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
1168 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
1172 assert(surface_index
.file
== BRW_IMMEDIATE_VALUE
);
1173 assert(sampler_index
.file
== BRW_IMMEDIATE_VALUE
);
1176 retype(dst
, BRW_REGISTER_TYPE_UW
),
1179 surface_index
.ud
+ base_binding_table_index
,
1180 sampler_index
.ud
% 16,
1182 inst
->size_written
/ REG_SIZE
,
1184 inst
->header_size
!= 0,
1190 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1193 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1195 * Ideally, we want to produce:
1198 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1199 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1200 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1201 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1202 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1203 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1204 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1205 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1207 * and add another set of two more subspans if in 16-pixel dispatch mode.
1209 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1210 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1211 * pair. But the ideal approximation may impose a huge performance cost on
1212 * sample_d. On at least Haswell, sample_d instruction does some
1213 * optimizations if the same LOD is used for all pixels in the subspan.
1215 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1216 * appropriate swizzling.
1219 fs_generator::generate_ddx(const fs_inst
*inst
,
1220 struct brw_reg dst
, struct brw_reg src
)
1222 unsigned vstride
, width
;
1224 if (devinfo
->gen
>= 8) {
1225 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1226 /* produce accurate derivatives */
1227 vstride
= BRW_VERTICAL_STRIDE_2
;
1228 width
= BRW_WIDTH_2
;
1230 /* replicate the derivative at the top-left pixel to other pixels */
1231 vstride
= BRW_VERTICAL_STRIDE_4
;
1232 width
= BRW_WIDTH_4
;
1235 struct brw_reg src0
= byte_offset(src
, type_sz(src
.type
));;
1236 struct brw_reg src1
= src
;
1238 src0
.vstride
= vstride
;
1240 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1241 src1
.vstride
= vstride
;
1243 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1245 brw_ADD(p
, dst
, src0
, negate(src1
));
1247 /* On Haswell and earlier, the region used above appears to not work
1248 * correctly for compressed instructions. At least on Haswell and
1249 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1250 * would have to split to SIMD8 no matter which method we choose, we
1251 * may as well use ALIGN16 on all platforms gen7 and earlier.
1253 struct brw_reg src0
= stride(src
, 4, 4, 1);
1254 struct brw_reg src1
= stride(src
, 4, 4, 1);
1255 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1256 src0
.swizzle
= BRW_SWIZZLE_XXZZ
;
1257 src1
.swizzle
= BRW_SWIZZLE_YYWW
;
1259 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1260 src1
.swizzle
= BRW_SWIZZLE_YYYY
;
1263 brw_push_insn_state(p
);
1264 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1265 brw_ADD(p
, dst
, negate(src0
), src1
);
1266 brw_pop_insn_state(p
);
1270 /* The negate_value boolean is used to negate the derivative computation for
1271 * FBOs, since they place the origin at the upper left instead of the lower
1275 fs_generator::generate_ddy(const fs_inst
*inst
,
1276 struct brw_reg dst
, struct brw_reg src
)
1278 const uint32_t type_size
= type_sz(src
.type
);
1280 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1281 /* produce accurate derivatives.
1283 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
1284 * "Register Region Restrictions", Section "1. Special Restrictions":
1286 * "In Align16 mode, the channel selects and channel enables apply to
1287 * a pair of half-floats, because these parameters are defined for
1288 * DWord elements ONLY. This is applicable when both source and
1289 * destination are half-floats."
1291 * So for half-float operations we use the Gen11+ Align1 path. CHV
1292 * inherits its FP16 hardware from SKL, so it is not affected.
1294 if (devinfo
->gen
>= 11 ||
1295 (devinfo
->is_broadwell
&& src
.type
== BRW_REGISTER_TYPE_HF
)) {
1296 src
= stride(src
, 0, 2, 1);
1298 brw_push_insn_state(p
);
1299 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1300 for (uint32_t g
= 0; g
< inst
->exec_size
; g
+= 4) {
1301 brw_set_default_group(p
, inst
->group
+ g
);
1302 brw_ADD(p
, byte_offset(dst
, g
* type_size
),
1303 negate(byte_offset(src
, g
* type_size
)),
1304 byte_offset(src
, (g
+ 2) * type_size
));
1305 brw_set_default_swsb(p
, tgl_swsb_null());
1307 brw_pop_insn_state(p
);
1309 struct brw_reg src0
= stride(src
, 4, 4, 1);
1310 struct brw_reg src1
= stride(src
, 4, 4, 1);
1311 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1312 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1314 brw_push_insn_state(p
);
1315 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1316 brw_ADD(p
, dst
, negate(src0
), src1
);
1317 brw_pop_insn_state(p
);
1320 /* replicate the derivative at the top-left pixel to other pixels */
1321 if (devinfo
->gen
>= 8) {
1322 struct brw_reg src0
= byte_offset(stride(src
, 4, 4, 0), 0 * type_size
);
1323 struct brw_reg src1
= byte_offset(stride(src
, 4, 4, 0), 2 * type_size
);
1325 brw_ADD(p
, dst
, negate(src0
), src1
);
1327 /* On Haswell and earlier, the region used above appears to not work
1328 * correctly for compressed instructions. At least on Haswell and
1329 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1330 * would have to split to SIMD8 no matter which method we choose, we
1331 * may as well use ALIGN16 on all platforms gen7 and earlier.
1333 struct brw_reg src0
= stride(src
, 4, 4, 1);
1334 struct brw_reg src1
= stride(src
, 4, 4, 1);
1335 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1336 src1
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1338 brw_push_insn_state(p
);
1339 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1340 brw_ADD(p
, dst
, negate(src0
), src1
);
1341 brw_pop_insn_state(p
);
1347 fs_generator::generate_discard_jump(fs_inst
*)
1349 assert(devinfo
->gen
>= 6);
1351 /* This HALT will be patched up at FB write time to point UIP at the end of
1352 * the program, and at brw_uip_jip() JIP will be set to the end of the
1353 * current block (or the program).
1355 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1360 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1362 /* The 32-wide messages only respect the first 16-wide half of the channel
1363 * enable signals which are replicated identically for the second group of
1364 * 16 channels, so we cannot use them unless the write is marked
1365 * force_writemask_all.
1367 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1368 MIN2(16, inst
->exec_size
);
1369 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1370 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1371 assert(inst
->mlen
!= 0);
1373 brw_push_insn_state(p
);
1374 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1375 brw_set_default_compression(p
, lower_size
> 8);
1377 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1378 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1381 assert(swsb
.mode
& TGL_SBID_SET
);
1382 brw_set_default_swsb(p
, tgl_swsb_sbid(TGL_SBID_SRC
, swsb
.sbid
));
1384 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1387 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1388 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1390 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1391 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1393 inst
->offset
+ block_size
* REG_SIZE
* i
);
1396 brw_pop_insn_state(p
);
1400 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1402 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1403 assert(inst
->mlen
!= 0);
1405 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1406 inst
->exec_size
/ 8, inst
->offset
);
1410 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1412 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1414 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1418 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1420 struct brw_reg index
,
1421 struct brw_reg offset
)
1423 assert(type_sz(dst
.type
) == 4);
1424 assert(inst
->mlen
!= 0);
1426 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1427 index
.type
== BRW_REGISTER_TYPE_UD
);
1428 uint32_t surf_index
= index
.ud
;
1430 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1431 offset
.type
== BRW_REGISTER_TYPE_UD
);
1432 uint32_t read_offset
= offset
.ud
;
1434 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1435 read_offset
, surf_index
);
1439 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1441 struct brw_reg index
,
1442 struct brw_reg payload
)
1444 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1445 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1446 assert(type_sz(dst
.type
) == 4);
1448 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1449 const uint32_t surf_index
= index
.ud
;
1451 brw_push_insn_state(p
);
1452 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1453 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1454 brw_pop_insn_state(p
);
1456 brw_inst_set_sfid(devinfo
, send
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
);
1457 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1458 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1459 brw_set_desc(p
, send
,
1460 brw_message_desc(devinfo
, 1, DIV_ROUND_UP(inst
->size_written
,
1462 brw_dp_read_desc(devinfo
, surf_index
,
1463 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1464 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1465 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1468 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1469 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1471 brw_push_insn_state(p
);
1472 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1474 /* a0.0 = surf_index & 0xff */
1475 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1476 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1477 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1478 brw_set_dest(p
, insn_and
, addr
);
1479 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1480 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1482 /* dst = send(payload, a0.0 | <descriptor>) */
1483 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1484 brw_send_indirect_message(
1485 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1486 retype(dst
, BRW_REGISTER_TYPE_UD
),
1487 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
,
1488 brw_message_desc(devinfo
, 1,
1489 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
), true) |
1490 brw_dp_read_desc(devinfo
, 0 /* surface */,
1491 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1492 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1493 BRW_DATAPORT_READ_TARGET_DATA_CACHE
),
1496 brw_pop_insn_state(p
);
1501 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1503 struct brw_reg index
)
1505 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1506 assert(inst
->header_size
!= 0);
1509 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1510 index
.type
== BRW_REGISTER_TYPE_UD
);
1511 uint32_t surf_index
= index
.ud
;
1513 uint32_t simd_mode
, rlen
, msg_type
;
1514 if (inst
->exec_size
== 16) {
1515 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1518 assert(inst
->exec_size
== 8);
1519 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1523 if (devinfo
->gen
>= 5)
1524 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1526 /* We always use the SIMD16 message so that we only have to load U, and
1529 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1530 assert(inst
->mlen
== 3);
1531 assert(inst
->size_written
== 8 * REG_SIZE
);
1533 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1536 struct brw_reg header
= brw_vec8_grf(0, 0);
1537 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1539 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1540 brw_inst_set_compression(devinfo
, send
, false);
1541 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1542 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1543 brw_set_src0(p
, send
, header
);
1544 if (devinfo
->gen
< 6)
1545 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1547 /* Our surface is set up as floats, regardless of what actual data is
1550 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1551 brw_set_desc(p
, send
,
1552 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
) |
1553 brw_sampler_desc(devinfo
, surf_index
,
1554 0, /* sampler (unused) */
1555 msg_type
, simd_mode
, return_format
));
1559 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1562 struct brw_reg msg_data
,
1565 const bool has_payload
= inst
->src
[0].file
!= BAD_FILE
;
1566 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1567 assert(inst
->size_written
% REG_SIZE
== 0);
1569 brw_pixel_interpolator_query(p
,
1570 retype(dst
, BRW_REGISTER_TYPE_UW
),
1571 /* If we don't have a payload, what we send doesn't matter */
1572 has_payload
? src
: brw_vec8_grf(0, 0),
1573 inst
->pi_noperspective
,
1576 has_payload
? 2 * inst
->exec_size
/ 8 : 1,
1577 inst
->size_written
/ REG_SIZE
);
1580 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1581 * the ADD instruction.
1584 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1586 struct brw_reg src0
,
1587 struct brw_reg src1
)
1589 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1590 dst
.type
== BRW_REGISTER_TYPE_UD
);
1591 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1592 src0
.type
== BRW_REGISTER_TYPE_UD
);
1594 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1595 const unsigned lower_size
= MIN2(inst
->exec_size
,
1596 devinfo
->gen
>= 8 ? 16 : 8);
1598 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1599 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1600 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1601 (i
* lower_size
/ (1 << src0
.width
))) *
1602 type_sz(src0
.type
) / REG_SIZE
),
1603 suboffset(reg
, i
* lower_size
/ 4));
1604 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1605 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1606 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1607 brw_set_default_swsb(p
, tgl_swsb_null());
1612 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1617 assert(devinfo
->gen
>= 7);
1618 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1619 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1620 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1622 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1624 * Because this instruction does not have a 16-bit floating-point type,
1625 * the destination data type must be Word (W).
1627 * The destination must be DWord-aligned and specify a horizontal stride
1628 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1629 * each destination channel and the upper word is not modified.
1631 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1633 /* Give each 32-bit channel of dst the form below, where "." means
1637 brw_F32TO16(p
, dst_w
, y
);
1642 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
1643 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1645 /* And, finally the form of packHalf2x16's output:
1648 brw_F32TO16(p
, dst_w
, x
);
1652 fs_generator::generate_shader_time_add(fs_inst
*,
1653 struct brw_reg payload
,
1654 struct brw_reg offset
,
1655 struct brw_reg value
)
1657 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1659 assert(devinfo
->gen
>= 7);
1660 brw_push_insn_state(p
);
1661 brw_set_default_mask_control(p
, true);
1662 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1664 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1665 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1667 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1670 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1671 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1672 value
.width
= BRW_WIDTH_1
;
1673 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1674 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1676 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1679 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1680 * case, and we don't really care about squeezing every bit of performance
1681 * out of this path, so we just emit the MOVs from here.
1683 brw_MOV(p
, payload_offset
, offset
);
1684 brw_set_default_swsb(p
, tgl_swsb_null());
1685 brw_MOV(p
, payload_value
, value
);
1686 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1687 brw_shader_time_add(p
, payload
,
1688 prog_data
->binding_table
.shader_time_start
);
1689 brw_pop_insn_state(p
);
1693 fs_generator::enable_debug(const char *shader_name
)
1696 this->shader_name
= shader_name
;
1700 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
,
1701 struct brw_compile_stats
*stats
)
1703 /* align to 64 byte boundary. */
1704 while (p
->next_insn_offset
% 64)
1707 this->dispatch_width
= dispatch_width
;
1709 int start_offset
= p
->next_insn_offset
;
1711 /* `send_count` explicitly does not include spills or fills, as we'd
1712 * like to use it as a metric for intentional memory access or other
1713 * shared function use. Otherwise, subtle changes to scheduling or
1714 * register allocation could cause it to fluctuate wildly - and that
1715 * effect is already counted in spill/fill counts.
1717 int spill_count
= 0, fill_count
= 0;
1718 int loop_count
= 0, send_count
= 0;
1719 bool is_accum_used
= false;
1721 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1723 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1724 if (inst
->opcode
== SHADER_OPCODE_UNDEF
)
1727 struct brw_reg src
[4], dst
;
1728 unsigned int last_insn_offset
= p
->next_insn_offset
;
1729 bool multiple_instructions_emitted
= false;
1731 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1732 * "Register Region Restrictions" section: for BDW, SKL:
1734 * "A POW/FDIV operation must not be followed by an instruction
1735 * that requires two destination registers."
1737 * The documentation is often lacking annotations for Atom parts,
1738 * and empirically this affects CHV as well.
1740 if (devinfo
->gen
>= 8 &&
1741 devinfo
->gen
<= 9 &&
1743 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1744 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1745 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1747 last_insn_offset
= p
->next_insn_offset
;
1750 /* GEN:BUG:14010017096:
1752 * Clear accumulator register before end of thread.
1754 if (inst
->eot
&& is_accum_used
&& devinfo
->gen
>= 12) {
1755 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
1756 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1757 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1758 brw_MOV(p
, brw_acc_reg(8), brw_imm_f(0.0f
));
1759 last_insn_offset
= p
->next_insn_offset
;
1762 if (!is_accum_used
&& !inst
->eot
) {
1763 is_accum_used
= inst
->writes_accumulator_implicitly(devinfo
) ||
1764 inst
->dst
.is_accumulator();
1767 if (unlikely(debug_flag
))
1768 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1770 /* If the instruction writes to more than one register, it needs to be
1771 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1772 * hardware figures out by itself what the right compression mode is,
1773 * but we still need to know whether the instruction is compressed to
1774 * set up the source register regions appropriately.
1776 * XXX - This is wrong for instructions that write a single register but
1777 * read more than one which should strictly speaking be treated as
1778 * compressed. For instructions that don't write any registers it
1779 * relies on the destination being a null register of the correct
1780 * type and regioning so the instruction is considered compressed
1781 * or not accordingly.
1783 const bool compressed
=
1784 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1785 brw_set_default_compression(p
, compressed
);
1786 brw_set_default_group(p
, inst
->group
);
1788 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1789 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1790 &inst
->src
[i
], compressed
);
1791 /* The accumulator result appears to get used for the
1792 * conditional modifier generation. When negating a UD
1793 * value, there is a 33rd bit generated for the sign in the
1794 * accumulator value, so now you can't check, for example,
1795 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1797 assert(!inst
->conditional_mod
||
1798 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1799 !inst
->src
[i
].negate
);
1801 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1802 &inst
->dst
, compressed
);
1804 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1805 brw_set_default_predicate_control(p
, inst
->predicate
);
1806 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1807 /* On gen7 and above, hardware automatically adds the group onto the
1808 * flag subregister number. On Sandy Bridge and older, we have to do it
1811 const unsigned flag_subreg
= inst
->flag_subreg
+
1812 (devinfo
->gen
>= 7 ? 0 : inst
->group
/ 16);
1813 brw_set_default_flag_reg(p
, flag_subreg
/ 2, flag_subreg
% 2);
1814 brw_set_default_saturate(p
, inst
->saturate
);
1815 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1816 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1817 brw_set_default_swsb(p
, inst
->sched
);
1819 unsigned exec_size
= inst
->exec_size
;
1820 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1821 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1825 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1827 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1828 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1829 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1830 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1832 switch (inst
->opcode
) {
1833 case BRW_OPCODE_SYNC
:
1834 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
1835 brw_SYNC(p
, tgl_sync_function(src
[0].ud
));
1837 case BRW_OPCODE_MOV
:
1838 brw_MOV(p
, dst
, src
[0]);
1840 case BRW_OPCODE_ADD
:
1841 brw_ADD(p
, dst
, src
[0], src
[1]);
1843 case BRW_OPCODE_MUL
:
1844 brw_MUL(p
, dst
, src
[0], src
[1]);
1846 case BRW_OPCODE_AVG
:
1847 brw_AVG(p
, dst
, src
[0], src
[1]);
1849 case BRW_OPCODE_MACH
:
1850 brw_MACH(p
, dst
, src
[0], src
[1]);
1853 case BRW_OPCODE_LINE
:
1854 brw_LINE(p
, dst
, src
[0], src
[1]);
1857 case BRW_OPCODE_MAD
:
1858 assert(devinfo
->gen
>= 6);
1859 if (devinfo
->gen
< 10)
1860 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1861 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1864 case BRW_OPCODE_LRP
:
1865 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1866 if (devinfo
->gen
< 10)
1867 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1868 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1871 case BRW_OPCODE_FRC
:
1872 brw_FRC(p
, dst
, src
[0]);
1874 case BRW_OPCODE_RNDD
:
1875 brw_RNDD(p
, dst
, src
[0]);
1877 case BRW_OPCODE_RNDE
:
1878 brw_RNDE(p
, dst
, src
[0]);
1880 case BRW_OPCODE_RNDZ
:
1881 brw_RNDZ(p
, dst
, src
[0]);
1884 case BRW_OPCODE_AND
:
1885 brw_AND(p
, dst
, src
[0], src
[1]);
1888 brw_OR(p
, dst
, src
[0], src
[1]);
1890 case BRW_OPCODE_XOR
:
1891 brw_XOR(p
, dst
, src
[0], src
[1]);
1893 case BRW_OPCODE_NOT
:
1894 brw_NOT(p
, dst
, src
[0]);
1896 case BRW_OPCODE_ASR
:
1897 brw_ASR(p
, dst
, src
[0], src
[1]);
1899 case BRW_OPCODE_SHR
:
1900 brw_SHR(p
, dst
, src
[0], src
[1]);
1902 case BRW_OPCODE_SHL
:
1903 brw_SHL(p
, dst
, src
[0], src
[1]);
1905 case BRW_OPCODE_ROL
:
1906 assert(devinfo
->gen
>= 11);
1907 assert(src
[0].type
== dst
.type
);
1908 brw_ROL(p
, dst
, src
[0], src
[1]);
1910 case BRW_OPCODE_ROR
:
1911 assert(devinfo
->gen
>= 11);
1912 assert(src
[0].type
== dst
.type
);
1913 brw_ROR(p
, dst
, src
[0], src
[1]);
1915 case BRW_OPCODE_F32TO16
:
1916 assert(devinfo
->gen
>= 7);
1917 brw_F32TO16(p
, dst
, src
[0]);
1919 case BRW_OPCODE_F16TO32
:
1920 assert(devinfo
->gen
>= 7);
1921 brw_F16TO32(p
, dst
, src
[0]);
1923 case BRW_OPCODE_CMP
:
1924 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1925 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1926 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1927 * implemented in the compiler is not sufficient. Overriding the
1928 * type when the destination is the null register is necessary but
1929 * not sufficient by itself.
1931 assert(dst
.nr
== BRW_ARF_NULL
);
1932 dst
.type
= BRW_REGISTER_TYPE_D
;
1934 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1936 case BRW_OPCODE_SEL
:
1937 brw_SEL(p
, dst
, src
[0], src
[1]);
1939 case BRW_OPCODE_CSEL
:
1940 assert(devinfo
->gen
>= 8);
1941 if (devinfo
->gen
< 10)
1942 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1943 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
1945 case BRW_OPCODE_BFREV
:
1946 assert(devinfo
->gen
>= 7);
1947 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1948 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1950 case BRW_OPCODE_FBH
:
1951 assert(devinfo
->gen
>= 7);
1952 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1954 case BRW_OPCODE_FBL
:
1955 assert(devinfo
->gen
>= 7);
1956 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1957 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1959 case BRW_OPCODE_LZD
:
1960 brw_LZD(p
, dst
, src
[0]);
1962 case BRW_OPCODE_CBIT
:
1963 assert(devinfo
->gen
>= 7);
1964 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1965 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1967 case BRW_OPCODE_ADDC
:
1968 assert(devinfo
->gen
>= 7);
1969 brw_ADDC(p
, dst
, src
[0], src
[1]);
1971 case BRW_OPCODE_SUBB
:
1972 assert(devinfo
->gen
>= 7);
1973 brw_SUBB(p
, dst
, src
[0], src
[1]);
1975 case BRW_OPCODE_MAC
:
1976 brw_MAC(p
, dst
, src
[0], src
[1]);
1979 case BRW_OPCODE_BFE
:
1980 assert(devinfo
->gen
>= 7);
1981 if (devinfo
->gen
< 10)
1982 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1983 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1986 case BRW_OPCODE_BFI1
:
1987 assert(devinfo
->gen
>= 7);
1988 brw_BFI1(p
, dst
, src
[0], src
[1]);
1990 case BRW_OPCODE_BFI2
:
1991 assert(devinfo
->gen
>= 7);
1992 if (devinfo
->gen
< 10)
1993 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1994 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1998 if (inst
->src
[0].file
!= BAD_FILE
) {
1999 /* The instruction has an embedded compare (only allowed on gen6) */
2000 assert(devinfo
->gen
== 6);
2001 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
2003 brw_IF(p
, brw_get_default_exec_size(p
));
2007 case BRW_OPCODE_ELSE
:
2010 case BRW_OPCODE_ENDIF
:
2015 brw_DO(p
, brw_get_default_exec_size(p
));
2018 case BRW_OPCODE_BREAK
:
2021 case BRW_OPCODE_CONTINUE
:
2025 case BRW_OPCODE_WHILE
:
2030 case SHADER_OPCODE_RCP
:
2031 case SHADER_OPCODE_RSQ
:
2032 case SHADER_OPCODE_SQRT
:
2033 case SHADER_OPCODE_EXP2
:
2034 case SHADER_OPCODE_LOG2
:
2035 case SHADER_OPCODE_SIN
:
2036 case SHADER_OPCODE_COS
:
2037 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2038 if (devinfo
->gen
>= 6) {
2039 assert(inst
->mlen
== 0);
2040 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
2041 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
2042 src
[0], brw_null_reg());
2044 assert(inst
->mlen
>= 1);
2045 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
2047 brw_math_function(inst
->opcode
),
2048 inst
->base_mrf
, src
[0],
2049 BRW_MATH_PRECISION_FULL
);
2053 case SHADER_OPCODE_INT_QUOTIENT
:
2054 case SHADER_OPCODE_INT_REMAINDER
:
2055 case SHADER_OPCODE_POW
:
2056 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2057 if (devinfo
->gen
>= 6) {
2058 assert(inst
->mlen
== 0);
2059 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
2060 inst
->exec_size
== 8);
2061 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
2063 assert(inst
->mlen
>= 1);
2064 assert(inst
->exec_size
== 8);
2065 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
2066 inst
->base_mrf
, src
[0],
2067 BRW_MATH_PRECISION_FULL
);
2071 case FS_OPCODE_LINTERP
:
2072 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
2074 case FS_OPCODE_PIXEL_X
:
2075 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2076 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2077 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2079 case FS_OPCODE_PIXEL_Y
:
2080 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2081 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2082 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2085 case SHADER_OPCODE_SEND
:
2086 generate_send(inst
, dst
, src
[0], src
[1], src
[2],
2087 inst
->ex_mlen
> 0 ? src
[3] : brw_null_reg());
2088 if ((inst
->desc
& 0xff) == BRW_BTI_STATELESS
||
2089 (inst
->desc
& 0xff) == GEN8_BTI_STATELESS_NON_COHERENT
) {
2090 if (inst
->size_written
)
2099 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2100 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2103 case SHADER_OPCODE_TEX
:
2105 case SHADER_OPCODE_TXD
:
2106 case SHADER_OPCODE_TXF
:
2107 case SHADER_OPCODE_TXF_CMS
:
2108 case SHADER_OPCODE_TXL
:
2109 case SHADER_OPCODE_TXS
:
2110 case SHADER_OPCODE_LOD
:
2111 case SHADER_OPCODE_TG4
:
2112 case SHADER_OPCODE_SAMPLEINFO
:
2113 assert(inst
->src
[0].file
== BAD_FILE
);
2114 generate_tex(inst
, dst
, src
[1], src
[2]);
2118 case FS_OPCODE_DDX_COARSE
:
2119 case FS_OPCODE_DDX_FINE
:
2120 generate_ddx(inst
, dst
, src
[0]);
2122 case FS_OPCODE_DDY_COARSE
:
2123 case FS_OPCODE_DDY_FINE
:
2124 generate_ddy(inst
, dst
, src
[0]);
2127 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2128 generate_scratch_write(inst
, src
[0]);
2132 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2133 generate_scratch_read(inst
, dst
);
2137 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2138 generate_scratch_read_gen7(inst
, dst
);
2142 case SHADER_OPCODE_MOV_INDIRECT
:
2143 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2146 case SHADER_OPCODE_URB_READ_SIMD8
:
2147 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2148 generate_urb_read(inst
, dst
, src
[0]);
2152 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2153 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2154 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2155 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2156 generate_urb_write(inst
, src
[0]);
2160 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2161 assert(inst
->force_writemask_all
);
2162 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2166 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2167 assert(inst
->force_writemask_all
);
2168 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2172 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2173 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2177 case FS_OPCODE_REP_FB_WRITE
:
2178 case FS_OPCODE_FB_WRITE
:
2179 generate_fb_write(inst
, src
[0]);
2183 case FS_OPCODE_FB_READ
:
2184 generate_fb_read(inst
, dst
, src
[0]);
2188 case FS_OPCODE_DISCARD_JUMP
:
2189 generate_discard_jump(inst
);
2192 case SHADER_OPCODE_SHADER_TIME_ADD
:
2193 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2196 case SHADER_OPCODE_MEMORY_FENCE
:
2197 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2198 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2199 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SEND
, src
[1].ud
, src
[2].ud
);
2203 case FS_OPCODE_SCHEDULING_FENCE
:
2204 if (unlikely(debug_flag
))
2205 disasm_info
->use_tail
= true;
2208 case SHADER_OPCODE_INTERLOCK
:
2209 assert(devinfo
->gen
>= 9);
2210 /* The interlock is basically a memory fence issued via sendc */
2211 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SENDC
, false, /* bti */ 0);
2214 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2215 const struct brw_reg mask
=
2216 brw_stage_has_packed_dispatch(devinfo
, stage
,
2217 prog_data
) ? brw_imm_ud(~0u) :
2218 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2220 brw_find_live_channel(p
, dst
, mask
);
2223 case FS_OPCODE_LOAD_LIVE_CHANNELS
: {
2224 assert(devinfo
->gen
>= 8);
2225 assert(inst
->force_writemask_all
&& inst
->group
== 0);
2226 assert(inst
->dst
.file
== BAD_FILE
);
2227 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
2228 brw_MOV(p
, retype(brw_flag_subreg(inst
->flag_subreg
),
2229 BRW_REGISTER_TYPE_UD
),
2230 retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD
));
2233 case SHADER_OPCODE_BROADCAST
:
2234 assert(inst
->force_writemask_all
);
2235 brw_broadcast(p
, dst
, src
[0], src
[1]);
2238 case SHADER_OPCODE_SHUFFLE
:
2239 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2242 case SHADER_OPCODE_SEL_EXEC
:
2243 assert(inst
->force_writemask_all
);
2244 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2245 brw_MOV(p
, dst
, src
[1]);
2246 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2247 brw_set_default_swsb(p
, tgl_swsb_null());
2248 brw_MOV(p
, dst
, src
[0]);
2251 case SHADER_OPCODE_QUAD_SWIZZLE
:
2252 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2253 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2254 generate_quad_swizzle(inst
, dst
, src
[0], src
[1].ud
);
2257 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2258 assert(!src
[0].negate
&& !src
[0].abs
);
2259 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2260 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2261 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2262 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2263 const unsigned component
= src
[1].ud
;
2264 const unsigned cluster_size
= src
[2].ud
;
2265 unsigned vstride
= cluster_size
;
2266 unsigned width
= cluster_size
;
2268 /* The maximum exec_size is 32, but the maximum width is only 16. */
2269 if (inst
->exec_size
== width
) {
2274 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2276 if (type_sz(src
[0].type
) > 4 &&
2277 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2278 /* IVB has an issue (which we found empirically) where it reads
2279 * two address register components per channel for indirectly
2280 * addressed 64-bit sources.
2282 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2284 * "When source or destination datatype is 64b or operation is
2285 * integer DWord multiply, indirect addressing must not be
2288 * To work around both of these, we do two integer MOVs insead of
2289 * one 64-bit MOV. Because no double value should ever cross a
2290 * register boundary, it's safe to use the immediate offset in the
2291 * indirect here to handle adding 4 bytes to the offset and avoid
2292 * the extra ADD to the register file.
2294 assert(src
[0].type
== dst
.type
);
2295 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2296 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2297 brw_set_default_swsb(p
, tgl_swsb_null());
2298 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2299 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2301 brw_MOV(p
, dst
, strided
);
2306 case FS_OPCODE_SET_SAMPLE_ID
:
2307 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2310 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2311 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2314 case FS_OPCODE_PLACEHOLDER_HALT
:
2315 /* This is the place where the final HALT needs to be inserted if
2316 * we've emitted any discards. If not, this will emit no code.
2318 if (!patch_discard_jumps_to_fb_writes()) {
2319 if (unlikely(debug_flag
)) {
2320 disasm_info
->use_tail
= true;
2325 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2326 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2327 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2331 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2332 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2333 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2337 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2338 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2339 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2343 case CS_OPCODE_CS_TERMINATE
:
2344 generate_cs_terminate(inst
, src
[0]);
2348 case SHADER_OPCODE_BARRIER
:
2349 generate_barrier(inst
, src
[0]);
2353 case BRW_OPCODE_DIM
:
2354 assert(devinfo
->is_haswell
);
2355 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2356 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2357 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2360 case SHADER_OPCODE_RND_MODE
: {
2361 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2363 * Changes the floating point rounding mode updating the control
2364 * register field defined at cr0.0[5-6] bits.
2366 enum brw_rnd_mode mode
=
2367 (enum brw_rnd_mode
) (src
[0].d
<< BRW_CR0_RND_MODE_SHIFT
);
2368 brw_float_controls_mode(p
, mode
, BRW_CR0_RND_MODE_MASK
);
2372 case SHADER_OPCODE_FLOAT_CONTROL_MODE
:
2373 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2374 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2375 brw_float_controls_mode(p
, src
[0].d
, src
[1].d
);
2379 unreachable("Unsupported opcode");
2381 case SHADER_OPCODE_LOAD_PAYLOAD
:
2382 unreachable("Should be lowered by lower_load_payload()");
2385 if (multiple_instructions_emitted
)
2388 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2389 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2390 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2391 "emitting more than 1 instruction");
2393 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2395 if (inst
->conditional_mod
)
2396 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2397 if (devinfo
->gen
< 12) {
2398 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2399 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2404 brw_set_uip_jip(p
, start_offset
);
2406 /* end of program sentinel */
2407 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2412 if (unlikely(debug_flag
))
2414 brw_validate_instructions(devinfo
, p
->store
,
2416 p
->next_insn_offset
,
2419 int before_size
= p
->next_insn_offset
- start_offset
;
2420 brw_compact_instructions(p
, start_offset
, disasm_info
);
2421 int after_size
= p
->next_insn_offset
- start_offset
;
2423 if (unlikely(debug_flag
)) {
2424 unsigned char sha1
[21];
2427 _mesa_sha1_compute(p
->store
+ start_offset
/ sizeof(brw_inst
),
2429 _mesa_sha1_format(sha1buf
, sha1
);
2431 fprintf(stderr
, "Native code for %s (sha1 %s)\n"
2432 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
2433 "%d:%d spills:fills, %u sends, "
2434 "scheduled with mode %s. "
2435 "Promoted %u constants. "
2436 "Compacted %d to %d bytes (%.0f%%)\n",
2437 shader_name
, sha1buf
,
2438 dispatch_width
, before_size
/ 16,
2439 loop_count
, cfg
->cycle_count
,
2440 spill_count
, fill_count
, send_count
,
2441 shader_stats
.scheduler_mode
,
2442 shader_stats
.promoted_constants
,
2443 before_size
, after_size
,
2444 100.0f
* (before_size
- after_size
) / before_size
);
2446 /* overriding the shader makes disasm_info invalid */
2447 if (!brw_try_override_assembly(p
, start_offset
, sha1buf
)) {
2448 dump_assembly(p
->store
, disasm_info
);
2450 fprintf(stderr
, "Successfully overrode shader with sha1 %s\n\n", sha1buf
);
2453 ralloc_free(disasm_info
);
2456 compiler
->shader_debug_log(log_data
,
2457 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2458 "%d:%d spills:fills, %u sends, "
2459 "scheduled with mode %s, "
2460 "Promoted %u constants, "
2461 "compacted %d to %d bytes.",
2462 _mesa_shader_stage_to_abbrev(stage
),
2463 dispatch_width
, before_size
/ 16,
2464 loop_count
, cfg
->cycle_count
,
2465 spill_count
, fill_count
, send_count
,
2466 shader_stats
.scheduler_mode
,
2467 shader_stats
.promoted_constants
,
2468 before_size
, after_size
);
2470 stats
->dispatch_width
= dispatch_width
;
2471 stats
->instructions
= before_size
/ 16;
2472 stats
->loops
= loop_count
;
2473 stats
->cycles
= cfg
->cycle_count
;
2474 stats
->spills
= spill_count
;
2475 stats
->fills
= fill_count
;
2478 return start_offset
;
2482 fs_generator::get_assembly()
2484 return brw_get_program(p
, &prog_data
->program_size
);