2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 emit_shader_float_controls_execution_mode();
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
44 nir_emit_system_values();
45 last_scratch
= ALIGN(nir
->scratch_size
, 4) * dispatch_width
;
47 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_shader_out_variable(var
, nir
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
, true);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
71 if (vec4s
[loc
] == 0) {
76 unsigned reg_size
= vec4s
[loc
];
78 /* Check if there are any ranges that start within this range and extend
79 * past it. If so, include them in this allocation.
81 for (unsigned i
= 1; i
< reg_size
; i
++)
82 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
84 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
85 for (unsigned i
= 0; i
< reg_size
; i
++)
86 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
93 fs_visitor::nir_setup_uniforms()
95 /* Only the first compile gets to set up uniforms. */
96 if (push_constant_loc
) {
97 assert(pull_constant_loc
);
101 uniforms
= nir
->num_uniforms
/ 4;
103 if (stage
== MESA_SHADER_COMPUTE
|| stage
== MESA_SHADER_KERNEL
) {
104 /* Add uniforms for builtins after regular NIR uniforms. */
105 assert(uniforms
== prog_data
->nr_params
);
108 if (nir
->info
.cs
.local_size_variable
&&
109 compiler
->lower_variable_group_size
) {
110 param
= brw_stage_prog_data_add_params(prog_data
, 3);
111 for (unsigned i
= 0; i
< 3; i
++) {
112 param
[i
] = (BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X
+ i
);
113 group_size
[i
] = fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
117 /* Subgroup ID must be the last uniform on the list. This will make
118 * easier later to split between cross thread and per thread
121 param
= brw_stage_prog_data_add_params(prog_data
, 1);
122 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
123 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
128 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
132 nir_foreach_instr(instr
, block
) {
133 if (instr
->type
!= nir_instr_type_intrinsic
)
136 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
137 switch (intrin
->intrinsic
) {
138 case nir_intrinsic_load_vertex_id
:
139 case nir_intrinsic_load_base_vertex
:
140 unreachable("should be lowered by nir_lower_system_values().");
142 case nir_intrinsic_load_vertex_id_zero_base
:
143 case nir_intrinsic_load_is_indexed_draw
:
144 case nir_intrinsic_load_first_vertex
:
145 case nir_intrinsic_load_instance_id
:
146 case nir_intrinsic_load_base_instance
:
147 case nir_intrinsic_load_draw_id
:
148 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
150 case nir_intrinsic_load_invocation_id
:
151 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
153 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
154 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
155 if (reg
->file
== BAD_FILE
) {
156 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
157 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
158 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
159 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
164 case nir_intrinsic_load_sample_pos
:
165 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
166 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
167 if (reg
->file
== BAD_FILE
)
168 *reg
= *v
->emit_samplepos_setup();
171 case nir_intrinsic_load_sample_id
:
172 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
173 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
174 if (reg
->file
== BAD_FILE
)
175 *reg
= *v
->emit_sampleid_setup();
178 case nir_intrinsic_load_sample_mask_in
:
179 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
180 assert(v
->devinfo
->gen
>= 7);
181 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
182 if (reg
->file
== BAD_FILE
)
183 *reg
= *v
->emit_samplemaskin_setup();
186 case nir_intrinsic_load_work_group_id
:
187 assert(v
->stage
== MESA_SHADER_COMPUTE
||
188 v
->stage
== MESA_SHADER_KERNEL
);
189 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
190 if (reg
->file
== BAD_FILE
)
191 *reg
= *v
->emit_cs_work_group_id_setup();
194 case nir_intrinsic_load_helper_invocation
:
195 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
196 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
197 if (reg
->file
== BAD_FILE
) {
198 const fs_builder abld
=
199 v
->bld
.annotate("gl_HelperInvocation", NULL
);
201 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
202 * pixel mask is in g1.7 of the thread payload.
204 * We move the per-channel pixel enable bit to the low bit of each
205 * channel by shifting the byte containing the pixel mask by the
206 * vector immediate 0x76543210UV.
208 * The region of <1,8,0> reads only 1 byte (the pixel masks for
209 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
210 * masks for 2 and 3) in SIMD16.
212 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
214 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
215 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
216 hbld
.SHR(offset(shifted
, hbld
, i
),
217 stride(retype(brw_vec1_grf(1 + i
, 7),
218 BRW_REGISTER_TYPE_UB
),
220 brw_imm_v(0x76543210));
223 /* A set bit in the pixel mask means the channel is enabled, but
224 * that is the opposite of gl_HelperInvocation so we need to invert
227 * The negate source-modifier bit of logical instructions on Gen8+
228 * performs 1's complement negation, so we can use that instead of
231 fs_reg inverted
= negate(shifted
);
232 if (v
->devinfo
->gen
< 8) {
233 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
234 abld
.NOT(inverted
, shifted
);
237 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
238 * with 1 and negating.
240 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
241 abld
.AND(anded
, inverted
, brw_imm_uw(1));
243 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
244 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
258 fs_visitor::nir_emit_system_values()
260 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
261 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
262 nir_system_values
[i
] = fs_reg();
265 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
266 * never end up using it.
269 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
270 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
271 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
273 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
274 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
275 if (dispatch_width
> 8)
276 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
277 if (dispatch_width
> 16) {
278 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
279 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
283 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
284 nir_foreach_block(block
, impl
)
285 emit_system_values_block(block
, this);
289 * Returns a type based on a reference_type (word, float, half-float) and a
292 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
294 * @FIXME: 64-bit return types are always DF on integer types to maintain
295 * compability with uses of DF previously to the introduction of int64
299 brw_reg_type_from_bit_size(const unsigned bit_size
,
300 const brw_reg_type reference_type
)
302 switch(reference_type
) {
303 case BRW_REGISTER_TYPE_HF
:
304 case BRW_REGISTER_TYPE_F
:
305 case BRW_REGISTER_TYPE_DF
:
308 return BRW_REGISTER_TYPE_HF
;
310 return BRW_REGISTER_TYPE_F
;
312 return BRW_REGISTER_TYPE_DF
;
314 unreachable("Invalid bit size");
316 case BRW_REGISTER_TYPE_B
:
317 case BRW_REGISTER_TYPE_W
:
318 case BRW_REGISTER_TYPE_D
:
319 case BRW_REGISTER_TYPE_Q
:
322 return BRW_REGISTER_TYPE_B
;
324 return BRW_REGISTER_TYPE_W
;
326 return BRW_REGISTER_TYPE_D
;
328 return BRW_REGISTER_TYPE_Q
;
330 unreachable("Invalid bit size");
332 case BRW_REGISTER_TYPE_UB
:
333 case BRW_REGISTER_TYPE_UW
:
334 case BRW_REGISTER_TYPE_UD
:
335 case BRW_REGISTER_TYPE_UQ
:
338 return BRW_REGISTER_TYPE_UB
;
340 return BRW_REGISTER_TYPE_UW
;
342 return BRW_REGISTER_TYPE_UD
;
344 return BRW_REGISTER_TYPE_UQ
;
346 unreachable("Invalid bit size");
349 unreachable("Unknown type");
354 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
356 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
357 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
358 nir_locals
[i
] = fs_reg();
361 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
362 unsigned array_elems
=
363 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
364 unsigned size
= array_elems
* reg
->num_components
;
365 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
366 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
367 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
370 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
373 nir_emit_cf_list(&impl
->body
);
377 fs_visitor::nir_emit_cf_list(exec_list
*list
)
379 exec_list_validate(list
);
380 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
381 switch (node
->type
) {
383 nir_emit_if(nir_cf_node_as_if(node
));
386 case nir_cf_node_loop
:
387 nir_emit_loop(nir_cf_node_as_loop(node
));
390 case nir_cf_node_block
:
391 nir_emit_block(nir_cf_node_as_block(node
));
395 unreachable("Invalid CFG node block");
401 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
406 /* If the condition has the form !other_condition, use other_condition as
407 * the source, but invert the predicate on the if instruction.
409 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
410 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
412 cond_reg
= get_nir_src(cond
->src
[0].src
);
415 cond_reg
= get_nir_src(if_stmt
->condition
);
418 /* first, put the condition into f0 */
419 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
420 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
421 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
423 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
425 nir_emit_cf_list(&if_stmt
->then_list
);
427 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
428 bld
.emit(BRW_OPCODE_ELSE
);
429 nir_emit_cf_list(&if_stmt
->else_list
);
432 bld
.emit(BRW_OPCODE_ENDIF
);
434 if (devinfo
->gen
< 7)
435 limit_dispatch_width(16, "Non-uniform control flow unsupported "
440 fs_visitor::nir_emit_loop(nir_loop
*loop
)
442 bld
.emit(BRW_OPCODE_DO
);
444 nir_emit_cf_list(&loop
->body
);
446 bld
.emit(BRW_OPCODE_WHILE
);
448 if (devinfo
->gen
< 7)
449 limit_dispatch_width(16, "Non-uniform control flow unsupported "
454 fs_visitor::nir_emit_block(nir_block
*block
)
456 nir_foreach_instr(instr
, block
) {
457 nir_emit_instr(instr
);
462 fs_visitor::nir_emit_instr(nir_instr
*instr
)
464 const fs_builder abld
= bld
.annotate(NULL
, instr
);
466 switch (instr
->type
) {
467 case nir_instr_type_alu
:
468 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
471 case nir_instr_type_deref
:
472 unreachable("All derefs should've been lowered");
475 case nir_instr_type_intrinsic
:
477 case MESA_SHADER_VERTEX
:
478 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
480 case MESA_SHADER_TESS_CTRL
:
481 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
483 case MESA_SHADER_TESS_EVAL
:
484 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
486 case MESA_SHADER_GEOMETRY
:
487 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
489 case MESA_SHADER_FRAGMENT
:
490 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
492 case MESA_SHADER_COMPUTE
:
493 case MESA_SHADER_KERNEL
:
494 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
497 unreachable("unsupported shader stage");
501 case nir_instr_type_tex
:
502 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
505 case nir_instr_type_load_const
:
506 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
509 case nir_instr_type_ssa_undef
:
510 /* We create a new VGRF for undefs on every use (by handling
511 * them in get_nir_src()), rather than for each definition.
512 * This helps register coalescing eliminate MOVs from undef.
516 case nir_instr_type_jump
:
517 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
521 unreachable("unknown instruction type");
526 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
530 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
531 const fs_reg
&result
)
533 if (!instr
->src
[0].src
.is_ssa
||
534 !instr
->src
[0].src
.ssa
->parent_instr
)
537 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
540 nir_alu_instr
*src0
=
541 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
543 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
544 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
547 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
549 /* Element type to extract.*/
550 const brw_reg_type type
= brw_int_type(
551 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
552 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
554 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
555 op0
.type
= brw_type_for_nir_type(devinfo
,
556 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
557 nir_src_bit_size(src0
->src
[0].src
)));
558 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
560 bld
.MOV(result
, subscript(op0
, type
, element
));
565 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
566 const fs_reg
&result
)
568 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
569 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
572 if (!nir_src_is_const(instr
->src
[1].src
) ||
573 !nir_src_is_const(instr
->src
[2].src
))
576 const float value1
= nir_src_as_float(instr
->src
[1].src
);
577 const float value2
= nir_src_as_float(instr
->src
[2].src
);
578 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
581 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
582 assert(value1
== -value2
);
584 fs_reg tmp
= vgrf(glsl_type::int_type
);
586 if (devinfo
->gen
>= 12) {
587 /* Bit 15 of g1.1 is 0 if the polygon is front facing. */
588 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
590 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
592 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
593 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
595 * and negate the result for (gl_FrontFacing ? -1.0 : 1.0).
597 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
598 g1
, brw_imm_uw(0x3f80));
601 bld
.MOV(tmp
, negate(tmp
));
603 } else if (devinfo
->gen
>= 6) {
604 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
605 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
607 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
609 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
610 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
612 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
614 * This negation looks like it's safe in practice, because bits 0:4 will
615 * surely be TRIANGLES
618 if (value1
== -1.0f
) {
622 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
623 g0
, brw_imm_uw(0x3f80));
625 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
626 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
628 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
630 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
631 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
633 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
635 * This negation looks like it's safe in practice, because bits 0:4 will
636 * surely be TRIANGLES
639 if (value1
== -1.0f
) {
643 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
645 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
651 emit_find_msb_using_lzd(const fs_builder
&bld
,
652 const fs_reg
&result
,
660 /* LZD of an absolute value source almost always does the right
661 * thing. There are two problem values:
663 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
664 * 0. However, findMSB(int(0x80000000)) == 30.
666 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
667 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
669 * For a value of zero or negative one, -1 will be returned.
671 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
672 * findMSB(-(1<<x)) should return x-1.
674 * For all negative number cases, including 0x80000000 and
675 * 0xffffffff, the correct value is obtained from LZD if instead of
676 * negating the (already negative) value the logical-not is used. A
677 * conditonal logical-not can be achieved in two instructions.
679 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
681 bld
.ASR(temp
, src
, brw_imm_d(31));
682 bld
.XOR(temp
, temp
, src
);
685 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
686 retype(temp
, BRW_REGISTER_TYPE_UD
));
688 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
689 * from the LSB side. Subtract the result from 31 to convert the MSB
690 * count into an LSB count. If no bits are set, LZD will return 32.
691 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
693 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
694 inst
->src
[0].negate
= true;
698 brw_rnd_mode_from_nir_op (const nir_op op
) {
700 case nir_op_f2f16_rtz
:
701 return BRW_RND_MODE_RTZ
;
702 case nir_op_f2f16_rtne
:
703 return BRW_RND_MODE_RTNE
;
705 unreachable("Operation doesn't support rounding mode");
710 brw_rnd_mode_from_execution_mode(unsigned execution_mode
)
712 if (nir_has_any_rounding_mode_rtne(execution_mode
))
713 return BRW_RND_MODE_RTNE
;
714 if (nir_has_any_rounding_mode_rtz(execution_mode
))
715 return BRW_RND_MODE_RTZ
;
716 return BRW_RND_MODE_UNSPECIFIED
;
720 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
721 nir_alu_instr
*instr
,
726 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
728 result
.type
= brw_type_for_nir_type(devinfo
,
729 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
730 nir_dest_bit_size(instr
->dest
.dest
)));
732 assert(!instr
->dest
.saturate
);
734 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
735 /* We don't lower to source modifiers so they should not exist. */
736 assert(!instr
->src
[i
].abs
);
737 assert(!instr
->src
[i
].negate
);
739 op
[i
] = get_nir_src(instr
->src
[i
].src
);
740 op
[i
].type
= brw_type_for_nir_type(devinfo
,
741 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
742 nir_src_bit_size(instr
->src
[i
].src
)));
745 /* Move and vecN instrutions may still be vectored. Return the raw,
746 * vectored source and destination so that fs_visitor::nir_emit_alu can
747 * handle it. Other callers should not have to handle these kinds of
762 /* At this point, we have dealt with any instruction that operates on
763 * more than a single channel. Therefore, we can just adjust the source
764 * and destination registers for that channel and emit the instruction.
766 unsigned channel
= 0;
767 if (nir_op_infos
[instr
->op
].output_size
== 0) {
768 /* Since NIR is doing the scalarizing for us, we should only ever see
769 * vectorized operations with a single channel.
771 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
772 channel
= ffs(instr
->dest
.write_mask
) - 1;
774 result
= offset(result
, bld
, channel
);
777 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
778 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
779 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
786 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
789 for (unsigned i
= 0; i
< 2; i
++) {
790 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
792 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
) {
793 /* The source of the inot is now the source of instr. */
794 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
796 assert(!op
[i
].negate
);
799 op
[i
] = resolve_source_modifiers(op
[i
]);
805 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
807 nir_alu_instr
*instr
)
809 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
812 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
814 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
817 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
818 * of valid size-changing combinations is a bit more complex.
820 * The source restriction is just because I was lazy about generating the
823 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
824 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
827 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
828 * this is float(1 + a).
832 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
834 /* Ignore the saturate modifier, if there is one. The result of the
835 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
837 bld
.ADD(result
, op
, brw_imm_d(1));
843 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
845 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
846 * the source of \c instr that is a \c nir_op_fsign.
849 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
850 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
854 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
855 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
857 if (instr
->op
!= nir_op_fsign
) {
858 const nir_alu_instr
*const fsign_instr
=
859 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
861 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
862 * fsign_src] has the other multiply source. This must be rearranged so
863 * that op[0] is the source of the fsign op[1] is the other multiply
869 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
871 const nir_alu_type t
=
872 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
873 nir_src_bit_size(fsign_instr
->src
[0].src
));
875 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
877 unsigned channel
= 0;
878 if (nir_op_infos
[instr
->op
].output_size
== 0) {
879 /* Since NIR is doing the scalarizing for us, we should only ever see
880 * vectorized operations with a single channel.
882 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
883 channel
= ffs(instr
->dest
.write_mask
) - 1;
886 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
889 if (type_sz(op
[0].type
) == 2) {
890 /* AND(val, 0x8000) gives the sign bit.
892 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
894 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
895 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
897 op
[0].type
= BRW_REGISTER_TYPE_UW
;
898 result
.type
= BRW_REGISTER_TYPE_UW
;
899 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
901 if (instr
->op
== nir_op_fsign
)
902 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
904 /* Use XOR here to get the result sign correct. */
905 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
908 inst
->predicate
= BRW_PREDICATE_NORMAL
;
909 } else if (type_sz(op
[0].type
) == 4) {
910 /* AND(val, 0x80000000) gives the sign bit.
912 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
915 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
917 op
[0].type
= BRW_REGISTER_TYPE_UD
;
918 result
.type
= BRW_REGISTER_TYPE_UD
;
919 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
921 if (instr
->op
== nir_op_fsign
)
922 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
924 /* Use XOR here to get the result sign correct. */
925 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
928 inst
->predicate
= BRW_PREDICATE_NORMAL
;
930 /* For doubles we do the same but we need to consider:
932 * - 2-src instructions can't operate with 64-bit immediates
933 * - The sign is encoded in the high 32-bit of each DF
934 * - We need to produce a DF result.
937 fs_reg zero
= vgrf(glsl_type::double_type
);
938 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
939 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
941 bld
.MOV(result
, zero
);
943 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
944 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
945 brw_imm_ud(0x80000000u
));
947 if (instr
->op
== nir_op_fsign
) {
948 set_predicate(BRW_PREDICATE_NORMAL
,
949 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
951 /* This could be done better in some cases. If the scale is an
952 * immediate with the low 32-bits all 0, emitting a separate XOR and
953 * OR would allow an algebraic optimization to remove the OR. There
954 * are currently zero instances of fsign(double(x))*IMM in shader-db
955 * or any test suite, so it is hard to care at this time.
957 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
958 inst
= bld
.XOR(result_int64
, result_int64
,
959 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
965 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
967 * Checks the operands of a \c nir_op_fmul to determine whether or not
968 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
970 * \param instr The multiplication instruction
972 * \param fsign_src The source of \c instr that may or may not be a
976 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
978 assert(instr
->op
== nir_op_fmul
);
980 nir_alu_instr
*const fsign_instr
=
981 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
985 * 1. instr->src[fsign_src] must be a nir_op_fsign.
986 * 2. The nir_op_fsign can only be used by this multiplication.
987 * 3. The source that is the nir_op_fsign does not have source modifiers.
988 * \c emit_fsign only examines the source modifiers of the source of the
991 * The nir_op_fsign must also not have the saturate modifier, but steps
992 * have already been taken (in nir_opt_algebraic) to ensure that.
994 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
995 is_used_once(fsign_instr
);
999 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
1002 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
1004 unsigned execution_mode
=
1005 bld
.shader
->nir
->info
.float_controls_execution_mode
;
1007 fs_reg op
[NIR_MAX_VEC_COMPONENTS
];
1008 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
1010 switch (instr
->op
) {
1016 case nir_op_vec16
: {
1017 fs_reg temp
= result
;
1018 bool need_extra_copy
= false;
1019 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1020 if (!instr
->src
[i
].src
.is_ssa
&&
1021 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1022 need_extra_copy
= true;
1023 temp
= bld
.vgrf(result
.type
, 4);
1028 for (unsigned i
= 0; i
< 4; i
++) {
1029 if (!(instr
->dest
.write_mask
& (1 << i
)))
1032 if (instr
->op
== nir_op_mov
) {
1033 inst
= bld
.MOV(offset(temp
, bld
, i
),
1034 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1036 inst
= bld
.MOV(offset(temp
, bld
, i
),
1037 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1041 /* In this case the source and destination registers were the same,
1042 * so we need to insert an extra set of moves in order to deal with
1045 if (need_extra_copy
) {
1046 for (unsigned i
= 0; i
< 4; i
++) {
1047 if (!(instr
->dest
.write_mask
& (1 << i
)))
1050 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1058 if (optimize_extract_to_float(instr
, result
))
1060 inst
= bld
.MOV(result
, op
[0]);
1063 case nir_op_f2f16_rtne
:
1064 case nir_op_f2f16_rtz
:
1065 case nir_op_f2f16
: {
1066 brw_rnd_mode rnd
= BRW_RND_MODE_UNSPECIFIED
;
1068 if (nir_op_f2f16
== instr
->op
)
1069 rnd
= brw_rnd_mode_from_execution_mode(execution_mode
);
1071 rnd
= brw_rnd_mode_from_nir_op(instr
->op
);
1073 if (BRW_RND_MODE_UNSPECIFIED
!= rnd
)
1074 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(), brw_imm_d(rnd
));
1076 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1077 * on the HW gen, it is a special hw opcode or just a MOV, and
1078 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1080 * But if we want to use that opcode, we need to provide support on
1081 * different optimizations and lowerings. As right now HF support is
1082 * only for gen8+, it will be better to use directly the MOV, and use
1083 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1085 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1086 inst
= bld
.MOV(result
, op
[0]);
1097 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1099 op
[0].type
= BRW_REGISTER_TYPE_D
;
1100 op
[0].negate
= !op
[0].negate
;
1123 if (result
.type
== BRW_REGISTER_TYPE_B
||
1124 result
.type
== BRW_REGISTER_TYPE_UB
||
1125 result
.type
== BRW_REGISTER_TYPE_HF
)
1126 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1128 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1129 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1130 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1131 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1133 inst
= bld
.MOV(result
, op
[0]);
1137 inst
= bld
.MOV(result
, op
[0]);
1138 inst
->saturate
= true;
1143 op
[0].negate
= true;
1144 inst
= bld
.MOV(result
, op
[0]);
1149 op
[0].negate
= false;
1151 inst
= bld
.MOV(result
, op
[0]);
1155 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1157 brw_rnd_mode_from_execution_mode(execution_mode
);
1158 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1162 if (op
[0].type
== BRW_REGISTER_TYPE_HF
)
1163 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1165 inst
= bld
.MOV(result
, op
[0]);
1169 emit_fsign(bld
, instr
, result
, op
, 0);
1173 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1177 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1181 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1185 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1189 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1193 if (fs_key
->high_quality_derivatives
) {
1194 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1196 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1199 case nir_op_fddx_fine
:
1200 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1202 case nir_op_fddx_coarse
:
1203 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1206 if (fs_key
->high_quality_derivatives
) {
1207 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1209 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1212 case nir_op_fddy_fine
:
1213 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1215 case nir_op_fddy_coarse
:
1216 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1220 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1222 brw_rnd_mode_from_execution_mode(execution_mode
);
1223 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1228 inst
= bld
.ADD(result
, op
[0], op
[1]);
1231 case nir_op_iadd_sat
:
1232 case nir_op_uadd_sat
:
1233 inst
= bld
.ADD(result
, op
[0], op
[1]);
1234 inst
->saturate
= true;
1237 case nir_op_isub_sat
:
1238 bld
.emit(SHADER_OPCODE_ISUB_SAT
, result
, op
[0], op
[1]);
1241 case nir_op_usub_sat
:
1242 bld
.emit(SHADER_OPCODE_USUB_SAT
, result
, op
[0], op
[1]);
1247 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1248 inst
= bld
.AVG(result
, op
[0], op
[1]);
1252 case nir_op_uhadd
: {
1253 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1254 fs_reg tmp
= bld
.vgrf(result
.type
);
1256 if (devinfo
->gen
>= 8) {
1257 op
[0] = resolve_source_modifiers(op
[0]);
1258 op
[1] = resolve_source_modifiers(op
[1]);
1261 /* AVG(x, y) - ((x ^ y) & 1) */
1262 bld
.XOR(tmp
, op
[0], op
[1]);
1263 bld
.AND(tmp
, tmp
, retype(brw_imm_ud(1), result
.type
));
1264 bld
.AVG(result
, op
[0], op
[1]);
1265 inst
= bld
.ADD(result
, result
, tmp
);
1266 inst
->src
[1].negate
= true;
1271 for (unsigned i
= 0; i
< 2; i
++) {
1272 if (can_fuse_fmul_fsign(instr
, i
)) {
1273 emit_fsign(bld
, instr
, result
, op
, i
);
1278 /* We emit the rounding mode after the previous fsign optimization since
1279 * it won't result in a MUL, but will try to negate the value by other
1282 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1284 brw_rnd_mode_from_execution_mode(execution_mode
);
1285 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1289 inst
= bld
.MUL(result
, op
[0], op
[1]);
1292 case nir_op_imul_2x32_64
:
1293 case nir_op_umul_2x32_64
:
1294 bld
.MUL(result
, op
[0], op
[1]);
1297 case nir_op_imul_32x16
:
1298 case nir_op_umul_32x16
: {
1299 const bool ud
= instr
->op
== nir_op_umul_32x16
;
1301 assert(nir_dest_bit_size(instr
->dest
.dest
) == 32);
1303 /* Before Gen7, the order of the 32-bit source and the 16-bit source was
1304 * swapped. The extension isn't enabled on those platforms, so don't
1305 * pretend to support the differences.
1307 assert(devinfo
->gen
>= 7);
1309 if (op
[1].file
== IMM
)
1310 op
[1] = ud
? brw_imm_uw(op
[1].ud
) : brw_imm_w(op
[1].d
);
1312 const enum brw_reg_type word_type
=
1313 ud
? BRW_REGISTER_TYPE_UW
: BRW_REGISTER_TYPE_W
;
1315 op
[1] = subscript(op
[1], word_type
, 0);
1318 const enum brw_reg_type dword_type
=
1319 ud
? BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_D
;
1321 bld
.MUL(result
, retype(op
[0], dword_type
), op
[1]);
1326 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1327 bld
.MUL(result
, op
[0], op
[1]);
1330 case nir_op_imul_high
:
1331 case nir_op_umul_high
:
1332 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1333 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1338 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1339 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1342 case nir_op_uadd_carry
:
1343 unreachable("Should have been lowered by carry_to_arith().");
1345 case nir_op_usub_borrow
:
1346 unreachable("Should have been lowered by borrow_to_arith().");
1350 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1351 * appears that our hardware just does the right thing for signed
1354 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1355 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1359 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1360 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1362 /* Math instructions don't support conditional mod */
1363 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1364 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1366 /* Now, we need to determine if signs of the sources are different.
1367 * When we XOR the sources, the top bit is 0 if they are the same and 1
1368 * if they are different. We can then use a conditional modifier to
1369 * turn that into a predicate. This leads us to an XOR.l instruction.
1371 * Technically, according to the PRM, you're not allowed to use .l on a
1372 * XOR instruction. However, emperical experiments and Curro's reading
1373 * of the simulator source both indicate that it's safe.
1375 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1376 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1377 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1378 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1380 /* If the result of the initial remainder operation is non-zero and the
1381 * two sources have different signs, add in a copy of op[1] to get the
1382 * final integer modulus value.
1384 inst
= bld
.ADD(result
, result
, op
[1]);
1385 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1392 case nir_op_fneu32
: {
1393 fs_reg dest
= result
;
1395 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1397 dest
= bld
.vgrf(op
[0].type
, 1);
1399 bld
.CMP(dest
, op
[0], op
[1], brw_cmod_for_nir_comparison(instr
->op
));
1401 if (bit_size
> 32) {
1402 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1403 } else if(bit_size
< 32) {
1404 /* When we convert the result to 32-bit we need to be careful and do
1405 * it as a signed conversion to get sign extension (for 32-bit true)
1407 const brw_reg_type src_type
=
1408 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1410 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1420 case nir_op_ine32
: {
1421 fs_reg dest
= result
;
1423 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1424 * type. So we convert both operands for the comparison.
1427 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1428 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1430 const uint32_t bit_size
= type_sz(temp_op
[0].type
) * 8;
1432 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1434 bld
.CMP(dest
, temp_op
[0], temp_op
[1],
1435 brw_cmod_for_nir_comparison(instr
->op
));
1437 if (bit_size
> 32) {
1438 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1439 } else if (bit_size
< 32) {
1440 /* When we convert the result to 32-bit we need to be careful and do
1441 * it as a signed conversion to get sign extension (for 32-bit true)
1443 const brw_reg_type src_type
=
1444 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1446 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1452 if (devinfo
->gen
>= 8) {
1453 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1455 if (inot_src_instr
!= NULL
&&
1456 (inot_src_instr
->op
== nir_op_ior
||
1457 inot_src_instr
->op
== nir_op_ixor
||
1458 inot_src_instr
->op
== nir_op_iand
)) {
1459 /* The sources of the source logical instruction are now the
1460 * sources of the instruction that will be generated.
1462 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1463 resolve_inot_sources(bld
, inot_src_instr
, op
);
1465 /* Smash all of the sources and destination to be signed. This
1466 * doesn't matter for the operation of the instruction, but cmod
1467 * propagation fails on unsigned sources with negation (due to
1468 * fs_inst::can_do_cmod returning false).
1471 brw_type_for_nir_type(devinfo
,
1472 (nir_alu_type
)(nir_type_int
|
1473 nir_dest_bit_size(instr
->dest
.dest
)));
1475 brw_type_for_nir_type(devinfo
,
1476 (nir_alu_type
)(nir_type_int
|
1477 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1479 brw_type_for_nir_type(devinfo
,
1480 (nir_alu_type
)(nir_type_int
|
1481 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1483 /* For XOR, only invert one of the sources. Arbitrarily choose
1486 op
[0].negate
= !op
[0].negate
;
1487 if (inot_src_instr
->op
!= nir_op_ixor
)
1488 op
[1].negate
= !op
[1].negate
;
1490 switch (inot_src_instr
->op
) {
1492 bld
.AND(result
, op
[0], op
[1]);
1496 bld
.OR(result
, op
[0], op
[1]);
1500 bld
.XOR(result
, op
[0], op
[1]);
1504 unreachable("impossible opcode");
1507 op
[0] = resolve_source_modifiers(op
[0]);
1509 bld
.NOT(result
, op
[0]);
1512 if (devinfo
->gen
>= 8) {
1513 resolve_inot_sources(bld
, instr
, op
);
1515 bld
.XOR(result
, op
[0], op
[1]);
1518 if (devinfo
->gen
>= 8) {
1519 resolve_inot_sources(bld
, instr
, op
);
1521 bld
.OR(result
, op
[0], op
[1]);
1524 if (devinfo
->gen
>= 8) {
1525 resolve_inot_sources(bld
, instr
, op
);
1527 bld
.AND(result
, op
[0], op
[1]);
1533 case nir_op_b32all_fequal2
:
1534 case nir_op_b32all_iequal2
:
1535 case nir_op_b32all_fequal3
:
1536 case nir_op_b32all_iequal3
:
1537 case nir_op_b32all_fequal4
:
1538 case nir_op_b32all_iequal4
:
1539 case nir_op_b32any_fnequal2
:
1540 case nir_op_b32any_inequal2
:
1541 case nir_op_b32any_fnequal3
:
1542 case nir_op_b32any_inequal3
:
1543 case nir_op_b32any_fnequal4
:
1544 case nir_op_b32any_inequal4
:
1545 unreachable("Lowered by nir_lower_alu_reductions");
1548 unreachable("not reached: should be handled by ldexp_to_arith()");
1551 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1555 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1559 case nir_op_f2b32
: {
1560 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1561 if (bit_size
== 64) {
1562 /* two-argument instructions can't take 64-bit immediates */
1566 if (instr
->op
== nir_op_f2b32
) {
1567 zero
= vgrf(glsl_type::double_type
);
1568 tmp
= vgrf(glsl_type::double_type
);
1569 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1571 zero
= vgrf(glsl_type::int64_t_type
);
1572 tmp
= vgrf(glsl_type::int64_t_type
);
1573 bld
.MOV(zero
, brw_imm_q(0));
1576 /* A SIMD16 execution needs to be split in two instructions, so use
1577 * a vgrf instead of the flag register as dst so instruction splitting
1580 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1581 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1584 if (bit_size
== 32) {
1585 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1587 assert(bit_size
== 16);
1588 zero
= instr
->op
== nir_op_f2b32
?
1589 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1591 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1597 inst
= bld
.RNDZ(result
, op
[0]);
1598 if (devinfo
->gen
< 6) {
1599 set_condmod(BRW_CONDITIONAL_R
, inst
);
1600 set_predicate(BRW_PREDICATE_NORMAL
,
1601 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1602 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1606 case nir_op_fceil
: {
1607 op
[0].negate
= !op
[0].negate
;
1608 fs_reg temp
= vgrf(glsl_type::float_type
);
1609 bld
.RNDD(temp
, op
[0]);
1611 inst
= bld
.MOV(result
, temp
);
1615 inst
= bld
.RNDD(result
, op
[0]);
1618 inst
= bld
.FRC(result
, op
[0]);
1620 case nir_op_fround_even
:
1621 inst
= bld
.RNDE(result
, op
[0]);
1622 if (devinfo
->gen
< 6) {
1623 set_condmod(BRW_CONDITIONAL_R
, inst
);
1624 set_predicate(BRW_PREDICATE_NORMAL
,
1625 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1626 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1630 case nir_op_fquantize2f16
: {
1631 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1632 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1633 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1635 /* The destination stride must be at least as big as the source stride. */
1636 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1639 /* Check for denormal */
1640 fs_reg abs_src0
= op
[0];
1641 abs_src0
.abs
= true;
1642 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1644 /* Get the appropriately signed zero */
1645 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1646 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1647 brw_imm_ud(0x80000000));
1648 /* Do the actual F32 -> F16 -> F32 conversion */
1649 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1650 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1651 /* Select that or zero based on normal status */
1652 inst
= bld
.SEL(result
, zero
, tmp32
);
1653 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1660 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1666 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1669 case nir_op_pack_snorm_2x16
:
1670 case nir_op_pack_snorm_4x8
:
1671 case nir_op_pack_unorm_2x16
:
1672 case nir_op_pack_unorm_4x8
:
1673 case nir_op_unpack_snorm_2x16
:
1674 case nir_op_unpack_snorm_4x8
:
1675 case nir_op_unpack_unorm_2x16
:
1676 case nir_op_unpack_unorm_4x8
:
1677 case nir_op_unpack_half_2x16
:
1678 case nir_op_pack_half_2x16
:
1679 unreachable("not reached: should be handled by lower_packing_builtins");
1681 case nir_op_unpack_half_2x16_split_x_flush_to_zero
:
1682 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1684 case nir_op_unpack_half_2x16_split_x
:
1685 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1686 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1689 case nir_op_unpack_half_2x16_split_y_flush_to_zero
:
1690 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1692 case nir_op_unpack_half_2x16_split_y
:
1693 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1694 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1697 case nir_op_pack_64_2x32_split
:
1698 case nir_op_pack_32_2x16_split
:
1699 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1702 case nir_op_unpack_64_2x32_split_x
:
1703 case nir_op_unpack_64_2x32_split_y
: {
1704 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1705 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1707 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1711 case nir_op_unpack_32_2x16_split_x
:
1712 case nir_op_unpack_32_2x16_split_y
: {
1713 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1714 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1716 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1721 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1724 case nir_op_bitfield_reverse
:
1725 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1726 bld
.BFREV(result
, op
[0]);
1729 case nir_op_bit_count
:
1730 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1731 bld
.CBIT(result
, op
[0]);
1734 case nir_op_ufind_msb
: {
1735 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1736 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1741 assert(nir_dest_bit_size(instr
->dest
.dest
) == 32);
1742 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1745 case nir_op_ifind_msb
: {
1746 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1748 if (devinfo
->gen
< 7) {
1749 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1751 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1753 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1754 * count from the LSB side. If FBH didn't return an error
1755 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1756 * count into an LSB count.
1758 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1760 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1761 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1762 inst
->src
[0].negate
= true;
1767 case nir_op_find_lsb
:
1768 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1770 if (devinfo
->gen
< 7) {
1771 fs_reg temp
= vgrf(glsl_type::int_type
);
1773 /* (x & -x) generates a value that consists of only the LSB of x.
1774 * For all powers of 2, findMSB(y) == findLSB(y).
1776 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1777 fs_reg negated_src
= src
;
1779 /* One must be negated, and the other must be non-negated. It
1780 * doesn't matter which is which.
1782 negated_src
.negate
= true;
1785 bld
.AND(temp
, src
, negated_src
);
1786 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1788 bld
.FBL(result
, op
[0]);
1792 case nir_op_ubitfield_extract
:
1793 case nir_op_ibitfield_extract
:
1794 unreachable("should have been lowered");
1797 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1798 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1801 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1802 bld
.BFI1(result
, op
[0], op
[1]);
1805 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1806 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1809 case nir_op_bitfield_insert
:
1810 unreachable("not reached: should have been lowered");
1813 bld
.SHL(result
, op
[0], op
[1]);
1816 bld
.ASR(result
, op
[0], op
[1]);
1819 bld
.SHR(result
, op
[0], op
[1]);
1823 bld
.ROL(result
, op
[0], op
[1]);
1826 bld
.ROR(result
, op
[0], op
[1]);
1829 case nir_op_pack_half_2x16_split
:
1830 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1834 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1836 brw_rnd_mode_from_execution_mode(execution_mode
);
1837 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1841 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1845 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1847 brw_rnd_mode_from_execution_mode(execution_mode
);
1848 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1852 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1855 case nir_op_b32csel
:
1856 if (optimize_frontfacing_ternary(instr
, result
))
1859 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1860 inst
= bld
.SEL(result
, op
[1], op
[2]);
1861 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1864 case nir_op_extract_u8
:
1865 case nir_op_extract_i8
: {
1866 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1871 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1872 * Use two instructions and a word or DWord intermediate integer type.
1874 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1875 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1877 if (instr
->op
== nir_op_extract_i8
) {
1878 /* If we need to sign extend, extract to a word first */
1879 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1880 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1881 bld
.MOV(result
, w_temp
);
1882 } else if (byte
& 1) {
1883 /* Extract the high byte from the word containing the desired byte
1887 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1890 /* Otherwise use an AND with 0xff and a word type */
1892 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1896 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1897 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1902 case nir_op_extract_u16
:
1903 case nir_op_extract_i16
: {
1904 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1905 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1906 bld
.MOV(result
, subscript(op
[0], type
, word
));
1911 unreachable("unhandled instruction");
1914 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1915 * to sign extend the low bit to 0/~0
1917 if (devinfo
->gen
<= 5 &&
1918 !result
.is_null() &&
1919 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1920 fs_reg masked
= vgrf(glsl_type::int_type
);
1921 bld
.AND(masked
, result
, brw_imm_d(1));
1922 masked
.negate
= true;
1923 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1928 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1929 nir_load_const_instr
*instr
)
1931 const brw_reg_type reg_type
=
1932 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1933 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1935 switch (instr
->def
.bit_size
) {
1937 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1938 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1942 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1943 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1947 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1948 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1952 assert(devinfo
->gen
>= 7);
1953 if (devinfo
->gen
== 7) {
1954 /* We don't get 64-bit integer types until gen8 */
1955 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1956 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1957 setup_imm_df(bld
, instr
->value
[i
].f64
));
1960 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1961 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1966 unreachable("Invalid bit size");
1969 nir_ssa_values
[instr
->def
.index
] = reg
;
1973 fs_visitor::get_nir_src(const nir_src
&src
)
1977 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1978 const brw_reg_type reg_type
=
1979 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1980 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1982 reg
= nir_ssa_values
[src
.ssa
->index
];
1985 /* We don't handle indirects on locals */
1986 assert(src
.reg
.indirect
== NULL
);
1987 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1988 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1991 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1992 /* The only 64-bit type available on gen7 is DF, so use that. */
1993 reg
.type
= BRW_REGISTER_TYPE_DF
;
1995 /* To avoid floating-point denorm flushing problems, set the type by
1996 * default to an integer type - instructions that need floating point
1997 * semantics will set this to F if they need to
1999 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
2000 BRW_REGISTER_TYPE_D
);
2007 * Return an IMM for constants; otherwise call get_nir_src() as normal.
2009 * This function should not be called on any value which may be 64 bits.
2010 * We could theoretically support 64-bit on gen8+ but we choose not to
2011 * because it wouldn't work in general (no gen7 support) and there are
2012 * enough restrictions in 64-bit immediates that you can't take the return
2013 * value and treat it the same as the result of get_nir_src().
2016 fs_visitor::get_nir_src_imm(const nir_src
&src
)
2018 assert(nir_src_bit_size(src
) == 32);
2019 return nir_src_is_const(src
) ?
2020 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
2024 fs_visitor::get_nir_dest(const nir_dest
&dest
)
2027 const brw_reg_type reg_type
=
2028 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
2029 dest
.ssa
.bit_size
== 8 ?
2030 BRW_REGISTER_TYPE_D
:
2031 BRW_REGISTER_TYPE_F
);
2032 nir_ssa_values
[dest
.ssa
.index
] =
2033 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
2034 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
2035 return nir_ssa_values
[dest
.ssa
.index
];
2037 /* We don't handle indirects on locals */
2038 assert(dest
.reg
.indirect
== NULL
);
2039 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
2040 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
2045 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
2048 for (unsigned i
= 0; i
< 4; i
++) {
2049 if (!((wr_mask
>> i
) & 1))
2052 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
2053 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
2054 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
2055 if (new_inst
->src
[j
].file
== VGRF
)
2056 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
2063 emit_pixel_interpolater_send(const fs_builder
&bld
,
2068 glsl_interp_mode interpolation
)
2070 struct brw_wm_prog_data
*wm_prog_data
=
2071 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
2073 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
2074 /* 2 floats per slot returned */
2075 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
2076 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
2078 wm_prog_data
->pulls_bary
= true;
2084 * Computes 1 << x, given a D/UD register containing some value x.
2087 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
2089 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
2091 fs_reg result
= bld
.vgrf(x
.type
, 1);
2092 fs_reg one
= bld
.vgrf(x
.type
, 1);
2094 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2095 bld
.SHL(result
, one
, x
);
2100 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2102 assert(stage
== MESA_SHADER_GEOMETRY
);
2104 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2106 if (gs_compile
->control_data_header_size_bits
== 0)
2109 /* We can only do EndPrimitive() functionality when the control data
2110 * consists of cut bits. Fortunately, the only time it isn't is when the
2111 * output type is points, in which case EndPrimitive() is a no-op.
2113 if (gs_prog_data
->control_data_format
!=
2114 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2118 /* Cut bits use one bit per vertex. */
2119 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2121 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2122 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2124 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2125 * vertex n, 0 otherwise. So all we need to do here is mark bit
2126 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2127 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2128 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2130 * Note that if EndPrimitive() is called before emitting any vertices, this
2131 * will cause us to set bit 31 of the control_data_bits register to 1.
2132 * That's fine because:
2134 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2135 * output, so the hardware will ignore cut bit 31.
2137 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2138 * last vertex, so setting cut bit 31 has no effect (since the primitive
2139 * is automatically ended when the GS terminates).
2141 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2142 * control_data_bits register to 0 when the first vertex is emitted.
2145 const fs_builder abld
= bld
.annotate("end primitive");
2147 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2148 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2149 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2150 fs_reg mask
= intexp2(abld
, prev_count
);
2151 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2152 * attention to the lower 5 bits of its second source argument, so on this
2153 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2154 * ((vertex_count - 1) % 32).
2156 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2160 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2162 assert(stage
== MESA_SHADER_GEOMETRY
);
2163 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2165 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2167 const fs_builder abld
= bld
.annotate("emit control data bits");
2168 const fs_builder fwa_bld
= bld
.exec_all();
2170 /* We use a single UD register to accumulate control data bits (32 bits
2171 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2174 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2175 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2176 * use the Channel Mask phase to enable/disable which DWord within that
2177 * group to write. (Remember, different SIMD8 channels may have emitted
2178 * different numbers of vertices, so we may need per-slot offsets.)
2180 * Channel masking presents an annoying problem: we may have to replicate
2181 * the data up to 4 times:
2183 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2185 * To avoid penalizing shaders that emit a small number of vertices, we
2186 * can avoid these sometimes: if the size of the control data header is
2187 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2188 * land in the same 128-bit group, so we can skip per-slot offsets.
2190 * Similarly, if the control data header is <= 32 bits, there is only one
2191 * DWord, so we can skip channel masks.
2193 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2195 fs_reg channel_mask
, per_slot_offset
;
2197 if (gs_compile
->control_data_header_size_bits
> 32) {
2198 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2199 channel_mask
= vgrf(glsl_type::uint_type
);
2202 if (gs_compile
->control_data_header_size_bits
> 128) {
2203 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2204 per_slot_offset
= vgrf(glsl_type::uint_type
);
2207 /* Figure out which DWord we're trying to write to using the formula:
2209 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2211 * Since bits_per_vertex is a power of two, and is known at compile
2212 * time, this can be optimized to:
2214 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2216 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2217 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2218 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2219 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2220 unsigned log2_bits_per_vertex
=
2221 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2222 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2224 if (per_slot_offset
.file
!= BAD_FILE
) {
2225 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2226 * the appropriate OWord within the control data header.
2228 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2231 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2232 * write to the appropriate DWORD within the OWORD.
2234 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2235 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2236 channel_mask
= intexp2(fwa_bld
, channel
);
2237 /* Then the channel masks need to be in bits 23:16. */
2238 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2241 /* Store the control data bits in the message payload and send it. */
2243 if (channel_mask
.file
!= BAD_FILE
)
2244 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2245 if (per_slot_offset
.file
!= BAD_FILE
)
2248 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2249 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2251 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2252 if (per_slot_offset
.file
!= BAD_FILE
)
2253 sources
[i
++] = per_slot_offset
;
2254 if (channel_mask
.file
!= BAD_FILE
)
2255 sources
[i
++] = channel_mask
;
2257 sources
[i
++] = this->control_data_bits
;
2260 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2261 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2263 /* We need to increment Global Offset by 256-bits to make room for
2264 * Broadwell's extra "Vertex Count" payload at the beginning of the
2265 * URB entry. Since this is an OWord message, Global Offset is counted
2266 * in 128-bit units, so we must set it to 2.
2268 if (gs_prog_data
->static_vertex_count
== -1)
2273 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2276 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2278 /* Note: we are calling this *before* increasing vertex_count, so
2279 * this->vertex_count == vertex_count - 1 in the formula above.
2282 /* Stream mode uses 2 bits per vertex */
2283 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2285 /* Must be a valid stream */
2286 assert(stream_id
< MAX_VERTEX_STREAMS
);
2288 /* Control data bits are initialized to 0 so we don't have to set any
2289 * bits when sending vertices to stream 0.
2294 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2296 /* reg::sid = stream_id */
2297 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2298 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2300 /* reg:shift_count = 2 * (vertex_count - 1) */
2301 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2302 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2304 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2305 * attention to the lower 5 bits of its second source argument, so on this
2306 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2307 * stream_id << ((2 * (vertex_count - 1)) % 32).
2309 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2310 abld
.SHL(mask
, sid
, shift_count
);
2311 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2315 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2318 assert(stage
== MESA_SHADER_GEOMETRY
);
2320 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2322 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2323 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2325 /* Haswell and later hardware ignores the "Render Stream Select" bits
2326 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2327 * and instead sends all primitives down the pipeline for rasterization.
2328 * If the SOL stage is enabled, "Render Stream Select" is honored and
2329 * primitives bound to non-zero streams are discarded after stream output.
2331 * Since the only purpose of primives sent to non-zero streams is to
2332 * be recorded by transform feedback, we can simply discard all geometry
2333 * bound to these streams when transform feedback is disabled.
2335 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2338 /* If we're outputting 32 control data bits or less, then we can wait
2339 * until the shader is over to output them all. Otherwise we need to
2340 * output them as we go. Now is the time to do it, since we're about to
2341 * output the vertex_count'th vertex, so it's guaranteed that the
2342 * control data bits associated with the (vertex_count - 1)th vertex are
2345 if (gs_compile
->control_data_header_size_bits
> 32) {
2346 const fs_builder abld
=
2347 bld
.annotate("emit vertex: emit control data bits");
2349 /* Only emit control data bits if we've finished accumulating a batch
2350 * of 32 bits. This is the case when:
2352 * (vertex_count * bits_per_vertex) % 32 == 0
2354 * (in other words, when the last 5 bits of vertex_count *
2355 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2356 * integer n (which is always the case, since bits_per_vertex is
2357 * always 1 or 2), this is equivalent to requiring that the last 5-n
2358 * bits of vertex_count are 0:
2360 * vertex_count & (2^(5-n) - 1) == 0
2362 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2365 * vertex_count & (32 / bits_per_vertex - 1) == 0
2367 * TODO: If vertex_count is an immediate, we could do some of this math
2368 * at compile time...
2371 abld
.AND(bld
.null_reg_d(), vertex_count
,
2372 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2373 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2375 abld
.IF(BRW_PREDICATE_NORMAL
);
2376 /* If vertex_count is 0, then no control data bits have been
2377 * accumulated yet, so we can skip emitting them.
2379 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2380 BRW_CONDITIONAL_NEQ
);
2381 abld
.IF(BRW_PREDICATE_NORMAL
);
2382 emit_gs_control_data_bits(vertex_count
);
2383 abld
.emit(BRW_OPCODE_ENDIF
);
2385 /* Reset control_data_bits to 0 so we can start accumulating a new
2388 * Note: in the case where vertex_count == 0, this neutralizes the
2389 * effect of any call to EndPrimitive() that the shader may have
2390 * made before outputting its first vertex.
2392 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2393 inst
->force_writemask_all
= true;
2394 abld
.emit(BRW_OPCODE_ENDIF
);
2397 emit_urb_writes(vertex_count
);
2399 /* In stream mode we have to set control data bits for all vertices
2400 * unless we have disabled control data bits completely (which we do
2401 * do for GL_POINTS outputs that don't use streams).
2403 if (gs_compile
->control_data_header_size_bits
> 0 &&
2404 gs_prog_data
->control_data_format
==
2405 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2406 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2411 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2412 const nir_src
&vertex_src
,
2413 unsigned base_offset
,
2414 const nir_src
&offset_src
,
2415 unsigned num_components
,
2416 unsigned first_component
)
2418 assert(type_sz(dst
.type
) == 4);
2419 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2420 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2422 /* TODO: figure out push input layout for invocations == 1 */
2423 if (gs_prog_data
->invocations
== 1 &&
2424 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2425 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2426 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2427 nir_src_as_uint(vertex_src
) * push_reg_count
;
2428 for (unsigned i
= 0; i
< num_components
; i
++) {
2429 bld
.MOV(offset(dst
, bld
, i
),
2430 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2435 /* Resort to the pull model. Ensure the VUE handles are provided. */
2436 assert(gs_prog_data
->base
.include_vue_handles
);
2438 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2439 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2441 if (gs_prog_data
->invocations
== 1) {
2442 if (nir_src_is_const(vertex_src
)) {
2443 /* The vertex index is constant; just select the proper URB handle. */
2445 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2446 BRW_REGISTER_TYPE_UD
);
2448 /* The vertex index is non-constant. We need to use indirect
2449 * addressing to fetch the proper URB handle.
2451 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2452 * indicating that channel <n> should read the handle from
2453 * DWord <n>. We convert that to bytes by multiplying by 4.
2455 * Next, we convert the vertex index to bytes by multiplying
2456 * by 32 (shifting by 5), and add the two together. This is
2457 * the final indirect byte offset.
2459 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2460 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2461 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2462 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2464 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2465 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2466 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2467 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2468 /* Convert vertex_index to bytes (multiply by 32) */
2469 bld
.SHL(vertex_offset_bytes
,
2470 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2472 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2474 /* Use first_icp_handle as the base offset. There is one register
2475 * of URB handles per vertex, so inform the register allocator that
2476 * we might read up to nir->info.gs.vertices_in registers.
2478 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2479 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2480 fs_reg(icp_offset_bytes
),
2481 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2484 assert(gs_prog_data
->invocations
> 1);
2486 if (nir_src_is_const(vertex_src
)) {
2487 unsigned vertex
= nir_src_as_uint(vertex_src
);
2488 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2490 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2491 BRW_REGISTER_TYPE_UD
));
2493 /* The vertex index is non-constant. We need to use indirect
2494 * addressing to fetch the proper URB handle.
2497 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2499 /* Convert vertex_index to bytes (multiply by 4) */
2500 bld
.SHL(icp_offset_bytes
,
2501 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2504 /* Use first_icp_handle as the base offset. There is one DWord
2505 * of URB handles per vertex, so inform the register allocator that
2506 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2508 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2509 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2510 fs_reg(icp_offset_bytes
),
2511 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2517 fs_reg indirect_offset
= get_nir_src(offset_src
);
2519 if (nir_src_is_const(offset_src
)) {
2520 /* Constant indexing - use global offset. */
2521 if (first_component
!= 0) {
2522 unsigned read_components
= num_components
+ first_component
;
2523 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2524 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2525 inst
->size_written
= read_components
*
2526 tmp
.component_size(inst
->exec_size
);
2527 for (unsigned i
= 0; i
< num_components
; i
++) {
2528 bld
.MOV(offset(dst
, bld
, i
),
2529 offset(tmp
, bld
, i
+ first_component
));
2532 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2533 inst
->size_written
= num_components
*
2534 dst
.component_size(inst
->exec_size
);
2536 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2539 /* Indirect indexing - use per-slot offsets as well. */
2540 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2541 unsigned read_components
= num_components
+ first_component
;
2542 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2543 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2544 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2545 if (first_component
!= 0) {
2546 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2548 inst
->size_written
= read_components
*
2549 tmp
.component_size(inst
->exec_size
);
2550 for (unsigned i
= 0; i
< num_components
; i
++) {
2551 bld
.MOV(offset(dst
, bld
, i
),
2552 offset(tmp
, bld
, i
+ first_component
));
2555 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2556 inst
->size_written
= num_components
*
2557 dst
.component_size(inst
->exec_size
);
2559 inst
->offset
= base_offset
;
2565 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2567 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2569 if (nir_src_is_const(*offset_src
)) {
2570 /* The only constant offset we should find is 0. brw_nir.c's
2571 * add_const_offset_to_base() will fold other constant offsets
2572 * into instr->const_index[0].
2574 assert(nir_src_as_uint(*offset_src
) == 0);
2578 return get_nir_src(*offset_src
);
2582 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2583 nir_intrinsic_instr
*instr
)
2585 assert(stage
== MESA_SHADER_VERTEX
);
2588 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2589 dest
= get_nir_dest(instr
->dest
);
2591 switch (instr
->intrinsic
) {
2592 case nir_intrinsic_load_vertex_id
:
2593 case nir_intrinsic_load_base_vertex
:
2594 unreachable("should be lowered by nir_lower_system_values()");
2596 case nir_intrinsic_load_input
: {
2597 assert(nir_dest_bit_size(instr
->dest
) == 32);
2598 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2599 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2600 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2602 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2603 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2607 case nir_intrinsic_load_vertex_id_zero_base
:
2608 case nir_intrinsic_load_instance_id
:
2609 case nir_intrinsic_load_base_instance
:
2610 case nir_intrinsic_load_draw_id
:
2611 case nir_intrinsic_load_first_vertex
:
2612 case nir_intrinsic_load_is_indexed_draw
:
2613 unreachable("lowered by brw_nir_lower_vs_inputs");
2616 nir_emit_intrinsic(bld
, instr
);
2622 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2623 nir_intrinsic_instr
*instr
)
2625 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2626 const nir_src
&vertex_src
= instr
->src
[0];
2627 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2630 if (nir_src_is_const(vertex_src
)) {
2631 /* Emit a MOV to resolve <0,1,0> regioning. */
2632 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2633 unsigned vertex
= nir_src_as_uint(vertex_src
);
2635 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2636 BRW_REGISTER_TYPE_UD
));
2637 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2638 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2639 /* For the common case of only 1 instance, an array index of
2640 * gl_InvocationID means reading g1. Skip all the indirect work.
2642 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2644 /* The vertex index is non-constant. We need to use indirect
2645 * addressing to fetch the proper URB handle.
2647 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2649 /* Each ICP handle is a single DWord (4 bytes) */
2650 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2651 bld
.SHL(vertex_offset_bytes
,
2652 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2655 /* Start at g1. We might read up to 4 registers. */
2656 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2657 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2658 brw_imm_ud(4 * REG_SIZE
));
2665 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2666 nir_intrinsic_instr
*instr
)
2668 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2669 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2670 const nir_src
&vertex_src
= instr
->src
[0];
2672 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2674 if (nir_src_is_const(vertex_src
)) {
2675 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2676 nir_src_as_uint(vertex_src
), 0),
2677 BRW_REGISTER_TYPE_UD
));
2680 /* The vertex index is non-constant. We need to use indirect
2681 * addressing to fetch the proper URB handle.
2683 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2684 * indicating that channel <n> should read the handle from
2685 * DWord <n>. We convert that to bytes by multiplying by 4.
2687 * Next, we convert the vertex index to bytes by multiplying
2688 * by 32 (shifting by 5), and add the two together. This is
2689 * the final indirect byte offset.
2691 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2692 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2693 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2694 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2695 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2697 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2698 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2699 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2700 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2701 /* Convert vertex_index to bytes (multiply by 32) */
2702 bld
.SHL(vertex_offset_bytes
,
2703 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2705 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2707 /* Use first_icp_handle as the base offset. There is one register
2708 * of URB handles per vertex, so inform the register allocator that
2709 * we might read up to nir->info.gs.vertices_in registers.
2711 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2712 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2713 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2719 fs_visitor::get_tcs_output_urb_handle()
2721 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2723 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2724 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2726 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2727 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2732 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2733 nir_intrinsic_instr
*instr
)
2735 assert(stage
== MESA_SHADER_TESS_CTRL
);
2736 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2737 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2738 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2741 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2744 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2745 dst
= get_nir_dest(instr
->dest
);
2747 switch (instr
->intrinsic
) {
2748 case nir_intrinsic_load_primitive_id
:
2749 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2750 : brw_vec1_grf(0, 1)));
2752 case nir_intrinsic_load_invocation_id
:
2753 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2755 case nir_intrinsic_load_patch_vertices_in
:
2756 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2757 brw_imm_d(tcs_key
->input_vertices
));
2760 case nir_intrinsic_control_barrier
: {
2761 if (tcs_prog_data
->instances
== 1)
2764 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2765 fs_reg m0_2
= component(m0
, 2);
2767 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2769 /* Zero the message header */
2770 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2772 if (devinfo
->gen
< 11) {
2773 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2774 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2775 brw_imm_ud(INTEL_MASK(16, 13)));
2777 /* Shift it up to bits 27:24. */
2778 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2780 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2781 brw_imm_ud(INTEL_MASK(30, 24)));
2784 /* Set the Barrier Count and the enable bit */
2785 if (devinfo
->gen
< 11) {
2786 chanbld
.OR(m0_2
, m0_2
,
2787 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2789 chanbld
.OR(m0_2
, m0_2
,
2790 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2793 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2797 case nir_intrinsic_load_input
:
2798 unreachable("nir_lower_io should never give us these.");
2801 case nir_intrinsic_load_per_vertex_input
: {
2802 assert(nir_dest_bit_size(instr
->dest
) == 32);
2803 fs_reg indirect_offset
= get_indirect_offset(instr
);
2804 unsigned imm_offset
= instr
->const_index
[0];
2808 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2809 : get_tcs_single_patch_icp_handle(bld
, instr
);
2811 /* We can only read two double components with each URB read, so
2812 * we send two read messages in that case, each one loading up to
2813 * two double components.
2815 unsigned num_components
= instr
->num_components
;
2816 unsigned first_component
= nir_intrinsic_component(instr
);
2818 if (indirect_offset
.file
== BAD_FILE
) {
2819 /* Constant indexing - use global offset. */
2820 if (first_component
!= 0) {
2821 unsigned read_components
= num_components
+ first_component
;
2822 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2823 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2824 for (unsigned i
= 0; i
< num_components
; i
++) {
2825 bld
.MOV(offset(dst
, bld
, i
),
2826 offset(tmp
, bld
, i
+ first_component
));
2829 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2831 inst
->offset
= imm_offset
;
2834 /* Indirect indexing - use per-slot offsets as well. */
2835 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2836 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2837 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2838 if (first_component
!= 0) {
2839 unsigned read_components
= num_components
+ first_component
;
2840 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2841 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2843 for (unsigned i
= 0; i
< num_components
; i
++) {
2844 bld
.MOV(offset(dst
, bld
, i
),
2845 offset(tmp
, bld
, i
+ first_component
));
2848 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2851 inst
->offset
= imm_offset
;
2854 inst
->size_written
= (num_components
+ first_component
) *
2855 inst
->dst
.component_size(inst
->exec_size
);
2857 /* Copy the temporary to the destination to deal with writemasking.
2859 * Also attempt to deal with gl_PointSize being in the .w component.
2861 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2862 assert(type_sz(dst
.type
) == 4);
2863 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2864 inst
->size_written
= 4 * REG_SIZE
;
2865 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2870 case nir_intrinsic_load_output
:
2871 case nir_intrinsic_load_per_vertex_output
: {
2872 assert(nir_dest_bit_size(instr
->dest
) == 32);
2873 fs_reg indirect_offset
= get_indirect_offset(instr
);
2874 unsigned imm_offset
= instr
->const_index
[0];
2875 unsigned first_component
= nir_intrinsic_component(instr
);
2877 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2880 if (indirect_offset
.file
== BAD_FILE
) {
2881 /* This MOV replicates the output handle to all enabled channels
2882 * is SINGLE_PATCH mode.
2884 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2885 bld
.MOV(patch_handle
, output_handles
);
2888 if (first_component
!= 0) {
2889 unsigned read_components
=
2890 instr
->num_components
+ first_component
;
2891 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2892 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2894 inst
->size_written
= read_components
* REG_SIZE
;
2895 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2896 bld
.MOV(offset(dst
, bld
, i
),
2897 offset(tmp
, bld
, i
+ first_component
));
2900 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2902 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2904 inst
->offset
= imm_offset
;
2908 /* Indirect indexing - use per-slot offsets as well. */
2909 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2910 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2911 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2912 if (first_component
!= 0) {
2913 unsigned read_components
=
2914 instr
->num_components
+ first_component
;
2915 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2916 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2918 inst
->size_written
= read_components
* REG_SIZE
;
2919 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2920 bld
.MOV(offset(dst
, bld
, i
),
2921 offset(tmp
, bld
, i
+ first_component
));
2924 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2926 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2928 inst
->offset
= imm_offset
;
2934 case nir_intrinsic_store_output
:
2935 case nir_intrinsic_store_per_vertex_output
: {
2936 assert(nir_src_bit_size(instr
->src
[0]) == 32);
2937 fs_reg value
= get_nir_src(instr
->src
[0]);
2938 fs_reg indirect_offset
= get_indirect_offset(instr
);
2939 unsigned imm_offset
= instr
->const_index
[0];
2940 unsigned mask
= instr
->const_index
[1];
2941 unsigned header_regs
= 0;
2942 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2945 srcs
[header_regs
++] = output_handles
;
2947 if (indirect_offset
.file
!= BAD_FILE
) {
2948 srcs
[header_regs
++] = indirect_offset
;
2954 unsigned num_components
= util_last_bit(mask
);
2957 /* We can only pack two 64-bit components in a single message, so send
2958 * 2 messages if we have more components
2960 unsigned first_component
= nir_intrinsic_component(instr
);
2961 mask
= mask
<< first_component
;
2963 if (mask
!= WRITEMASK_XYZW
) {
2964 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2965 opcode
= indirect_offset
.file
!= BAD_FILE
?
2966 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2967 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2969 opcode
= indirect_offset
.file
!= BAD_FILE
?
2970 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2971 SHADER_OPCODE_URB_WRITE_SIMD8
;
2974 for (unsigned i
= 0; i
< num_components
; i
++) {
2975 if (!(mask
& (1 << (i
+ first_component
))))
2978 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2981 unsigned mlen
= header_regs
+ num_components
+ first_component
;
2983 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2984 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2986 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2987 inst
->offset
= imm_offset
;
2993 nir_emit_intrinsic(bld
, instr
);
2999 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
3000 nir_intrinsic_instr
*instr
)
3002 assert(stage
== MESA_SHADER_TESS_EVAL
);
3003 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
3006 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3007 dest
= get_nir_dest(instr
->dest
);
3009 switch (instr
->intrinsic
) {
3010 case nir_intrinsic_load_primitive_id
:
3011 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
3013 case nir_intrinsic_load_tess_coord
:
3014 /* gl_TessCoord is part of the payload in g1-3 */
3015 for (unsigned i
= 0; i
< 3; i
++) {
3016 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
3020 case nir_intrinsic_load_input
:
3021 case nir_intrinsic_load_per_vertex_input
: {
3022 assert(nir_dest_bit_size(instr
->dest
) == 32);
3023 fs_reg indirect_offset
= get_indirect_offset(instr
);
3024 unsigned imm_offset
= instr
->const_index
[0];
3025 unsigned first_component
= nir_intrinsic_component(instr
);
3028 if (indirect_offset
.file
== BAD_FILE
) {
3029 /* Arbitrarily only push up to 32 vec4 slots worth of data,
3030 * which is 16 registers (since each holds 2 vec4 slots).
3032 const unsigned max_push_slots
= 32;
3033 if (imm_offset
< max_push_slots
) {
3034 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
3035 for (int i
= 0; i
< instr
->num_components
; i
++) {
3036 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
3037 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3040 tes_prog_data
->base
.urb_read_length
=
3041 MAX2(tes_prog_data
->base
.urb_read_length
,
3042 (imm_offset
/ 2) + 1);
3044 /* Replicate the patch handle to all enabled channels */
3045 const fs_reg srcs
[] = {
3046 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3048 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3049 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3051 if (first_component
!= 0) {
3052 unsigned read_components
=
3053 instr
->num_components
+ first_component
;
3054 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3055 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3057 inst
->size_written
= read_components
* REG_SIZE
;
3058 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3059 bld
.MOV(offset(dest
, bld
, i
),
3060 offset(tmp
, bld
, i
+ first_component
));
3063 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3065 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3068 inst
->offset
= imm_offset
;
3071 /* Indirect indexing - use per-slot offsets as well. */
3073 /* We can only read two double components with each URB read, so
3074 * we send two read messages in that case, each one loading up to
3075 * two double components.
3077 unsigned num_components
= instr
->num_components
;
3078 const fs_reg srcs
[] = {
3079 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3082 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3083 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3085 if (first_component
!= 0) {
3086 unsigned read_components
=
3087 num_components
+ first_component
;
3088 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3089 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3091 for (unsigned i
= 0; i
< num_components
; i
++) {
3092 bld
.MOV(offset(dest
, bld
, i
),
3093 offset(tmp
, bld
, i
+ first_component
));
3096 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3100 inst
->offset
= imm_offset
;
3101 inst
->size_written
= (num_components
+ first_component
) *
3102 inst
->dst
.component_size(inst
->exec_size
);
3107 nir_emit_intrinsic(bld
, instr
);
3113 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3114 nir_intrinsic_instr
*instr
)
3116 assert(stage
== MESA_SHADER_GEOMETRY
);
3117 fs_reg indirect_offset
;
3120 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3121 dest
= get_nir_dest(instr
->dest
);
3123 switch (instr
->intrinsic
) {
3124 case nir_intrinsic_load_primitive_id
:
3125 assert(stage
== MESA_SHADER_GEOMETRY
);
3126 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3127 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3128 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3131 case nir_intrinsic_load_input
:
3132 unreachable("load_input intrinsics are invalid for the GS stage");
3134 case nir_intrinsic_load_per_vertex_input
:
3135 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3136 instr
->src
[1], instr
->num_components
,
3137 nir_intrinsic_component(instr
));
3140 case nir_intrinsic_emit_vertex_with_counter
:
3141 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3144 case nir_intrinsic_end_primitive_with_counter
:
3145 emit_gs_end_primitive(instr
->src
[0]);
3148 case nir_intrinsic_set_vertex_count
:
3149 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3152 case nir_intrinsic_load_invocation_id
: {
3153 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3154 assert(val
.file
!= BAD_FILE
);
3155 dest
.type
= val
.type
;
3161 nir_emit_intrinsic(bld
, instr
);
3167 * Fetch the current render target layer index.
3170 fetch_render_target_array_index(const fs_builder
&bld
)
3172 if (bld
.shader
->devinfo
->gen
>= 12) {
3173 /* The render target array index is provided in the thread payload as
3174 * bits 26:16 of r1.1.
3176 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3177 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 1, 3),
3180 } else if (bld
.shader
->devinfo
->gen
>= 6) {
3181 /* The render target array index is provided in the thread payload as
3182 * bits 26:16 of r0.0.
3184 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3185 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3189 /* Pre-SNB we only ever render into the first layer of the framebuffer
3190 * since layered rendering is not implemented.
3192 return brw_imm_ud(0);
3197 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3198 * framebuffer at the current fragment coordinates and sample index.
3201 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3204 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3206 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3207 const brw_wm_prog_key
*wm_key
=
3208 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3209 assert(!wm_key
->coherent_fb_fetch
);
3210 const struct brw_wm_prog_data
*wm_prog_data
=
3211 brw_wm_prog_data(stage_prog_data
);
3213 /* Calculate the surface index relative to the start of the texture binding
3214 * table block, since that's what the texturing messages expect.
3216 const unsigned surface
= target
+
3217 wm_prog_data
->binding_table
.render_target_read_start
-
3218 wm_prog_data
->base
.binding_table
.texture_start
;
3220 /* Calculate the fragment coordinates. */
3221 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3222 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3223 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3224 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3226 /* Calculate the sample index and MCS payload when multisampling. Luckily
3227 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3228 * shouldn't be necessary to recompile based on whether the framebuffer is
3231 if (wm_key
->multisample_fbo
&&
3232 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3233 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3235 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3236 const fs_reg mcs
= wm_key
->multisample_fbo
?
3237 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3239 /* Use either a normal or a CMS texel fetch message depending on whether
3240 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3241 * message just in case the framebuffer uses 16x multisampling, it should
3242 * be equivalent to the normal CMS fetch for lower multisampling modes.
3244 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3245 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3246 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3248 /* Emit the instruction. */
3249 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3250 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3251 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3252 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3253 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3254 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3255 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3256 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3257 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3259 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3260 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3266 * Actual coherent framebuffer read implemented using the native render target
3267 * read message. Requires SKL+.
3270 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3272 assert(bld
.shader
->devinfo
->gen
>= 9);
3273 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3274 inst
->target
= target
;
3275 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3281 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3283 if (n
&& regs
[0].file
!= BAD_FILE
) {
3287 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3289 for (unsigned i
= 0; i
< n
; i
++)
3297 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3299 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3300 const brw_wm_prog_key
*const key
=
3301 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3302 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3303 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3305 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3306 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3308 else if (l
== FRAG_RESULT_COLOR
)
3309 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3310 MAX2(key
->nr_color_regions
, 1));
3312 else if (l
== FRAG_RESULT_DEPTH
)
3313 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3315 else if (l
== FRAG_RESULT_STENCIL
)
3316 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3318 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3319 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3321 else if (l
>= FRAG_RESULT_DATA0
&&
3322 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3323 return alloc_temporary(v
->bld
, 4,
3324 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3327 unreachable("Invalid location");
3331 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3332 nir_intrinsic_instr
*instr
)
3334 assert(stage
== MESA_SHADER_FRAGMENT
);
3337 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3338 dest
= get_nir_dest(instr
->dest
);
3340 switch (instr
->intrinsic
) {
3341 case nir_intrinsic_load_front_face
:
3342 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3343 *emit_frontfacing_interpolation());
3346 case nir_intrinsic_load_sample_pos
: {
3347 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3348 assert(sample_pos
.file
!= BAD_FILE
);
3349 dest
.type
= sample_pos
.type
;
3350 bld
.MOV(dest
, sample_pos
);
3351 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3355 case nir_intrinsic_load_layer_id
:
3356 dest
.type
= BRW_REGISTER_TYPE_UD
;
3357 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3360 case nir_intrinsic_is_helper_invocation
: {
3361 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3362 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3363 * consideration demoted invocations. That information is stored in
3366 dest
.type
= BRW_REGISTER_TYPE_UD
;
3368 bld
.MOV(dest
, brw_imm_ud(0));
3370 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3371 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3372 mov
->predicate_inverse
= true;
3373 mov
->flag_subreg
= sample_mask_flag_subreg(this);
3377 case nir_intrinsic_load_helper_invocation
:
3378 case nir_intrinsic_load_sample_mask_in
:
3379 case nir_intrinsic_load_sample_id
: {
3380 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3381 fs_reg val
= nir_system_values
[sv
];
3382 assert(val
.file
!= BAD_FILE
);
3383 dest
.type
= val
.type
;
3388 case nir_intrinsic_store_output
: {
3389 const fs_reg src
= get_nir_src(instr
->src
[0]);
3390 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3391 const unsigned location
= nir_intrinsic_base(instr
) +
3392 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3393 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3396 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3397 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3398 offset(src
, bld
, j
));
3403 case nir_intrinsic_load_output
: {
3404 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3405 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3406 assert(l
>= FRAG_RESULT_DATA0
);
3407 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3408 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3409 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3411 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3412 emit_coherent_fb_read(bld
, tmp
, target
);
3414 emit_non_coherent_fb_read(bld
, tmp
, target
);
3416 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3417 bld
.MOV(offset(dest
, bld
, j
),
3418 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3424 case nir_intrinsic_demote
:
3425 case nir_intrinsic_discard
:
3426 case nir_intrinsic_demote_if
:
3427 case nir_intrinsic_discard_if
: {
3428 /* We track our discarded pixels in f0.1/f1.0. By predicating on it, we
3429 * can update just the flag bits that aren't yet discarded. If there's
3430 * no condition, we emit a CMP of g0 != g0, so all currently executing
3431 * channels will get turned off.
3433 fs_inst
*cmp
= NULL
;
3434 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3435 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3436 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3439 alu
->op
!= nir_op_bcsel
&&
3440 (devinfo
->gen
> 5 ||
3441 (alu
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) != BRW_NIR_BOOLEAN_NEEDS_RESOLVE
||
3442 alu
->op
== nir_op_fneu32
|| alu
->op
== nir_op_feq32
||
3443 alu
->op
== nir_op_flt32
|| alu
->op
== nir_op_fge32
||
3444 alu
->op
== nir_op_ine32
|| alu
->op
== nir_op_ieq32
||
3445 alu
->op
== nir_op_ilt32
|| alu
->op
== nir_op_ige32
||
3446 alu
->op
== nir_op_ult32
|| alu
->op
== nir_op_uge32
)) {
3447 /* Re-emit the instruction that generated the Boolean value, but
3448 * do not store it. Since this instruction will be conditional,
3449 * other instructions that want to use the real Boolean value may
3450 * get garbage. This was a problem for piglit's fs-discard-exit-2
3453 * Ideally we'd detect that the instruction cannot have a
3454 * conditional modifier before emitting the instructions. Alas,
3455 * that is nigh impossible. Instead, we're going to assume the
3456 * instruction (or last instruction) generated can have a
3457 * conditional modifier. If it cannot, fallback to the old-style
3458 * compare, and hope dead code elimination will clean up the
3459 * extra instructions generated.
3461 nir_emit_alu(bld
, alu
, false);
3463 cmp
= (fs_inst
*) instructions
.get_tail();
3464 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3465 if (cmp
->can_do_cmod())
3466 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3470 /* The old sequence that would have been generated is,
3471 * basically, bool_result == false. This is equivalent to
3472 * !bool_result, so negate the old modifier.
3474 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3479 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3480 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3483 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3484 BRW_REGISTER_TYPE_UW
));
3485 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3488 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3489 cmp
->flag_subreg
= sample_mask_flag_subreg(this);
3491 emit_discard_jump();
3493 if (devinfo
->gen
< 7)
3494 limit_dispatch_width(
3495 16, "Fragment discard/demote not implemented in SIMD32 mode.\n");
3499 case nir_intrinsic_load_input
: {
3500 /* load_input is only used for flat inputs */
3501 assert(nir_dest_bit_size(instr
->dest
) == 32);
3502 unsigned base
= nir_intrinsic_base(instr
);
3503 unsigned comp
= nir_intrinsic_component(instr
);
3504 unsigned num_components
= instr
->num_components
;
3506 /* Special case fields in the VUE header */
3507 if (base
== VARYING_SLOT_LAYER
)
3509 else if (base
== VARYING_SLOT_VIEWPORT
)
3512 for (unsigned int i
= 0; i
< num_components
; i
++) {
3513 bld
.MOV(offset(dest
, bld
, i
),
3514 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3519 case nir_intrinsic_load_fs_input_interp_deltas
: {
3520 assert(stage
== MESA_SHADER_FRAGMENT
);
3521 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3522 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3523 nir_intrinsic_component(instr
));
3524 dest
.type
= BRW_REGISTER_TYPE_F
;
3525 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3526 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3527 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3531 case nir_intrinsic_load_barycentric_pixel
:
3532 case nir_intrinsic_load_barycentric_centroid
:
3533 case nir_intrinsic_load_barycentric_sample
: {
3534 /* Use the delta_xy values computed from the payload */
3535 const glsl_interp_mode interp_mode
=
3536 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3537 enum brw_barycentric_mode bary
=
3538 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3539 const fs_reg srcs
[] = { offset(this->delta_xy
[bary
], bld
, 0),
3540 offset(this->delta_xy
[bary
], bld
, 1) };
3541 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3545 case nir_intrinsic_load_barycentric_at_sample
: {
3546 const glsl_interp_mode interpolation
=
3547 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3549 if (nir_src_is_const(instr
->src
[0])) {
3550 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3552 emit_pixel_interpolater_send(bld
,
3553 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3556 brw_imm_ud(msg_data
),
3559 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3560 BRW_REGISTER_TYPE_UD
);
3562 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3563 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3564 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3565 bld
.exec_all().group(1, 0)
3566 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3567 emit_pixel_interpolater_send(bld
,
3568 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3571 component(msg_data
, 0),
3574 /* Make a loop that sends a message to the pixel interpolater
3575 * for the sample number in each live channel. If there are
3576 * multiple channels with the same sample number then these
3577 * will be handled simultaneously with a single interation of
3580 bld
.emit(BRW_OPCODE_DO
);
3582 /* Get the next live sample number into sample_id_reg */
3583 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3585 /* Set the flag register so that we can perform the send
3586 * message on all channels that have the same sample number
3588 bld
.CMP(bld
.null_reg_ud(),
3589 sample_src
, sample_id
,
3590 BRW_CONDITIONAL_EQ
);
3591 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3592 bld
.exec_all().group(1, 0)
3593 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3595 emit_pixel_interpolater_send(bld
,
3596 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3599 component(msg_data
, 0),
3601 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3603 /* Continue the loop if there are any live channels left */
3604 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3606 bld
.emit(BRW_OPCODE_WHILE
));
3612 case nir_intrinsic_load_barycentric_at_offset
: {
3613 const glsl_interp_mode interpolation
=
3614 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3616 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3619 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3620 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3621 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3623 emit_pixel_interpolater_send(bld
,
3624 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3627 brw_imm_ud(off_x
| (off_y
<< 4)),
3630 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3631 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3632 BRW_REGISTER_TYPE_F
);
3633 for (int i
= 0; i
< 2; i
++) {
3634 fs_reg temp
= vgrf(glsl_type::float_type
);
3635 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3636 fs_reg itemp
= vgrf(glsl_type::int_type
);
3638 bld
.MOV(itemp
, temp
);
3640 /* Clamp the upper end of the range to +7/16.
3641 * ARB_gpu_shader5 requires that we support a maximum offset
3642 * of +0.5, which isn't representable in a S0.4 value -- if
3643 * we didn't clamp it, we'd end up with -8/16, which is the
3644 * opposite of what the shader author wanted.
3646 * This is legal due to ARB_gpu_shader5's quantization
3649 * "Not all values of <offset> may be supported; x and y
3650 * offsets may be rounded to fixed-point values with the
3651 * number of fraction bits given by the
3652 * implementation-dependent constant
3653 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3655 set_condmod(BRW_CONDITIONAL_L
,
3656 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3659 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3660 emit_pixel_interpolater_send(bld
,
3670 case nir_intrinsic_load_frag_coord
:
3671 emit_fragcoord_interpolation(dest
);
3674 case nir_intrinsic_load_interpolated_input
: {
3675 assert(instr
->src
[0].ssa
&&
3676 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3677 nir_intrinsic_instr
*bary_intrinsic
=
3678 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3679 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3680 enum glsl_interp_mode interp_mode
=
3681 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3684 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3685 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3686 /* Use the result of the PI message. */
3687 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3689 /* Use the delta_xy values computed from the payload */
3690 enum brw_barycentric_mode bary
=
3691 brw_barycentric_mode(interp_mode
, bary_intrin
);
3692 dst_xy
= this->delta_xy
[bary
];
3695 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3697 component(interp_reg(nir_intrinsic_base(instr
),
3698 nir_intrinsic_component(instr
) + i
), 0);
3699 interp
.type
= BRW_REGISTER_TYPE_F
;
3700 dest
.type
= BRW_REGISTER_TYPE_F
;
3702 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3703 fs_reg tmp
= vgrf(glsl_type::float_type
);
3704 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3705 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3707 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3714 nir_emit_intrinsic(bld
, instr
);
3720 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3721 nir_intrinsic_instr
*instr
)
3723 assert(stage
== MESA_SHADER_COMPUTE
|| stage
== MESA_SHADER_KERNEL
);
3724 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3727 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3728 dest
= get_nir_dest(instr
->dest
);
3730 switch (instr
->intrinsic
) {
3731 case nir_intrinsic_control_barrier
:
3732 /* The whole workgroup fits in a single HW thread, so all the
3733 * invocations are already executed lock-step. Instead of an actual
3734 * barrier just emit a scheduling fence, that will generate no code.
3736 if (!nir
->info
.cs
.local_size_variable
&&
3737 workgroup_size() <= dispatch_width
) {
3738 bld
.exec_all().group(1, 0).emit(FS_OPCODE_SCHEDULING_FENCE
);
3743 cs_prog_data
->uses_barrier
= true;
3746 case nir_intrinsic_load_subgroup_id
:
3747 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3750 case nir_intrinsic_load_local_invocation_id
:
3751 case nir_intrinsic_load_work_group_id
: {
3752 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3753 fs_reg val
= nir_system_values
[sv
];
3754 assert(val
.file
!= BAD_FILE
);
3755 dest
.type
= val
.type
;
3756 for (unsigned i
= 0; i
< 3; i
++)
3757 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3761 case nir_intrinsic_load_num_work_groups
: {
3762 const unsigned surface
=
3763 cs_prog_data
->binding_table
.work_groups_start
;
3765 cs_prog_data
->uses_num_work_groups
= true;
3767 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3768 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3769 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3770 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3772 /* Read the 3 GLuint components of gl_NumWorkGroups */
3773 for (unsigned i
= 0; i
< 3; i
++) {
3774 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3775 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3776 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3781 case nir_intrinsic_shared_atomic_add
:
3782 case nir_intrinsic_shared_atomic_imin
:
3783 case nir_intrinsic_shared_atomic_umin
:
3784 case nir_intrinsic_shared_atomic_imax
:
3785 case nir_intrinsic_shared_atomic_umax
:
3786 case nir_intrinsic_shared_atomic_and
:
3787 case nir_intrinsic_shared_atomic_or
:
3788 case nir_intrinsic_shared_atomic_xor
:
3789 case nir_intrinsic_shared_atomic_exchange
:
3790 case nir_intrinsic_shared_atomic_comp_swap
:
3791 nir_emit_shared_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3793 case nir_intrinsic_shared_atomic_fmin
:
3794 case nir_intrinsic_shared_atomic_fmax
:
3795 case nir_intrinsic_shared_atomic_fcomp_swap
:
3796 nir_emit_shared_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3799 case nir_intrinsic_load_shared
: {
3800 assert(devinfo
->gen
>= 7);
3801 assert(stage
== MESA_SHADER_COMPUTE
|| stage
== MESA_SHADER_KERNEL
);
3803 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3804 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3805 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3806 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3807 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3809 /* Make dest unsigned because that's what the temporary will be */
3810 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3812 /* Read the vector */
3813 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3814 assert(nir_intrinsic_align(instr
) > 0);
3815 if (nir_dest_bit_size(instr
->dest
) == 32 &&
3816 nir_intrinsic_align(instr
) >= 4) {
3817 assert(nir_dest_num_components(instr
->dest
) <= 4);
3818 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3820 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3821 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3822 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3824 assert(nir_dest_num_components(instr
->dest
) == 1);
3825 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3827 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3828 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3829 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3830 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3835 case nir_intrinsic_store_shared
: {
3836 assert(devinfo
->gen
>= 7);
3837 assert(stage
== MESA_SHADER_COMPUTE
|| stage
== MESA_SHADER_KERNEL
);
3839 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3840 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3841 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3842 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3843 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3845 fs_reg data
= get_nir_src(instr
->src
[0]);
3846 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3848 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3849 assert(nir_intrinsic_write_mask(instr
) ==
3850 (1u << instr
->num_components
) - 1);
3851 assert(nir_intrinsic_align(instr
) > 0);
3852 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
3853 nir_intrinsic_align(instr
) >= 4) {
3854 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3855 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3856 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3857 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3858 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3860 assert(nir_src_num_components(instr
->src
[0]) == 1);
3861 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3863 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3864 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3866 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3867 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3872 case nir_intrinsic_load_local_group_size
: {
3873 assert(compiler
->lower_variable_group_size
);
3874 assert(nir
->info
.cs
.local_size_variable
);
3875 for (unsigned i
= 0; i
< 3; i
++) {
3876 bld
.MOV(retype(offset(dest
, bld
, i
), BRW_REGISTER_TYPE_UD
),
3883 nir_emit_intrinsic(bld
, instr
);
3889 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3890 nir_op op
, brw_reg_type type
)
3892 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3893 switch (type_sz(type
)) {
3895 if (type
== BRW_REGISTER_TYPE_UB
) {
3896 return brw_imm_uw(value
.u8
);
3898 assert(type
== BRW_REGISTER_TYPE_B
);
3899 return brw_imm_w(value
.i8
);
3902 return retype(brw_imm_uw(value
.u16
), type
);
3904 return retype(brw_imm_ud(value
.u32
), type
);
3906 if (type
== BRW_REGISTER_TYPE_DF
)
3907 return setup_imm_df(bld
, value
.f64
);
3909 return retype(brw_imm_u64(value
.u64
), type
);
3911 unreachable("Invalid type size");
3916 brw_op_for_nir_reduction_op(nir_op op
)
3919 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3920 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3921 case nir_op_imul
: return BRW_OPCODE_MUL
;
3922 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3923 case nir_op_imin
: return BRW_OPCODE_SEL
;
3924 case nir_op_umin
: return BRW_OPCODE_SEL
;
3925 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3926 case nir_op_imax
: return BRW_OPCODE_SEL
;
3927 case nir_op_umax
: return BRW_OPCODE_SEL
;
3928 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3929 case nir_op_iand
: return BRW_OPCODE_AND
;
3930 case nir_op_ior
: return BRW_OPCODE_OR
;
3931 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3933 unreachable("Invalid reduction operation");
3937 static brw_conditional_mod
3938 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3941 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3942 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3943 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3944 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3945 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3946 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3947 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3948 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3949 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3950 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3951 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3952 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3953 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3955 unreachable("Invalid reduction operation");
3960 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3961 nir_intrinsic_instr
*instr
)
3963 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3964 fs_reg surf_index
= image
;
3966 if (stage_prog_data
->binding_table
.image_start
> 0) {
3967 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3969 brw_imm_ud(image
.d
+ stage_prog_data
->binding_table
.image_start
);
3971 surf_index
= vgrf(glsl_type::uint_type
);
3972 bld
.ADD(surf_index
, image
,
3973 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3977 return bld
.emit_uniformize(surf_index
);
3981 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3982 nir_intrinsic_instr
*instr
)
3984 /* SSBO stores are weird in that their index is in src[1] */
3985 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3988 if (nir_src_is_const(instr
->src
[src
])) {
3989 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3990 nir_src_as_uint(instr
->src
[src
]);
3991 surf_index
= brw_imm_ud(index
);
3993 surf_index
= vgrf(glsl_type::uint_type
);
3994 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3995 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3998 return bld
.emit_uniformize(surf_index
);
4002 * The offsets we get from NIR act as if each SIMD channel has it's own blob
4003 * of contiguous space. However, if we actually place each SIMD channel in
4004 * it's own space, we end up with terrible cache performance because each SIMD
4005 * channel accesses a different cache line even when they're all accessing the
4006 * same byte offset. To deal with this problem, we swizzle the address using
4007 * a simple algorithm which ensures that any time a SIMD message reads or
4008 * writes the same address, it's all in the same cache line. We have to keep
4009 * the bottom two bits fixed so that we can read/write up to a dword at a time
4010 * and the individual element is contiguous. We do this by splitting the
4011 * address as follows:
4014 * +-------------------------------+------------+----------+
4015 * | Hi address bits | chan index | addr low |
4016 * +-------------------------------+------------+----------+
4018 * In other words, the bottom two address bits stay, and the top 30 get
4019 * shifted up so that we can stick the SIMD channel index in the middle. This
4020 * way, we can access 8, 16, or 32-bit elements and, when accessing a 32-bit
4021 * at the same logical offset, the scratch read/write instruction acts on
4022 * continuous elements and we get good cache locality.
4025 fs_visitor::swizzle_nir_scratch_addr(const brw::fs_builder
&bld
,
4026 const fs_reg
&nir_addr
,
4029 const fs_reg
&chan_index
=
4030 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
4031 const unsigned chan_index_bits
= ffs(dispatch_width
) - 1;
4033 fs_reg addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4035 /* In this case, we know the address is aligned to a DWORD and we want
4036 * the final address in DWORDs.
4038 bld
.SHL(addr
, nir_addr
, brw_imm_ud(chan_index_bits
- 2));
4039 bld
.OR(addr
, addr
, chan_index
);
4041 /* This case substantially more annoying because we have to pay
4042 * attention to those pesky two bottom bits.
4044 fs_reg addr_hi
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4045 bld
.AND(addr_hi
, nir_addr
, brw_imm_ud(~0x3u
));
4046 bld
.SHL(addr_hi
, addr_hi
, brw_imm_ud(chan_index_bits
));
4047 fs_reg chan_addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4048 bld
.SHL(chan_addr
, chan_index
, brw_imm_ud(2));
4049 bld
.AND(addr
, nir_addr
, brw_imm_ud(0x3u
));
4050 bld
.OR(addr
, addr
, addr_hi
);
4051 bld
.OR(addr
, addr
, chan_addr
);
4057 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4060 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4061 dest
= get_nir_dest(instr
->dest
);
4063 switch (instr
->intrinsic
) {
4064 case nir_intrinsic_image_load
:
4065 case nir_intrinsic_image_store
:
4066 case nir_intrinsic_image_atomic_add
:
4067 case nir_intrinsic_image_atomic_imin
:
4068 case nir_intrinsic_image_atomic_umin
:
4069 case nir_intrinsic_image_atomic_imax
:
4070 case nir_intrinsic_image_atomic_umax
:
4071 case nir_intrinsic_image_atomic_and
:
4072 case nir_intrinsic_image_atomic_or
:
4073 case nir_intrinsic_image_atomic_xor
:
4074 case nir_intrinsic_image_atomic_exchange
:
4075 case nir_intrinsic_image_atomic_comp_swap
:
4076 case nir_intrinsic_bindless_image_load
:
4077 case nir_intrinsic_bindless_image_store
:
4078 case nir_intrinsic_bindless_image_atomic_add
:
4079 case nir_intrinsic_bindless_image_atomic_imin
:
4080 case nir_intrinsic_bindless_image_atomic_umin
:
4081 case nir_intrinsic_bindless_image_atomic_imax
:
4082 case nir_intrinsic_bindless_image_atomic_umax
:
4083 case nir_intrinsic_bindless_image_atomic_and
:
4084 case nir_intrinsic_bindless_image_atomic_or
:
4085 case nir_intrinsic_bindless_image_atomic_xor
:
4086 case nir_intrinsic_bindless_image_atomic_exchange
:
4087 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4088 /* Get some metadata from the image intrinsic. */
4089 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4091 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4093 switch (instr
->intrinsic
) {
4094 case nir_intrinsic_image_load
:
4095 case nir_intrinsic_image_store
:
4096 case nir_intrinsic_image_atomic_add
:
4097 case nir_intrinsic_image_atomic_imin
:
4098 case nir_intrinsic_image_atomic_umin
:
4099 case nir_intrinsic_image_atomic_imax
:
4100 case nir_intrinsic_image_atomic_umax
:
4101 case nir_intrinsic_image_atomic_and
:
4102 case nir_intrinsic_image_atomic_or
:
4103 case nir_intrinsic_image_atomic_xor
:
4104 case nir_intrinsic_image_atomic_exchange
:
4105 case nir_intrinsic_image_atomic_comp_swap
:
4106 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4107 get_nir_image_intrinsic_image(bld
, instr
);
4112 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4113 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4117 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4118 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4119 brw_imm_ud(nir_image_intrinsic_coord_components(instr
));
4121 /* Emit an image load, store or atomic op. */
4122 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4123 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4124 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4126 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4127 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4128 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4129 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4130 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4131 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4132 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4133 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4134 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4136 unsigned num_srcs
= info
->num_srcs
;
4137 int op
= brw_aop_for_nir_intrinsic(instr
);
4138 if (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
) {
4139 assert(num_srcs
== 4);
4143 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4147 data
= get_nir_src(instr
->src
[3]);
4148 if (num_srcs
>= 5) {
4149 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4150 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4151 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4154 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4156 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4157 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4162 case nir_intrinsic_image_size
:
4163 case nir_intrinsic_bindless_image_size
: {
4164 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4165 * into will handle the binding table index for us in the geneerator.
4166 * Incidentally, this means that we can handle bindless with exactly the
4169 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4170 BRW_REGISTER_TYPE_UD
);
4171 image
= bld
.emit_uniformize(image
);
4173 assert(nir_src_as_uint(instr
->src
[1]) == 0);
4175 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4176 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4177 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4179 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4180 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4181 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4182 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4184 /* Since the image size is always uniform, we can just emit a SIMD8
4185 * query instruction and splat the result out.
4187 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4189 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4190 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4191 tmp
, srcs
, ARRAY_SIZE(srcs
));
4192 inst
->size_written
= 4 * REG_SIZE
;
4194 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4195 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4196 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4197 offset(retype(dest
, tmp
.type
), bld
, c
),
4198 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4200 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4201 component(offset(tmp
, ubld
, c
), 0));
4207 case nir_intrinsic_image_load_raw_intel
: {
4208 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4209 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4210 get_nir_image_intrinsic_image(bld
, instr
);
4211 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4212 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4213 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4216 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4217 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4218 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4222 case nir_intrinsic_image_store_raw_intel
: {
4223 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4224 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4225 get_nir_image_intrinsic_image(bld
, instr
);
4226 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4227 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4228 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4229 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4231 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4232 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4236 case nir_intrinsic_scoped_barrier
:
4237 assert(nir_intrinsic_execution_scope(instr
) == NIR_SCOPE_NONE
);
4239 case nir_intrinsic_group_memory_barrier
:
4240 case nir_intrinsic_memory_barrier_shared
:
4241 case nir_intrinsic_memory_barrier_buffer
:
4242 case nir_intrinsic_memory_barrier_image
:
4243 case nir_intrinsic_memory_barrier
:
4244 case nir_intrinsic_begin_invocation_interlock
:
4245 case nir_intrinsic_end_invocation_interlock
: {
4246 bool l3_fence
, slm_fence
;
4247 const enum opcode opcode
=
4248 instr
->intrinsic
== nir_intrinsic_begin_invocation_interlock
?
4249 SHADER_OPCODE_INTERLOCK
: SHADER_OPCODE_MEMORY_FENCE
;
4251 switch (instr
->intrinsic
) {
4252 case nir_intrinsic_scoped_barrier
: {
4253 nir_variable_mode modes
= nir_intrinsic_memory_modes(instr
);
4254 l3_fence
= modes
& (nir_var_shader_out
|
4256 nir_var_mem_global
);
4257 slm_fence
= modes
& nir_var_mem_shared
;
4261 case nir_intrinsic_begin_invocation_interlock
:
4262 case nir_intrinsic_end_invocation_interlock
:
4263 /* For beginInvocationInterlockARB(), we will generate a memory fence
4264 * but with a different opcode so that generator can pick SENDC
4267 * For endInvocationInterlockARB(), we need to insert a memory fence which
4268 * stalls in the shader until the memory transactions prior to that
4269 * fence are complete. This ensures that the shader does not end before
4270 * any writes from its critical section have landed. Otherwise, you can
4271 * end up with a case where the next invocation on that pixel properly
4272 * stalls for previous FS invocation on its pixel to complete but
4273 * doesn't actually wait for the dataport memory transactions from that
4274 * thread to land before submitting its own.
4276 * Handling them here will allow the logic for IVB render cache (see
4277 * below) to be reused.
4284 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4285 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4286 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4287 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4291 if (stage
!= MESA_SHADER_COMPUTE
&& stage
!= MESA_SHADER_KERNEL
)
4294 /* If the workgroup fits in a single HW thread, the messages for SLM are
4295 * processed in-order and the shader itself is already synchronized so
4296 * the memory fence is not necessary.
4298 * TODO: Check if applies for many HW threads sharing same Data Port.
4300 if (!nir
->info
.cs
.local_size_variable
&&
4301 slm_fence
&& workgroup_size() <= dispatch_width
)
4304 /* Prior to Gen11, there's only L3 fence, so emit that instead. */
4305 if (slm_fence
&& devinfo
->gen
< 11) {
4310 /* IVB does typed surface access through the render cache, so we need
4313 const bool needs_render_fence
=
4314 devinfo
->gen
== 7 && !devinfo
->is_haswell
;
4316 /* Be conservative in Gen11+ and always stall in a fence. Since there
4317 * are two different fences, and shader might want to synchronize
4320 * TODO: Use scope and visibility information for the barriers from NIR
4321 * to make a better decision on whether we need to stall.
4323 const bool stall
= devinfo
->gen
>= 11 || needs_render_fence
||
4324 instr
->intrinsic
== nir_intrinsic_end_invocation_interlock
;
4326 const bool commit_enable
= stall
||
4327 devinfo
->gen
>= 10; /* HSD ES # 1404612949 */
4329 unsigned fence_regs_count
= 0;
4330 fs_reg fence_regs
[2] = {};
4332 const fs_builder ubld
= bld
.group(8, 0);
4337 ubld
.vgrf(BRW_REGISTER_TYPE_UD
),
4339 brw_imm_ud(commit_enable
),
4340 brw_imm_ud(/* bti */ 0));
4341 fence
->sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
4343 fence_regs
[fence_regs_count
++] = fence
->dst
;
4345 if (needs_render_fence
) {
4346 fs_inst
*render_fence
=
4348 ubld
.vgrf(BRW_REGISTER_TYPE_UD
),
4350 brw_imm_ud(commit_enable
),
4351 brw_imm_ud(/* bti */ 0));
4352 render_fence
->sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
4354 fence_regs
[fence_regs_count
++] = render_fence
->dst
;
4359 assert(opcode
== SHADER_OPCODE_MEMORY_FENCE
);
4362 ubld
.vgrf(BRW_REGISTER_TYPE_UD
),
4364 brw_imm_ud(commit_enable
),
4365 brw_imm_ud(GEN7_BTI_SLM
));
4366 fence
->sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
4368 fence_regs
[fence_regs_count
++] = fence
->dst
;
4371 assert(fence_regs_count
<= 2);
4373 if (stall
|| fence_regs_count
== 0) {
4374 ubld
.exec_all().group(1, 0).emit(
4375 FS_OPCODE_SCHEDULING_FENCE
, ubld
.null_reg_ud(),
4376 fence_regs
, fence_regs_count
);
4382 case nir_intrinsic_memory_barrier_tcs_patch
:
4385 case nir_intrinsic_shader_clock
: {
4386 /* We cannot do anything if there is an event, so ignore it for now */
4387 const fs_reg shader_clock
= get_timestamp(bld
);
4388 const fs_reg srcs
[] = { component(shader_clock
, 0),
4389 component(shader_clock
, 1) };
4390 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4394 case nir_intrinsic_image_samples
:
4395 /* The driver does not support multi-sampled images. */
4396 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4399 case nir_intrinsic_load_uniform
: {
4400 /* Offsets are in bytes but they should always aligned to
4403 assert(instr
->const_index
[0] % 4 == 0 ||
4404 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4406 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4408 if (nir_src_is_const(instr
->src
[0])) {
4409 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4410 assert(load_offset
% type_sz(dest
.type
) == 0);
4411 /* For 16-bit types we add the module of the const_index[0]
4412 * offset to access to not 32-bit aligned element
4414 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4416 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4417 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4420 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4421 BRW_REGISTER_TYPE_UD
);
4423 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4424 * go past the end of the uniform. In order to keep the n'th
4425 * component from running past, we subtract off the size of all but
4426 * one component of the vector.
4428 assert(instr
->const_index
[1] >=
4429 instr
->num_components
* (int) type_sz(dest
.type
));
4430 unsigned read_size
= instr
->const_index
[1] -
4431 (instr
->num_components
- 1) * type_sz(dest
.type
);
4433 bool supports_64bit_indirects
=
4434 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4436 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4437 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4438 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4439 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4440 indirect
, brw_imm_ud(read_size
));
4443 const unsigned num_mov_indirects
=
4444 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4445 /* We read a little bit less per MOV INDIRECT, as they are now
4446 * 32-bits ones instead of 64-bit. Fix read_size then.
4448 const unsigned read_size_32bit
= read_size
-
4449 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4450 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4451 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4452 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4453 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4454 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4455 indirect
, brw_imm_ud(read_size_32bit
));
4463 case nir_intrinsic_load_ubo
: {
4465 if (nir_src_is_const(instr
->src
[0])) {
4466 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4467 nir_src_as_uint(instr
->src
[0]);
4468 surf_index
= brw_imm_ud(index
);
4470 /* The block index is not a constant. Evaluate the index expression
4471 * per-channel and add the base UBO index; we have to select a value
4472 * from any live channel.
4474 surf_index
= vgrf(glsl_type::uint_type
);
4475 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4476 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4477 surf_index
= bld
.emit_uniformize(surf_index
);
4480 if (!nir_src_is_const(instr
->src
[1])) {
4481 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4482 BRW_REGISTER_TYPE_UD
);
4484 for (int i
= 0; i
< instr
->num_components
; i
++)
4485 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4486 base_offset
, i
* type_sz(dest
.type
));
4488 prog_data
->has_ubo_pull
= true;
4490 /* Even if we are loading doubles, a pull constant load will load
4491 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4492 * need to load a full dvec4 we will have to emit 2 loads. This is
4493 * similar to demote_pull_constants(), except that in that case we
4494 * see individual accesses to each component of the vector and then
4495 * we let CSE deal with duplicate loads. Here we see a vector access
4496 * and we have to split it if necessary.
4498 const unsigned type_size
= type_sz(dest
.type
);
4499 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4501 /* See if we've selected this as a push constant candidate */
4502 if (nir_src_is_const(instr
->src
[0])) {
4503 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4504 const unsigned offset_256b
= load_offset
/ 32;
4507 for (int i
= 0; i
< 4; i
++) {
4508 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4509 if (range
->block
== ubo_block
&&
4510 offset_256b
>= range
->start
&&
4511 offset_256b
< range
->start
+ range
->length
) {
4513 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4514 push_reg
.offset
= load_offset
- 32 * range
->start
;
4519 if (push_reg
.file
!= BAD_FILE
) {
4520 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4521 bld
.MOV(offset(dest
, bld
, i
),
4522 byte_offset(push_reg
, i
* type_size
));
4528 prog_data
->has_ubo_pull
= true;
4530 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4531 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4532 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4534 for (unsigned c
= 0; c
< instr
->num_components
;) {
4535 const unsigned base
= load_offset
+ c
* type_size
;
4536 /* Number of usable components in the next block-aligned load. */
4537 const unsigned count
= MIN2(instr
->num_components
- c
,
4538 (block_sz
- base
% block_sz
) / type_size
);
4540 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4541 packed_consts
, surf_index
,
4542 brw_imm_ud(base
& ~(block_sz
- 1)));
4544 const fs_reg consts
=
4545 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4548 for (unsigned d
= 0; d
< count
; d
++)
4549 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4557 case nir_intrinsic_load_global
:
4558 case nir_intrinsic_load_global_constant
: {
4559 assert(devinfo
->gen
>= 8);
4561 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4562 assert(nir_intrinsic_align(instr
) > 0);
4563 if (nir_dest_bit_size(instr
->dest
) == 32 &&
4564 nir_intrinsic_align(instr
) >= 4) {
4565 assert(nir_dest_num_components(instr
->dest
) <= 4);
4566 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4568 get_nir_src(instr
->src
[0]), /* Address */
4569 fs_reg(), /* No source data */
4570 brw_imm_ud(instr
->num_components
));
4571 inst
->size_written
= instr
->num_components
*
4572 inst
->dst
.component_size(inst
->exec_size
);
4574 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4575 assert(nir_dest_num_components(instr
->dest
) == 1);
4576 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4577 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4579 get_nir_src(instr
->src
[0]), /* Address */
4580 fs_reg(), /* No source data */
4581 brw_imm_ud(bit_size
));
4582 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4587 case nir_intrinsic_store_global
:
4588 assert(devinfo
->gen
>= 8);
4590 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4591 assert(nir_intrinsic_write_mask(instr
) ==
4592 (1u << instr
->num_components
) - 1);
4593 assert(nir_intrinsic_align(instr
) > 0);
4594 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4595 nir_intrinsic_align(instr
) >= 4) {
4596 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4597 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4599 get_nir_src(instr
->src
[1]), /* Address */
4600 get_nir_src(instr
->src
[0]), /* Data */
4601 brw_imm_ud(instr
->num_components
));
4603 assert(nir_src_num_components(instr
->src
[0]) == 1);
4604 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4605 brw_reg_type data_type
=
4606 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4607 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4608 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4609 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4611 get_nir_src(instr
->src
[1]), /* Address */
4613 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4617 case nir_intrinsic_global_atomic_add
:
4618 case nir_intrinsic_global_atomic_imin
:
4619 case nir_intrinsic_global_atomic_umin
:
4620 case nir_intrinsic_global_atomic_imax
:
4621 case nir_intrinsic_global_atomic_umax
:
4622 case nir_intrinsic_global_atomic_and
:
4623 case nir_intrinsic_global_atomic_or
:
4624 case nir_intrinsic_global_atomic_xor
:
4625 case nir_intrinsic_global_atomic_exchange
:
4626 case nir_intrinsic_global_atomic_comp_swap
:
4627 nir_emit_global_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4629 case nir_intrinsic_global_atomic_fmin
:
4630 case nir_intrinsic_global_atomic_fmax
:
4631 case nir_intrinsic_global_atomic_fcomp_swap
:
4632 nir_emit_global_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4635 case nir_intrinsic_load_ssbo
: {
4636 assert(devinfo
->gen
>= 7);
4638 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4639 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4640 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4641 get_nir_ssbo_intrinsic_index(bld
, instr
);
4642 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4643 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4645 /* Make dest unsigned because that's what the temporary will be */
4646 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4648 /* Read the vector */
4649 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4650 assert(nir_intrinsic_align(instr
) > 0);
4651 if (nir_dest_bit_size(instr
->dest
) == 32 &&
4652 nir_intrinsic_align(instr
) >= 4) {
4653 assert(nir_dest_num_components(instr
->dest
) <= 4);
4654 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4656 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4657 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4658 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4660 assert(nir_dest_num_components(instr
->dest
) == 1);
4661 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4663 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4664 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4665 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4666 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4671 case nir_intrinsic_store_ssbo
: {
4672 assert(devinfo
->gen
>= 7);
4674 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4675 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4676 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4677 get_nir_ssbo_intrinsic_index(bld
, instr
);
4678 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4679 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4681 fs_reg data
= get_nir_src(instr
->src
[0]);
4682 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4684 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4685 assert(nir_intrinsic_write_mask(instr
) ==
4686 (1u << instr
->num_components
) - 1);
4687 assert(nir_intrinsic_align(instr
) > 0);
4688 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4689 nir_intrinsic_align(instr
) >= 4) {
4690 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4691 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4692 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4693 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4694 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4696 assert(nir_src_num_components(instr
->src
[0]) == 1);
4697 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4699 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4700 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4702 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4703 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4708 case nir_intrinsic_store_output
: {
4709 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4710 fs_reg src
= get_nir_src(instr
->src
[0]);
4712 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4713 unsigned num_components
= instr
->num_components
;
4714 unsigned first_component
= nir_intrinsic_component(instr
);
4716 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4717 4 * store_offset
), src
.type
);
4718 for (unsigned j
= 0; j
< num_components
; j
++) {
4719 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4720 offset(src
, bld
, j
));
4725 case nir_intrinsic_ssbo_atomic_add
:
4726 case nir_intrinsic_ssbo_atomic_imin
:
4727 case nir_intrinsic_ssbo_atomic_umin
:
4728 case nir_intrinsic_ssbo_atomic_imax
:
4729 case nir_intrinsic_ssbo_atomic_umax
:
4730 case nir_intrinsic_ssbo_atomic_and
:
4731 case nir_intrinsic_ssbo_atomic_or
:
4732 case nir_intrinsic_ssbo_atomic_xor
:
4733 case nir_intrinsic_ssbo_atomic_exchange
:
4734 case nir_intrinsic_ssbo_atomic_comp_swap
:
4735 nir_emit_ssbo_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4737 case nir_intrinsic_ssbo_atomic_fmin
:
4738 case nir_intrinsic_ssbo_atomic_fmax
:
4739 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4740 nir_emit_ssbo_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4743 case nir_intrinsic_get_buffer_size
: {
4744 assert(nir_src_num_components(instr
->src
[0]) == 1);
4745 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4746 nir_src_as_uint(instr
->src
[0]) : 0;
4748 /* A resinfo's sampler message is used to get the buffer size. The
4749 * SIMD8's writeback message consists of four registers and SIMD16's
4750 * writeback message consists of 8 destination registers (two per each
4751 * component). Because we are only interested on the first channel of
4752 * the first returned component, where resinfo returns the buffer size
4753 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4754 * the dispatch width.
4756 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4757 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4758 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4761 ubld
.MOV(src_payload
, brw_imm_d(0));
4763 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4764 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4765 src_payload
, brw_imm_ud(index
));
4766 inst
->header_size
= 0;
4768 inst
->size_written
= 4 * REG_SIZE
;
4770 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4772 * "Out-of-bounds checking is always performed at a DWord granularity. If
4773 * any part of the DWord is out-of-bounds then the whole DWord is
4774 * considered out-of-bounds."
4776 * This implies that types with size smaller than 4-bytes need to be
4777 * padded if they don't complete the last dword of the buffer. But as we
4778 * need to maintain the original size we need to reverse the padding
4779 * calculation to return the correct size to know the number of elements
4780 * of an unsized array. As we stored in the last two bits of the surface
4781 * size the needed padding for the buffer, we calculate here the
4782 * original buffer_size reversing the surface_size calculation:
4784 * surface_size = isl_align(buffer_size, 4) +
4785 * (isl_align(buffer_size) - buffer_size)
4787 * buffer_size = surface_size & ~3 - surface_size & 3
4790 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4791 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4792 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4794 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4795 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4796 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4798 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4802 case nir_intrinsic_load_scratch
: {
4803 assert(devinfo
->gen
>= 7);
4805 assert(nir_dest_num_components(instr
->dest
) == 1);
4806 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4807 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4809 if (devinfo
->gen
>= 8) {
4810 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4811 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4813 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4816 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4817 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4818 const fs_reg nir_addr
= get_nir_src(instr
->src
[0]);
4820 /* Make dest unsigned because that's what the temporary will be */
4821 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4823 /* Read the vector */
4824 assert(nir_dest_num_components(instr
->dest
) == 1);
4825 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4826 assert(nir_intrinsic_align(instr
) > 0);
4827 if (nir_dest_bit_size(instr
->dest
) >= 4 &&
4828 nir_intrinsic_align(instr
) >= 4) {
4829 /* The offset for a DWORD scattered message is in dwords. */
4830 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4831 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4833 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
,
4834 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4836 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4837 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4839 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4840 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4841 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4842 bld
.MOV(dest
, read_result
);
4847 case nir_intrinsic_store_scratch
: {
4848 assert(devinfo
->gen
>= 7);
4850 assert(nir_src_num_components(instr
->src
[0]) == 1);
4851 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4852 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4854 if (devinfo
->gen
>= 8) {
4855 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4856 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4858 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4861 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4862 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4863 const fs_reg nir_addr
= get_nir_src(instr
->src
[1]);
4865 fs_reg data
= get_nir_src(instr
->src
[0]);
4866 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4868 assert(nir_src_num_components(instr
->src
[0]) == 1);
4869 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4870 assert(nir_intrinsic_write_mask(instr
) == 1);
4871 assert(nir_intrinsic_align(instr
) > 0);
4872 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4873 nir_intrinsic_align(instr
) >= 4) {
4874 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4876 /* The offset for a DWORD scattered message is in dwords. */
4877 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4878 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4880 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
,
4881 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4883 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4884 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4886 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4887 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4889 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4890 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4895 case nir_intrinsic_load_subgroup_size
:
4896 /* This should only happen for fragment shaders because every other case
4897 * is lowered in NIR so we can optimize on it.
4899 assert(stage
== MESA_SHADER_FRAGMENT
);
4900 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4903 case nir_intrinsic_load_subgroup_invocation
:
4904 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4905 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4908 case nir_intrinsic_load_subgroup_eq_mask
:
4909 case nir_intrinsic_load_subgroup_ge_mask
:
4910 case nir_intrinsic_load_subgroup_gt_mask
:
4911 case nir_intrinsic_load_subgroup_le_mask
:
4912 case nir_intrinsic_load_subgroup_lt_mask
:
4913 unreachable("not reached");
4915 case nir_intrinsic_vote_any
: {
4916 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4918 /* The any/all predicates do not consider channel enables. To prevent
4919 * dead channels from affecting the result, we initialize the flag with
4920 * with the identity value for the logical operation.
4922 if (dispatch_width
== 32) {
4923 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4924 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4927 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4929 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4931 /* For some reason, the any/all predicates don't work properly with
4932 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4933 * doesn't read the correct subset of the flag register and you end up
4934 * getting garbage in the second half. Work around this by using a pair
4935 * of 1-wide MOVs and scattering the result.
4937 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4938 ubld
.MOV(res1
, brw_imm_d(0));
4939 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4940 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4941 BRW_PREDICATE_ALIGN1_ANY32H
,
4942 ubld
.MOV(res1
, brw_imm_d(-1)));
4944 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4947 case nir_intrinsic_vote_all
: {
4948 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4950 /* The any/all predicates do not consider channel enables. To prevent
4951 * dead channels from affecting the result, we initialize the flag with
4952 * with the identity value for the logical operation.
4954 if (dispatch_width
== 32) {
4955 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4956 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4957 brw_imm_ud(0xffffffff));
4959 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4961 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4963 /* For some reason, the any/all predicates don't work properly with
4964 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4965 * doesn't read the correct subset of the flag register and you end up
4966 * getting garbage in the second half. Work around this by using a pair
4967 * of 1-wide MOVs and scattering the result.
4969 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4970 ubld
.MOV(res1
, brw_imm_d(0));
4971 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4972 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4973 BRW_PREDICATE_ALIGN1_ALL32H
,
4974 ubld
.MOV(res1
, brw_imm_d(-1)));
4976 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4979 case nir_intrinsic_vote_feq
:
4980 case nir_intrinsic_vote_ieq
: {
4981 fs_reg value
= get_nir_src(instr
->src
[0]);
4982 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4983 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4984 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4985 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4988 fs_reg uniformized
= bld
.emit_uniformize(value
);
4989 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4991 /* The any/all predicates do not consider channel enables. To prevent
4992 * dead channels from affecting the result, we initialize the flag with
4993 * with the identity value for the logical operation.
4995 if (dispatch_width
== 32) {
4996 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4997 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4998 brw_imm_ud(0xffffffff));
5000 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
5002 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
5004 /* For some reason, the any/all predicates don't work properly with
5005 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
5006 * doesn't read the correct subset of the flag register and you end up
5007 * getting garbage in the second half. Work around this by using a pair
5008 * of 1-wide MOVs and scattering the result.
5010 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
5011 ubld
.MOV(res1
, brw_imm_d(0));
5012 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
5013 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
5014 BRW_PREDICATE_ALIGN1_ALL32H
,
5015 ubld
.MOV(res1
, brw_imm_d(-1)));
5017 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
5021 case nir_intrinsic_ballot
: {
5022 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
5023 BRW_REGISTER_TYPE_UD
);
5024 struct brw_reg flag
= brw_flag_reg(0, 0);
5025 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
5026 * as f0.0. This is a problem for fragment programs as we currently use
5027 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
5028 * programs yet so this isn't a problem. When we do, something will
5031 if (dispatch_width
== 32)
5032 flag
.type
= BRW_REGISTER_TYPE_UD
;
5034 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
5035 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
5037 if (instr
->dest
.ssa
.bit_size
> 32) {
5038 dest
.type
= BRW_REGISTER_TYPE_UQ
;
5040 dest
.type
= BRW_REGISTER_TYPE_UD
;
5042 bld
.MOV(dest
, flag
);
5046 case nir_intrinsic_read_invocation
: {
5047 const fs_reg value
= get_nir_src(instr
->src
[0]);
5048 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
5049 fs_reg tmp
= bld
.vgrf(value
.type
);
5051 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
5052 bld
.emit_uniformize(invocation
));
5054 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
5058 case nir_intrinsic_read_first_invocation
: {
5059 const fs_reg value
= get_nir_src(instr
->src
[0]);
5060 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
5064 case nir_intrinsic_shuffle
: {
5065 const fs_reg value
= get_nir_src(instr
->src
[0]);
5066 const fs_reg index
= get_nir_src(instr
->src
[1]);
5068 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
5072 case nir_intrinsic_first_invocation
: {
5073 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5074 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
5075 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
5076 fs_reg(component(tmp
, 0)));
5080 case nir_intrinsic_quad_broadcast
: {
5081 const fs_reg value
= get_nir_src(instr
->src
[0]);
5082 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
5084 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
5085 value
, brw_imm_ud(index
), brw_imm_ud(4));
5089 case nir_intrinsic_quad_swap_horizontal
: {
5090 const fs_reg value
= get_nir_src(instr
->src
[0]);
5091 const fs_reg tmp
= bld
.vgrf(value
.type
);
5092 if (devinfo
->gen
<= 7) {
5093 /* The hardware doesn't seem to support these crazy regions with
5094 * compressed instructions on gen7 and earlier so we fall back to
5095 * using quad swizzles. Fortunately, we don't support 64-bit
5096 * anything in Vulkan on gen7.
5098 assert(nir_src_bit_size(instr
->src
[0]) == 32);
5099 const fs_builder ubld
= bld
.exec_all();
5100 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5101 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
5102 bld
.MOV(retype(dest
, value
.type
), tmp
);
5104 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
5106 const fs_reg src_left
= horiz_stride(value
, 2);
5107 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
5108 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
5109 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
5111 ubld
.MOV(tmp_left
, src_right
);
5112 ubld
.MOV(tmp_right
, src_left
);
5115 bld
.MOV(retype(dest
, value
.type
), tmp
);
5119 case nir_intrinsic_quad_swap_vertical
: {
5120 const fs_reg value
= get_nir_src(instr
->src
[0]);
5121 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5122 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5123 const fs_reg tmp
= bld
.vgrf(value
.type
);
5124 const fs_builder ubld
= bld
.exec_all();
5125 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5126 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
5127 bld
.MOV(retype(dest
, value
.type
), tmp
);
5129 /* For larger data types, we have to either emit dispatch_width many
5130 * MOVs or else fall back to doing indirects.
5132 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5133 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5135 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5140 case nir_intrinsic_quad_swap_diagonal
: {
5141 const fs_reg value
= get_nir_src(instr
->src
[0]);
5142 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5143 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5144 const fs_reg tmp
= bld
.vgrf(value
.type
);
5145 const fs_builder ubld
= bld
.exec_all();
5146 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5147 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
5148 bld
.MOV(retype(dest
, value
.type
), tmp
);
5150 /* For larger data types, we have to either emit dispatch_width many
5151 * MOVs or else fall back to doing indirects.
5153 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5154 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5156 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5161 case nir_intrinsic_reduce
: {
5162 fs_reg src
= get_nir_src(instr
->src
[0]);
5163 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5164 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
5165 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
5166 cluster_size
= dispatch_width
;
5168 /* Figure out the source type */
5169 src
.type
= brw_type_for_nir_type(devinfo
,
5170 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5171 nir_src_bit_size(instr
->src
[0])));
5173 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5174 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5175 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5177 /* There are a couple of register region issues that make things
5178 * complicated for 8-bit types:
5180 * 1. Only raw moves are allowed to write to a packed 8-bit
5182 * 2. If we use a strided destination, the efficient way to do scan
5183 * operations ends up using strides that are too big to encode in
5186 * To get around these issues, we just do all 8-bit scan operations in
5187 * 16 bits. It's actually fewer instructions than what we'd have to do
5188 * if we were trying to do it in native 8-bit types and the results are
5189 * the same once we truncate to 8 bits at the end.
5191 brw_reg_type scan_type
= src
.type
;
5192 if (type_sz(scan_type
) == 1)
5193 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5195 /* Set up a register for all of our scratching around and initialize it
5196 * to reduction operation's identity value.
5198 fs_reg scan
= bld
.vgrf(scan_type
);
5199 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5201 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
5203 dest
.type
= src
.type
;
5204 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
5205 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
5206 * the distance between clusters is at least 2 GRFs. In this case,
5207 * we don't need the weird striding of the CLUSTER_BROADCAST
5208 * instruction and can just do regular MOVs.
5210 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
5211 const unsigned groups
=
5212 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
5213 const unsigned group_size
= dispatch_width
/ groups
;
5214 for (unsigned i
= 0; i
< groups
; i
++) {
5215 const unsigned cluster
= (i
* group_size
) / cluster_size
;
5216 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
5217 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
5218 component(scan
, comp
));
5221 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
5222 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
5227 case nir_intrinsic_inclusive_scan
:
5228 case nir_intrinsic_exclusive_scan
: {
5229 fs_reg src
= get_nir_src(instr
->src
[0]);
5230 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5232 /* Figure out the source type */
5233 src
.type
= brw_type_for_nir_type(devinfo
,
5234 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5235 nir_src_bit_size(instr
->src
[0])));
5237 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5238 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5239 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5241 /* There are a couple of register region issues that make things
5242 * complicated for 8-bit types:
5244 * 1. Only raw moves are allowed to write to a packed 8-bit
5246 * 2. If we use a strided destination, the efficient way to do scan
5247 * operations ends up using strides that are too big to encode in
5250 * To get around these issues, we just do all 8-bit scan operations in
5251 * 16 bits. It's actually fewer instructions than what we'd have to do
5252 * if we were trying to do it in native 8-bit types and the results are
5253 * the same once we truncate to 8 bits at the end.
5255 brw_reg_type scan_type
= src
.type
;
5256 if (type_sz(scan_type
) == 1)
5257 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5259 /* Set up a register for all of our scratching around and initialize it
5260 * to reduction operation's identity value.
5262 fs_reg scan
= bld
.vgrf(scan_type
);
5263 const fs_builder allbld
= bld
.exec_all();
5264 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5266 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5267 /* Exclusive scan is a bit harder because we have to do an annoying
5268 * shift of the contents before we can begin. To make things worse,
5269 * we can't do this with a normal stride; we have to use indirects.
5271 fs_reg shifted
= bld
.vgrf(scan_type
);
5272 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5273 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5275 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5276 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5280 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5282 bld
.MOV(retype(dest
, src
.type
), scan
);
5287 unreachable("unknown intrinsic");
5292 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5293 int op
, nir_intrinsic_instr
*instr
)
5295 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5296 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5297 * appear to exist. However, if you look at Vol 2a, there are no message
5298 * descriptors provided for Qword atomic ops except for A64 messages.
5300 assert(nir_dest_bit_size(instr
->dest
) == 32);
5303 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5304 dest
= get_nir_dest(instr
->dest
);
5306 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5307 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5308 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5309 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5310 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5313 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5314 data
= get_nir_src(instr
->src
[2]);
5316 if (op
== BRW_AOP_CMPWR
) {
5317 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5318 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5319 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5322 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5324 /* Emit the actual atomic operation */
5326 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5327 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5331 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5332 int op
, nir_intrinsic_instr
*instr
)
5335 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5336 dest
= get_nir_dest(instr
->dest
);
5338 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5339 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5340 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5341 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5342 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5344 fs_reg data
= get_nir_src(instr
->src
[2]);
5345 if (op
== BRW_AOP_FCMPWR
) {
5346 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5347 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5348 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5351 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5353 /* Emit the actual atomic operation */
5355 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5356 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5360 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5361 int op
, nir_intrinsic_instr
*instr
)
5364 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5365 dest
= get_nir_dest(instr
->dest
);
5367 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5368 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5369 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5370 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5373 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5374 data
= get_nir_src(instr
->src
[1]);
5375 if (op
== BRW_AOP_CMPWR
) {
5376 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5377 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5378 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5381 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5383 /* Get the offset */
5384 if (nir_src_is_const(instr
->src
[0])) {
5385 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5386 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5388 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5389 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5390 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5391 brw_imm_ud(instr
->const_index
[0]));
5394 /* Emit the actual atomic operation operation */
5396 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5397 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5401 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5402 int op
, nir_intrinsic_instr
*instr
)
5405 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5406 dest
= get_nir_dest(instr
->dest
);
5408 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5409 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5410 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5411 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5413 fs_reg data
= get_nir_src(instr
->src
[1]);
5414 if (op
== BRW_AOP_FCMPWR
) {
5415 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5416 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5417 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5420 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5422 /* Get the offset */
5423 if (nir_src_is_const(instr
->src
[0])) {
5424 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5425 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5427 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5428 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5429 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5430 brw_imm_ud(instr
->const_index
[0]));
5433 /* Emit the actual atomic operation operation */
5435 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5436 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5440 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5441 int op
, nir_intrinsic_instr
*instr
)
5444 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5445 dest
= get_nir_dest(instr
->dest
);
5447 fs_reg addr
= get_nir_src(instr
->src
[0]);
5450 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5451 data
= get_nir_src(instr
->src
[1]);
5453 if (op
== BRW_AOP_CMPWR
) {
5454 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5455 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5456 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5460 if (nir_dest_bit_size(instr
->dest
) == 64) {
5461 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5462 dest
, addr
, data
, brw_imm_ud(op
));
5464 assert(nir_dest_bit_size(instr
->dest
) == 32);
5465 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5466 dest
, addr
, data
, brw_imm_ud(op
));
5471 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5472 int op
, nir_intrinsic_instr
*instr
)
5474 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5475 fs_reg dest
= get_nir_dest(instr
->dest
);
5477 fs_reg addr
= get_nir_src(instr
->src
[0]);
5479 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5480 fs_reg data
= get_nir_src(instr
->src
[1]);
5482 if (op
== BRW_AOP_FCMPWR
) {
5483 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5484 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5485 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5489 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5490 dest
, addr
, data
, brw_imm_ud(op
));
5494 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5496 unsigned texture
= instr
->texture_index
;
5497 unsigned sampler
= instr
->sampler_index
;
5499 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5501 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5502 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5504 int lod_components
= 0;
5506 /* The hardware requires a LOD for buffer textures */
5507 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5508 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5510 uint32_t header_bits
= 0;
5511 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5512 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5513 switch (instr
->src
[i
].src_type
) {
5514 case nir_tex_src_bias
:
5515 srcs
[TEX_LOGICAL_SRC_LOD
] =
5516 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5518 case nir_tex_src_comparator
:
5519 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5521 case nir_tex_src_coord
:
5522 switch (instr
->op
) {
5524 case nir_texop_txf_ms
:
5525 case nir_texop_txf_ms_mcs
:
5526 case nir_texop_samples_identical
:
5527 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5530 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5534 case nir_tex_src_ddx
:
5535 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5536 lod_components
= nir_tex_instr_src_size(instr
, i
);
5538 case nir_tex_src_ddy
:
5539 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5541 case nir_tex_src_lod
:
5542 switch (instr
->op
) {
5544 srcs
[TEX_LOGICAL_SRC_LOD
] =
5545 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5548 srcs
[TEX_LOGICAL_SRC_LOD
] =
5549 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5552 srcs
[TEX_LOGICAL_SRC_LOD
] =
5553 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5557 case nir_tex_src_min_lod
:
5558 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5559 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5561 case nir_tex_src_ms_index
:
5562 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5565 case nir_tex_src_offset
: {
5566 uint32_t offset_bits
= 0;
5567 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5568 header_bits
|= offset_bits
;
5570 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5571 retype(src
, BRW_REGISTER_TYPE_D
);
5576 case nir_tex_src_projector
:
5577 unreachable("should be lowered");
5579 case nir_tex_src_texture_offset
: {
5580 /* Emit code to evaluate the actual indexing expression */
5581 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5582 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5583 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5587 case nir_tex_src_sampler_offset
: {
5588 /* Emit code to evaluate the actual indexing expression */
5589 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5590 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5591 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5595 case nir_tex_src_texture_handle
:
5596 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5597 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5598 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5601 case nir_tex_src_sampler_handle
:
5602 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5603 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5604 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5607 case nir_tex_src_ms_mcs
:
5608 assert(instr
->op
== nir_texop_txf_ms
);
5609 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5612 case nir_tex_src_plane
: {
5613 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5614 const uint32_t texture_index
=
5615 instr
->texture_index
+
5616 stage_prog_data
->binding_table
.plane_start
[plane
] -
5617 stage_prog_data
->binding_table
.texture_start
;
5619 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5624 unreachable("unknown texture source");
5628 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5629 (instr
->op
== nir_texop_txf_ms
||
5630 instr
->op
== nir_texop_samples_identical
)) {
5631 if (devinfo
->gen
>= 7 &&
5632 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5633 srcs
[TEX_LOGICAL_SRC_MCS
] =
5634 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5635 instr
->coord_components
,
5636 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5637 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5639 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5643 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5644 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5647 switch (instr
->op
) {
5649 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5652 opcode
= FS_OPCODE_TXB_LOGICAL
;
5655 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5658 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5661 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5663 case nir_texop_txf_ms
:
5664 if ((key_tex
->msaa_16
& (1 << sampler
)))
5665 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5667 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5669 case nir_texop_txf_ms_mcs
:
5670 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5672 case nir_texop_query_levels
:
5674 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5677 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5680 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5681 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5683 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5685 case nir_texop_texture_samples
:
5686 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5688 case nir_texop_samples_identical
: {
5689 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5691 /* If mcs is an immediate value, it means there is no MCS. In that case
5692 * just return false.
5694 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5695 bld
.MOV(dst
, brw_imm_ud(0u));
5696 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5697 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5698 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5699 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5700 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5702 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5703 BRW_CONDITIONAL_EQ
);
5708 unreachable("unknown texture opcode");
5711 if (instr
->op
== nir_texop_tg4
) {
5712 if (instr
->component
== 1 &&
5713 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5714 /* gather4 sampler is broken for green channel on RG32F --
5715 * we must ask for blue instead.
5717 header_bits
|= 2 << 16;
5719 header_bits
|= instr
->component
<< 16;
5723 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5724 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5725 inst
->offset
= header_bits
;
5727 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5728 if (devinfo
->gen
>= 9 &&
5729 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5730 unsigned write_mask
= instr
->dest
.is_ssa
?
5731 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5732 (1 << dest_size
) - 1;
5733 assert(write_mask
!= 0); /* dead code should have been eliminated */
5734 inst
->size_written
= util_last_bit(write_mask
) *
5735 inst
->dst
.component_size(inst
->exec_size
);
5737 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5740 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5741 inst
->shadow_compare
= true;
5743 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5744 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5747 for (unsigned i
= 0; i
< dest_size
; i
++)
5748 nir_dest
[i
] = offset(dst
, bld
, i
);
5750 if (instr
->op
== nir_texop_query_levels
) {
5751 /* # levels is in .w */
5752 nir_dest
[0] = offset(dst
, bld
, 3);
5753 } else if (instr
->op
== nir_texop_txs
&&
5754 dest_size
>= 3 && devinfo
->gen
< 7) {
5755 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5756 fs_reg depth
= offset(dst
, bld
, 2);
5757 nir_dest
[2] = vgrf(glsl_type::int_type
);
5758 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5761 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5765 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5767 switch (instr
->type
) {
5768 case nir_jump_break
:
5769 bld
.emit(BRW_OPCODE_BREAK
);
5771 case nir_jump_continue
:
5772 bld
.emit(BRW_OPCODE_CONTINUE
);
5774 case nir_jump_return
:
5776 unreachable("unknown jump");
5781 * This helper takes a source register and un/shuffles it into the destination
5784 * If source type size is smaller than destination type size the operation
5785 * needed is a component shuffle. The opposite case would be an unshuffle. If
5786 * source/destination type size is equal a shuffle is done that would be
5787 * equivalent to a simple MOV.
5789 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5790 * components .xyz 16-bit vector on SIMD8 would be.
5792 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5793 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5795 * This helper will return the following 2 32-bit components with the 16-bit
5798 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5799 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5801 * For unshuffle, the example would be the opposite, a 64-bit type source
5802 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5805 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5806 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5807 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5808 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5810 * The returned result would be the following 4 32-bit components unshuffled:
5812 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5813 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5814 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5815 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5817 * - Source and destination register must not be overlapped.
5818 * - components units are measured in terms of the smaller type between
5819 * source and destination because we are un/shuffling the smaller
5820 * components from/into the bigger ones.
5821 * - first_component parameter allows skipping source components.
5824 shuffle_src_to_dst(const fs_builder
&bld
,
5827 uint32_t first_component
,
5828 uint32_t components
)
5830 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5831 assert(!regions_overlap(dst
,
5832 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5833 offset(src
, bld
, first_component
),
5834 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5835 for (unsigned i
= 0; i
< components
; i
++) {
5836 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5837 offset(src
, bld
, i
+ first_component
));
5839 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5840 /* Source is shuffled into destination */
5841 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5842 assert(!regions_overlap(dst
,
5843 type_sz(dst
.type
) * bld
.dispatch_width() *
5844 DIV_ROUND_UP(components
, size_ratio
),
5845 offset(src
, bld
, first_component
),
5846 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5848 brw_reg_type shuffle_type
=
5849 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5850 BRW_REGISTER_TYPE_D
);
5851 for (unsigned i
= 0; i
< components
; i
++) {
5852 fs_reg shuffle_component_i
=
5853 subscript(offset(dst
, bld
, i
/ size_ratio
),
5854 shuffle_type
, i
% size_ratio
);
5855 bld
.MOV(shuffle_component_i
,
5856 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5859 /* Source is unshuffled into destination */
5860 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5861 assert(!regions_overlap(dst
,
5862 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5863 offset(src
, bld
, first_component
/ size_ratio
),
5864 type_sz(src
.type
) * bld
.dispatch_width() *
5865 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5868 brw_reg_type shuffle_type
=
5869 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5870 BRW_REGISTER_TYPE_D
);
5871 for (unsigned i
= 0; i
< components
; i
++) {
5872 fs_reg shuffle_component_i
=
5873 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5874 shuffle_type
, (first_component
+ i
) % size_ratio
);
5875 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5876 shuffle_component_i
);
5882 shuffle_from_32bit_read(const fs_builder
&bld
,
5885 uint32_t first_component
,
5886 uint32_t components
)
5888 assert(type_sz(src
.type
) == 4);
5890 /* This function takes components in units of the destination type while
5891 * shuffle_src_to_dst takes components in units of the smallest type
5893 if (type_sz(dst
.type
) > 4) {
5894 assert(type_sz(dst
.type
) == 8);
5895 first_component
*= 2;
5899 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5903 setup_imm_df(const fs_builder
&bld
, double v
)
5905 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5906 assert(devinfo
->gen
>= 7);
5908 if (devinfo
->gen
>= 8)
5909 return brw_imm_df(v
);
5911 /* gen7.5 does not support DF immediates straighforward but the DIM
5912 * instruction allows to set the 64-bit immediate value.
5914 if (devinfo
->is_haswell
) {
5915 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5916 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5917 ubld
.DIM(dst
, brw_imm_df(v
));
5918 return component(dst
, 0);
5921 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5922 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5923 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5925 * Alternatively, we could also produce a normal VGRF (without stride 0)
5926 * by writing to all the channels in the VGRF, however, that would hit the
5927 * gen7 bug where we have to split writes that span more than 1 register
5928 * into instructions with a width of 4 (otherwise the write to the second
5929 * register written runs into an execmask hardware bug) which isn't very
5942 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5943 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5944 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5945 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5947 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5951 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5953 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5954 bld
.MOV(tmp
, brw_imm_w(v
));
5959 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5961 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5962 bld
.MOV(tmp
, brw_imm_uw(v
));