src/intel/compiler/brw_fs_register_coalesce.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /** @file brw_fs_register_coalesce.cpp
  25  *
  26  * Implements register coalescing: Checks if the two registers involved in a
  27  * raw move don't interfere, in which case they can both be stored in the same
  28  * place and the MOV removed.
  29  *
  30  * To do this, all uses of the source of the MOV in the shader are replaced
  31  * with the destination of the MOV. For example:
  32  *
  33  * add vgrf3:F, vgrf1:F, vgrf2:F
  34  * mov vgrf4:F, vgrf3:F
  35  * mul vgrf5:F, vgrf5:F, vgrf4:F
  36  *
  37  * becomes
  38  *
  39  * add vgrf4:F, vgrf1:F, vgrf2:F
  40  * mul vgrf5:F, vgrf5:F, vgrf4:F
  41  */
  42
  43 #include "brw_fs.h"
  44 #include "brw_cfg.h"
  45 #include "brw_fs_live_variables.h"
  46
  47 static bool
  48 is_nop_mov(const fs_inst *inst)
  49 {
  50    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
  51       fs_reg dst = inst->dst;
  52       for (int i = 0; i < inst->sources; i++) {
  53          if (!dst.equals(inst->src[i])) {
  54             return false;
  55          }
  56          dst.offset += (i < inst->header_size ? REG_SIZE :
  57                         inst->exec_size * dst.stride *
  58                         type_sz(inst->src[i].type));
  59       }
  60       return true;
  61    } else if (inst->opcode == BRW_OPCODE_MOV) {
  62       return inst->dst.equals(inst->src[0]);
  63    }
  64
  65    return false;
  66 }
  67
  68 static bool
  69 is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst)
  70 {
  71    if ((inst->opcode != BRW_OPCODE_MOV &&
  72         inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) ||
  73        inst->is_partial_write() ||
  74        inst->saturate ||
  75        inst->src[0].file != VGRF ||
  76        inst->src[0].negate ||
  77        inst->src[0].abs ||
  78        !inst->src[0].is_contiguous() ||
  79        inst->dst.file != VGRF ||
  80        inst->dst.type != inst->src[0].type) {
  81       return false;
  82    }
  83
  84    if (v->alloc.sizes[inst->src[0].nr] >
  85        v->alloc.sizes[inst->dst.nr])
  86       return false;
  87
  88    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
  89       if (!inst->is_copy_payload(v->alloc)) {
  90          return false;
  91       }
  92    }
  93
  94    return true;
  95 }
  96
  97 static bool
  98 can_coalesce_vars(brw::fs_live_variables *live_intervals,
  99                   const cfg_t *cfg, const fs_inst *inst,
 100                   int dst_var, int src_var)
 101 {
 102    if (!live_intervals->vars_interfere(src_var, dst_var))
 103       return true;
 104
 105    int dst_start = live_intervals->start[dst_var];
 106    int dst_end = live_intervals->end[dst_var];
 107    int src_start = live_intervals->start[src_var];
 108    int src_end = live_intervals->end[src_var];
 109
 110    /* Variables interfere and one line range isn't a subset of the other. */
 111    if ((dst_end > src_end && src_start < dst_start) ||
 112        (src_end > dst_end && dst_start < src_start))
 113       return false;
 114
 115    /* Check for a write to either register in the intersection of their live
 116     * ranges.
 117     */
 118    int start_ip = MAX2(dst_start, src_start);
 119    int end_ip = MIN2(dst_end, src_end);
 120
 121    foreach_block(block, cfg) {
 122       if (block->end_ip < start_ip)
 123          continue;
 124
 125       int scan_ip = block->start_ip - 1;
 126
 127       foreach_inst_in_block(fs_inst, scan_inst, block) {
 128          scan_ip++;
 129
 130          /* Ignore anything before the intersection of the live ranges */
 131          if (scan_ip < start_ip)
 132             continue;
 133
 134          /* Ignore the copying instruction itself */
 135          if (scan_inst == inst)
 136             continue;
 137
 138          if (scan_ip > end_ip)
 139             return true; /* registers do not interfere */
 140
 141          if (regions_overlap(scan_inst->dst, scan_inst->size_written,
 142                              inst->dst, inst->size_written) ||
 143              regions_overlap(scan_inst->dst, scan_inst->size_written,
 144                              inst->src[0], inst->size_read(0)))
 145             return false; /* registers interfere */
 146       }
 147    }
 148
 149    return true;
 150 }
 151
 152 bool
 153 fs_visitor::register_coalesce()
 154 {
 155    bool progress = false;
 156
 157    calculate_live_intervals();
 158
 159    int src_size = 0;
 160    int channels_remaining = 0;
 161    unsigned src_reg = ~0u, dst_reg = ~0u;
 162    int dst_reg_offset[MAX_VGRF_SIZE];
 163    fs_inst *mov[MAX_VGRF_SIZE];
 164    int dst_var[MAX_VGRF_SIZE];
 165    int src_var[MAX_VGRF_SIZE];
 166
 167    foreach_block_and_inst(block, fs_inst, inst, cfg) {
 168       if (!is_coalesce_candidate(this, inst))
 169          continue;
 170
 171       if (is_nop_mov(inst)) {
 172          inst->opcode = BRW_OPCODE_NOP;
 173          progress = true;
 174          continue;
 175       }
 176
 177       if (src_reg != inst->src[0].nr) {
 178          src_reg = inst->src[0].nr;
 179
 180          src_size = alloc.sizes[inst->src[0].nr];
 181          assert(src_size <= MAX_VGRF_SIZE);
 182
 183          channels_remaining = src_size;
 184          memset(mov, 0, sizeof(mov));
 185
 186          dst_reg = inst->dst.nr;
 187       }
 188
 189       if (dst_reg != inst->dst.nr)
 190          continue;
 191
 192       if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
 193          for (int i = 0; i < src_size; i++) {
 194             dst_reg_offset[i] = i;
 195          }
 196          mov[0] = inst;
 197          channels_remaining -= regs_written(inst);
 198       } else {
 199          const int offset = inst->src[0].offset / REG_SIZE;
 200          if (mov[offset]) {
 201             /* This is the second time that this offset in the register has
 202              * been set.  This means, in particular, that inst->dst was
 203              * live before this instruction and that the live ranges of
 204              * inst->dst and inst->src[0] overlap and we can't coalesce the
 205              * two variables.  Let's ensure that doesn't happen.
 206              */
 207             channels_remaining = -1;
 208             continue;
 209          }
 210          for (unsigned i = 0; i < MAX2(inst->size_written / REG_SIZE, 1); i++)
 211             dst_reg_offset[offset + i] = inst->dst.offset / REG_SIZE + i;
 212          mov[offset] = inst;
 213          channels_remaining -= regs_written(inst);
 214       }
 215
 216       if (channels_remaining)
 217          continue;
 218
 219       bool can_coalesce = true;
 220       for (int i = 0; i < src_size; i++) {
 221          if (dst_reg_offset[i] != dst_reg_offset[0] + i) {
 222             /* Registers are out-of-order. */
 223             can_coalesce = false;
 224             src_reg = ~0u;
 225             break;
 226          }
 227
 228          dst_var[i] = live_intervals->var_from_vgrf[dst_reg] + dst_reg_offset[i];
 229          src_var[i] = live_intervals->var_from_vgrf[src_reg] + i;
 230
 231          if (!can_coalesce_vars(live_intervals, cfg, inst,
 232                                 dst_var[i], src_var[i])) {
 233             can_coalesce = false;
 234             src_reg = ~0u;
 235             break;
 236          }
 237       }
 238
 239       if (!can_coalesce)
 240          continue;
 241
 242       progress = true;
 243
 244       for (int i = 0; i < src_size; i++) {
 245          if (mov[i]) {
 246             mov[i]->opcode = BRW_OPCODE_NOP;
 247             mov[i]->conditional_mod = BRW_CONDITIONAL_NONE;
 248             mov[i]->dst = reg_undef;
 249             for (int j = 0; j < mov[i]->sources; j++) {
 250                mov[i]->src[j] = reg_undef;
 251             }
 252          }
 253       }
 254
 255       foreach_block_and_inst(block, fs_inst, scan_inst, cfg) {
 256          if (scan_inst->dst.file == VGRF &&
 257              scan_inst->dst.nr == src_reg) {
 258             scan_inst->dst.nr = dst_reg;
 259             scan_inst->dst.offset = scan_inst->dst.offset % REG_SIZE +
 260                dst_reg_offset[scan_inst->dst.offset / REG_SIZE] * REG_SIZE;
 261          }
 262
 263          for (int j = 0; j < scan_inst->sources; j++) {
 264             if (scan_inst->src[j].file == VGRF &&
 265                 scan_inst->src[j].nr == src_reg) {
 266                scan_inst->src[j].nr = dst_reg;
 267                scan_inst->src[j].offset = scan_inst->src[j].offset % REG_SIZE +
 268                   dst_reg_offset[scan_inst->src[j].offset / REG_SIZE] * REG_SIZE;
 269             }
 270          }
 271       }
 272
 273       for (int i = 0; i < src_size; i++) {
 274          live_intervals->start[dst_var[i]] =
 275             MIN2(live_intervals->start[dst_var[i]],
 276                  live_intervals->start[src_var[i]]);
 277          live_intervals->end[dst_var[i]] =
 278             MAX2(live_intervals->end[dst_var[i]],
 279                  live_intervals->end[src_var[i]]);
 280       }
 281       src_reg = ~0u;
 282    }
 283
 284    if (progress) {
 285       foreach_block_and_inst_safe (block, backend_instruction, inst, cfg) {
 286          if (inst->opcode == BRW_OPCODE_NOP) {
 287             inst->remove(block);
 288          }
 289       }
 290
 291       invalidate_live_intervals();
 292    }
 293
 294    return progress;
 295 }