src/intel/compiler/brw_ir_fs.h

   1 /* -*- c++ -*- */
   2 /*
   3  * Copyright © 2010-2015 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef BRW_IR_FS_H
  26 #define BRW_IR_FS_H
  27
  28 #include "brw_shader.h"
  29
  30 class fs_inst;
  31
  32 class fs_reg : public backend_reg {
  33 public:
  34    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  35
  36    void init();
  37
  38    fs_reg();
  39    fs_reg(struct ::brw_reg reg);
  40    fs_reg(enum brw_reg_file file, int nr);
  41    fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type);
  42
  43    bool equals(const fs_reg &r) const;
  44    bool negative_equals(const fs_reg &r) const;
  45    bool is_contiguous() const;
  46
  47    /**
  48     * Return the size in bytes of a single logical component of the
  49     * register assuming the given execution width.
  50     */
  51    unsigned component_size(unsigned width) const;
  52
  53    /** Register region horizontal stride */
  54    uint8_t stride;
  55 };
  56
  57 static inline fs_reg
  58 negate(fs_reg reg)
  59 {
  60    assert(reg.file != IMM);
  61    reg.negate = !reg.negate;
  62    return reg;
  63 }
  64
  65 static inline fs_reg
  66 retype(fs_reg reg, enum brw_reg_type type)
  67 {
  68    reg.type = type;
  69    return reg;
  70 }
  71
  72 static inline fs_reg
  73 byte_offset(fs_reg reg, unsigned delta)
  74 {
  75    switch (reg.file) {
  76    case BAD_FILE:
  77       break;
  78    case VGRF:
  79    case ATTR:
  80    case UNIFORM:
  81       reg.offset += delta;
  82       break;
  83    case MRF: {
  84       const unsigned suboffset = reg.offset + delta;
  85       reg.nr += suboffset / REG_SIZE;
  86       reg.offset = suboffset % REG_SIZE;
  87       break;
  88    }
  89    case ARF:
  90    case FIXED_GRF: {
  91       const unsigned suboffset = reg.subnr + delta;
  92       reg.nr += suboffset / REG_SIZE;
  93       reg.subnr = suboffset % REG_SIZE;
  94       break;
  95    }
  96    case IMM:
  97    default:
  98       assert(delta == 0);
  99    }
 100    return reg;
 101 }
 102
 103 static inline fs_reg
 104 horiz_offset(const fs_reg &reg, unsigned delta)
 105 {
 106    switch (reg.file) {
 107    case BAD_FILE:
 108    case UNIFORM:
 109    case IMM:
 110       /* These only have a single component that is implicitly splatted.  A
 111        * horizontal offset should be a harmless no-op.
 112        * XXX - Handle vector immediates correctly.
 113        */
 114       return reg;
 115    case VGRF:
 116    case MRF:
 117    case ATTR:
 118       return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
 119    case ARF:
 120    case FIXED_GRF:
 121       if (reg.is_null()) {
 122          return reg;
 123       } else {
 124          const unsigned stride = reg.hstride ? 1 << (reg.hstride - 1) : 0;
 125          return byte_offset(reg, delta * stride * type_sz(reg.type));
 126       }
 127    }
 128    unreachable("Invalid register file");
 129 }
 130
 131 static inline fs_reg
 132 offset(fs_reg reg, unsigned width, unsigned delta)
 133 {
 134    switch (reg.file) {
 135    case BAD_FILE:
 136       break;
 137    case ARF:
 138    case FIXED_GRF:
 139    case MRF:
 140    case VGRF:
 141    case ATTR:
 142    case UNIFORM:
 143       return byte_offset(reg, delta * reg.component_size(width));
 144    case IMM:
 145       assert(delta == 0);
 146    }
 147    return reg;
 148 }
 149
 150 /**
 151  * Get the scalar channel of \p reg given by \p idx and replicate it to all
 152  * channels of the result.
 153  */
 154 static inline fs_reg
 155 component(fs_reg reg, unsigned idx)
 156 {
 157    reg = horiz_offset(reg, idx);
 158    reg.stride = 0;
 159    return reg;
 160 }
 161
 162 /**
 163  * Return an integer identifying the discrete address space a register is
 164  * contained in.  A register is by definition fully contained in the single
 165  * reg_space it belongs to, so two registers with different reg_space ids are
 166  * guaranteed not to overlap.  Most register files are a single reg_space of
 167  * its own, only the VGRF file is composed of multiple discrete address
 168  * spaces, one for each VGRF allocation.
 169  */
 170 static inline uint32_t
 171 reg_space(const fs_reg &r)
 172 {
 173    return r.file << 16 | (r.file == VGRF ? r.nr : 0);
 174 }
 175
 176 /**
 177  * Return the base offset in bytes of a register relative to the start of its
 178  * reg_space().
 179  */
 180 static inline unsigned
 181 reg_offset(const fs_reg &r)
 182 {
 183    return (r.file == VGRF || r.file == IMM ? 0 : r.nr) *
 184           (r.file == UNIFORM ? 4 : REG_SIZE) + r.offset +
 185           (r.file == ARF || r.file == FIXED_GRF ? r.subnr : 0);
 186 }
 187
 188 /**
 189  * Return the amount of padding in bytes left unused between individual
 190  * components of register \p r due to a (horizontal) stride value greater than
 191  * one, or zero if components are tightly packed in the register file.
 192  */
 193 static inline unsigned
 194 reg_padding(const fs_reg &r)
 195 {
 196    const unsigned stride = ((r.file != ARF && r.file != FIXED_GRF) ? r.stride :
 197                             r.hstride == 0 ? 0 :
 198                             1 << (r.hstride - 1));
 199    return (MAX2(1, stride) - 1) * type_sz(r.type);
 200 }
 201
 202 /**
 203  * Return whether the register region starting at \p r and spanning \p dr
 204  * bytes could potentially overlap the register region starting at \p s and
 205  * spanning \p ds bytes.
 206  */
 207 static inline bool
 208 regions_overlap(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds)
 209 {
 210    if (r.file == MRF && (r.nr & BRW_MRF_COMPR4)) {
 211       fs_reg t = r;
 212       t.nr &= ~BRW_MRF_COMPR4;
 213       /* COMPR4 regions are translated by the hardware during decompression
 214        * into two separate half-regions 4 MRFs apart from each other.
 215        */
 216       return regions_overlap(t, dr / 2, s, ds) ||
 217              regions_overlap(byte_offset(t, 4 * REG_SIZE), dr / 2, s, ds);
 218
 219    } else if (s.file == MRF && (s.nr & BRW_MRF_COMPR4)) {
 220       return regions_overlap(s, ds, r, dr);
 221
 222    } else {
 223       return reg_space(r) == reg_space(s) &&
 224              !(reg_offset(r) + dr <= reg_offset(s) ||
 225                reg_offset(s) + ds <= reg_offset(r));
 226    }
 227 }
 228
 229 /**
 230  * Check that the register region given by r [r.offset, r.offset + dr[
 231  * is fully contained inside the register region given by s
 232  * [s.offset, s.offset + ds[.
 233  */
 234 static inline bool
 235 region_contained_in(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds)
 236 {
 237    return reg_space(r) == reg_space(s) &&
 238           reg_offset(r) >= reg_offset(s) &&
 239           reg_offset(r) + dr <= reg_offset(s) + ds;
 240 }
 241
 242 /**
 243  * Return whether the given register region is n-periodic, i.e. whether the
 244  * original region remains invariant after shifting it by \p n scalar
 245  * channels.
 246  */
 247 static inline bool
 248 is_periodic(const fs_reg &reg, unsigned n)
 249 {
 250    if (reg.file == BAD_FILE || reg.is_null()) {
 251       return true;
 252
 253    } else if (reg.file == IMM) {
 254       const unsigned period = (reg.type == BRW_REGISTER_TYPE_UV ||
 255                                reg.type == BRW_REGISTER_TYPE_V ? 8 :
 256                                reg.type == BRW_REGISTER_TYPE_VF ? 4 :
 257                                1);
 258       return n % period == 0;
 259
 260    } else if (reg.file == ARF || reg.file == FIXED_GRF) {
 261       const unsigned period = (reg.hstride == 0 && reg.vstride == 0 ? 1 :
 262                                reg.vstride == 0 ? 1 << reg.width :
 263                                ~0);
 264       return n % period == 0;
 265
 266    } else {
 267       return reg.stride == 0;
 268    }
 269 }
 270
 271 static inline bool
 272 is_uniform(const fs_reg &reg)
 273 {
 274    return is_periodic(reg, 1);
 275 }
 276
 277 /**
 278  * Get the specified 8-component quarter of a register.
 279  * XXX - Maybe come up with a less misleading name for this (e.g. quarter())?
 280  */
 281 static inline fs_reg
 282 half(const fs_reg &reg, unsigned idx)
 283 {
 284    assert(idx < 2);
 285    return horiz_offset(reg, 8 * idx);
 286 }
 287
 288 /**
 289  * Reinterpret each channel of register \p reg as a vector of values of the
 290  * given smaller type and take the i-th subcomponent from each.
 291  */
 292 static inline fs_reg
 293 subscript(fs_reg reg, brw_reg_type type, unsigned i)
 294 {
 295    assert((i + 1) * type_sz(type) <= type_sz(reg.type));
 296
 297    if (reg.file == ARF || reg.file == FIXED_GRF) {
 298       /* The stride is encoded inconsistently for fixed GRF and ARF registers
 299        * as the log2 of the actual vertical and horizontal strides.
 300        */
 301       const int delta = _mesa_logbase2(type_sz(reg.type)) -
 302                         _mesa_logbase2(type_sz(type));
 303       reg.hstride += (reg.hstride ? delta : 0);
 304       reg.vstride += (reg.vstride ? delta : 0);
 305
 306    } else if (reg.file == IMM) {
 307       assert(reg.type == type);
 308
 309    } else {
 310       reg.stride *= type_sz(reg.type) / type_sz(type);
 311    }
 312
 313    return byte_offset(retype(reg, type), i * type_sz(type));
 314 }
 315
 316 static inline fs_reg
 317 horiz_stride(fs_reg reg, unsigned s)
 318 {
 319    reg.stride *= s;
 320    return reg;
 321 }
 322
 323 static const fs_reg reg_undef;
 324
 325 class fs_inst : public backend_instruction {
 326    fs_inst &operator=(const fs_inst &);
 327
 328    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 329              const fs_reg *src, unsigned sources);
 330
 331 public:
 332    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 333
 334    fs_inst();
 335    fs_inst(enum opcode opcode, uint8_t exec_size);
 336    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst);
 337    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 338            const fs_reg &src0);
 339    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 340            const fs_reg &src0, const fs_reg &src1);
 341    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 342            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 343    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 344            const fs_reg src[], unsigned sources);
 345    fs_inst(const fs_inst &that);
 346    ~fs_inst();
 347
 348    void resize_sources(uint8_t num_sources);
 349
 350    bool is_send_from_grf() const;
 351    bool is_payload(unsigned arg) const;
 352    bool is_partial_write() const;
 353    bool is_copy_payload(const brw::simple_allocator &grf_alloc) const;
 354    unsigned components_read(unsigned i) const;
 355    unsigned size_read(int arg) const;
 356    bool can_do_source_mods(const struct gen_device_info *devinfo) const;
 357    bool can_do_cmod();
 358    bool can_change_types() const;
 359    bool has_source_and_destination_hazard() const;
 360
 361    /**
 362     * Return whether \p arg is a control source of a virtual instruction which
 363     * shouldn't contribute to the execution type and usual regioning
 364     * restriction calculations of arithmetic instructions.
 365     */
 366    bool is_control_source(unsigned arg) const;
 367
 368    /**
 369     * Return the subset of flag registers read by the instruction as a bitset
 370     * with byte granularity.
 371     */
 372    unsigned flags_read(const gen_device_info *devinfo) const;
 373
 374    /**
 375     * Return the subset of flag registers updated by the instruction (either
 376     * partially or fully) as a bitset with byte granularity.
 377     */
 378    unsigned flags_written() const;
 379
 380    fs_reg dst;
 381    fs_reg *src;
 382
 383    uint8_t sources; /**< Number of fs_reg sources. */
 384
 385    bool last_rt:1;
 386    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 387
 388    tgl_swsb sched; /**< Scheduling info. */
 389 };
 390
 391 /**
 392  * Make the execution of \p inst dependent on the evaluation of a possibly
 393  * inverted predicate.
 394  */
 395 static inline fs_inst *
 396 set_predicate_inv(enum brw_predicate pred, bool inverse,
 397                   fs_inst *inst)
 398 {
 399    inst->predicate = pred;
 400    inst->predicate_inverse = inverse;
 401    return inst;
 402 }
 403
 404 /**
 405  * Make the execution of \p inst dependent on the evaluation of a predicate.
 406  */
 407 static inline fs_inst *
 408 set_predicate(enum brw_predicate pred, fs_inst *inst)
 409 {
 410    return set_predicate_inv(pred, false, inst);
 411 }
 412
 413 /**
 414  * Write the result of evaluating the condition given by \p mod to a flag
 415  * register.
 416  */
 417 static inline fs_inst *
 418 set_condmod(enum brw_conditional_mod mod, fs_inst *inst)
 419 {
 420    inst->conditional_mod = mod;
 421    return inst;
 422 }
 423
 424 /**
 425  * Clamp the result of \p inst to the saturation range of its destination
 426  * datatype.
 427  */
 428 static inline fs_inst *
 429 set_saturate(bool saturate, fs_inst *inst)
 430 {
 431    inst->saturate = saturate;
 432    return inst;
 433 }
 434
 435 /**
 436  * Return the number of dataflow registers written by the instruction (either
 437  * fully or partially) counted from 'floor(reg_offset(inst->dst) /
 438  * register_size)'.  The somewhat arbitrary register size unit is 4B for the
 439  * UNIFORM and IMM files and 32B for all other files.
 440  */
 441 inline unsigned
 442 regs_written(const fs_inst *inst)
 443 {
 444    assert(inst->dst.file != UNIFORM && inst->dst.file != IMM);
 445    return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE +
 446                        inst->size_written -
 447                        MIN2(inst->size_written, reg_padding(inst->dst)),
 448                        REG_SIZE);
 449 }
 450
 451 /**
 452  * Return the number of dataflow registers read by the instruction (either
 453  * fully or partially) counted from 'floor(reg_offset(inst->src[i]) /
 454  * register_size)'.  The somewhat arbitrary register size unit is 4B for the
 455  * UNIFORM and IMM files and 32B for all other files.
 456  */
 457 inline unsigned
 458 regs_read(const fs_inst *inst, unsigned i)
 459 {
 460    const unsigned reg_size =
 461       inst->src[i].file == UNIFORM || inst->src[i].file == IMM ? 4 : REG_SIZE;
 462    return DIV_ROUND_UP(reg_offset(inst->src[i]) % reg_size +
 463                        inst->size_read(i) -
 464                        MIN2(inst->size_read(i), reg_padding(inst->src[i])),
 465                        reg_size);
 466 }
 467
 468 static inline enum brw_reg_type
 469 get_exec_type(const fs_inst *inst)
 470 {
 471    brw_reg_type exec_type = BRW_REGISTER_TYPE_B;
 472
 473    for (int i = 0; i < inst->sources; i++) {
 474       if (inst->src[i].file != BAD_FILE &&
 475           !inst->is_control_source(i)) {
 476          const brw_reg_type t = get_exec_type(inst->src[i].type);
 477          if (type_sz(t) > type_sz(exec_type))
 478             exec_type = t;
 479          else if (type_sz(t) == type_sz(exec_type) &&
 480                   brw_reg_type_is_floating_point(t))
 481             exec_type = t;
 482       }
 483    }
 484
 485    if (exec_type == BRW_REGISTER_TYPE_B)
 486       exec_type = inst->dst.type;
 487
 488    assert(exec_type != BRW_REGISTER_TYPE_B);
 489
 490    /* Promotion of the execution type to 32-bit for conversions from or to
 491     * half-float seems to be consistent with the following text from the
 492     * Cherryview PRM Vol. 7, "Execution Data Type":
 493     *
 494     * "When single precision and half precision floats are mixed between
 495     *  source operands or between source and destination operand [..] single
 496     *  precision float is the execution datatype."
 497     *
 498     * and from "Register Region Restrictions":
 499     *
 500     * "Conversion between Integer and HF (Half Float) must be DWord aligned
 501     *  and strided by a DWord on the destination."
 502     */
 503    if (type_sz(exec_type) == 2 &&
 504        inst->dst.type != exec_type) {
 505       if (exec_type == BRW_REGISTER_TYPE_HF)
 506          exec_type = BRW_REGISTER_TYPE_F;
 507       else if (inst->dst.type == BRW_REGISTER_TYPE_HF)
 508          exec_type = BRW_REGISTER_TYPE_D;
 509    }
 510
 511    return exec_type;
 512 }
 513
 514 static inline unsigned
 515 get_exec_type_size(const fs_inst *inst)
 516 {
 517    return type_sz(get_exec_type(inst));
 518 }
 519
 520 static inline bool
 521 is_send(const fs_inst *inst)
 522 {
 523    return inst->mlen || inst->is_send_from_grf();
 524 }
 525
 526 /**
 527  * Return whether the instruction isn't an ALU instruction and cannot be
 528  * assumed to complete in-order.
 529  */
 530 static inline bool
 531 is_unordered(const fs_inst *inst)
 532 {
 533    return is_send(inst) || inst->is_math();
 534 }
 535
 536 /**
 537  * Return whether the following regioning restriction applies to the specified
 538  * instruction.  From the Cherryview PRM Vol 7. "Register Region
 539  * Restrictions":
 540  *
 541  * "When source or destination datatype is 64b or operation is integer DWord
 542  *  multiply, regioning in Align1 must follow these rules:
 543  *
 544  *  1. Source and Destination horizontal stride must be aligned to the same qword.
 545  *  2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
 546  *  3. Source and Destination offset must be the same, except the case of
 547  *     scalar source."
 548  */
 549 static inline bool
 550 has_dst_aligned_region_restriction(const gen_device_info *devinfo,
 551                                    const fs_inst *inst)
 552 {
 553    const brw_reg_type exec_type = get_exec_type(inst);
 554    /* Even though the hardware spec claims that "integer DWord multiply"
 555     * operations are restricted, empirical evidence and the behavior of the
 556     * simulator suggest that only 32x32-bit integer multiplication is
 557     * restricted.
 558     */
 559    const bool is_dword_multiply = !brw_reg_type_is_floating_point(exec_type) &&
 560       ((inst->opcode == BRW_OPCODE_MUL &&
 561         MIN2(type_sz(inst->src[0].type), type_sz(inst->src[1].type)) >= 4) ||
 562        (inst->opcode == BRW_OPCODE_MAD &&
 563         MIN2(type_sz(inst->src[1].type), type_sz(inst->src[2].type)) >= 4));
 564
 565    if (type_sz(inst->dst.type) > 4 || type_sz(exec_type) > 4 ||
 566        (type_sz(exec_type) == 4 && is_dword_multiply))
 567       return devinfo->is_cherryview || gen_device_info_is_9lp(devinfo);
 568    else
 569       return false;
 570 }
 571
 572 #endif