2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_shader.h"
26 #include "common/gen_debug.h"
27 #include "compiler/glsl_types.h"
28 #include "compiler/nir/nir_builder.h"
31 is_input(nir_intrinsic_instr
*intrin
)
33 return intrin
->intrinsic
== nir_intrinsic_load_input
||
34 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
||
35 intrin
->intrinsic
== nir_intrinsic_load_interpolated_input
;
39 is_output(nir_intrinsic_instr
*intrin
)
41 return intrin
->intrinsic
== nir_intrinsic_load_output
||
42 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_output
||
43 intrin
->intrinsic
== nir_intrinsic_store_output
||
44 intrin
->intrinsic
== nir_intrinsic_store_per_vertex_output
;
48 * In many cases, we just add the base and offset together, so there's no
49 * reason to keep them separate. Sometimes, combining them is essential:
50 * if a shader only accesses part of a compound variable (such as a matrix
51 * or array), the variable's base may not actually exist in the VUE map.
53 * This pass adds constant offsets to instr->const_index[0], and resets
54 * the offset source to 0. Non-constant offsets remain unchanged - since
55 * we don't know what part of a compound variable is accessed, we allocate
56 * storage for the entire thing.
60 add_const_offset_to_base_block(nir_block
*block
, nir_builder
*b
,
61 nir_variable_mode mode
)
63 nir_foreach_instr_safe(instr
, block
) {
64 if (instr
->type
!= nir_instr_type_intrinsic
)
67 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
69 if ((mode
== nir_var_shader_in
&& is_input(intrin
)) ||
70 (mode
== nir_var_shader_out
&& is_output(intrin
))) {
71 nir_src
*offset
= nir_get_io_offset_src(intrin
);
72 nir_const_value
*const_offset
= nir_src_as_const_value(*offset
);
75 intrin
->const_index
[0] += const_offset
->u32
[0];
76 b
->cursor
= nir_before_instr(&intrin
->instr
);
77 nir_instr_rewrite_src(&intrin
->instr
, offset
,
78 nir_src_for_ssa(nir_imm_int(b
, 0)));
86 add_const_offset_to_base(nir_shader
*nir
, nir_variable_mode mode
)
88 nir_foreach_function(f
, nir
) {
91 nir_builder_init(&b
, f
->impl
);
92 nir_foreach_block(block
, f
->impl
) {
93 add_const_offset_to_base_block(block
, &b
, mode
);
100 remap_tess_levels(nir_builder
*b
, nir_intrinsic_instr
*intr
,
101 GLenum primitive_mode
)
103 const int location
= nir_intrinsic_base(intr
);
104 const unsigned component
= nir_intrinsic_component(intr
);
107 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
) {
108 switch (primitive_mode
) {
110 /* gl_TessLevelInner[0..1] lives at DWords 3-2 (reversed). */
111 nir_intrinsic_set_base(intr
, 0);
112 nir_intrinsic_set_component(intr
, 3 - component
);
113 out_of_bounds
= false;
116 /* gl_TessLevelInner[0] lives at DWord 4. */
117 nir_intrinsic_set_base(intr
, 1);
118 out_of_bounds
= component
> 0;
121 out_of_bounds
= true;
124 unreachable("Bogus tessellation domain");
126 } else if (location
== VARYING_SLOT_TESS_LEVEL_OUTER
) {
127 if (primitive_mode
== GL_ISOLINES
) {
128 /* gl_TessLevelOuter[0..1] lives at DWords 6-7 (in order). */
129 nir_intrinsic_set_base(intr
, 1);
130 nir_intrinsic_set_component(intr
, 2 + nir_intrinsic_component(intr
));
131 out_of_bounds
= component
> 1;
133 /* Triangles use DWords 7-5 (reversed); Quads use 7-4 (reversed) */
134 nir_intrinsic_set_base(intr
, 1);
135 nir_intrinsic_set_component(intr
, 3 - nir_intrinsic_component(intr
));
136 out_of_bounds
= component
== 3 && primitive_mode
== GL_TRIANGLES
;
143 if (nir_intrinsic_infos
[intr
->intrinsic
].has_dest
) {
144 b
->cursor
= nir_before_instr(&intr
->instr
);
145 nir_ssa_def
*undef
= nir_ssa_undef(b
, 1, 32);
146 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
, nir_src_for_ssa(undef
));
148 nir_instr_remove(&intr
->instr
);
155 remap_patch_urb_offsets(nir_block
*block
, nir_builder
*b
,
156 const struct brw_vue_map
*vue_map
,
157 GLenum tes_primitive_mode
)
159 const bool is_passthrough_tcs
= b
->shader
->info
.name
&&
160 strcmp(b
->shader
->info
.name
, "passthrough") == 0;
162 nir_foreach_instr_safe(instr
, block
) {
163 if (instr
->type
!= nir_instr_type_intrinsic
)
166 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
168 gl_shader_stage stage
= b
->shader
->stage
;
170 if ((stage
== MESA_SHADER_TESS_CTRL
&& is_output(intrin
)) ||
171 (stage
== MESA_SHADER_TESS_EVAL
&& is_input(intrin
))) {
173 if (!is_passthrough_tcs
&&
174 remap_tess_levels(b
, intrin
, tes_primitive_mode
))
177 int vue_slot
= vue_map
->varying_to_slot
[intrin
->const_index
[0]];
178 assert(vue_slot
!= -1);
179 intrin
->const_index
[0] = vue_slot
;
181 nir_src
*vertex
= nir_get_io_vertex_index_src(intrin
);
183 nir_const_value
*const_vertex
= nir_src_as_const_value(*vertex
);
185 intrin
->const_index
[0] += const_vertex
->u32
[0] *
186 vue_map
->num_per_vertex_slots
;
188 b
->cursor
= nir_before_instr(&intrin
->instr
);
190 /* Multiply by the number of per-vertex slots. */
191 nir_ssa_def
*vertex_offset
=
193 nir_ssa_for_src(b
, *vertex
, 1),
195 vue_map
->num_per_vertex_slots
));
197 /* Add it to the existing offset */
198 nir_src
*offset
= nir_get_io_offset_src(intrin
);
199 nir_ssa_def
*total_offset
=
200 nir_iadd(b
, vertex_offset
,
201 nir_ssa_for_src(b
, *offset
, 1));
203 nir_instr_rewrite_src(&intrin
->instr
, offset
,
204 nir_src_for_ssa(total_offset
));
213 brw_nir_lower_vs_inputs(nir_shader
*nir
,
214 bool use_legacy_snorm_formula
,
215 const uint8_t *vs_attrib_wa_flags
)
217 /* Start with the location of the variable's base. */
218 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
219 var
->data
.driver_location
= var
->data
.location
;
222 /* Now use nir_lower_io to walk dereference chains. Attribute arrays are
223 * loaded as one vec4 or dvec4 per element (or matrix column), depending on
224 * whether it is a double-precision type or not.
226 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
228 /* This pass needs actual constants */
229 nir_opt_constant_folding(nir
);
231 add_const_offset_to_base(nir
, nir_var_shader_in
);
233 brw_nir_apply_attribute_workarounds(nir
, use_legacy_snorm_formula
,
236 /* The last step is to remap VERT_ATTRIB_* to actual registers */
238 /* Whether or not we have any system generated values. gl_DrawID is not
239 * included here as it lives in its own vec4.
241 const bool has_sgvs
=
242 nir
->info
.system_values_read
&
243 (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
) |
244 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
245 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
246 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
));
248 const unsigned num_inputs
= _mesa_bitcount_64(nir
->info
.inputs_read
);
250 nir_foreach_function(function
, nir
) {
255 nir_builder_init(&b
, function
->impl
);
257 nir_foreach_block(block
, function
->impl
) {
258 nir_foreach_instr_safe(instr
, block
) {
259 if (instr
->type
!= nir_instr_type_intrinsic
)
262 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
264 switch (intrin
->intrinsic
) {
265 case nir_intrinsic_load_base_vertex
:
266 case nir_intrinsic_load_base_instance
:
267 case nir_intrinsic_load_vertex_id_zero_base
:
268 case nir_intrinsic_load_instance_id
:
269 case nir_intrinsic_load_draw_id
: {
270 b
.cursor
= nir_after_instr(&intrin
->instr
);
272 /* gl_VertexID and friends are stored by the VF as the last
273 * vertex element. We convert them to load_input intrinsics at
274 * the right location.
276 nir_intrinsic_instr
*load
=
277 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_input
);
278 load
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
280 nir_intrinsic_set_base(load
, num_inputs
);
281 switch (intrin
->intrinsic
) {
282 case nir_intrinsic_load_base_vertex
:
283 nir_intrinsic_set_component(load
, 0);
285 case nir_intrinsic_load_base_instance
:
286 nir_intrinsic_set_component(load
, 1);
288 case nir_intrinsic_load_vertex_id_zero_base
:
289 nir_intrinsic_set_component(load
, 2);
291 case nir_intrinsic_load_instance_id
:
292 nir_intrinsic_set_component(load
, 3);
294 case nir_intrinsic_load_draw_id
:
295 /* gl_DrawID is stored right after gl_VertexID and friends
296 * if any of them exist.
298 nir_intrinsic_set_base(load
, num_inputs
+ has_sgvs
);
299 nir_intrinsic_set_component(load
, 0);
302 unreachable("Invalid system value intrinsic");
305 load
->num_components
= 1;
306 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 1, 32, NULL
);
307 nir_builder_instr_insert(&b
, &load
->instr
);
309 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
310 nir_src_for_ssa(&load
->dest
.ssa
));
311 nir_instr_remove(&intrin
->instr
);
315 case nir_intrinsic_load_input
: {
316 /* Attributes come in a contiguous block, ordered by their
317 * gl_vert_attrib value. That means we can compute the slot
318 * number for an attribute by masking out the enabled attributes
319 * before it and counting the bits.
321 int attr
= nir_intrinsic_base(intrin
);
322 int slot
= _mesa_bitcount_64(nir
->info
.inputs_read
&
323 BITFIELD64_MASK(attr
));
324 nir_intrinsic_set_base(intrin
, slot
);
329 break; /* Nothing to do */
337 brw_nir_lower_vue_inputs(nir_shader
*nir
,
338 const struct brw_vue_map
*vue_map
)
340 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
341 var
->data
.driver_location
= var
->data
.location
;
344 /* Inputs are stored in vec4 slots, so use type_size_vec4(). */
345 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
347 /* This pass needs actual constants */
348 nir_opt_constant_folding(nir
);
350 add_const_offset_to_base(nir
, nir_var_shader_in
);
352 nir_foreach_function(function
, nir
) {
356 nir_foreach_block(block
, function
->impl
) {
357 nir_foreach_instr(instr
, block
) {
358 if (instr
->type
!= nir_instr_type_intrinsic
)
361 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
363 if (intrin
->intrinsic
== nir_intrinsic_load_input
||
364 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
) {
365 /* Offset 0 is the VUE header, which contains
366 * VARYING_SLOT_LAYER [.y], VARYING_SLOT_VIEWPORT [.z], and
367 * VARYING_SLOT_PSIZ [.w].
369 int varying
= nir_intrinsic_base(intrin
);
372 case VARYING_SLOT_PSIZ
:
373 nir_intrinsic_set_base(intrin
, 0);
374 nir_intrinsic_set_component(intrin
, 3);
378 vue_slot
= vue_map
->varying_to_slot
[varying
];
379 assert(vue_slot
!= -1);
380 nir_intrinsic_set_base(intrin
, vue_slot
);
390 brw_nir_lower_tes_inputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
)
392 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
393 var
->data
.driver_location
= var
->data
.location
;
396 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
398 /* This pass needs actual constants */
399 nir_opt_constant_folding(nir
);
401 add_const_offset_to_base(nir
, nir_var_shader_in
);
403 nir_foreach_function(function
, nir
) {
404 if (function
->impl
) {
406 nir_builder_init(&b
, function
->impl
);
407 nir_foreach_block(block
, function
->impl
) {
408 remap_patch_urb_offsets(block
, &b
, vue_map
,
409 nir
->info
.tess
.primitive_mode
);
416 brw_nir_lower_fs_inputs(nir_shader
*nir
,
417 const struct gen_device_info
*devinfo
,
418 const struct brw_wm_prog_key
*key
)
420 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
421 var
->data
.driver_location
= var
->data
.location
;
423 /* Apply default interpolation mode.
425 * Everything defaults to smooth except for the legacy GL color
426 * built-in variables, which might be flat depending on API state.
428 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
429 const bool flat
= key
->flat_shade
&&
430 (var
->data
.location
== VARYING_SLOT_COL0
||
431 var
->data
.location
== VARYING_SLOT_COL1
);
433 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
434 : INTERP_MODE_SMOOTH
;
437 /* On Ironlake and below, there is only one interpolation mode.
438 * Centroid interpolation doesn't mean anything on this hardware --
439 * there is no multisampling.
441 if (devinfo
->gen
< 6) {
442 var
->data
.centroid
= false;
443 var
->data
.sample
= false;
447 nir_lower_io_options lower_io_options
= 0;
448 if (key
->persample_interp
)
449 lower_io_options
|= nir_lower_io_force_sample_interpolation
;
451 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, lower_io_options
);
453 /* This pass needs actual constants */
454 nir_opt_constant_folding(nir
);
456 add_const_offset_to_base(nir
, nir_var_shader_in
);
460 brw_nir_lower_vue_outputs(nir_shader
*nir
,
463 nir_foreach_variable(var
, &nir
->outputs
) {
464 var
->data
.driver_location
= var
->data
.location
;
467 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
, 0);
471 brw_nir_lower_tcs_outputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
,
472 GLenum tes_primitive_mode
)
474 nir_foreach_variable(var
, &nir
->outputs
) {
475 var
->data
.driver_location
= var
->data
.location
;
478 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
, 0);
480 /* This pass needs actual constants */
481 nir_opt_constant_folding(nir
);
483 add_const_offset_to_base(nir
, nir_var_shader_out
);
485 nir_foreach_function(function
, nir
) {
486 if (function
->impl
) {
488 nir_builder_init(&b
, function
->impl
);
489 nir_foreach_block(block
, function
->impl
) {
490 remap_patch_urb_offsets(block
, &b
, vue_map
, tes_primitive_mode
);
497 brw_nir_lower_fs_outputs(nir_shader
*nir
)
499 nir_foreach_variable(var
, &nir
->outputs
) {
500 var
->data
.driver_location
=
501 SET_FIELD(var
->data
.index
, BRW_NIR_FRAG_OUTPUT_INDEX
) |
502 SET_FIELD(var
->data
.location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
505 nir_lower_io(nir
, nir_var_shader_out
, type_size_dvec4
, 0);
509 brw_nir_lower_cs_shared(nir_shader
*nir
)
511 nir_assign_var_locations(&nir
->shared
, &nir
->num_shared
,
512 type_size_scalar_bytes
);
513 nir_lower_io(nir
, nir_var_shared
, type_size_scalar_bytes
, 0);
516 #define OPT(pass, ...) ({ \
517 bool this_progress = false; \
518 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
525 nir_optimize(nir_shader
*nir
, const struct brw_compiler
*compiler
,
528 nir_variable_mode indirect_mask
= 0;
529 if (compiler
->glsl_compiler_options
[nir
->stage
].EmitNoIndirectInput
)
530 indirect_mask
|= nir_var_shader_in
;
531 if (compiler
->glsl_compiler_options
[nir
->stage
].EmitNoIndirectOutput
)
532 indirect_mask
|= nir_var_shader_out
;
533 if (compiler
->glsl_compiler_options
[nir
->stage
].EmitNoIndirectTemp
)
534 indirect_mask
|= nir_var_local
;
539 OPT(nir_lower_vars_to_ssa
);
540 OPT(nir_opt_copy_prop_vars
);
543 OPT(nir_lower_alu_to_scalar
);
549 OPT(nir_lower_phis_to_scalar
);
555 OPT(nir_opt_peephole_select
, 0);
556 OPT(nir_opt_intrinsics
);
557 OPT(nir_opt_algebraic
);
558 OPT(nir_opt_constant_folding
);
559 OPT(nir_opt_dead_cf
);
560 if (OPT(nir_opt_trivial_continues
)) {
561 /* If nir_opt_trivial_continues makes progress, then we need to clean
562 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
569 if (nir
->options
->max_unroll_iterations
!= 0) {
570 OPT(nir_opt_loop_unroll
, indirect_mask
);
572 OPT(nir_opt_remove_phis
);
574 OPT(nir_lower_doubles
, nir_lower_drcp
|
581 nir_lower_dround_even
|
583 OPT(nir_lower_64bit_pack
);
589 /* Does some simple lowering and runs the standard suite of optimizations
591 * This is intended to be called more-or-less directly after you get the
592 * shader out of GLSL or some other source. While it is geared towards i965,
593 * it is not at all generator-specific except for the is_scalar flag. Even
594 * there, it is safe to call with is_scalar = false for a shader that is
595 * intended for the FS backend as long as nir_optimize is called again with
596 * is_scalar = true to scalarize everything prior to code gen.
599 brw_preprocess_nir(const struct brw_compiler
*compiler
, nir_shader
*nir
)
601 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
602 UNUSED
bool progress
; /* Written by OPT */
604 const bool is_scalar
= compiler
->scalar_stage
[nir
->stage
];
606 if (nir
->stage
== MESA_SHADER_GEOMETRY
)
607 OPT(nir_lower_gs_intrinsics
);
609 /* See also brw_nir_trig_workarounds.py */
610 if (compiler
->precise_trig
&&
611 !(devinfo
->gen
>= 10 || devinfo
->is_kabylake
))
612 OPT(brw_nir_apply_trig_workarounds
);
614 static const nir_lower_tex_options tex_options
= {
616 .lower_txf_offset
= true,
617 .lower_rect_offset
= true,
618 .lower_txd_cube_map
= true,
621 OPT(nir_lower_tex
, &tex_options
);
622 OPT(nir_normalize_cubemap_coords
);
623 OPT(nir_lower_read_invocation_to_scalar
);
625 OPT(nir_lower_global_vars_to_local
);
627 OPT(nir_split_var_copies
);
629 nir
= nir_optimize(nir
, compiler
, is_scalar
);
632 OPT(nir_lower_load_const_to_scalar
);
635 /* Lower a bunch of stuff */
636 OPT(nir_lower_var_copies
);
638 OPT(nir_lower_clip_cull_distance_arrays
);
640 nir_variable_mode indirect_mask
= 0;
641 if (compiler
->glsl_compiler_options
[nir
->stage
].EmitNoIndirectInput
)
642 indirect_mask
|= nir_var_shader_in
;
643 if (compiler
->glsl_compiler_options
[nir
->stage
].EmitNoIndirectOutput
)
644 indirect_mask
|= nir_var_shader_out
;
645 if (compiler
->glsl_compiler_options
[nir
->stage
].EmitNoIndirectTemp
)
646 indirect_mask
|= nir_var_local
;
648 nir_lower_indirect_derefs(nir
, indirect_mask
);
650 nir_lower_int64(nir
, nir_lower_imul64
|
654 /* Get rid of split copies */
655 nir
= nir_optimize(nir
, compiler
, is_scalar
);
657 OPT(nir_remove_dead_variables
, nir_var_local
);
662 /* Prepare the given shader for codegen
664 * This function is intended to be called right before going into the actual
665 * backend and is highly backend-specific. Also, once this function has been
666 * called on a shader, it will no longer be in SSA form so most optimizations
670 brw_postprocess_nir(nir_shader
*nir
, const struct brw_compiler
*compiler
,
673 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
675 (INTEL_DEBUG
& intel_debug_flag_for_shader_stage(nir
->stage
));
677 UNUSED
bool progress
; /* Written by OPT */
682 OPT(nir_opt_algebraic_before_ffma
);
685 nir
= nir_optimize(nir
, compiler
, is_scalar
);
687 if (devinfo
->gen
>= 6) {
688 /* Try and fuse multiply-adds */
689 OPT(brw_nir_opt_peephole_ffma
);
692 OPT(nir_opt_algebraic_late
);
694 OPT(nir_lower_to_source_mods
);
697 OPT(nir_opt_move_comparisons
);
699 OPT(nir_lower_locals_to_regs
);
701 if (unlikely(debug_enabled
)) {
702 /* Re-index SSA defs so we print more sensible numbers. */
703 nir_foreach_function(function
, nir
) {
705 nir_index_ssa_defs(function
->impl
);
708 fprintf(stderr
, "NIR (SSA form) for %s shader:\n",
709 _mesa_shader_stage_to_string(nir
->stage
));
710 nir_print_shader(nir
, stderr
);
713 OPT(nir_convert_from_ssa
, true);
716 OPT(nir_move_vec_src_uses_to_dest
);
717 OPT(nir_lower_vec_to_movs
);
720 /* This is the last pass we run before we start emitting stuff. It
721 * determines when we need to insert boolean resolves on Gen <= 5. We
722 * run it last because it stashes data in instr->pass_flags and we don't
723 * want that to be squashed by other NIR passes.
725 if (devinfo
->gen
<= 5)
726 brw_nir_analyze_boolean_resolves(nir
);
730 if (unlikely(debug_enabled
)) {
731 fprintf(stderr
, "NIR (final form) for %s shader:\n",
732 _mesa_shader_stage_to_string(nir
->stage
));
733 nir_print_shader(nir
, stderr
);
740 brw_nir_apply_sampler_key(nir_shader
*nir
,
741 const struct brw_compiler
*compiler
,
742 const struct brw_sampler_prog_key_data
*key_tex
,
745 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
746 nir_lower_tex_options tex_options
= { 0 };
748 /* Iron Lake and prior require lowering of all rectangle textures */
749 if (devinfo
->gen
< 6)
750 tex_options
.lower_rect
= true;
752 /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
753 if (devinfo
->gen
< 8) {
754 tex_options
.saturate_s
= key_tex
->gl_clamp_mask
[0];
755 tex_options
.saturate_t
= key_tex
->gl_clamp_mask
[1];
756 tex_options
.saturate_r
= key_tex
->gl_clamp_mask
[2];
759 /* Prior to Haswell, we have to fake texture swizzle */
760 for (unsigned s
= 0; s
< MAX_SAMPLERS
; s
++) {
761 if (key_tex
->swizzles
[s
] == SWIZZLE_NOOP
)
764 tex_options
.swizzle_result
|= (1 << s
);
765 for (unsigned c
= 0; c
< 4; c
++)
766 tex_options
.swizzles
[s
][c
] = GET_SWZ(key_tex
->swizzles
[s
], c
);
769 /* Prior to Haswell, we have to lower gradients on shadow samplers */
770 tex_options
.lower_txd_shadow
= devinfo
->gen
< 8 && !devinfo
->is_haswell
;
772 tex_options
.lower_y_uv_external
= key_tex
->y_uv_image_mask
;
773 tex_options
.lower_y_u_v_external
= key_tex
->y_u_v_image_mask
;
774 tex_options
.lower_yx_xuxv_external
= key_tex
->yx_xuxv_image_mask
;
775 tex_options
.lower_xy_uxvx_external
= key_tex
->xy_uxvx_image_mask
;
777 if (nir_lower_tex(nir
, &tex_options
)) {
778 nir_validate_shader(nir
);
779 nir
= nir_optimize(nir
, compiler
, is_scalar
);
786 brw_type_for_nir_type(const struct gen_device_info
*devinfo
, nir_alu_type type
)
790 case nir_type_uint32
:
791 return BRW_REGISTER_TYPE_UD
;
794 case nir_type_bool32
:
796 return BRW_REGISTER_TYPE_D
;
798 case nir_type_float32
:
799 return BRW_REGISTER_TYPE_F
;
800 case nir_type_float64
:
801 return BRW_REGISTER_TYPE_DF
;
803 return devinfo
->gen
< 8 ? BRW_REGISTER_TYPE_DF
: BRW_REGISTER_TYPE_Q
;
804 case nir_type_uint64
:
805 return devinfo
->gen
< 8 ? BRW_REGISTER_TYPE_DF
: BRW_REGISTER_TYPE_UQ
;
807 unreachable("unknown type");
810 return BRW_REGISTER_TYPE_F
;
813 /* Returns the glsl_base_type corresponding to a nir_alu_type.
814 * This is used by both brw_vec4_nir and brw_fs_nir.
817 brw_glsl_base_type_for_nir_type(nir_alu_type type
)
821 case nir_type_float32
:
822 return GLSL_TYPE_FLOAT
;
824 case nir_type_float64
:
825 return GLSL_TYPE_DOUBLE
;
829 return GLSL_TYPE_INT
;
832 case nir_type_uint32
:
833 return GLSL_TYPE_UINT
;
836 unreachable("bad type");