2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include "brw_fs_live_variables.h"
32 #include "brw_shader.h"
36 /** @file brw_fs_schedule_instructions.cpp
38 * List scheduling of FS instructions.
40 * The basic model of the list scheduler is to take a basic block,
41 * compute a DAG of the dependencies (RAW ordering with latency, WAW
42 * ordering with latency, WAR ordering), and make a list of the DAG heads.
43 * Heuristically pick a DAG head, then put all the children that are
44 * now DAG heads into the list of things to schedule.
46 * The heuristic is the important part. We're trying to be cheap,
47 * since actually computing the optimal scheduling is NP complete.
48 * What we do is track a "current clock". When we schedule a node, we
49 * update the earliest-unblocked clock time of its children, and
50 * increment the clock. Then, when trying to schedule, we just pick
51 * the earliest-unblocked instruction to schedule.
53 * Note that often there will be many things which could execute
54 * immediately, and there are a range of heuristic options to choose
55 * from in picking among those.
58 static bool debug
= false;
60 class instruction_scheduler
;
62 class schedule_node
: public exec_node
65 schedule_node(backend_instruction
*inst
, instruction_scheduler
*sched
);
66 void set_latency_gen4();
67 void set_latency_gen7(bool is_haswell
);
69 backend_instruction
*inst
;
70 schedule_node
**children
;
79 * Which iteration of pushing groups of children onto the candidates list
80 * this node was a part of.
82 unsigned cand_generation
;
85 * This is the sum of the instruction's latency plus the maximum delay of
86 * its children, or just the issue_time if it's a leaf node.
91 * Preferred exit node among the (direct or indirect) successors of this
92 * node. Among the scheduler nodes blocked by this node, this will be the
93 * one that may cause earliest program termination, or NULL if none of the
94 * successors is an exit node.
100 * Lower bound of the scheduling time after which one of the instructions
101 * blocked by this node may lead to program termination.
103 * exit_unblocked_time() determines a strict partial ordering relation '«' on
104 * the set of scheduler nodes as follows:
106 * n « m <-> exit_unblocked_time(n) < exit_unblocked_time(m)
108 * which can be used to heuristically order nodes according to how early they
109 * can unblock an exit node and lead to program termination.
112 exit_unblocked_time(const schedule_node
*n
)
114 return n
->exit
? n
->exit
->unblocked_time
: INT_MAX
;
118 schedule_node::set_latency_gen4()
121 int math_latency
= 22;
123 switch (inst
->opcode
) {
124 case SHADER_OPCODE_RCP
:
125 this->latency
= 1 * chans
* math_latency
;
127 case SHADER_OPCODE_RSQ
:
128 this->latency
= 2 * chans
* math_latency
;
130 case SHADER_OPCODE_INT_QUOTIENT
:
131 case SHADER_OPCODE_SQRT
:
132 case SHADER_OPCODE_LOG2
:
133 /* full precision log. partial is 2. */
134 this->latency
= 3 * chans
* math_latency
;
136 case SHADER_OPCODE_INT_REMAINDER
:
137 case SHADER_OPCODE_EXP2
:
138 /* full precision. partial is 3, same throughput. */
139 this->latency
= 4 * chans
* math_latency
;
141 case SHADER_OPCODE_POW
:
142 this->latency
= 8 * chans
* math_latency
;
144 case SHADER_OPCODE_SIN
:
145 case SHADER_OPCODE_COS
:
146 /* minimum latency, max is 12 rounds. */
147 this->latency
= 5 * chans
* math_latency
;
156 schedule_node::set_latency_gen7(bool is_haswell
)
158 switch (inst
->opcode
) {
161 * (since the last two src operands are in different register banks):
162 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
164 * 3 cycles on IVB, 4 on HSW
165 * (since the last two src operands are in the same register bank):
166 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
168 * 18 cycles on IVB, 16 on HSW
169 * (since the last two src operands are in different register banks):
170 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
171 * mov(8) null g4<4,5,1>F { align16 WE_normal 1Q };
173 * 20 cycles on IVB, 18 on HSW
174 * (since the last two src operands are in the same register bank):
175 * mad(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
176 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
179 /* Our register allocator doesn't know about register banks, so use the
182 latency
= is_haswell
? 16 : 18;
187 * (since the last two src operands are in different register banks):
188 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
190 * 3 cycles on IVB, 4 on HSW
191 * (since the last two src operands are in the same register bank):
192 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
194 * 16 cycles on IVB, 14 on HSW
195 * (since the last two src operands are in different register banks):
196 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g3.1<4,4,1>F.x { align16 WE_normal 1Q };
197 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
200 * (since the last two src operands are in the same register bank):
201 * lrp(8) g4<1>F g2.2<4,4,1>F.x g2<4,4,1>F.x g2.1<4,4,1>F.x { align16 WE_normal 1Q };
202 * mov(8) null g4<4,4,1>F { align16 WE_normal 1Q };
205 /* Our register allocator doesn't know about register banks, so use the
211 case SHADER_OPCODE_RCP
:
212 case SHADER_OPCODE_RSQ
:
213 case SHADER_OPCODE_SQRT
:
214 case SHADER_OPCODE_LOG2
:
215 case SHADER_OPCODE_EXP2
:
216 case SHADER_OPCODE_SIN
:
217 case SHADER_OPCODE_COS
:
219 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
222 * math inv(8) g4<1>F g2<0,1,0>F null { align1 WE_normal 1Q };
223 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
225 * Same for exp2, log2, rsq, sqrt, sin, cos.
227 latency
= is_haswell
? 14 : 16;
230 case SHADER_OPCODE_POW
:
232 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
235 * math pow(8) g4<1>F g2<0,1,0>F g2.1<0,1,0>F { align1 WE_normal 1Q };
236 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
238 latency
= is_haswell
? 22 : 24;
241 case SHADER_OPCODE_TEX
:
242 case SHADER_OPCODE_TXD
:
243 case SHADER_OPCODE_TXF
:
244 case SHADER_OPCODE_TXF_LZ
:
245 case SHADER_OPCODE_TXL
:
246 case SHADER_OPCODE_TXL_LZ
:
248 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
249 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
250 * send(8) g4<1>UW g114<8,8,1>F
251 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
253 * 697 +/-49 cycles (min 610, n=26):
254 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
255 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
256 * send(8) g4<1>UW g114<8,8,1>F
257 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
258 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
260 * So the latency on our first texture load of the batchbuffer takes
261 * ~700 cycles, since the caches are cold at that point.
263 * 840 +/- 92 cycles (min 720, n=25):
264 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
265 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
266 * send(8) g4<1>UW g114<8,8,1>F
267 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
268 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
269 * send(8) g4<1>UW g114<8,8,1>F
270 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
271 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
273 * On the second load, it takes just an extra ~140 cycles, and after
274 * accounting for the 14 cycles of the MOV's latency, that makes ~130.
276 * 683 +/- 49 cycles (min = 602, n=47):
277 * mov(8) g115<1>F 0F { align1 WE_normal 1Q };
278 * mov(8) g114<1>F 0F { align1 WE_normal 1Q };
279 * send(8) g4<1>UW g114<8,8,1>F
280 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
281 * send(8) g50<1>UW g114<8,8,1>F
282 * sampler (10, 0, 0, 1) mlen 2 rlen 4 { align1 WE_normal 1Q };
283 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
285 * The unit appears to be pipelined, since this matches up with the
286 * cache-cold case, despite there being two loads here. If you replace
287 * the g4 in the MOV to null with g50, it's still 693 +/- 52 (n=39).
289 * So, take some number between the cache-hot 140 cycles and the
290 * cache-cold 700 cycles. No particular tuning was done on this.
292 * I haven't done significant testing of the non-TEX opcodes. TXL at
293 * least looked about the same as TEX.
298 case SHADER_OPCODE_TXS
:
299 /* Testing textureSize(sampler2D, 0), one load was 420 +/- 41
301 * mov(8) g114<1>UD 0D { align1 WE_normal 1Q };
302 * send(8) g6<1>UW g114<8,8,1>F
303 * sampler (10, 0, 10, 1) mlen 1 rlen 4 { align1 WE_normal 1Q };
304 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1Q };
307 * Two loads was 535 +/- 30 cycles (n=19):
308 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
309 * send(16) g6<1>UW g114<8,8,1>F
310 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
311 * mov(16) g114<1>UD 0D { align1 WE_normal 1H };
312 * mov(16) g6<1>F g6<8,8,1>D { align1 WE_normal 1H };
313 * send(16) g8<1>UW g114<8,8,1>F
314 * sampler (10, 0, 10, 2) mlen 2 rlen 8 { align1 WE_normal 1H };
315 * mov(16) g8<1>F g8<8,8,1>D { align1 WE_normal 1H };
316 * add(16) g6<1>F g6<8,8,1>F g8<8,8,1>F { align1 WE_normal 1H };
318 * Since the only caches that should matter are just the
319 * instruction/state cache containing the surface state, assume that we
320 * always have hot caches.
325 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
326 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
327 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
328 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
329 case VS_OPCODE_PULL_CONSTANT_LOAD
:
330 /* testing using varying-index pull constants:
333 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
334 * send(8) g4<1>F g4<8,8,1>D
335 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
338 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
339 * send(8) g4<1>F g4<8,8,1>D
340 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
341 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
344 * mov(8) g4<1>D g2.1<0,1,0>F { align1 WE_normal 1Q };
345 * send(8) g4<1>F g4<8,8,1>D
346 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
347 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
348 * send(8) g4<1>F g4<8,8,1>D
349 * data (9, 2, 3) mlen 1 rlen 1 { align1 WE_normal 1Q };
350 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
352 * So, if it's cache-hot, it's about 140. If it's cache cold, it's
353 * about 460. We expect to mostly be cache hot, so pick something more
359 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
360 /* Testing a load from offset 0, that had been previously written:
362 * send(8) g114<1>UW g0<8,8,1>F data (0, 0, 0) mlen 1 rlen 1 { align1 WE_normal 1Q };
363 * mov(8) null g114<8,8,1>F { align1 WE_normal 1Q };
365 * The cycles spent seemed to be grouped around 40-50 (as low as 38),
366 * then around 140. Presumably this is cache hit vs miss.
371 case SHADER_OPCODE_UNTYPED_ATOMIC
:
372 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT
:
373 case SHADER_OPCODE_TYPED_ATOMIC
:
375 * mov(8) g112<1>ud 0x00000000ud { align1 WE_all 1Q };
376 * mov(1) g112.7<1>ud g1.7<0,1,0>ud { align1 WE_all };
377 * mov(8) g113<1>ud 0x00000000ud { align1 WE_normal 1Q };
378 * send(8) g4<1>ud g112<8,8,1>ud
379 * data (38, 5, 6) mlen 2 rlen 1 { align1 WE_normal 1Q };
381 * Running it 100 times as fragment shader on a 128x128 quad
382 * gives an average latency of 13867 cycles per atomic op,
383 * standard deviation 3%. Note that this is a rather
384 * pessimistic estimate, the actual latency in cases with few
385 * collisions between threads and favorable pipelining has been
386 * seen to be reduced by a factor of 100.
391 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
392 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
393 case SHADER_OPCODE_TYPED_SURFACE_READ
:
394 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
396 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
397 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
398 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
399 * send(8) g4<1>UD g112<8,8,1>UD
400 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
402 * . [repeats 8 times]
404 * mov(8) g112<1>UD 0x00000000UD { align1 WE_all 1Q };
405 * mov(1) g112.7<1>UD g1.7<0,1,0>UD { align1 WE_all };
406 * mov(8) g113<1>UD 0x00000000UD { align1 WE_normal 1Q };
407 * send(8) g4<1>UD g112<8,8,1>UD
408 * data (38, 6, 5) mlen 2 rlen 1 { align1 WE_normal 1Q };
410 * Running it 100 times as fragment shader on a 128x128 quad
411 * gives an average latency of 583 cycles per surface read,
412 * standard deviation 0.9%.
414 latency
= is_haswell
? 300 : 600;
419 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
422 * mul(8) g4<1>F g2<0,1,0>F 0.5F { align1 WE_normal 1Q };
423 * mov(8) null g4<8,8,1>F { align1 WE_normal 1Q };
430 class instruction_scheduler
{
432 instruction_scheduler(backend_shader
*s
, int grf_count
,
433 unsigned hw_reg_count
, int block_count
,
434 instruction_scheduler_mode mode
)
437 this->mem_ctx
= ralloc_context(NULL
);
438 this->grf_count
= grf_count
;
439 this->hw_reg_count
= hw_reg_count
;
440 this->instructions
.make_empty();
441 this->instructions_to_schedule
= 0;
442 this->post_reg_alloc
= (mode
== SCHEDULE_POST
);
444 if (!post_reg_alloc
) {
445 this->reg_pressure_in
= rzalloc_array(mem_ctx
, int, block_count
);
447 this->livein
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
448 for (int i
= 0; i
< block_count
; i
++)
449 this->livein
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
450 BITSET_WORDS(grf_count
));
452 this->liveout
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
453 for (int i
= 0; i
< block_count
; i
++)
454 this->liveout
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
455 BITSET_WORDS(grf_count
));
457 this->hw_liveout
= ralloc_array(mem_ctx
, BITSET_WORD
*, block_count
);
458 for (int i
= 0; i
< block_count
; i
++)
459 this->hw_liveout
[i
] = rzalloc_array(mem_ctx
, BITSET_WORD
,
460 BITSET_WORDS(hw_reg_count
));
462 this->written
= rzalloc_array(mem_ctx
, bool, grf_count
);
464 this->reads_remaining
= rzalloc_array(mem_ctx
, int, grf_count
);
466 this->hw_reads_remaining
= rzalloc_array(mem_ctx
, int, hw_reg_count
);
468 this->reg_pressure_in
= NULL
;
470 this->liveout
= NULL
;
471 this->hw_liveout
= NULL
;
472 this->written
= NULL
;
473 this->reads_remaining
= NULL
;
474 this->hw_reads_remaining
= NULL
;
478 ~instruction_scheduler()
480 ralloc_free(this->mem_ctx
);
482 void add_barrier_deps(schedule_node
*n
);
483 void add_dep(schedule_node
*before
, schedule_node
*after
, int latency
);
484 void add_dep(schedule_node
*before
, schedule_node
*after
);
486 void run(cfg_t
*cfg
);
487 void add_insts_from_block(bblock_t
*block
);
488 void compute_delays();
489 void compute_exits();
490 virtual void calculate_deps() = 0;
491 virtual schedule_node
*choose_instruction_to_schedule() = 0;
494 * Returns how many cycles it takes the instruction to issue.
496 * Instructions in gen hardware are handled one simd4 vector at a time,
497 * with 1 cycle per vector dispatched. Thus SIMD8 pixel shaders take 2
498 * cycles to dispatch and SIMD16 (compressed) instructions take 4.
500 virtual int issue_time(backend_instruction
*inst
) = 0;
502 virtual void count_reads_remaining(backend_instruction
*inst
) = 0;
503 virtual void setup_liveness(cfg_t
*cfg
) = 0;
504 virtual void update_register_pressure(backend_instruction
*inst
) = 0;
505 virtual int get_register_pressure_benefit(backend_instruction
*inst
) = 0;
507 void schedule_instructions(bblock_t
*block
);
512 int instructions_to_schedule
;
514 unsigned hw_reg_count
;
517 exec_list instructions
;
520 instruction_scheduler_mode mode
;
523 * The register pressure at the beginning of each basic block.
526 int *reg_pressure_in
;
529 * The virtual GRF's whose range overlaps the beginning of each basic block.
532 BITSET_WORD
**livein
;
535 * The virtual GRF's whose range overlaps the end of each basic block.
538 BITSET_WORD
**liveout
;
541 * The hardware GRF's whose range overlaps the end of each basic block.
544 BITSET_WORD
**hw_liveout
;
547 * Whether we've scheduled a write for this virtual GRF yet.
553 * How many reads we haven't scheduled for this virtual GRF yet.
556 int *reads_remaining
;
559 * How many reads we haven't scheduled for this hardware GRF yet.
562 int *hw_reads_remaining
;
565 class fs_instruction_scheduler
: public instruction_scheduler
568 fs_instruction_scheduler(fs_visitor
*v
, int grf_count
, int hw_reg_count
,
570 instruction_scheduler_mode mode
);
571 void calculate_deps();
572 bool is_compressed(fs_inst
*inst
);
573 schedule_node
*choose_instruction_to_schedule();
574 int issue_time(backend_instruction
*inst
);
577 void count_reads_remaining(backend_instruction
*inst
);
578 void setup_liveness(cfg_t
*cfg
);
579 void update_register_pressure(backend_instruction
*inst
);
580 int get_register_pressure_benefit(backend_instruction
*inst
);
583 fs_instruction_scheduler::fs_instruction_scheduler(fs_visitor
*v
,
584 int grf_count
, int hw_reg_count
,
586 instruction_scheduler_mode mode
)
587 : instruction_scheduler(v
, grf_count
, hw_reg_count
, block_count
, mode
),
593 is_src_duplicate(fs_inst
*inst
, int src
)
595 for (int i
= 0; i
< src
; i
++)
596 if (inst
->src
[i
].equals(inst
->src
[src
]))
603 fs_instruction_scheduler::count_reads_remaining(backend_instruction
*be
)
605 fs_inst
*inst
= (fs_inst
*)be
;
607 if (!reads_remaining
)
610 for (int i
= 0; i
< inst
->sources
; i
++) {
611 if (is_src_duplicate(inst
, i
))
614 if (inst
->src
[i
].file
== VGRF
) {
615 reads_remaining
[inst
->src
[i
].nr
]++;
616 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
617 if (inst
->src
[i
].nr
>= hw_reg_count
)
620 for (unsigned j
= 0; j
< regs_read(inst
, i
); j
++)
621 hw_reads_remaining
[inst
->src
[i
].nr
+ j
]++;
627 fs_instruction_scheduler::setup_liveness(cfg_t
*cfg
)
629 /* First, compute liveness on a per-GRF level using the in/out sets from
630 * liveness calculation.
632 for (int block
= 0; block
< cfg
->num_blocks
; block
++) {
633 for (int i
= 0; i
< v
->live_intervals
->num_vars
; i
++) {
634 if (BITSET_TEST(v
->live_intervals
->block_data
[block
].livein
, i
)) {
635 int vgrf
= v
->live_intervals
->vgrf_from_var
[i
];
636 if (!BITSET_TEST(livein
[block
], vgrf
)) {
637 reg_pressure_in
[block
] += v
->alloc
.sizes
[vgrf
];
638 BITSET_SET(livein
[block
], vgrf
);
642 if (BITSET_TEST(v
->live_intervals
->block_data
[block
].liveout
, i
))
643 BITSET_SET(liveout
[block
], v
->live_intervals
->vgrf_from_var
[i
]);
647 /* Now, extend the live in/live out sets for when a range crosses a block
648 * boundary, which matches what our register allocator/interference code
649 * does to account for force_writemask_all and incompatible exec_mask's.
651 for (int block
= 0; block
< cfg
->num_blocks
- 1; block
++) {
652 for (int i
= 0; i
< grf_count
; i
++) {
653 if (v
->virtual_grf_start
[i
] <= cfg
->blocks
[block
]->end_ip
&&
654 v
->virtual_grf_end
[i
] >= cfg
->blocks
[block
+ 1]->start_ip
) {
655 if (!BITSET_TEST(livein
[block
+ 1], i
)) {
656 reg_pressure_in
[block
+ 1] += v
->alloc
.sizes
[i
];
657 BITSET_SET(livein
[block
+ 1], i
);
660 BITSET_SET(liveout
[block
], i
);
665 int payload_last_use_ip
[hw_reg_count
];
666 v
->calculate_payload_ranges(hw_reg_count
, payload_last_use_ip
);
668 for (unsigned i
= 0; i
< hw_reg_count
; i
++) {
669 if (payload_last_use_ip
[i
] == -1)
672 for (int block
= 0; block
< cfg
->num_blocks
; block
++) {
673 if (cfg
->blocks
[block
]->start_ip
<= payload_last_use_ip
[i
])
674 reg_pressure_in
[block
]++;
676 if (cfg
->blocks
[block
]->end_ip
<= payload_last_use_ip
[i
])
677 BITSET_SET(hw_liveout
[block
], i
);
683 fs_instruction_scheduler::update_register_pressure(backend_instruction
*be
)
685 fs_inst
*inst
= (fs_inst
*)be
;
687 if (!reads_remaining
)
690 if (inst
->dst
.file
== VGRF
) {
691 written
[inst
->dst
.nr
] = true;
694 for (int i
= 0; i
< inst
->sources
; i
++) {
695 if (is_src_duplicate(inst
, i
))
698 if (inst
->src
[i
].file
== VGRF
) {
699 reads_remaining
[inst
->src
[i
].nr
]--;
700 } else if (inst
->src
[i
].file
== FIXED_GRF
&&
701 inst
->src
[i
].nr
< hw_reg_count
) {
702 for (unsigned off
= 0; off
< regs_read(inst
, i
); off
++)
703 hw_reads_remaining
[inst
->src
[i
].nr
+ off
]--;
709 fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*be
)
711 fs_inst
*inst
= (fs_inst
*)be
;
714 if (inst
->dst
.file
== VGRF
) {
715 if (!BITSET_TEST(livein
[block_idx
], inst
->dst
.nr
) &&
716 !written
[inst
->dst
.nr
])
717 benefit
-= v
->alloc
.sizes
[inst
->dst
.nr
];
720 for (int i
= 0; i
< inst
->sources
; i
++) {
721 if (is_src_duplicate(inst
, i
))
724 if (inst
->src
[i
].file
== VGRF
&&
725 !BITSET_TEST(liveout
[block_idx
], inst
->src
[i
].nr
) &&
726 reads_remaining
[inst
->src
[i
].nr
] == 1)
727 benefit
+= v
->alloc
.sizes
[inst
->src
[i
].nr
];
729 if (inst
->src
[i
].file
== FIXED_GRF
&&
730 inst
->src
[i
].nr
< hw_reg_count
) {
731 for (unsigned off
= 0; off
< regs_read(inst
, i
); off
++) {
732 int reg
= inst
->src
[i
].nr
+ off
;
733 if (!BITSET_TEST(hw_liveout
[block_idx
], reg
) &&
734 hw_reads_remaining
[reg
] == 1) {
744 class vec4_instruction_scheduler
: public instruction_scheduler
747 vec4_instruction_scheduler(vec4_visitor
*v
, int grf_count
);
748 void calculate_deps();
749 schedule_node
*choose_instruction_to_schedule();
750 int issue_time(backend_instruction
*inst
);
753 void count_reads_remaining(backend_instruction
*inst
);
754 void setup_liveness(cfg_t
*cfg
);
755 void update_register_pressure(backend_instruction
*inst
);
756 int get_register_pressure_benefit(backend_instruction
*inst
);
759 vec4_instruction_scheduler::vec4_instruction_scheduler(vec4_visitor
*v
,
761 : instruction_scheduler(v
, grf_count
, 0, 0, SCHEDULE_POST
),
767 vec4_instruction_scheduler::count_reads_remaining(backend_instruction
*)
772 vec4_instruction_scheduler::setup_liveness(cfg_t
*)
777 vec4_instruction_scheduler::update_register_pressure(backend_instruction
*)
782 vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*)
787 schedule_node::schedule_node(backend_instruction
*inst
,
788 instruction_scheduler
*sched
)
790 const struct gen_device_info
*devinfo
= sched
->bs
->devinfo
;
793 this->child_array_size
= 0;
794 this->children
= NULL
;
795 this->child_latency
= NULL
;
796 this->child_count
= 0;
797 this->parent_count
= 0;
798 this->unblocked_time
= 0;
799 this->cand_generation
= 0;
803 /* We can't measure Gen6 timings directly but expect them to be much
804 * closer to Gen7 than Gen4.
806 if (!sched
->post_reg_alloc
)
808 else if (devinfo
->gen
>= 6)
809 set_latency_gen7(devinfo
->is_haswell
);
815 instruction_scheduler::add_insts_from_block(bblock_t
*block
)
817 foreach_inst_in_block(backend_instruction
, inst
, block
) {
818 schedule_node
*n
= new(mem_ctx
) schedule_node(inst
, this);
820 instructions
.push_tail(n
);
823 this->instructions_to_schedule
= block
->end_ip
- block
->start_ip
+ 1;
826 /** Computation of the delay member of each node. */
828 instruction_scheduler::compute_delays()
830 foreach_in_list_reverse(schedule_node
, n
, &instructions
) {
831 if (!n
->child_count
) {
832 n
->delay
= issue_time(n
->inst
);
834 for (int i
= 0; i
< n
->child_count
; i
++) {
835 assert(n
->children
[i
]->delay
);
836 n
->delay
= MAX2(n
->delay
, n
->latency
+ n
->children
[i
]->delay
);
843 instruction_scheduler::compute_exits()
845 /* Calculate a lower bound of the scheduling time of each node in the
846 * graph. This is analogous to the node's critical path but calculated
847 * from the top instead of from the bottom of the block.
849 foreach_in_list(schedule_node
, n
, &instructions
) {
850 for (int i
= 0; i
< n
->child_count
; i
++) {
851 n
->children
[i
]->unblocked_time
=
852 MAX2(n
->children
[i
]->unblocked_time
,
853 n
->unblocked_time
+ issue_time(n
->inst
) + n
->child_latency
[i
]);
857 /* Calculate the exit of each node by induction based on the exit nodes of
858 * its children. The preferred exit of a node is the one among the exit
859 * nodes of its children which can be unblocked first according to the
860 * optimistic unblocked time estimate calculated above.
862 foreach_in_list_reverse(schedule_node
, n
, &instructions
) {
863 n
->exit
= (n
->inst
->opcode
== FS_OPCODE_DISCARD_JUMP
? n
: NULL
);
865 for (int i
= 0; i
< n
->child_count
; i
++) {
866 if (exit_unblocked_time(n
->children
[i
]) < exit_unblocked_time(n
))
867 n
->exit
= n
->children
[i
]->exit
;
873 * Add a dependency between two instruction nodes.
875 * The @after node will be scheduled after @before. We will try to
876 * schedule it @latency cycles after @before, but no guarantees there.
879 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
,
882 if (!before
|| !after
)
885 assert(before
!= after
);
887 for (int i
= 0; i
< before
->child_count
; i
++) {
888 if (before
->children
[i
] == after
) {
889 before
->child_latency
[i
] = MAX2(before
->child_latency
[i
], latency
);
894 if (before
->child_array_size
<= before
->child_count
) {
895 if (before
->child_array_size
< 16)
896 before
->child_array_size
= 16;
898 before
->child_array_size
*= 2;
900 before
->children
= reralloc(mem_ctx
, before
->children
,
902 before
->child_array_size
);
903 before
->child_latency
= reralloc(mem_ctx
, before
->child_latency
,
904 int, before
->child_array_size
);
907 before
->children
[before
->child_count
] = after
;
908 before
->child_latency
[before
->child_count
] = latency
;
909 before
->child_count
++;
910 after
->parent_count
++;
914 instruction_scheduler::add_dep(schedule_node
*before
, schedule_node
*after
)
919 add_dep(before
, after
, before
->latency
);
923 is_scheduling_barrier(const backend_instruction
*inst
)
925 return inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
||
926 inst
->is_control_flow() ||
927 inst
->has_side_effects();
931 * Sometimes we really want this node to execute after everything that
932 * was before it and before everything that followed it. This adds
936 instruction_scheduler::add_barrier_deps(schedule_node
*n
)
938 schedule_node
*prev
= (schedule_node
*)n
->prev
;
939 schedule_node
*next
= (schedule_node
*)n
->next
;
942 while (!prev
->is_head_sentinel()) {
944 if (is_scheduling_barrier(prev
->inst
))
946 prev
= (schedule_node
*)prev
->prev
;
951 while (!next
->is_tail_sentinel()) {
953 if (is_scheduling_barrier(next
->inst
))
955 next
= (schedule_node
*)next
->next
;
960 /* instruction scheduling needs to be aware of when an MRF write
961 * actually writes 2 MRFs.
964 fs_instruction_scheduler::is_compressed(fs_inst
*inst
)
966 return inst
->exec_size
== 16;
970 fs_instruction_scheduler::calculate_deps()
972 /* Pre-register-allocation, this tracks the last write per VGRF offset.
973 * After register allocation, reg_offsets are gone and we track individual
976 schedule_node
**last_grf_write
;
977 schedule_node
*last_mrf_write
[BRW_MAX_MRF(v
->devinfo
->gen
)];
978 schedule_node
*last_conditional_mod
[8] = {};
979 schedule_node
*last_accumulator_write
= NULL
;
980 /* Fixed HW registers are assumed to be separate from the virtual
981 * GRFs, so they can be tracked separately. We don't really write
982 * to fixed GRFs much, so don't bother tracking them on a more
985 schedule_node
*last_fixed_grf_write
= NULL
;
987 last_grf_write
= (schedule_node
**)calloc(sizeof(schedule_node
*), grf_count
* 16);
988 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
990 /* top-to-bottom dependencies: RAW and WAW. */
991 foreach_in_list(schedule_node
, n
, &instructions
) {
992 fs_inst
*inst
= (fs_inst
*)n
->inst
;
994 if (is_scheduling_barrier(inst
))
997 /* read-after-write deps. */
998 for (int i
= 0; i
< inst
->sources
; i
++) {
999 if (inst
->src
[i
].file
== VGRF
) {
1000 if (post_reg_alloc
) {
1001 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1002 add_dep(last_grf_write
[inst
->src
[i
].nr
+ r
], n
);
1004 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++) {
1005 add_dep(last_grf_write
[inst
->src
[i
].nr
* 16 +
1006 inst
->src
[i
].offset
/ REG_SIZE
+ r
], n
);
1009 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1010 if (post_reg_alloc
) {
1011 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1012 add_dep(last_grf_write
[inst
->src
[i
].nr
+ r
], n
);
1014 add_dep(last_fixed_grf_write
, n
);
1016 } else if (inst
->src
[i
].is_accumulator()) {
1017 add_dep(last_accumulator_write
, n
);
1018 } else if (inst
->src
[i
].file
== ARF
) {
1019 add_barrier_deps(n
);
1023 if (inst
->base_mrf
!= -1) {
1024 for (int i
= 0; i
< inst
->mlen
; i
++) {
1025 /* It looks like the MRF regs are released in the send
1026 * instruction once it's sent, not when the result comes
1029 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1033 if (const unsigned mask
= inst
->flags_read(v
->devinfo
)) {
1034 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1036 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1037 if (mask
& (1 << i
))
1038 add_dep(last_conditional_mod
[i
], n
);
1042 if (inst
->reads_accumulator_implicitly()) {
1043 add_dep(last_accumulator_write
, n
);
1046 /* write-after-write deps. */
1047 if (inst
->dst
.file
== VGRF
) {
1048 if (post_reg_alloc
) {
1049 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1050 add_dep(last_grf_write
[inst
->dst
.nr
+ r
], n
);
1051 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1054 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1055 add_dep(last_grf_write
[inst
->dst
.nr
* 16 +
1056 inst
->dst
.offset
/ REG_SIZE
+ r
], n
);
1057 last_grf_write
[inst
->dst
.nr
* 16 +
1058 inst
->dst
.offset
/ REG_SIZE
+ r
] = n
;
1061 } else if (inst
->dst
.file
== MRF
) {
1062 int reg
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
1064 add_dep(last_mrf_write
[reg
], n
);
1065 last_mrf_write
[reg
] = n
;
1066 if (is_compressed(inst
)) {
1067 if (inst
->dst
.nr
& BRW_MRF_COMPR4
)
1071 add_dep(last_mrf_write
[reg
], n
);
1072 last_mrf_write
[reg
] = n
;
1074 } else if (inst
->dst
.file
== FIXED_GRF
) {
1075 if (post_reg_alloc
) {
1076 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1077 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1079 last_fixed_grf_write
= n
;
1081 } else if (inst
->dst
.is_accumulator()) {
1082 add_dep(last_accumulator_write
, n
);
1083 last_accumulator_write
= n
;
1084 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1085 add_barrier_deps(n
);
1088 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
1089 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1090 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1091 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1095 if (const unsigned mask
= inst
->flags_written()) {
1096 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1098 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1099 if (mask
& (1 << i
)) {
1100 add_dep(last_conditional_mod
[i
], n
, 0);
1101 last_conditional_mod
[i
] = n
;
1106 if (inst
->writes_accumulator_implicitly(v
->devinfo
) &&
1107 !inst
->dst
.is_accumulator()) {
1108 add_dep(last_accumulator_write
, n
);
1109 last_accumulator_write
= n
;
1113 /* bottom-to-top dependencies: WAR */
1114 memset(last_grf_write
, 0, sizeof(schedule_node
*) * grf_count
* 16);
1115 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1116 memset(last_conditional_mod
, 0, sizeof(last_conditional_mod
));
1117 last_accumulator_write
= NULL
;
1118 last_fixed_grf_write
= NULL
;
1120 foreach_in_list_reverse_safe(schedule_node
, n
, &instructions
) {
1121 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1123 /* write-after-read deps. */
1124 for (int i
= 0; i
< inst
->sources
; i
++) {
1125 if (inst
->src
[i
].file
== VGRF
) {
1126 if (post_reg_alloc
) {
1127 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1128 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ r
], 0);
1130 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++) {
1131 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
* 16 +
1132 inst
->src
[i
].offset
/ REG_SIZE
+ r
], 0);
1135 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1136 if (post_reg_alloc
) {
1137 for (unsigned r
= 0; r
< regs_read(inst
, i
); r
++)
1138 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ r
], 0);
1140 add_dep(n
, last_fixed_grf_write
, 0);
1142 } else if (inst
->src
[i
].is_accumulator()) {
1143 add_dep(n
, last_accumulator_write
, 0);
1144 } else if (inst
->src
[i
].file
== ARF
) {
1145 add_barrier_deps(n
);
1149 if (inst
->base_mrf
!= -1) {
1150 for (int i
= 0; i
< inst
->mlen
; i
++) {
1151 /* It looks like the MRF regs are released in the send
1152 * instruction once it's sent, not when the result comes
1155 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1159 if (const unsigned mask
= inst
->flags_read(v
->devinfo
)) {
1160 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1162 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1163 if (mask
& (1 << i
))
1164 add_dep(n
, last_conditional_mod
[i
]);
1168 if (inst
->reads_accumulator_implicitly()) {
1169 add_dep(n
, last_accumulator_write
);
1172 /* Update the things this instruction wrote, so earlier reads
1173 * can mark this as WAR dependency.
1175 if (inst
->dst
.file
== VGRF
) {
1176 if (post_reg_alloc
) {
1177 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1178 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1180 for (unsigned r
= 0; r
< regs_written(inst
); r
++) {
1181 last_grf_write
[inst
->dst
.nr
* 16 +
1182 inst
->dst
.offset
/ REG_SIZE
+ r
] = n
;
1185 } else if (inst
->dst
.file
== MRF
) {
1186 int reg
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
1188 last_mrf_write
[reg
] = n
;
1190 if (is_compressed(inst
)) {
1191 if (inst
->dst
.nr
& BRW_MRF_COMPR4
)
1196 last_mrf_write
[reg
] = n
;
1198 } else if (inst
->dst
.file
== FIXED_GRF
) {
1199 if (post_reg_alloc
) {
1200 for (unsigned r
= 0; r
< regs_written(inst
); r
++)
1201 last_grf_write
[inst
->dst
.nr
+ r
] = n
;
1203 last_fixed_grf_write
= n
;
1205 } else if (inst
->dst
.is_accumulator()) {
1206 last_accumulator_write
= n
;
1207 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1208 add_barrier_deps(n
);
1211 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
1212 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1213 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1217 if (const unsigned mask
= inst
->flags_written()) {
1218 assert(mask
< (1 << ARRAY_SIZE(last_conditional_mod
)));
1220 for (unsigned i
= 0; i
< ARRAY_SIZE(last_conditional_mod
); i
++) {
1221 if (mask
& (1 << i
))
1222 last_conditional_mod
[i
] = n
;
1226 if (inst
->writes_accumulator_implicitly(v
->devinfo
)) {
1227 last_accumulator_write
= n
;
1231 free(last_grf_write
);
1235 vec4_instruction_scheduler::calculate_deps()
1237 schedule_node
*last_grf_write
[grf_count
];
1238 schedule_node
*last_mrf_write
[BRW_MAX_MRF(v
->devinfo
->gen
)];
1239 schedule_node
*last_conditional_mod
= NULL
;
1240 schedule_node
*last_accumulator_write
= NULL
;
1241 /* Fixed HW registers are assumed to be separate from the virtual
1242 * GRFs, so they can be tracked separately. We don't really write
1243 * to fixed GRFs much, so don't bother tracking them on a more
1246 schedule_node
*last_fixed_grf_write
= NULL
;
1248 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1249 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1251 /* top-to-bottom dependencies: RAW and WAW. */
1252 foreach_in_list(schedule_node
, n
, &instructions
) {
1253 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1255 if (is_scheduling_barrier(inst
))
1256 add_barrier_deps(n
);
1258 /* read-after-write deps. */
1259 for (int i
= 0; i
< 3; i
++) {
1260 if (inst
->src
[i
].file
== VGRF
) {
1261 for (unsigned j
= 0; j
< regs_read(inst
, i
); ++j
)
1262 add_dep(last_grf_write
[inst
->src
[i
].nr
+ j
], n
);
1263 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1264 add_dep(last_fixed_grf_write
, n
);
1265 } else if (inst
->src
[i
].is_accumulator()) {
1266 assert(last_accumulator_write
);
1267 add_dep(last_accumulator_write
, n
);
1268 } else if (inst
->src
[i
].file
== ARF
) {
1269 add_barrier_deps(n
);
1273 if (inst
->reads_g0_implicitly())
1274 add_dep(last_fixed_grf_write
, n
);
1276 if (!inst
->is_send_from_grf()) {
1277 for (int i
= 0; i
< inst
->mlen
; i
++) {
1278 /* It looks like the MRF regs are released in the send
1279 * instruction once it's sent, not when the result comes
1282 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1286 if (inst
->reads_flag()) {
1287 assert(last_conditional_mod
);
1288 add_dep(last_conditional_mod
, n
);
1291 if (inst
->reads_accumulator_implicitly()) {
1292 assert(last_accumulator_write
);
1293 add_dep(last_accumulator_write
, n
);
1296 /* write-after-write deps. */
1297 if (inst
->dst
.file
== VGRF
) {
1298 for (unsigned j
= 0; j
< regs_written(inst
); ++j
) {
1299 add_dep(last_grf_write
[inst
->dst
.nr
+ j
], n
);
1300 last_grf_write
[inst
->dst
.nr
+ j
] = n
;
1302 } else if (inst
->dst
.file
== MRF
) {
1303 add_dep(last_mrf_write
[inst
->dst
.nr
], n
);
1304 last_mrf_write
[inst
->dst
.nr
] = n
;
1305 } else if (inst
->dst
.file
== FIXED_GRF
) {
1306 last_fixed_grf_write
= n
;
1307 } else if (inst
->dst
.is_accumulator()) {
1308 add_dep(last_accumulator_write
, n
);
1309 last_accumulator_write
= n
;
1310 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1311 add_barrier_deps(n
);
1314 if (inst
->mlen
> 0 && !inst
->is_send_from_grf()) {
1315 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1316 add_dep(last_mrf_write
[inst
->base_mrf
+ i
], n
);
1317 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1321 if (inst
->writes_flag()) {
1322 add_dep(last_conditional_mod
, n
, 0);
1323 last_conditional_mod
= n
;
1326 if (inst
->writes_accumulator_implicitly(v
->devinfo
) &&
1327 !inst
->dst
.is_accumulator()) {
1328 add_dep(last_accumulator_write
, n
);
1329 last_accumulator_write
= n
;
1333 /* bottom-to-top dependencies: WAR */
1334 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1335 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1336 last_conditional_mod
= NULL
;
1337 last_accumulator_write
= NULL
;
1338 last_fixed_grf_write
= NULL
;
1340 foreach_in_list_reverse_safe(schedule_node
, n
, &instructions
) {
1341 vec4_instruction
*inst
= (vec4_instruction
*)n
->inst
;
1343 /* write-after-read deps. */
1344 for (int i
= 0; i
< 3; i
++) {
1345 if (inst
->src
[i
].file
== VGRF
) {
1346 for (unsigned j
= 0; j
< regs_read(inst
, i
); ++j
)
1347 add_dep(n
, last_grf_write
[inst
->src
[i
].nr
+ j
]);
1348 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1349 add_dep(n
, last_fixed_grf_write
);
1350 } else if (inst
->src
[i
].is_accumulator()) {
1351 add_dep(n
, last_accumulator_write
);
1352 } else if (inst
->src
[i
].file
== ARF
) {
1353 add_barrier_deps(n
);
1357 if (!inst
->is_send_from_grf()) {
1358 for (int i
= 0; i
< inst
->mlen
; i
++) {
1359 /* It looks like the MRF regs are released in the send
1360 * instruction once it's sent, not when the result comes
1363 add_dep(n
, last_mrf_write
[inst
->base_mrf
+ i
], 2);
1367 if (inst
->reads_flag()) {
1368 add_dep(n
, last_conditional_mod
);
1371 if (inst
->reads_accumulator_implicitly()) {
1372 add_dep(n
, last_accumulator_write
);
1375 /* Update the things this instruction wrote, so earlier reads
1376 * can mark this as WAR dependency.
1378 if (inst
->dst
.file
== VGRF
) {
1379 for (unsigned j
= 0; j
< regs_written(inst
); ++j
)
1380 last_grf_write
[inst
->dst
.nr
+ j
] = n
;
1381 } else if (inst
->dst
.file
== MRF
) {
1382 last_mrf_write
[inst
->dst
.nr
] = n
;
1383 } else if (inst
->dst
.file
== FIXED_GRF
) {
1384 last_fixed_grf_write
= n
;
1385 } else if (inst
->dst
.is_accumulator()) {
1386 last_accumulator_write
= n
;
1387 } else if (inst
->dst
.file
== ARF
&& !inst
->dst
.is_null()) {
1388 add_barrier_deps(n
);
1391 if (inst
->mlen
> 0 && !inst
->is_send_from_grf()) {
1392 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
1393 last_mrf_write
[inst
->base_mrf
+ i
] = n
;
1397 if (inst
->writes_flag()) {
1398 last_conditional_mod
= n
;
1401 if (inst
->writes_accumulator_implicitly(v
->devinfo
)) {
1402 last_accumulator_write
= n
;
1408 fs_instruction_scheduler::choose_instruction_to_schedule()
1410 schedule_node
*chosen
= NULL
;
1412 if (mode
== SCHEDULE_PRE
|| mode
== SCHEDULE_POST
) {
1413 int chosen_time
= 0;
1415 /* Of the instructions ready to execute or the closest to being ready,
1416 * choose the one most likely to unblock an early program exit, or
1417 * otherwise the oldest one.
1419 foreach_in_list(schedule_node
, n
, &instructions
) {
1421 exit_unblocked_time(n
) < exit_unblocked_time(chosen
) ||
1422 (exit_unblocked_time(n
) == exit_unblocked_time(chosen
) &&
1423 n
->unblocked_time
< chosen_time
)) {
1425 chosen_time
= n
->unblocked_time
;
1429 /* Before register allocation, we don't care about the latencies of
1430 * instructions. All we care about is reducing live intervals of
1431 * variables so that we can avoid register spilling, or get SIMD16
1432 * shaders which naturally do a better job of hiding instruction
1435 foreach_in_list(schedule_node
, n
, &instructions
) {
1436 fs_inst
*inst
= (fs_inst
*)n
->inst
;
1443 /* Most important: If we can definitely reduce register pressure, do
1446 int register_pressure_benefit
= get_register_pressure_benefit(n
->inst
);
1447 int chosen_register_pressure_benefit
=
1448 get_register_pressure_benefit(chosen
->inst
);
1450 if (register_pressure_benefit
> 0 &&
1451 register_pressure_benefit
> chosen_register_pressure_benefit
) {
1454 } else if (chosen_register_pressure_benefit
> 0 &&
1455 (register_pressure_benefit
<
1456 chosen_register_pressure_benefit
)) {
1460 if (mode
== SCHEDULE_PRE_LIFO
) {
1461 /* Prefer instructions that recently became available for
1462 * scheduling. These are the things that are most likely to
1463 * (eventually) make a variable dead and reduce register pressure.
1464 * Typical register pressure estimates don't work for us because
1465 * most of our pressure comes from texturing, where no single
1466 * instruction to schedule will make a vec4 value dead.
1468 if (n
->cand_generation
> chosen
->cand_generation
) {
1471 } else if (n
->cand_generation
< chosen
->cand_generation
) {
1475 /* On MRF-using chips, prefer non-SEND instructions. If we don't
1476 * do this, then because we prefer instructions that just became
1477 * candidates, we'll end up in a pattern of scheduling a SEND,
1478 * then the MRFs for the next SEND, then the next SEND, then the
1479 * MRFs, etc., without ever consuming the results of a send.
1481 if (v
->devinfo
->gen
< 7) {
1482 fs_inst
*chosen_inst
= (fs_inst
*)chosen
->inst
;
1484 /* We use size_written > 4 * exec_size as our test for the kind
1485 * of send instruction to avoid -- only sends generate many
1486 * regs, and a single-result send is probably actually reducing
1487 * register pressure.
1489 if (inst
->size_written
<= 4 * inst
->exec_size
&&
1490 chosen_inst
->size_written
> 4 * chosen_inst
->exec_size
) {
1493 } else if (inst
->size_written
> chosen_inst
->size_written
) {
1499 /* For instructions pushed on the cands list at the same time, prefer
1500 * the one with the highest delay to the end of the program. This is
1501 * most likely to have its values able to be consumed first (such as
1502 * for a large tree of lowered ubo loads, which appear reversed in
1503 * the instruction stream with respect to when they can be consumed).
1505 if (n
->delay
> chosen
->delay
) {
1508 } else if (n
->delay
< chosen
->delay
) {
1512 /* Prefer the node most likely to unblock an early program exit.
1514 if (exit_unblocked_time(n
) < exit_unblocked_time(chosen
)) {
1517 } else if (exit_unblocked_time(n
) > exit_unblocked_time(chosen
)) {
1521 /* If all other metrics are equal, we prefer the first instruction in
1522 * the list (program execution).
1531 vec4_instruction_scheduler::choose_instruction_to_schedule()
1533 schedule_node
*chosen
= NULL
;
1534 int chosen_time
= 0;
1536 /* Of the instructions ready to execute or the closest to being ready,
1537 * choose the oldest one.
1539 foreach_in_list(schedule_node
, n
, &instructions
) {
1540 if (!chosen
|| n
->unblocked_time
< chosen_time
) {
1542 chosen_time
= n
->unblocked_time
;
1550 fs_instruction_scheduler::issue_time(backend_instruction
*inst
)
1552 const unsigned overhead
= v
->bank_conflict_cycles((fs_inst
*)inst
);
1553 if (is_compressed((fs_inst
*)inst
))
1554 return 4 + overhead
;
1556 return 2 + overhead
;
1560 vec4_instruction_scheduler::issue_time(backend_instruction
*)
1562 /* We always execute as two vec4s in parallel. */
1567 instruction_scheduler::schedule_instructions(bblock_t
*block
)
1569 const struct gen_device_info
*devinfo
= bs
->devinfo
;
1571 if (!post_reg_alloc
)
1572 reg_pressure
= reg_pressure_in
[block
->num
];
1573 block_idx
= block
->num
;
1575 /* Remove non-DAG heads from the list. */
1576 foreach_in_list_safe(schedule_node
, n
, &instructions
) {
1577 if (n
->parent_count
!= 0)
1581 unsigned cand_generation
= 1;
1582 while (!instructions
.is_empty()) {
1583 schedule_node
*chosen
= choose_instruction_to_schedule();
1585 /* Schedule this instruction. */
1588 chosen
->inst
->exec_node::remove();
1589 block
->instructions
.push_tail(chosen
->inst
);
1590 instructions_to_schedule
--;
1592 if (!post_reg_alloc
) {
1593 reg_pressure
-= get_register_pressure_benefit(chosen
->inst
);
1594 update_register_pressure(chosen
->inst
);
1597 /* If we expected a delay for scheduling, then bump the clock to reflect
1598 * that. In reality, the hardware will switch to another hyperthread
1599 * and may not return to dispatching our thread for a while even after
1600 * we're unblocked. After this, we have the time when the chosen
1601 * instruction will start executing.
1603 time
= MAX2(time
, chosen
->unblocked_time
);
1605 /* Update the clock for how soon an instruction could start after the
1608 time
+= issue_time(chosen
->inst
);
1611 fprintf(stderr
, "clock %4d, scheduled: ", time
);
1612 bs
->dump_instruction(chosen
->inst
);
1613 if (!post_reg_alloc
)
1614 fprintf(stderr
, "(register pressure %d)\n", reg_pressure
);
1617 /* Now that we've scheduled a new instruction, some of its
1618 * children can be promoted to the list of instructions ready to
1619 * be scheduled. Update the children's unblocked time for this
1620 * DAG edge as we do so.
1622 for (int i
= chosen
->child_count
- 1; i
>= 0; i
--) {
1623 schedule_node
*child
= chosen
->children
[i
];
1625 child
->unblocked_time
= MAX2(child
->unblocked_time
,
1626 time
+ chosen
->child_latency
[i
]);
1629 fprintf(stderr
, "\tchild %d, %d parents: ", i
, child
->parent_count
);
1630 bs
->dump_instruction(child
->inst
);
1633 child
->cand_generation
= cand_generation
;
1634 child
->parent_count
--;
1635 if (child
->parent_count
== 0) {
1637 fprintf(stderr
, "\t\tnow available\n");
1639 instructions
.push_head(child
);
1644 /* Shared resource: the mathbox. There's one mathbox per EU on Gen6+
1645 * but it's more limited pre-gen6, so if we send something off to it then
1646 * the next math instruction isn't going to make progress until the first
1649 if (devinfo
->gen
< 6 && chosen
->inst
->is_math()) {
1650 foreach_in_list(schedule_node
, n
, &instructions
) {
1651 if (n
->inst
->is_math())
1652 n
->unblocked_time
= MAX2(n
->unblocked_time
,
1653 time
+ chosen
->latency
);
1658 assert(instructions_to_schedule
== 0);
1660 block
->cycle_count
= time
;
1663 static unsigned get_cycle_count(cfg_t
*cfg
)
1665 unsigned count
= 0, multiplier
= 1;
1666 foreach_block(block
, cfg
) {
1667 if (block
->start()->opcode
== BRW_OPCODE_DO
)
1668 multiplier
*= 10; /* assume that loops execute ~10 times */
1670 count
+= block
->cycle_count
* multiplier
;
1672 if (block
->end()->opcode
== BRW_OPCODE_WHILE
)
1680 instruction_scheduler::run(cfg_t
*cfg
)
1682 if (debug
&& !post_reg_alloc
) {
1683 fprintf(stderr
, "\nInstructions before scheduling (reg_alloc %d)\n",
1685 bs
->dump_instructions();
1688 if (!post_reg_alloc
)
1689 setup_liveness(cfg
);
1691 foreach_block(block
, cfg
) {
1692 if (reads_remaining
) {
1693 memset(reads_remaining
, 0,
1694 grf_count
* sizeof(*reads_remaining
));
1695 memset(hw_reads_remaining
, 0,
1696 hw_reg_count
* sizeof(*hw_reads_remaining
));
1697 memset(written
, 0, grf_count
* sizeof(*written
));
1699 foreach_inst_in_block(fs_inst
, inst
, block
)
1700 count_reads_remaining(inst
);
1703 add_insts_from_block(block
);
1710 schedule_instructions(block
);
1713 if (debug
&& !post_reg_alloc
) {
1714 fprintf(stderr
, "\nInstructions after scheduling (reg_alloc %d)\n",
1716 bs
->dump_instructions();
1719 cfg
->cycle_count
= get_cycle_count(cfg
);
1723 fs_visitor::schedule_instructions(instruction_scheduler_mode mode
)
1725 if (mode
!= SCHEDULE_POST
)
1726 calculate_live_intervals();
1729 if (mode
== SCHEDULE_POST
)
1730 grf_count
= grf_used
;
1732 grf_count
= alloc
.count
;
1734 fs_instruction_scheduler
sched(this, grf_count
, first_non_payload_grf
,
1735 cfg
->num_blocks
, mode
);
1738 invalidate_live_intervals();
1742 vec4_visitor::opt_schedule_instructions()
1744 vec4_instruction_scheduler
sched(this, prog_data
->total_grf
);
1747 invalidate_live_intervals();