src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "dev/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_INT8:
  48       return BRW_REGISTER_TYPE_B;
  49    case GLSL_TYPE_UINT:
  50       return BRW_REGISTER_TYPE_UD;
  51    case GLSL_TYPE_UINT16:
  52       return BRW_REGISTER_TYPE_UW;
  53    case GLSL_TYPE_UINT8:
  54       return BRW_REGISTER_TYPE_UB;
  55    case GLSL_TYPE_ARRAY:
  56       return brw_type_for_base_type(type->fields.array);
  57    case GLSL_TYPE_STRUCT:
  58    case GLSL_TYPE_INTERFACE:
  59    case GLSL_TYPE_SAMPLER:
  60    case GLSL_TYPE_ATOMIC_UINT:
  61       /* These should be overridden with the type of the member when
  62        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  63        * way to trip up if we don't.
  64        */
  65       return BRW_REGISTER_TYPE_UD;
  66    case GLSL_TYPE_IMAGE:
  67       return BRW_REGISTER_TYPE_UD;
  68    case GLSL_TYPE_DOUBLE:
  69       return BRW_REGISTER_TYPE_DF;
  70    case GLSL_TYPE_UINT64:
  71       return BRW_REGISTER_TYPE_UQ;
  72    case GLSL_TYPE_INT64:
  73       return BRW_REGISTER_TYPE_Q;
  74    case GLSL_TYPE_VOID:
  75    case GLSL_TYPE_ERROR:
  76    case GLSL_TYPE_FUNCTION:
  77       unreachable("not reached");
  78    }
  79
  80    return BRW_REGISTER_TYPE_F;
  81 }
  82
  83 enum brw_conditional_mod
  84 brw_conditional_for_comparison(unsigned int op)
  85 {
  86    switch (op) {
  87    case ir_binop_less:
  88       return BRW_CONDITIONAL_L;
  89    case ir_binop_gequal:
  90       return BRW_CONDITIONAL_GE;
  91    case ir_binop_equal:
  92    case ir_binop_all_equal: /* same as equal for scalars */
  93       return BRW_CONDITIONAL_Z;
  94    case ir_binop_nequal:
  95    case ir_binop_any_nequal: /* same as nequal for scalars */
  96       return BRW_CONDITIONAL_NZ;
  97    default:
  98       unreachable("not reached: bad operation for comparison");
  99    }
 100 }
 101
 102 uint32_t
 103 brw_math_function(enum opcode op)
 104 {
 105    switch (op) {
 106    case SHADER_OPCODE_RCP:
 107       return BRW_MATH_FUNCTION_INV;
 108    case SHADER_OPCODE_RSQ:
 109       return BRW_MATH_FUNCTION_RSQ;
 110    case SHADER_OPCODE_SQRT:
 111       return BRW_MATH_FUNCTION_SQRT;
 112    case SHADER_OPCODE_EXP2:
 113       return BRW_MATH_FUNCTION_EXP;
 114    case SHADER_OPCODE_LOG2:
 115       return BRW_MATH_FUNCTION_LOG;
 116    case SHADER_OPCODE_POW:
 117       return BRW_MATH_FUNCTION_POW;
 118    case SHADER_OPCODE_SIN:
 119       return BRW_MATH_FUNCTION_SIN;
 120    case SHADER_OPCODE_COS:
 121       return BRW_MATH_FUNCTION_COS;
 122    case SHADER_OPCODE_INT_QUOTIENT:
 123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 124    case SHADER_OPCODE_INT_REMAINDER:
 125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 126    default:
 127       unreachable("not reached: unknown math function");
 128    }
 129 }
 130
 131 bool
 132 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 133 {
 134    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 135
 136    /* offset out of bounds; caller will handle it. */
 137    for (unsigned i = 0; i < num_components; i++)
 138       if (offsets[i] > 7 || offsets[i] < -8)
 139          return false;
 140
 141    /* Combine all three offsets into a single unsigned dword:
 142     *
 143     *    bits 11:8 - U Offset (X component)
 144     *    bits  7:4 - V Offset (Y component)
 145     *    bits  3:0 - R Offset (Z component)
 146     */
 147    *offset_bits = 0;
 148    for (unsigned i = 0; i < num_components; i++) {
 149       const unsigned shift = 4 * (2 - i);
 150       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 151    }
 152    return true;
 153 }
 154
 155 const char *
 156 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 157 {
 158    switch (op) {
 159    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 160       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 161        * start of a loop in the IR.
 162        */
 163       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 164          return "do";
 165
 166       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 167        * then to mark that we want to do the conversion.
 168        */
 169       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 170          return "f32to16";
 171
 172       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 173          return "f16to32";
 174
 175       assert(brw_opcode_desc(devinfo, op)->name);
 176       return brw_opcode_desc(devinfo, op)->name;
 177    case FS_OPCODE_FB_WRITE:
 178       return "fb_write";
 179    case FS_OPCODE_FB_WRITE_LOGICAL:
 180       return "fb_write_logical";
 181    case FS_OPCODE_REP_FB_WRITE:
 182       return "rep_fb_write";
 183    case FS_OPCODE_FB_READ:
 184       return "fb_read";
 185    case FS_OPCODE_FB_READ_LOGICAL:
 186       return "fb_read_logical";
 187
 188    case SHADER_OPCODE_RCP:
 189       return "rcp";
 190    case SHADER_OPCODE_RSQ:
 191       return "rsq";
 192    case SHADER_OPCODE_SQRT:
 193       return "sqrt";
 194    case SHADER_OPCODE_EXP2:
 195       return "exp2";
 196    case SHADER_OPCODE_LOG2:
 197       return "log2";
 198    case SHADER_OPCODE_POW:
 199       return "pow";
 200    case SHADER_OPCODE_INT_QUOTIENT:
 201       return "int_quot";
 202    case SHADER_OPCODE_INT_REMAINDER:
 203       return "int_rem";
 204    case SHADER_OPCODE_SIN:
 205       return "sin";
 206    case SHADER_OPCODE_COS:
 207       return "cos";
 208
 209    case SHADER_OPCODE_SEND:
 210       return "send";
 211
 212    case SHADER_OPCODE_TEX:
 213       return "tex";
 214    case SHADER_OPCODE_TEX_LOGICAL:
 215       return "tex_logical";
 216    case SHADER_OPCODE_TXD:
 217       return "txd";
 218    case SHADER_OPCODE_TXD_LOGICAL:
 219       return "txd_logical";
 220    case SHADER_OPCODE_TXF:
 221       return "txf";
 222    case SHADER_OPCODE_TXF_LOGICAL:
 223       return "txf_logical";
 224    case SHADER_OPCODE_TXF_LZ:
 225       return "txf_lz";
 226    case SHADER_OPCODE_TXL:
 227       return "txl";
 228    case SHADER_OPCODE_TXL_LOGICAL:
 229       return "txl_logical";
 230    case SHADER_OPCODE_TXL_LZ:
 231       return "txl_lz";
 232    case SHADER_OPCODE_TXS:
 233       return "txs";
 234    case SHADER_OPCODE_TXS_LOGICAL:
 235       return "txs_logical";
 236    case FS_OPCODE_TXB:
 237       return "txb";
 238    case FS_OPCODE_TXB_LOGICAL:
 239       return "txb_logical";
 240    case SHADER_OPCODE_TXF_CMS:
 241       return "txf_cms";
 242    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 243       return "txf_cms_logical";
 244    case SHADER_OPCODE_TXF_CMS_W:
 245       return "txf_cms_w";
 246    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 247       return "txf_cms_w_logical";
 248    case SHADER_OPCODE_TXF_UMS:
 249       return "txf_ums";
 250    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 251       return "txf_ums_logical";
 252    case SHADER_OPCODE_TXF_MCS:
 253       return "txf_mcs";
 254    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 255       return "txf_mcs_logical";
 256    case SHADER_OPCODE_LOD:
 257       return "lod";
 258    case SHADER_OPCODE_LOD_LOGICAL:
 259       return "lod_logical";
 260    case SHADER_OPCODE_TG4:
 261       return "tg4";
 262    case SHADER_OPCODE_TG4_LOGICAL:
 263       return "tg4_logical";
 264    case SHADER_OPCODE_TG4_OFFSET:
 265       return "tg4_offset";
 266    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 267       return "tg4_offset_logical";
 268    case SHADER_OPCODE_SAMPLEINFO:
 269       return "sampleinfo";
 270    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 271       return "sampleinfo_logical";
 272
 273    case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
 274       return "image_size_logical";
 275
 276    case SHADER_OPCODE_SHADER_TIME_ADD:
 277       return "shader_time_add";
 278
 279    case VEC4_OPCODE_UNTYPED_ATOMIC:
 280       return "untyped_atomic";
 281    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 282       return "untyped_atomic_logical";
 283    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 284       return "untyped_atomic_float_logical";
 285    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
 286       return "untyped_surface_read";
 287    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 288       return "untyped_surface_read_logical";
 289    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
 290       return "untyped_surface_write";
 291    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 292       return "untyped_surface_write_logical";
 293    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
 294       return "a64_untyped_read_logical";
 295    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
 296       return "a64_untyped_write_logical";
 297    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
 298       return "a64_byte_scattered_read_logical";
 299    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
 300       return "a64_byte_scattered_write_logical";
 301    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
 302       return "a64_untyped_atomic_logical";
 303    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 304       return "a64_untyped_atomic_float_logical";
 305    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 306       return "typed_atomic_logical";
 307    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 308       return "typed_surface_read_logical";
 309    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 310       return "typed_surface_write_logical";
 311    case SHADER_OPCODE_MEMORY_FENCE:
 312       return "memory_fence";
 313    case SHADER_OPCODE_INTERLOCK:
 314       /* For an interlock we actually issue a memory fence via sendc. */
 315       return "interlock";
 316
 317    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 318       return "byte_scattered_read_logical";
 319    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 320       return "byte_scattered_write_logical";
 321
 322    case SHADER_OPCODE_LOAD_PAYLOAD:
 323       return "load_payload";
 324    case FS_OPCODE_PACK:
 325       return "pack";
 326
 327    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 328       return "gen4_scratch_read";
 329    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 330       return "gen4_scratch_write";
 331    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 332       return "gen7_scratch_read";
 333    case SHADER_OPCODE_URB_WRITE_SIMD8:
 334       return "gen8_urb_write_simd8";
 335    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 336       return "gen8_urb_write_simd8_per_slot";
 337    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 338       return "gen8_urb_write_simd8_masked";
 339    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 340       return "gen8_urb_write_simd8_masked_per_slot";
 341    case SHADER_OPCODE_URB_READ_SIMD8:
 342       return "urb_read_simd8";
 343    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 344       return "urb_read_simd8_per_slot";
 345
 346    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 347       return "find_live_channel";
 348    case SHADER_OPCODE_BROADCAST:
 349       return "broadcast";
 350    case SHADER_OPCODE_SHUFFLE:
 351       return "shuffle";
 352    case SHADER_OPCODE_SEL_EXEC:
 353       return "sel_exec";
 354    case SHADER_OPCODE_QUAD_SWIZZLE:
 355       return "quad_swizzle";
 356    case SHADER_OPCODE_CLUSTER_BROADCAST:
 357       return "cluster_broadcast";
 358
 359    case SHADER_OPCODE_GET_BUFFER_SIZE:
 360       return "get_buffer_size";
 361
 362    case VEC4_OPCODE_MOV_BYTES:
 363       return "mov_bytes";
 364    case VEC4_OPCODE_PACK_BYTES:
 365       return "pack_bytes";
 366    case VEC4_OPCODE_UNPACK_UNIFORM:
 367       return "unpack_uniform";
 368    case VEC4_OPCODE_DOUBLE_TO_F32:
 369       return "double_to_f32";
 370    case VEC4_OPCODE_DOUBLE_TO_D32:
 371       return "double_to_d32";
 372    case VEC4_OPCODE_DOUBLE_TO_U32:
 373       return "double_to_u32";
 374    case VEC4_OPCODE_TO_DOUBLE:
 375       return "single_to_double";
 376    case VEC4_OPCODE_PICK_LOW_32BIT:
 377       return "pick_low_32bit";
 378    case VEC4_OPCODE_PICK_HIGH_32BIT:
 379       return "pick_high_32bit";
 380    case VEC4_OPCODE_SET_LOW_32BIT:
 381       return "set_low_32bit";
 382    case VEC4_OPCODE_SET_HIGH_32BIT:
 383       return "set_high_32bit";
 384
 385    case FS_OPCODE_DDX_COARSE:
 386       return "ddx_coarse";
 387    case FS_OPCODE_DDX_FINE:
 388       return "ddx_fine";
 389    case FS_OPCODE_DDY_COARSE:
 390       return "ddy_coarse";
 391    case FS_OPCODE_DDY_FINE:
 392       return "ddy_fine";
 393
 394    case FS_OPCODE_LINTERP:
 395       return "linterp";
 396
 397    case FS_OPCODE_PIXEL_X:
 398       return "pixel_x";
 399    case FS_OPCODE_PIXEL_Y:
 400       return "pixel_y";
 401
 402    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 403       return "uniform_pull_const";
 404    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 405       return "uniform_pull_const_gen7";
 406    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 407       return "varying_pull_const_gen4";
 408    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 409       return "varying_pull_const_logical";
 410
 411    case FS_OPCODE_DISCARD_JUMP:
 412       return "discard_jump";
 413
 414    case FS_OPCODE_SET_SAMPLE_ID:
 415       return "set_sample_id";
 416
 417    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 418       return "pack_half_2x16_split";
 419
 420    case FS_OPCODE_PLACEHOLDER_HALT:
 421       return "placeholder_halt";
 422
 423    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 424       return "interp_sample";
 425    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 426       return "interp_shared_offset";
 427    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 428       return "interp_per_slot_offset";
 429
 430    case VS_OPCODE_URB_WRITE:
 431       return "vs_urb_write";
 432    case VS_OPCODE_PULL_CONSTANT_LOAD:
 433       return "pull_constant_load";
 434    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 435       return "pull_constant_load_gen7";
 436
 437    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 438       return "set_simd4x2_header_gen9";
 439
 440    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 441       return "unpack_flags_simd4x2";
 442
 443    case GS_OPCODE_URB_WRITE:
 444       return "gs_urb_write";
 445    case GS_OPCODE_URB_WRITE_ALLOCATE:
 446       return "gs_urb_write_allocate";
 447    case GS_OPCODE_THREAD_END:
 448       return "gs_thread_end";
 449    case GS_OPCODE_SET_WRITE_OFFSET:
 450       return "set_write_offset";
 451    case GS_OPCODE_SET_VERTEX_COUNT:
 452       return "set_vertex_count";
 453    case GS_OPCODE_SET_DWORD_2:
 454       return "set_dword_2";
 455    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 456       return "prepare_channel_masks";
 457    case GS_OPCODE_SET_CHANNEL_MASKS:
 458       return "set_channel_masks";
 459    case GS_OPCODE_GET_INSTANCE_ID:
 460       return "get_instance_id";
 461    case GS_OPCODE_FF_SYNC:
 462       return "ff_sync";
 463    case GS_OPCODE_SET_PRIMITIVE_ID:
 464       return "set_primitive_id";
 465    case GS_OPCODE_SVB_WRITE:
 466       return "gs_svb_write";
 467    case GS_OPCODE_SVB_SET_DST_INDEX:
 468       return "gs_svb_set_dst_index";
 469    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 470       return "gs_ff_sync_set_primitives";
 471    case CS_OPCODE_CS_TERMINATE:
 472       return "cs_terminate";
 473    case SHADER_OPCODE_BARRIER:
 474       return "barrier";
 475    case SHADER_OPCODE_MULH:
 476       return "mulh";
 477    case SHADER_OPCODE_MOV_INDIRECT:
 478       return "mov_indirect";
 479
 480    case VEC4_OPCODE_URB_READ:
 481       return "urb_read";
 482    case TCS_OPCODE_GET_INSTANCE_ID:
 483       return "tcs_get_instance_id";
 484    case TCS_OPCODE_URB_WRITE:
 485       return "tcs_urb_write";
 486    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 487       return "tcs_set_input_urb_offsets";
 488    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 489       return "tcs_set_output_urb_offsets";
 490    case TCS_OPCODE_GET_PRIMITIVE_ID:
 491       return "tcs_get_primitive_id";
 492    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 493       return "tcs_create_barrier_header";
 494    case TCS_OPCODE_SRC0_010_IS_ZERO:
 495       return "tcs_src0<0,1,0>_is_zero";
 496    case TCS_OPCODE_RELEASE_INPUT:
 497       return "tcs_release_input";
 498    case TCS_OPCODE_THREAD_END:
 499       return "tcs_thread_end";
 500    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 501       return "tes_create_input_read_header";
 502    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 503       return "tes_add_indirect_urb_offset";
 504    case TES_OPCODE_GET_PRIMITIVE_ID:
 505       return "tes_get_primitive_id";
 506
 507    case SHADER_OPCODE_RND_MODE:
 508       return "rnd_mode";
 509    }
 510
 511    unreachable("not reached");
 512 }
 513
 514 bool
 515 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 516 {
 517    union {
 518       unsigned ud;
 519       int d;
 520       float f;
 521       double df;
 522    } imm, sat_imm = { 0 };
 523
 524    const unsigned size = type_sz(type);
 525
 526    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 527     * irrelevant, so just check the size of the type and copy from/to an
 528     * appropriately sized field.
 529     */
 530    if (size < 8)
 531       imm.ud = reg->ud;
 532    else
 533       imm.df = reg->df;
 534
 535    switch (type) {
 536    case BRW_REGISTER_TYPE_UD:
 537    case BRW_REGISTER_TYPE_D:
 538    case BRW_REGISTER_TYPE_UW:
 539    case BRW_REGISTER_TYPE_W:
 540    case BRW_REGISTER_TYPE_UQ:
 541    case BRW_REGISTER_TYPE_Q:
 542       /* Nothing to do. */
 543       return false;
 544    case BRW_REGISTER_TYPE_F:
 545       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 546       break;
 547    case BRW_REGISTER_TYPE_DF:
 548       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 549       break;
 550    case BRW_REGISTER_TYPE_UB:
 551    case BRW_REGISTER_TYPE_B:
 552       unreachable("no UB/B immediates");
 553    case BRW_REGISTER_TYPE_V:
 554    case BRW_REGISTER_TYPE_UV:
 555    case BRW_REGISTER_TYPE_VF:
 556       unreachable("unimplemented: saturate vector immediate");
 557    case BRW_REGISTER_TYPE_HF:
 558       unreachable("unimplemented: saturate HF immediate");
 559    case BRW_REGISTER_TYPE_NF:
 560       unreachable("no NF immediates");
 561    }
 562
 563    if (size < 8) {
 564       if (imm.ud != sat_imm.ud) {
 565          reg->ud = sat_imm.ud;
 566          return true;
 567       }
 568    } else {
 569       if (imm.df != sat_imm.df) {
 570          reg->df = sat_imm.df;
 571          return true;
 572       }
 573    }
 574    return false;
 575 }
 576
 577 bool
 578 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 579 {
 580    switch (type) {
 581    case BRW_REGISTER_TYPE_D:
 582    case BRW_REGISTER_TYPE_UD:
 583       reg->d = -reg->d;
 584       return true;
 585    case BRW_REGISTER_TYPE_W:
 586    case BRW_REGISTER_TYPE_UW: {
 587       uint16_t value = -(int16_t)reg->ud;
 588       reg->ud = value | (uint32_t)value << 16;
 589       return true;
 590    }
 591    case BRW_REGISTER_TYPE_F:
 592       reg->f = -reg->f;
 593       return true;
 594    case BRW_REGISTER_TYPE_VF:
 595       reg->ud ^= 0x80808080;
 596       return true;
 597    case BRW_REGISTER_TYPE_DF:
 598       reg->df = -reg->df;
 599       return true;
 600    case BRW_REGISTER_TYPE_UQ:
 601    case BRW_REGISTER_TYPE_Q:
 602       reg->d64 = -reg->d64;
 603       return true;
 604    case BRW_REGISTER_TYPE_UB:
 605    case BRW_REGISTER_TYPE_B:
 606       unreachable("no UB/B immediates");
 607    case BRW_REGISTER_TYPE_UV:
 608    case BRW_REGISTER_TYPE_V:
 609       assert(!"unimplemented: negate UV/V immediate");
 610    case BRW_REGISTER_TYPE_HF:
 611       reg->ud ^= 0x80008000;
 612       return true;
 613    case BRW_REGISTER_TYPE_NF:
 614       unreachable("no NF immediates");
 615    }
 616
 617    return false;
 618 }
 619
 620 bool
 621 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 622 {
 623    switch (type) {
 624    case BRW_REGISTER_TYPE_D:
 625       reg->d = abs(reg->d);
 626       return true;
 627    case BRW_REGISTER_TYPE_W: {
 628       uint16_t value = abs((int16_t)reg->ud);
 629       reg->ud = value | (uint32_t)value << 16;
 630       return true;
 631    }
 632    case BRW_REGISTER_TYPE_F:
 633       reg->f = fabsf(reg->f);
 634       return true;
 635    case BRW_REGISTER_TYPE_DF:
 636       reg->df = fabs(reg->df);
 637       return true;
 638    case BRW_REGISTER_TYPE_VF:
 639       reg->ud &= ~0x80808080;
 640       return true;
 641    case BRW_REGISTER_TYPE_Q:
 642       reg->d64 = imaxabs(reg->d64);
 643       return true;
 644    case BRW_REGISTER_TYPE_UB:
 645    case BRW_REGISTER_TYPE_B:
 646       unreachable("no UB/B immediates");
 647    case BRW_REGISTER_TYPE_UQ:
 648    case BRW_REGISTER_TYPE_UD:
 649    case BRW_REGISTER_TYPE_UW:
 650    case BRW_REGISTER_TYPE_UV:
 651       /* Presumably the absolute value modifier on an unsigned source is a
 652        * nop, but it would be nice to confirm.
 653        */
 654       assert(!"unimplemented: abs unsigned immediate");
 655    case BRW_REGISTER_TYPE_V:
 656       assert(!"unimplemented: abs V immediate");
 657    case BRW_REGISTER_TYPE_HF:
 658       reg->ud &= ~0x80008000;
 659       return true;
 660    case BRW_REGISTER_TYPE_NF:
 661       unreachable("no NF immediates");
 662    }
 663
 664    return false;
 665 }
 666
 667 backend_shader::backend_shader(const struct brw_compiler *compiler,
 668                                void *log_data,
 669                                void *mem_ctx,
 670                                const nir_shader *shader,
 671                                struct brw_stage_prog_data *stage_prog_data)
 672    : compiler(compiler),
 673      log_data(log_data),
 674      devinfo(compiler->devinfo),
 675      nir(shader),
 676      stage_prog_data(stage_prog_data),
 677      mem_ctx(mem_ctx),
 678      cfg(NULL),
 679      stage(shader->info.stage)
 680 {
 681    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 682    stage_name = _mesa_shader_stage_to_string(stage);
 683    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 684 }
 685
 686 backend_shader::~backend_shader()
 687 {
 688 }
 689
 690 bool
 691 backend_reg::equals(const backend_reg &r) const
 692 {
 693    return brw_regs_equal(this, &r) && offset == r.offset;
 694 }
 695
 696 bool
 697 backend_reg::negative_equals(const backend_reg &r) const
 698 {
 699    return brw_regs_negative_equal(this, &r) && offset == r.offset;
 700 }
 701
 702 bool
 703 backend_reg::is_zero() const
 704 {
 705    if (file != IMM)
 706       return false;
 707
 708    switch (type) {
 709    case BRW_REGISTER_TYPE_F:
 710       return f == 0;
 711    case BRW_REGISTER_TYPE_DF:
 712       return df == 0;
 713    case BRW_REGISTER_TYPE_D:
 714    case BRW_REGISTER_TYPE_UD:
 715       return d == 0;
 716    case BRW_REGISTER_TYPE_UQ:
 717    case BRW_REGISTER_TYPE_Q:
 718       return u64 == 0;
 719    default:
 720       return false;
 721    }
 722 }
 723
 724 bool
 725 backend_reg::is_one() const
 726 {
 727    if (file != IMM)
 728       return false;
 729
 730    switch (type) {
 731    case BRW_REGISTER_TYPE_F:
 732       return f == 1.0f;
 733    case BRW_REGISTER_TYPE_DF:
 734       return df == 1.0;
 735    case BRW_REGISTER_TYPE_D:
 736    case BRW_REGISTER_TYPE_UD:
 737       return d == 1;
 738    case BRW_REGISTER_TYPE_UQ:
 739    case BRW_REGISTER_TYPE_Q:
 740       return u64 == 1;
 741    default:
 742       return false;
 743    }
 744 }
 745
 746 bool
 747 backend_reg::is_negative_one() const
 748 {
 749    if (file != IMM)
 750       return false;
 751
 752    switch (type) {
 753    case BRW_REGISTER_TYPE_F:
 754       return f == -1.0;
 755    case BRW_REGISTER_TYPE_DF:
 756       return df == -1.0;
 757    case BRW_REGISTER_TYPE_D:
 758       return d == -1;
 759    case BRW_REGISTER_TYPE_Q:
 760       return d64 == -1;
 761    default:
 762       return false;
 763    }
 764 }
 765
 766 bool
 767 backend_reg::is_null() const
 768 {
 769    return file == ARF && nr == BRW_ARF_NULL;
 770 }
 771
 772
 773 bool
 774 backend_reg::is_accumulator() const
 775 {
 776    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 777 }
 778
 779 bool
 780 backend_instruction::is_commutative() const
 781 {
 782    switch (opcode) {
 783    case BRW_OPCODE_AND:
 784    case BRW_OPCODE_OR:
 785    case BRW_OPCODE_XOR:
 786    case BRW_OPCODE_ADD:
 787    case BRW_OPCODE_MUL:
 788    case SHADER_OPCODE_MULH:
 789       return true;
 790    case BRW_OPCODE_SEL:
 791       /* MIN and MAX are commutative. */
 792       if (conditional_mod == BRW_CONDITIONAL_GE ||
 793           conditional_mod == BRW_CONDITIONAL_L) {
 794          return true;
 795       }
 796       /* fallthrough */
 797    default:
 798       return false;
 799    }
 800 }
 801
 802 bool
 803 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 804 {
 805    return ::is_3src(devinfo, opcode);
 806 }
 807
 808 bool
 809 backend_instruction::is_tex() const
 810 {
 811    return (opcode == SHADER_OPCODE_TEX ||
 812            opcode == FS_OPCODE_TXB ||
 813            opcode == SHADER_OPCODE_TXD ||
 814            opcode == SHADER_OPCODE_TXF ||
 815            opcode == SHADER_OPCODE_TXF_LZ ||
 816            opcode == SHADER_OPCODE_TXF_CMS ||
 817            opcode == SHADER_OPCODE_TXF_CMS_W ||
 818            opcode == SHADER_OPCODE_TXF_UMS ||
 819            opcode == SHADER_OPCODE_TXF_MCS ||
 820            opcode == SHADER_OPCODE_TXL ||
 821            opcode == SHADER_OPCODE_TXL_LZ ||
 822            opcode == SHADER_OPCODE_TXS ||
 823            opcode == SHADER_OPCODE_LOD ||
 824            opcode == SHADER_OPCODE_TG4 ||
 825            opcode == SHADER_OPCODE_TG4_OFFSET ||
 826            opcode == SHADER_OPCODE_SAMPLEINFO);
 827 }
 828
 829 bool
 830 backend_instruction::is_math() const
 831 {
 832    return (opcode == SHADER_OPCODE_RCP ||
 833            opcode == SHADER_OPCODE_RSQ ||
 834            opcode == SHADER_OPCODE_SQRT ||
 835            opcode == SHADER_OPCODE_EXP2 ||
 836            opcode == SHADER_OPCODE_LOG2 ||
 837            opcode == SHADER_OPCODE_SIN ||
 838            opcode == SHADER_OPCODE_COS ||
 839            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 840            opcode == SHADER_OPCODE_INT_REMAINDER ||
 841            opcode == SHADER_OPCODE_POW);
 842 }
 843
 844 bool
 845 backend_instruction::is_control_flow() const
 846 {
 847    switch (opcode) {
 848    case BRW_OPCODE_DO:
 849    case BRW_OPCODE_WHILE:
 850    case BRW_OPCODE_IF:
 851    case BRW_OPCODE_ELSE:
 852    case BRW_OPCODE_ENDIF:
 853    case BRW_OPCODE_BREAK:
 854    case BRW_OPCODE_CONTINUE:
 855       return true;
 856    default:
 857       return false;
 858    }
 859 }
 860
 861 bool
 862 backend_instruction::can_do_source_mods() const
 863 {
 864    switch (opcode) {
 865    case BRW_OPCODE_ADDC:
 866    case BRW_OPCODE_BFE:
 867    case BRW_OPCODE_BFI1:
 868    case BRW_OPCODE_BFI2:
 869    case BRW_OPCODE_BFREV:
 870    case BRW_OPCODE_CBIT:
 871    case BRW_OPCODE_FBH:
 872    case BRW_OPCODE_FBL:
 873    case BRW_OPCODE_SUBB:
 874    case SHADER_OPCODE_BROADCAST:
 875    case SHADER_OPCODE_CLUSTER_BROADCAST:
 876    case SHADER_OPCODE_MOV_INDIRECT:
 877       return false;
 878    default:
 879       return true;
 880    }
 881 }
 882
 883 bool
 884 backend_instruction::can_do_saturate() const
 885 {
 886    switch (opcode) {
 887    case BRW_OPCODE_ADD:
 888    case BRW_OPCODE_ASR:
 889    case BRW_OPCODE_AVG:
 890    case BRW_OPCODE_DP2:
 891    case BRW_OPCODE_DP3:
 892    case BRW_OPCODE_DP4:
 893    case BRW_OPCODE_DPH:
 894    case BRW_OPCODE_F16TO32:
 895    case BRW_OPCODE_F32TO16:
 896    case BRW_OPCODE_LINE:
 897    case BRW_OPCODE_LRP:
 898    case BRW_OPCODE_MAC:
 899    case BRW_OPCODE_MAD:
 900    case BRW_OPCODE_MATH:
 901    case BRW_OPCODE_MOV:
 902    case BRW_OPCODE_MUL:
 903    case SHADER_OPCODE_MULH:
 904    case BRW_OPCODE_PLN:
 905    case BRW_OPCODE_RNDD:
 906    case BRW_OPCODE_RNDE:
 907    case BRW_OPCODE_RNDU:
 908    case BRW_OPCODE_RNDZ:
 909    case BRW_OPCODE_SEL:
 910    case BRW_OPCODE_SHL:
 911    case BRW_OPCODE_SHR:
 912    case FS_OPCODE_LINTERP:
 913    case SHADER_OPCODE_COS:
 914    case SHADER_OPCODE_EXP2:
 915    case SHADER_OPCODE_LOG2:
 916    case SHADER_OPCODE_POW:
 917    case SHADER_OPCODE_RCP:
 918    case SHADER_OPCODE_RSQ:
 919    case SHADER_OPCODE_SIN:
 920    case SHADER_OPCODE_SQRT:
 921       return true;
 922    default:
 923       return false;
 924    }
 925 }
 926
 927 bool
 928 backend_instruction::can_do_cmod() const
 929 {
 930    switch (opcode) {
 931    case BRW_OPCODE_ADD:
 932    case BRW_OPCODE_ADDC:
 933    case BRW_OPCODE_AND:
 934    case BRW_OPCODE_ASR:
 935    case BRW_OPCODE_AVG:
 936    case BRW_OPCODE_CMP:
 937    case BRW_OPCODE_CMPN:
 938    case BRW_OPCODE_DP2:
 939    case BRW_OPCODE_DP3:
 940    case BRW_OPCODE_DP4:
 941    case BRW_OPCODE_DPH:
 942    case BRW_OPCODE_F16TO32:
 943    case BRW_OPCODE_F32TO16:
 944    case BRW_OPCODE_FRC:
 945    case BRW_OPCODE_LINE:
 946    case BRW_OPCODE_LRP:
 947    case BRW_OPCODE_LZD:
 948    case BRW_OPCODE_MAC:
 949    case BRW_OPCODE_MACH:
 950    case BRW_OPCODE_MAD:
 951    case BRW_OPCODE_MOV:
 952    case BRW_OPCODE_MUL:
 953    case BRW_OPCODE_NOT:
 954    case BRW_OPCODE_OR:
 955    case BRW_OPCODE_PLN:
 956    case BRW_OPCODE_RNDD:
 957    case BRW_OPCODE_RNDE:
 958    case BRW_OPCODE_RNDU:
 959    case BRW_OPCODE_RNDZ:
 960    case BRW_OPCODE_SAD2:
 961    case BRW_OPCODE_SADA2:
 962    case BRW_OPCODE_SHL:
 963    case BRW_OPCODE_SHR:
 964    case BRW_OPCODE_SUBB:
 965    case BRW_OPCODE_XOR:
 966    case FS_OPCODE_LINTERP:
 967       return true;
 968    default:
 969       return false;
 970    }
 971 }
 972
 973 bool
 974 backend_instruction::reads_accumulator_implicitly() const
 975 {
 976    switch (opcode) {
 977    case BRW_OPCODE_MAC:
 978    case BRW_OPCODE_MACH:
 979    case BRW_OPCODE_SADA2:
 980       return true;
 981    default:
 982       return false;
 983    }
 984 }
 985
 986 bool
 987 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 988 {
 989    return writes_accumulator ||
 990           (devinfo->gen < 6 &&
 991            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 992             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
 993           (opcode == FS_OPCODE_LINTERP &&
 994            (!devinfo->has_pln || devinfo->gen <= 6));
 995 }
 996
 997 bool
 998 backend_instruction::has_side_effects() const
 999 {
1000    switch (opcode) {
1001    case SHADER_OPCODE_SEND:
1002       return send_has_side_effects;
1003
1004    case VEC4_OPCODE_UNTYPED_ATOMIC:
1005    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1006    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1007    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1008    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1009    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1010    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
1011    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
1012    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
1013    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1014    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1015    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1016    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1017    case SHADER_OPCODE_MEMORY_FENCE:
1018    case SHADER_OPCODE_INTERLOCK:
1019    case SHADER_OPCODE_URB_WRITE_SIMD8:
1020    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1021    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1022    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1023    case FS_OPCODE_FB_WRITE:
1024    case FS_OPCODE_FB_WRITE_LOGICAL:
1025    case FS_OPCODE_REP_FB_WRITE:
1026    case SHADER_OPCODE_BARRIER:
1027    case TCS_OPCODE_URB_WRITE:
1028    case TCS_OPCODE_RELEASE_INPUT:
1029    case SHADER_OPCODE_RND_MODE:
1030       return true;
1031    default:
1032       return eot;
1033    }
1034 }
1035
1036 bool
1037 backend_instruction::is_volatile() const
1038 {
1039    switch (opcode) {
1040    case SHADER_OPCODE_SEND:
1041       return send_is_volatile;
1042
1043    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
1044    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1045    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1046    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1047    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
1048    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
1049    case SHADER_OPCODE_URB_READ_SIMD8:
1050    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1051    case VEC4_OPCODE_URB_READ:
1052       return true;
1053    default:
1054       return false;
1055    }
1056 }
1057
1058 #ifndef NDEBUG
1059 static bool
1060 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1061 {
1062    bool found = false;
1063    foreach_inst_in_block (backend_instruction, i, block) {
1064       if (inst == i) {
1065          found = true;
1066       }
1067    }
1068    return found;
1069 }
1070 #endif
1071
1072 static void
1073 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1074 {
1075    for (bblock_t *block_iter = start_block->next();
1076         block_iter;
1077         block_iter = block_iter->next()) {
1078       block_iter->start_ip += ip_adjustment;
1079       block_iter->end_ip += ip_adjustment;
1080    }
1081 }
1082
1083 void
1084 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1085 {
1086    assert(this != inst);
1087
1088    if (!this->is_head_sentinel())
1089       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1090
1091    block->end_ip++;
1092
1093    adjust_later_block_ips(block, 1);
1094
1095    exec_node::insert_after(inst);
1096 }
1097
1098 void
1099 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1100 {
1101    assert(this != inst);
1102
1103    if (!this->is_tail_sentinel())
1104       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1105
1106    block->end_ip++;
1107
1108    adjust_later_block_ips(block, 1);
1109
1110    exec_node::insert_before(inst);
1111 }
1112
1113 void
1114 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1115 {
1116    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1117
1118    unsigned num_inst = list->length();
1119
1120    block->end_ip += num_inst;
1121
1122    adjust_later_block_ips(block, num_inst);
1123
1124    exec_node::insert_before(list);
1125 }
1126
1127 void
1128 backend_instruction::remove(bblock_t *block)
1129 {
1130    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1131
1132    adjust_later_block_ips(block, -1);
1133
1134    if (block->start_ip == block->end_ip) {
1135       block->cfg->remove_block(block);
1136    } else {
1137       block->end_ip--;
1138    }
1139
1140    exec_node::remove();
1141 }
1142
1143 void
1144 backend_shader::dump_instructions()
1145 {
1146    dump_instructions(NULL);
1147 }
1148
1149 void
1150 backend_shader::dump_instructions(const char *name)
1151 {
1152    FILE *file = stderr;
1153    if (name && geteuid() != 0) {
1154       file = fopen(name, "w");
1155       if (!file)
1156          file = stderr;
1157    }
1158
1159    if (cfg) {
1160       int ip = 0;
1161       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1162          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1163             fprintf(file, "%4d: ", ip++);
1164          dump_instruction(inst, file);
1165       }
1166    } else {
1167       int ip = 0;
1168       foreach_in_list(backend_instruction, inst, &instructions) {
1169          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1170             fprintf(file, "%4d: ", ip++);
1171          dump_instruction(inst, file);
1172       }
1173    }
1174
1175    if (file != stderr) {
1176       fclose(file);
1177    }
1178 }
1179
1180 void
1181 backend_shader::calculate_cfg()
1182 {
1183    if (this->cfg)
1184       return;
1185    cfg = new(mem_ctx) cfg_t(&this->instructions);
1186 }
1187
1188 extern "C" const unsigned *
1189 brw_compile_tes(const struct brw_compiler *compiler,
1190                 void *log_data,
1191                 void *mem_ctx,
1192                 const struct brw_tes_prog_key *key,
1193                 const struct brw_vue_map *input_vue_map,
1194                 struct brw_tes_prog_data *prog_data,
1195                 nir_shader *nir,
1196                 struct gl_program *prog,
1197                 int shader_time_index,
1198                 char **error_str)
1199 {
1200    const struct gen_device_info *devinfo = compiler->devinfo;
1201    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1202    const unsigned *assembly;
1203
1204    nir->info.inputs_read = key->inputs_read;
1205    nir->info.patch_inputs_read = key->patch_inputs_read;
1206
1207    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1208    brw_nir_lower_tes_inputs(nir, input_vue_map);
1209    brw_nir_lower_vue_outputs(nir);
1210    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1211
1212    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1213                        nir->info.outputs_written,
1214                        nir->info.separate_shader);
1215
1216    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1217
1218    assert(output_size_bytes >= 1);
1219    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1220       if (error_str)
1221          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1222       return NULL;
1223    }
1224
1225    prog_data->base.clip_distance_mask =
1226       ((1 << nir->info.clip_distance_array_size) - 1);
1227    prog_data->base.cull_distance_mask =
1228       ((1 << nir->info.cull_distance_array_size) - 1) <<
1229       nir->info.clip_distance_array_size;
1230
1231    /* URB entry sizes are stored as a multiple of 64 bytes. */
1232    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1233
1234    /* On Cannonlake software shall not program an allocation size that
1235     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1236     */
1237    if (devinfo->gen == 10 &&
1238        prog_data->base.urb_entry_size % 3 == 0)
1239       prog_data->base.urb_entry_size++;
1240
1241    prog_data->base.urb_read_length = 0;
1242
1243    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1244    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1245                  TESS_SPACING_FRACTIONAL_ODD - 1);
1246    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1247                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1248
1249    prog_data->partitioning =
1250       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1251
1252    switch (nir->info.tess.primitive_mode) {
1253    case GL_QUADS:
1254       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1255       break;
1256    case GL_TRIANGLES:
1257       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1258       break;
1259    case GL_ISOLINES:
1260       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1261       break;
1262    default:
1263       unreachable("invalid domain shader primitive mode");
1264    }
1265
1266    if (nir->info.tess.point_mode) {
1267       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1268    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1269       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1270    } else {
1271       /* Hardware winding order is backwards from OpenGL */
1272       prog_data->output_topology =
1273          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1274                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1275    }
1276
1277    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1278       fprintf(stderr, "TES Input ");
1279       brw_print_vue_map(stderr, input_vue_map);
1280       fprintf(stderr, "TES Output ");
1281       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1282    }
1283
1284    if (is_scalar) {
1285       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1286                    &prog_data->base.base, NULL, nir, 8,
1287                    shader_time_index, input_vue_map);
1288       if (!v.run_tes()) {
1289          if (error_str)
1290             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1291          return NULL;
1292       }
1293
1294       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1295       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1296
1297       fs_generator g(compiler, log_data, mem_ctx,
1298                      &prog_data->base.base, v.promoted_constants, false,
1299                      MESA_SHADER_TESS_EVAL);
1300       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1301          g.enable_debug(ralloc_asprintf(mem_ctx,
1302                                         "%s tessellation evaluation shader %s",
1303                                         nir->info.label ? nir->info.label
1304                                                         : "unnamed",
1305                                         nir->info.name));
1306       }
1307
1308       g.generate_code(v.cfg, 8);
1309
1310       assembly = g.get_assembly();
1311    } else {
1312       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1313                               nir, mem_ctx, shader_time_index);
1314       if (!v.run()) {
1315          if (error_str)
1316             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1317          return NULL;
1318       }
1319
1320       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1321          v.dump_instructions();
1322
1323       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1324                                             &prog_data->base, v.cfg);
1325    }
1326
1327    return assembly;
1328 }