2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_vec4_tes.h"
29 #include "common/gen_debug.h"
30 #include "main/uniforms.h"
31 #include "util/macros.h"
34 brw_type_for_base_type(const struct glsl_type
*type
)
36 switch (type
->base_type
) {
37 case GLSL_TYPE_FLOAT16
:
38 return BRW_REGISTER_TYPE_HF
;
40 return BRW_REGISTER_TYPE_F
;
43 case GLSL_TYPE_SUBROUTINE
:
44 return BRW_REGISTER_TYPE_D
;
46 return BRW_REGISTER_TYPE_W
;
48 return BRW_REGISTER_TYPE_UD
;
49 case GLSL_TYPE_UINT16
:
50 return BRW_REGISTER_TYPE_UW
;
52 return brw_type_for_base_type(type
->fields
.array
);
53 case GLSL_TYPE_STRUCT
:
54 case GLSL_TYPE_SAMPLER
:
55 case GLSL_TYPE_ATOMIC_UINT
:
56 /* These should be overridden with the type of the member when
57 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
58 * way to trip up if we don't.
60 return BRW_REGISTER_TYPE_UD
;
62 return BRW_REGISTER_TYPE_UD
;
63 case GLSL_TYPE_DOUBLE
:
64 return BRW_REGISTER_TYPE_DF
;
65 case GLSL_TYPE_UINT64
:
66 return BRW_REGISTER_TYPE_UQ
;
68 return BRW_REGISTER_TYPE_Q
;
71 case GLSL_TYPE_INTERFACE
:
72 case GLSL_TYPE_FUNCTION
:
73 unreachable("not reached");
76 return BRW_REGISTER_TYPE_F
;
79 enum brw_conditional_mod
80 brw_conditional_for_comparison(unsigned int op
)
84 return BRW_CONDITIONAL_L
;
86 return BRW_CONDITIONAL_GE
;
88 case ir_binop_all_equal
: /* same as equal for scalars */
89 return BRW_CONDITIONAL_Z
;
91 case ir_binop_any_nequal
: /* same as nequal for scalars */
92 return BRW_CONDITIONAL_NZ
;
94 unreachable("not reached: bad operation for comparison");
99 brw_math_function(enum opcode op
)
102 case SHADER_OPCODE_RCP
:
103 return BRW_MATH_FUNCTION_INV
;
104 case SHADER_OPCODE_RSQ
:
105 return BRW_MATH_FUNCTION_RSQ
;
106 case SHADER_OPCODE_SQRT
:
107 return BRW_MATH_FUNCTION_SQRT
;
108 case SHADER_OPCODE_EXP2
:
109 return BRW_MATH_FUNCTION_EXP
;
110 case SHADER_OPCODE_LOG2
:
111 return BRW_MATH_FUNCTION_LOG
;
112 case SHADER_OPCODE_POW
:
113 return BRW_MATH_FUNCTION_POW
;
114 case SHADER_OPCODE_SIN
:
115 return BRW_MATH_FUNCTION_SIN
;
116 case SHADER_OPCODE_COS
:
117 return BRW_MATH_FUNCTION_COS
;
118 case SHADER_OPCODE_INT_QUOTIENT
:
119 return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
;
120 case SHADER_OPCODE_INT_REMAINDER
:
121 return BRW_MATH_FUNCTION_INT_DIV_REMAINDER
;
123 unreachable("not reached: unknown math function");
128 brw_texture_offset(int *offsets
, unsigned num_components
, uint32_t *offset_bits
)
130 if (!offsets
) return false; /* nonconstant offset; caller will handle it. */
132 /* offset out of bounds; caller will handle it. */
133 for (unsigned i
= 0; i
< num_components
; i
++)
134 if (offsets
[i
] > 7 || offsets
[i
] < -8)
137 /* Combine all three offsets into a single unsigned dword:
139 * bits 11:8 - U Offset (X component)
140 * bits 7:4 - V Offset (Y component)
141 * bits 3:0 - R Offset (Z component)
144 for (unsigned i
= 0; i
< num_components
; i
++) {
145 const unsigned shift
= 4 * (2 - i
);
146 *offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
152 brw_instruction_name(const struct gen_device_info
*devinfo
, enum opcode op
)
155 case BRW_OPCODE_ILLEGAL
... BRW_OPCODE_NOP
:
156 /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
157 * start of a loop in the IR.
159 if (devinfo
->gen
>= 6 && op
== BRW_OPCODE_DO
)
162 /* The following conversion opcodes doesn't exist on Gen8+, but we use
163 * then to mark that we want to do the conversion.
165 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F32TO16
)
168 if (devinfo
->gen
> 7 && op
== BRW_OPCODE_F16TO32
)
171 assert(brw_opcode_desc(devinfo
, op
)->name
);
172 return brw_opcode_desc(devinfo
, op
)->name
;
173 case FS_OPCODE_FB_WRITE
:
175 case FS_OPCODE_FB_WRITE_LOGICAL
:
176 return "fb_write_logical";
177 case FS_OPCODE_REP_FB_WRITE
:
178 return "rep_fb_write";
179 case FS_OPCODE_FB_READ
:
181 case FS_OPCODE_FB_READ_LOGICAL
:
182 return "fb_read_logical";
184 case SHADER_OPCODE_RCP
:
186 case SHADER_OPCODE_RSQ
:
188 case SHADER_OPCODE_SQRT
:
190 case SHADER_OPCODE_EXP2
:
192 case SHADER_OPCODE_LOG2
:
194 case SHADER_OPCODE_POW
:
196 case SHADER_OPCODE_INT_QUOTIENT
:
198 case SHADER_OPCODE_INT_REMAINDER
:
200 case SHADER_OPCODE_SIN
:
202 case SHADER_OPCODE_COS
:
205 case SHADER_OPCODE_TEX
:
207 case SHADER_OPCODE_TEX_LOGICAL
:
208 return "tex_logical";
209 case SHADER_OPCODE_TXD
:
211 case SHADER_OPCODE_TXD_LOGICAL
:
212 return "txd_logical";
213 case SHADER_OPCODE_TXF
:
215 case SHADER_OPCODE_TXF_LOGICAL
:
216 return "txf_logical";
217 case SHADER_OPCODE_TXF_LZ
:
219 case SHADER_OPCODE_TXL
:
221 case SHADER_OPCODE_TXL_LOGICAL
:
222 return "txl_logical";
223 case SHADER_OPCODE_TXL_LZ
:
225 case SHADER_OPCODE_TXS
:
227 case SHADER_OPCODE_TXS_LOGICAL
:
228 return "txs_logical";
231 case FS_OPCODE_TXB_LOGICAL
:
232 return "txb_logical";
233 case SHADER_OPCODE_TXF_CMS
:
235 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
236 return "txf_cms_logical";
237 case SHADER_OPCODE_TXF_CMS_W
:
239 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
240 return "txf_cms_w_logical";
241 case SHADER_OPCODE_TXF_UMS
:
243 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
244 return "txf_ums_logical";
245 case SHADER_OPCODE_TXF_MCS
:
247 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
248 return "txf_mcs_logical";
249 case SHADER_OPCODE_LOD
:
251 case SHADER_OPCODE_LOD_LOGICAL
:
252 return "lod_logical";
253 case SHADER_OPCODE_TG4
:
255 case SHADER_OPCODE_TG4_LOGICAL
:
256 return "tg4_logical";
257 case SHADER_OPCODE_TG4_OFFSET
:
259 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
260 return "tg4_offset_logical";
261 case SHADER_OPCODE_SAMPLEINFO
:
263 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
264 return "sampleinfo_logical";
266 case SHADER_OPCODE_SHADER_TIME_ADD
:
267 return "shader_time_add";
269 case SHADER_OPCODE_UNTYPED_ATOMIC
:
270 return "untyped_atomic";
271 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
272 return "untyped_atomic_logical";
273 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
274 return "untyped_surface_read";
275 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
276 return "untyped_surface_read_logical";
277 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
278 return "untyped_surface_write";
279 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
280 return "untyped_surface_write_logical";
281 case SHADER_OPCODE_TYPED_ATOMIC
:
282 return "typed_atomic";
283 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
284 return "typed_atomic_logical";
285 case SHADER_OPCODE_TYPED_SURFACE_READ
:
286 return "typed_surface_read";
287 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
288 return "typed_surface_read_logical";
289 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
290 return "typed_surface_write";
291 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
292 return "typed_surface_write_logical";
293 case SHADER_OPCODE_MEMORY_FENCE
:
294 return "memory_fence";
296 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
297 return "byte_scattered_read";
298 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
299 return "byte_scattered_read_logical";
300 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
301 return "byte_scattered_write";
302 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
303 return "byte_scattered_write_logical";
305 case SHADER_OPCODE_LOAD_PAYLOAD
:
306 return "load_payload";
310 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
311 return "gen4_scratch_read";
312 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
313 return "gen4_scratch_write";
314 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
315 return "gen7_scratch_read";
316 case SHADER_OPCODE_URB_WRITE_SIMD8
:
317 return "gen8_urb_write_simd8";
318 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
319 return "gen8_urb_write_simd8_per_slot";
320 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
321 return "gen8_urb_write_simd8_masked";
322 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
323 return "gen8_urb_write_simd8_masked_per_slot";
324 case SHADER_OPCODE_URB_READ_SIMD8
:
325 return "urb_read_simd8";
326 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
327 return "urb_read_simd8_per_slot";
329 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
330 return "find_live_channel";
331 case SHADER_OPCODE_BROADCAST
:
334 case VEC4_OPCODE_MOV_BYTES
:
336 case VEC4_OPCODE_PACK_BYTES
:
338 case VEC4_OPCODE_UNPACK_UNIFORM
:
339 return "unpack_uniform";
340 case VEC4_OPCODE_DOUBLE_TO_F32
:
341 return "double_to_f32";
342 case VEC4_OPCODE_DOUBLE_TO_D32
:
343 return "double_to_d32";
344 case VEC4_OPCODE_DOUBLE_TO_U32
:
345 return "double_to_u32";
346 case VEC4_OPCODE_TO_DOUBLE
:
347 return "single_to_double";
348 case VEC4_OPCODE_PICK_LOW_32BIT
:
349 return "pick_low_32bit";
350 case VEC4_OPCODE_PICK_HIGH_32BIT
:
351 return "pick_high_32bit";
352 case VEC4_OPCODE_SET_LOW_32BIT
:
353 return "set_low_32bit";
354 case VEC4_OPCODE_SET_HIGH_32BIT
:
355 return "set_high_32bit";
357 case FS_OPCODE_DDX_COARSE
:
359 case FS_OPCODE_DDX_FINE
:
361 case FS_OPCODE_DDY_COARSE
:
363 case FS_OPCODE_DDY_FINE
:
366 case FS_OPCODE_CINTERP
:
368 case FS_OPCODE_LINTERP
:
371 case FS_OPCODE_PIXEL_X
:
373 case FS_OPCODE_PIXEL_Y
:
376 case FS_OPCODE_GET_BUFFER_SIZE
:
377 return "fs_get_buffer_size";
379 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
380 return "uniform_pull_const";
381 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
382 return "uniform_pull_const_gen7";
383 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
384 return "varying_pull_const_gen4";
385 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
386 return "varying_pull_const_gen7";
387 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
388 return "varying_pull_const_logical";
390 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
391 return "mov_dispatch_to_flags";
392 case FS_OPCODE_DISCARD_JUMP
:
393 return "discard_jump";
395 case FS_OPCODE_SET_SAMPLE_ID
:
396 return "set_sample_id";
398 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
399 return "pack_half_2x16_split";
400 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
401 return "unpack_half_2x16_split_x";
402 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
403 return "unpack_half_2x16_split_y";
405 case FS_OPCODE_PLACEHOLDER_HALT
:
406 return "placeholder_halt";
408 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
409 return "interp_sample";
410 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
411 return "interp_shared_offset";
412 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
413 return "interp_per_slot_offset";
415 case VS_OPCODE_URB_WRITE
:
416 return "vs_urb_write";
417 case VS_OPCODE_PULL_CONSTANT_LOAD
:
418 return "pull_constant_load";
419 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
420 return "pull_constant_load_gen7";
422 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
423 return "set_simd4x2_header_gen9";
425 case VS_OPCODE_GET_BUFFER_SIZE
:
426 return "vs_get_buffer_size";
428 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
429 return "unpack_flags_simd4x2";
431 case GS_OPCODE_URB_WRITE
:
432 return "gs_urb_write";
433 case GS_OPCODE_URB_WRITE_ALLOCATE
:
434 return "gs_urb_write_allocate";
435 case GS_OPCODE_THREAD_END
:
436 return "gs_thread_end";
437 case GS_OPCODE_SET_WRITE_OFFSET
:
438 return "set_write_offset";
439 case GS_OPCODE_SET_VERTEX_COUNT
:
440 return "set_vertex_count";
441 case GS_OPCODE_SET_DWORD_2
:
442 return "set_dword_2";
443 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
444 return "prepare_channel_masks";
445 case GS_OPCODE_SET_CHANNEL_MASKS
:
446 return "set_channel_masks";
447 case GS_OPCODE_GET_INSTANCE_ID
:
448 return "get_instance_id";
449 case GS_OPCODE_FF_SYNC
:
451 case GS_OPCODE_SET_PRIMITIVE_ID
:
452 return "set_primitive_id";
453 case GS_OPCODE_SVB_WRITE
:
454 return "gs_svb_write";
455 case GS_OPCODE_SVB_SET_DST_INDEX
:
456 return "gs_svb_set_dst_index";
457 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
458 return "gs_ff_sync_set_primitives";
459 case CS_OPCODE_CS_TERMINATE
:
460 return "cs_terminate";
461 case SHADER_OPCODE_BARRIER
:
463 case SHADER_OPCODE_MULH
:
465 case SHADER_OPCODE_MOV_INDIRECT
:
466 return "mov_indirect";
468 case VEC4_OPCODE_URB_READ
:
470 case TCS_OPCODE_GET_INSTANCE_ID
:
471 return "tcs_get_instance_id";
472 case TCS_OPCODE_URB_WRITE
:
473 return "tcs_urb_write";
474 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
475 return "tcs_set_input_urb_offsets";
476 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
477 return "tcs_set_output_urb_offsets";
478 case TCS_OPCODE_GET_PRIMITIVE_ID
:
479 return "tcs_get_primitive_id";
480 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
481 return "tcs_create_barrier_header";
482 case TCS_OPCODE_SRC0_010_IS_ZERO
:
483 return "tcs_src0<0,1,0>_is_zero";
484 case TCS_OPCODE_RELEASE_INPUT
:
485 return "tcs_release_input";
486 case TCS_OPCODE_THREAD_END
:
487 return "tcs_thread_end";
488 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
489 return "tes_create_input_read_header";
490 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
491 return "tes_add_indirect_urb_offset";
492 case TES_OPCODE_GET_PRIMITIVE_ID
:
493 return "tes_get_primitive_id";
495 case SHADER_OPCODE_RND_MODE
:
499 unreachable("not reached");
503 brw_saturate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
510 } imm
, sat_imm
= { 0 };
512 const unsigned size
= type_sz(type
);
514 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
515 * irrelevant, so just check the size of the type and copy from/to an
516 * appropriately sized field.
524 case BRW_REGISTER_TYPE_UD
:
525 case BRW_REGISTER_TYPE_D
:
526 case BRW_REGISTER_TYPE_UW
:
527 case BRW_REGISTER_TYPE_W
:
528 case BRW_REGISTER_TYPE_UQ
:
529 case BRW_REGISTER_TYPE_Q
:
532 case BRW_REGISTER_TYPE_F
:
533 sat_imm
.f
= CLAMP(imm
.f
, 0.0f
, 1.0f
);
535 case BRW_REGISTER_TYPE_DF
:
536 sat_imm
.df
= CLAMP(imm
.df
, 0.0, 1.0);
538 case BRW_REGISTER_TYPE_UB
:
539 case BRW_REGISTER_TYPE_B
:
540 unreachable("no UB/B immediates");
541 case BRW_REGISTER_TYPE_V
:
542 case BRW_REGISTER_TYPE_UV
:
543 case BRW_REGISTER_TYPE_VF
:
544 unreachable("unimplemented: saturate vector immediate");
545 case BRW_REGISTER_TYPE_HF
:
546 unreachable("unimplemented: saturate HF immediate");
550 if (imm
.ud
!= sat_imm
.ud
) {
551 reg
->ud
= sat_imm
.ud
;
555 if (imm
.df
!= sat_imm
.df
) {
556 reg
->df
= sat_imm
.df
;
564 brw_negate_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
567 case BRW_REGISTER_TYPE_D
:
568 case BRW_REGISTER_TYPE_UD
:
571 case BRW_REGISTER_TYPE_W
:
572 case BRW_REGISTER_TYPE_UW
:
573 reg
->d
= -(int16_t)reg
->ud
;
575 case BRW_REGISTER_TYPE_F
:
578 case BRW_REGISTER_TYPE_VF
:
579 reg
->ud
^= 0x80808080;
581 case BRW_REGISTER_TYPE_DF
:
584 case BRW_REGISTER_TYPE_UQ
:
585 case BRW_REGISTER_TYPE_Q
:
586 reg
->d64
= -reg
->d64
;
588 case BRW_REGISTER_TYPE_UB
:
589 case BRW_REGISTER_TYPE_B
:
590 unreachable("no UB/B immediates");
591 case BRW_REGISTER_TYPE_UV
:
592 case BRW_REGISTER_TYPE_V
:
593 assert(!"unimplemented: negate UV/V immediate");
594 case BRW_REGISTER_TYPE_HF
:
595 assert(!"unimplemented: negate HF immediate");
602 brw_abs_immediate(enum brw_reg_type type
, struct brw_reg
*reg
)
605 case BRW_REGISTER_TYPE_D
:
606 reg
->d
= abs(reg
->d
);
608 case BRW_REGISTER_TYPE_W
:
609 reg
->d
= abs((int16_t)reg
->ud
);
611 case BRW_REGISTER_TYPE_F
:
612 reg
->f
= fabsf(reg
->f
);
614 case BRW_REGISTER_TYPE_DF
:
615 reg
->df
= fabs(reg
->df
);
617 case BRW_REGISTER_TYPE_VF
:
618 reg
->ud
&= ~0x80808080;
620 case BRW_REGISTER_TYPE_Q
:
621 reg
->d64
= imaxabs(reg
->d64
);
623 case BRW_REGISTER_TYPE_UB
:
624 case BRW_REGISTER_TYPE_B
:
625 unreachable("no UB/B immediates");
626 case BRW_REGISTER_TYPE_UQ
:
627 case BRW_REGISTER_TYPE_UD
:
628 case BRW_REGISTER_TYPE_UW
:
629 case BRW_REGISTER_TYPE_UV
:
630 /* Presumably the absolute value modifier on an unsigned source is a
631 * nop, but it would be nice to confirm.
633 assert(!"unimplemented: abs unsigned immediate");
634 case BRW_REGISTER_TYPE_V
:
635 assert(!"unimplemented: abs V immediate");
636 case BRW_REGISTER_TYPE_HF
:
637 assert(!"unimplemented: abs HF immediate");
643 backend_shader::backend_shader(const struct brw_compiler
*compiler
,
646 const nir_shader
*shader
,
647 struct brw_stage_prog_data
*stage_prog_data
)
648 : compiler(compiler
),
650 devinfo(compiler
->devinfo
),
652 stage_prog_data(stage_prog_data
),
655 stage(shader
->info
.stage
)
657 debug_enabled
= INTEL_DEBUG
& intel_debug_flag_for_shader_stage(stage
);
658 stage_name
= _mesa_shader_stage_to_string(stage
);
659 stage_abbrev
= _mesa_shader_stage_to_abbrev(stage
);
662 backend_shader::~backend_shader()
667 backend_reg::equals(const backend_reg
&r
) const
669 return brw_regs_equal(this, &r
) && offset
== r
.offset
;
673 backend_reg::is_zero() const
679 case BRW_REGISTER_TYPE_F
:
681 case BRW_REGISTER_TYPE_DF
:
683 case BRW_REGISTER_TYPE_D
:
684 case BRW_REGISTER_TYPE_UD
:
686 case BRW_REGISTER_TYPE_UQ
:
687 case BRW_REGISTER_TYPE_Q
:
695 backend_reg::is_one() const
701 case BRW_REGISTER_TYPE_F
:
703 case BRW_REGISTER_TYPE_DF
:
705 case BRW_REGISTER_TYPE_D
:
706 case BRW_REGISTER_TYPE_UD
:
708 case BRW_REGISTER_TYPE_UQ
:
709 case BRW_REGISTER_TYPE_Q
:
717 backend_reg::is_negative_one() const
723 case BRW_REGISTER_TYPE_F
:
725 case BRW_REGISTER_TYPE_DF
:
727 case BRW_REGISTER_TYPE_D
:
729 case BRW_REGISTER_TYPE_Q
:
737 backend_reg::is_null() const
739 return file
== ARF
&& nr
== BRW_ARF_NULL
;
744 backend_reg::is_accumulator() const
746 return file
== ARF
&& nr
== BRW_ARF_ACCUMULATOR
;
750 backend_instruction::is_commutative() const
758 case SHADER_OPCODE_MULH
:
761 /* MIN and MAX are commutative. */
762 if (conditional_mod
== BRW_CONDITIONAL_GE
||
763 conditional_mod
== BRW_CONDITIONAL_L
) {
773 backend_instruction::is_3src(const struct gen_device_info
*devinfo
) const
775 return ::is_3src(devinfo
, opcode
);
779 backend_instruction::is_tex() const
781 return (opcode
== SHADER_OPCODE_TEX
||
782 opcode
== FS_OPCODE_TXB
||
783 opcode
== SHADER_OPCODE_TXD
||
784 opcode
== SHADER_OPCODE_TXF
||
785 opcode
== SHADER_OPCODE_TXF_LZ
||
786 opcode
== SHADER_OPCODE_TXF_CMS
||
787 opcode
== SHADER_OPCODE_TXF_CMS_W
||
788 opcode
== SHADER_OPCODE_TXF_UMS
||
789 opcode
== SHADER_OPCODE_TXF_MCS
||
790 opcode
== SHADER_OPCODE_TXL
||
791 opcode
== SHADER_OPCODE_TXL_LZ
||
792 opcode
== SHADER_OPCODE_TXS
||
793 opcode
== SHADER_OPCODE_LOD
||
794 opcode
== SHADER_OPCODE_TG4
||
795 opcode
== SHADER_OPCODE_TG4_OFFSET
||
796 opcode
== SHADER_OPCODE_SAMPLEINFO
);
800 backend_instruction::is_math() const
802 return (opcode
== SHADER_OPCODE_RCP
||
803 opcode
== SHADER_OPCODE_RSQ
||
804 opcode
== SHADER_OPCODE_SQRT
||
805 opcode
== SHADER_OPCODE_EXP2
||
806 opcode
== SHADER_OPCODE_LOG2
||
807 opcode
== SHADER_OPCODE_SIN
||
808 opcode
== SHADER_OPCODE_COS
||
809 opcode
== SHADER_OPCODE_INT_QUOTIENT
||
810 opcode
== SHADER_OPCODE_INT_REMAINDER
||
811 opcode
== SHADER_OPCODE_POW
);
815 backend_instruction::is_control_flow() const
819 case BRW_OPCODE_WHILE
:
821 case BRW_OPCODE_ELSE
:
822 case BRW_OPCODE_ENDIF
:
823 case BRW_OPCODE_BREAK
:
824 case BRW_OPCODE_CONTINUE
:
832 backend_instruction::can_do_source_mods() const
835 case BRW_OPCODE_ADDC
:
837 case BRW_OPCODE_BFI1
:
838 case BRW_OPCODE_BFI2
:
839 case BRW_OPCODE_BFREV
:
840 case BRW_OPCODE_CBIT
:
843 case BRW_OPCODE_SUBB
:
844 case SHADER_OPCODE_BROADCAST
:
845 case SHADER_OPCODE_MOV_INDIRECT
:
853 backend_instruction::can_do_saturate() const
863 case BRW_OPCODE_F16TO32
:
864 case BRW_OPCODE_F32TO16
:
865 case BRW_OPCODE_LINE
:
869 case BRW_OPCODE_MATH
:
872 case SHADER_OPCODE_MULH
:
874 case BRW_OPCODE_RNDD
:
875 case BRW_OPCODE_RNDE
:
876 case BRW_OPCODE_RNDU
:
877 case BRW_OPCODE_RNDZ
:
881 case FS_OPCODE_LINTERP
:
882 case SHADER_OPCODE_COS
:
883 case SHADER_OPCODE_EXP2
:
884 case SHADER_OPCODE_LOG2
:
885 case SHADER_OPCODE_POW
:
886 case SHADER_OPCODE_RCP
:
887 case SHADER_OPCODE_RSQ
:
888 case SHADER_OPCODE_SIN
:
889 case SHADER_OPCODE_SQRT
:
897 backend_instruction::can_do_cmod() const
901 case BRW_OPCODE_ADDC
:
906 case BRW_OPCODE_CMPN
:
911 case BRW_OPCODE_F16TO32
:
912 case BRW_OPCODE_F32TO16
:
914 case BRW_OPCODE_LINE
:
918 case BRW_OPCODE_MACH
:
925 case BRW_OPCODE_RNDD
:
926 case BRW_OPCODE_RNDE
:
927 case BRW_OPCODE_RNDU
:
928 case BRW_OPCODE_RNDZ
:
929 case BRW_OPCODE_SAD2
:
930 case BRW_OPCODE_SADA2
:
933 case BRW_OPCODE_SUBB
:
935 case FS_OPCODE_CINTERP
:
936 case FS_OPCODE_LINTERP
:
944 backend_instruction::reads_accumulator_implicitly() const
948 case BRW_OPCODE_MACH
:
949 case BRW_OPCODE_SADA2
:
957 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info
*devinfo
) const
959 return writes_accumulator
||
961 ((opcode
>= BRW_OPCODE_ADD
&& opcode
< BRW_OPCODE_NOP
) ||
962 (opcode
>= FS_OPCODE_DDX_COARSE
&& opcode
<= FS_OPCODE_LINTERP
&&
963 opcode
!= FS_OPCODE_CINTERP
)));
967 backend_instruction::has_side_effects() const
970 case SHADER_OPCODE_UNTYPED_ATOMIC
:
971 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
972 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
973 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
974 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
975 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
976 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
977 case SHADER_OPCODE_TYPED_ATOMIC
:
978 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
979 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
980 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
981 case SHADER_OPCODE_MEMORY_FENCE
:
982 case SHADER_OPCODE_URB_WRITE_SIMD8
:
983 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
984 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
985 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
986 case FS_OPCODE_FB_WRITE
:
987 case FS_OPCODE_FB_WRITE_LOGICAL
:
988 case SHADER_OPCODE_BARRIER
:
989 case TCS_OPCODE_URB_WRITE
:
990 case TCS_OPCODE_RELEASE_INPUT
:
991 case SHADER_OPCODE_RND_MODE
:
999 backend_instruction::is_volatile() const
1002 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1003 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
1004 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1005 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
1006 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
1007 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
1008 case SHADER_OPCODE_URB_READ_SIMD8
:
1009 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
1010 case VEC4_OPCODE_URB_READ
:
1019 inst_is_in_block(const bblock_t
*block
, const backend_instruction
*inst
)
1022 foreach_inst_in_block (backend_instruction
, i
, block
) {
1032 adjust_later_block_ips(bblock_t
*start_block
, int ip_adjustment
)
1034 for (bblock_t
*block_iter
= start_block
->next();
1036 block_iter
= block_iter
->next()) {
1037 block_iter
->start_ip
+= ip_adjustment
;
1038 block_iter
->end_ip
+= ip_adjustment
;
1043 backend_instruction::insert_after(bblock_t
*block
, backend_instruction
*inst
)
1045 assert(this != inst
);
1047 if (!this->is_head_sentinel())
1048 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1052 adjust_later_block_ips(block
, 1);
1054 exec_node::insert_after(inst
);
1058 backend_instruction::insert_before(bblock_t
*block
, backend_instruction
*inst
)
1060 assert(this != inst
);
1062 if (!this->is_tail_sentinel())
1063 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1067 adjust_later_block_ips(block
, 1);
1069 exec_node::insert_before(inst
);
1073 backend_instruction::insert_before(bblock_t
*block
, exec_list
*list
)
1075 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1077 unsigned num_inst
= list
->length();
1079 block
->end_ip
+= num_inst
;
1081 adjust_later_block_ips(block
, num_inst
);
1083 exec_node::insert_before(list
);
1087 backend_instruction::remove(bblock_t
*block
)
1089 assert(inst_is_in_block(block
, this) || !"Instruction not in block");
1091 adjust_later_block_ips(block
, -1);
1093 if (block
->start_ip
== block
->end_ip
) {
1094 block
->cfg
->remove_block(block
);
1099 exec_node::remove();
1103 backend_shader::dump_instructions()
1105 dump_instructions(NULL
);
1109 backend_shader::dump_instructions(const char *name
)
1111 FILE *file
= stderr
;
1112 if (name
&& geteuid() != 0) {
1113 file
= fopen(name
, "w");
1120 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
1121 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1122 fprintf(file
, "%4d: ", ip
++);
1123 dump_instruction(inst
, file
);
1127 foreach_in_list(backend_instruction
, inst
, &instructions
) {
1128 if (!unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
))
1129 fprintf(file
, "%4d: ", ip
++);
1130 dump_instruction(inst
, file
);
1134 if (file
!= stderr
) {
1140 backend_shader::calculate_cfg()
1144 cfg
= new(mem_ctx
) cfg_t(&this->instructions
);
1147 extern "C" const unsigned *
1148 brw_compile_tes(const struct brw_compiler
*compiler
,
1151 const struct brw_tes_prog_key
*key
,
1152 const struct brw_vue_map
*input_vue_map
,
1153 struct brw_tes_prog_data
*prog_data
,
1154 const nir_shader
*src_shader
,
1155 struct gl_program
*prog
,
1156 int shader_time_index
,
1159 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
1160 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
];
1161 const unsigned *assembly
;
1163 nir_shader
*nir
= nir_shader_clone(mem_ctx
, src_shader
);
1164 nir
->info
.inputs_read
= key
->inputs_read
;
1165 nir
->info
.patch_inputs_read
= key
->patch_inputs_read
;
1167 nir
= brw_nir_apply_sampler_key(nir
, compiler
, &key
->tex
, is_scalar
);
1168 brw_nir_lower_tes_inputs(nir
, input_vue_map
);
1169 brw_nir_lower_vue_outputs(nir
, is_scalar
);
1170 nir
= brw_postprocess_nir(nir
, compiler
, is_scalar
);
1172 brw_compute_vue_map(devinfo
, &prog_data
->base
.vue_map
,
1173 nir
->info
.outputs_written
,
1174 nir
->info
.separate_shader
);
1176 unsigned output_size_bytes
= prog_data
->base
.vue_map
.num_slots
* 4 * 4;
1178 assert(output_size_bytes
>= 1);
1179 if (output_size_bytes
> GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES
) {
1181 *error_str
= ralloc_strdup(mem_ctx
, "DS outputs exceed maximum size");
1185 prog_data
->base
.clip_distance_mask
=
1186 ((1 << nir
->info
.clip_distance_array_size
) - 1);
1187 prog_data
->base
.cull_distance_mask
=
1188 ((1 << nir
->info
.cull_distance_array_size
) - 1) <<
1189 nir
->info
.clip_distance_array_size
;
1191 /* URB entry sizes are stored as a multiple of 64 bytes. */
1192 prog_data
->base
.urb_entry_size
= ALIGN(output_size_bytes
, 64) / 64;
1194 /* On Cannonlake software shall not program an allocation size that
1195 * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1197 if (devinfo
->gen
== 10 &&
1198 prog_data
->base
.urb_entry_size
% 3 == 0)
1199 prog_data
->base
.urb_entry_size
++;
1201 prog_data
->base
.urb_read_length
= 0;
1203 STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER
== TESS_SPACING_EQUAL
- 1);
1204 STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL
==
1205 TESS_SPACING_FRACTIONAL_ODD
- 1);
1206 STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
==
1207 TESS_SPACING_FRACTIONAL_EVEN
- 1);
1209 prog_data
->partitioning
=
1210 (enum brw_tess_partitioning
) (nir
->info
.tess
.spacing
- 1);
1212 switch (nir
->info
.tess
.primitive_mode
) {
1214 prog_data
->domain
= BRW_TESS_DOMAIN_QUAD
;
1217 prog_data
->domain
= BRW_TESS_DOMAIN_TRI
;
1220 prog_data
->domain
= BRW_TESS_DOMAIN_ISOLINE
;
1223 unreachable("invalid domain shader primitive mode");
1226 if (nir
->info
.tess
.point_mode
) {
1227 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_POINT
;
1228 } else if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
) {
1229 prog_data
->output_topology
= BRW_TESS_OUTPUT_TOPOLOGY_LINE
;
1231 /* Hardware winding order is backwards from OpenGL */
1232 prog_data
->output_topology
=
1233 nir
->info
.tess
.ccw
? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1234 : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
;
1237 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1238 fprintf(stderr
, "TES Input ");
1239 brw_print_vue_map(stderr
, input_vue_map
);
1240 fprintf(stderr
, "TES Output ");
1241 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
1245 fs_visitor
v(compiler
, log_data
, mem_ctx
, (void *) key
,
1246 &prog_data
->base
.base
, NULL
, nir
, 8,
1247 shader_time_index
, input_vue_map
);
1250 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1254 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
1255 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
1257 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
1258 &prog_data
->base
.base
, v
.promoted_constants
, false,
1259 MESA_SHADER_TESS_EVAL
);
1260 if (unlikely(INTEL_DEBUG
& DEBUG_TES
)) {
1261 g
.enable_debug(ralloc_asprintf(mem_ctx
,
1262 "%s tessellation evaluation shader %s",
1263 nir
->info
.label
? nir
->info
.label
1268 g
.generate_code(v
.cfg
, 8);
1270 assembly
= g
.get_assembly(&prog_data
->base
.base
.program_size
);
1272 brw::vec4_tes_visitor
v(compiler
, log_data
, key
, prog_data
,
1273 nir
, mem_ctx
, shader_time_index
);
1276 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
1280 if (unlikely(INTEL_DEBUG
& DEBUG_TES
))
1281 v
.dump_instructions();
1283 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
, nir
,
1284 &prog_data
->base
, v
.cfg
,
1285 &prog_data
->base
.base
.program_size
);