src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT:
  38       return BRW_REGISTER_TYPE_F;
  39    case GLSL_TYPE_INT:
  40    case GLSL_TYPE_BOOL:
  41    case GLSL_TYPE_SUBROUTINE:
  42       return BRW_REGISTER_TYPE_D;
  43    case GLSL_TYPE_UINT:
  44       return BRW_REGISTER_TYPE_UD;
  45    case GLSL_TYPE_ARRAY:
  46       return brw_type_for_base_type(type->fields.array);
  47    case GLSL_TYPE_STRUCT:
  48    case GLSL_TYPE_SAMPLER:
  49    case GLSL_TYPE_ATOMIC_UINT:
  50       /* These should be overridden with the type of the member when
  51        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  52        * way to trip up if we don't.
  53        */
  54       return BRW_REGISTER_TYPE_UD;
  55    case GLSL_TYPE_IMAGE:
  56       return BRW_REGISTER_TYPE_UD;
  57    case GLSL_TYPE_DOUBLE:
  58       return BRW_REGISTER_TYPE_DF;
  59    case GLSL_TYPE_UINT64:
  60       return BRW_REGISTER_TYPE_UQ;
  61    case GLSL_TYPE_INT64:
  62       return BRW_REGISTER_TYPE_Q;
  63    case GLSL_TYPE_VOID:
  64    case GLSL_TYPE_ERROR:
  65    case GLSL_TYPE_INTERFACE:
  66    case GLSL_TYPE_FUNCTION:
  67       unreachable("not reached");
  68    }
  69
  70    return BRW_REGISTER_TYPE_F;
  71 }
  72
  73 enum brw_conditional_mod
  74 brw_conditional_for_comparison(unsigned int op)
  75 {
  76    switch (op) {
  77    case ir_binop_less:
  78       return BRW_CONDITIONAL_L;
  79    case ir_binop_greater:
  80       return BRW_CONDITIONAL_G;
  81    case ir_binop_lequal:
  82       return BRW_CONDITIONAL_LE;
  83    case ir_binop_gequal:
  84       return BRW_CONDITIONAL_GE;
  85    case ir_binop_equal:
  86    case ir_binop_all_equal: /* same as equal for scalars */
  87       return BRW_CONDITIONAL_Z;
  88    case ir_binop_nequal:
  89    case ir_binop_any_nequal: /* same as nequal for scalars */
  90       return BRW_CONDITIONAL_NZ;
  91    default:
  92       unreachable("not reached: bad operation for comparison");
  93    }
  94 }
  95
  96 uint32_t
  97 brw_math_function(enum opcode op)
  98 {
  99    switch (op) {
 100    case SHADER_OPCODE_RCP:
 101       return BRW_MATH_FUNCTION_INV;
 102    case SHADER_OPCODE_RSQ:
 103       return BRW_MATH_FUNCTION_RSQ;
 104    case SHADER_OPCODE_SQRT:
 105       return BRW_MATH_FUNCTION_SQRT;
 106    case SHADER_OPCODE_EXP2:
 107       return BRW_MATH_FUNCTION_EXP;
 108    case SHADER_OPCODE_LOG2:
 109       return BRW_MATH_FUNCTION_LOG;
 110    case SHADER_OPCODE_POW:
 111       return BRW_MATH_FUNCTION_POW;
 112    case SHADER_OPCODE_SIN:
 113       return BRW_MATH_FUNCTION_SIN;
 114    case SHADER_OPCODE_COS:
 115       return BRW_MATH_FUNCTION_COS;
 116    case SHADER_OPCODE_INT_QUOTIENT:
 117       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 118    case SHADER_OPCODE_INT_REMAINDER:
 119       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 120    default:
 121       unreachable("not reached: unknown math function");
 122    }
 123 }
 124
 125 bool
 126 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 127 {
 128    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 129
 130    /* offset out of bounds; caller will handle it. */
 131    for (unsigned i = 0; i < num_components; i++)
 132       if (offsets[i] > 7 || offsets[i] < -8)
 133          return false;
 134
 135    /* Combine all three offsets into a single unsigned dword:
 136     *
 137     *    bits 11:8 - U Offset (X component)
 138     *    bits  7:4 - V Offset (Y component)
 139     *    bits  3:0 - R Offset (Z component)
 140     */
 141    *offset_bits = 0;
 142    for (unsigned i = 0; i < num_components; i++) {
 143       const unsigned shift = 4 * (2 - i);
 144       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 145    }
 146    return true;
 147 }
 148
 149 const char *
 150 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 151 {
 152    switch (op) {
 153    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 154       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 155        * start of a loop in the IR.
 156        */
 157       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 158          return "do";
 159
 160       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 161        * then to mark that we want to do the conversion.
 162        */
 163       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 164          return "f32to16";
 165
 166       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 167          return "f16to32";
 168
 169       assert(brw_opcode_desc(devinfo, op)->name);
 170       return brw_opcode_desc(devinfo, op)->name;
 171    case FS_OPCODE_FB_WRITE:
 172       return "fb_write";
 173    case FS_OPCODE_FB_WRITE_LOGICAL:
 174       return "fb_write_logical";
 175    case FS_OPCODE_REP_FB_WRITE:
 176       return "rep_fb_write";
 177    case FS_OPCODE_FB_READ:
 178       return "fb_read";
 179    case FS_OPCODE_FB_READ_LOGICAL:
 180       return "fb_read_logical";
 181
 182    case SHADER_OPCODE_RCP:
 183       return "rcp";
 184    case SHADER_OPCODE_RSQ:
 185       return "rsq";
 186    case SHADER_OPCODE_SQRT:
 187       return "sqrt";
 188    case SHADER_OPCODE_EXP2:
 189       return "exp2";
 190    case SHADER_OPCODE_LOG2:
 191       return "log2";
 192    case SHADER_OPCODE_POW:
 193       return "pow";
 194    case SHADER_OPCODE_INT_QUOTIENT:
 195       return "int_quot";
 196    case SHADER_OPCODE_INT_REMAINDER:
 197       return "int_rem";
 198    case SHADER_OPCODE_SIN:
 199       return "sin";
 200    case SHADER_OPCODE_COS:
 201       return "cos";
 202
 203    case SHADER_OPCODE_TEX:
 204       return "tex";
 205    case SHADER_OPCODE_TEX_LOGICAL:
 206       return "tex_logical";
 207    case SHADER_OPCODE_TXD:
 208       return "txd";
 209    case SHADER_OPCODE_TXD_LOGICAL:
 210       return "txd_logical";
 211    case SHADER_OPCODE_TXF:
 212       return "txf";
 213    case SHADER_OPCODE_TXF_LOGICAL:
 214       return "txf_logical";
 215    case SHADER_OPCODE_TXF_LZ:
 216       return "txf_lz";
 217    case SHADER_OPCODE_TXL:
 218       return "txl";
 219    case SHADER_OPCODE_TXL_LOGICAL:
 220       return "txl_logical";
 221    case SHADER_OPCODE_TXL_LZ:
 222       return "txl_lz";
 223    case SHADER_OPCODE_TXS:
 224       return "txs";
 225    case SHADER_OPCODE_TXS_LOGICAL:
 226       return "txs_logical";
 227    case FS_OPCODE_TXB:
 228       return "txb";
 229    case FS_OPCODE_TXB_LOGICAL:
 230       return "txb_logical";
 231    case SHADER_OPCODE_TXF_CMS:
 232       return "txf_cms";
 233    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 234       return "txf_cms_logical";
 235    case SHADER_OPCODE_TXF_CMS_W:
 236       return "txf_cms_w";
 237    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 238       return "txf_cms_w_logical";
 239    case SHADER_OPCODE_TXF_UMS:
 240       return "txf_ums";
 241    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 242       return "txf_ums_logical";
 243    case SHADER_OPCODE_TXF_MCS:
 244       return "txf_mcs";
 245    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 246       return "txf_mcs_logical";
 247    case SHADER_OPCODE_LOD:
 248       return "lod";
 249    case SHADER_OPCODE_LOD_LOGICAL:
 250       return "lod_logical";
 251    case SHADER_OPCODE_TG4:
 252       return "tg4";
 253    case SHADER_OPCODE_TG4_LOGICAL:
 254       return "tg4_logical";
 255    case SHADER_OPCODE_TG4_OFFSET:
 256       return "tg4_offset";
 257    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 258       return "tg4_offset_logical";
 259    case SHADER_OPCODE_SAMPLEINFO:
 260       return "sampleinfo";
 261    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 262       return "sampleinfo_logical";
 263
 264    case SHADER_OPCODE_SHADER_TIME_ADD:
 265       return "shader_time_add";
 266
 267    case SHADER_OPCODE_UNTYPED_ATOMIC:
 268       return "untyped_atomic";
 269    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 270       return "untyped_atomic_logical";
 271    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 272       return "untyped_surface_read";
 273    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 274       return "untyped_surface_read_logical";
 275    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 276       return "untyped_surface_write";
 277    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 278       return "untyped_surface_write_logical";
 279    case SHADER_OPCODE_TYPED_ATOMIC:
 280       return "typed_atomic";
 281    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 282       return "typed_atomic_logical";
 283    case SHADER_OPCODE_TYPED_SURFACE_READ:
 284       return "typed_surface_read";
 285    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 286       return "typed_surface_read_logical";
 287    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 288       return "typed_surface_write";
 289    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 290       return "typed_surface_write_logical";
 291    case SHADER_OPCODE_MEMORY_FENCE:
 292       return "memory_fence";
 293
 294    case SHADER_OPCODE_LOAD_PAYLOAD:
 295       return "load_payload";
 296    case FS_OPCODE_PACK:
 297       return "pack";
 298
 299    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 300       return "gen4_scratch_read";
 301    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 302       return "gen4_scratch_write";
 303    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 304       return "gen7_scratch_read";
 305    case SHADER_OPCODE_URB_WRITE_SIMD8:
 306       return "gen8_urb_write_simd8";
 307    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 308       return "gen8_urb_write_simd8_per_slot";
 309    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 310       return "gen8_urb_write_simd8_masked";
 311    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 312       return "gen8_urb_write_simd8_masked_per_slot";
 313    case SHADER_OPCODE_URB_READ_SIMD8:
 314       return "urb_read_simd8";
 315    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 316       return "urb_read_simd8_per_slot";
 317
 318    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 319       return "find_live_channel";
 320    case SHADER_OPCODE_BROADCAST:
 321       return "broadcast";
 322
 323    case VEC4_OPCODE_MOV_BYTES:
 324       return "mov_bytes";
 325    case VEC4_OPCODE_PACK_BYTES:
 326       return "pack_bytes";
 327    case VEC4_OPCODE_UNPACK_UNIFORM:
 328       return "unpack_uniform";
 329    case VEC4_OPCODE_DOUBLE_TO_F32:
 330       return "double_to_f32";
 331    case VEC4_OPCODE_DOUBLE_TO_D32:
 332       return "double_to_d32";
 333    case VEC4_OPCODE_DOUBLE_TO_U32:
 334       return "double_to_u32";
 335    case VEC4_OPCODE_TO_DOUBLE:
 336       return "single_to_double";
 337    case VEC4_OPCODE_PICK_LOW_32BIT:
 338       return "pick_low_32bit";
 339    case VEC4_OPCODE_PICK_HIGH_32BIT:
 340       return "pick_high_32bit";
 341    case VEC4_OPCODE_SET_LOW_32BIT:
 342       return "set_low_32bit";
 343    case VEC4_OPCODE_SET_HIGH_32BIT:
 344       return "set_high_32bit";
 345
 346    case FS_OPCODE_DDX_COARSE:
 347       return "ddx_coarse";
 348    case FS_OPCODE_DDX_FINE:
 349       return "ddx_fine";
 350    case FS_OPCODE_DDY_COARSE:
 351       return "ddy_coarse";
 352    case FS_OPCODE_DDY_FINE:
 353       return "ddy_fine";
 354
 355    case FS_OPCODE_CINTERP:
 356       return "cinterp";
 357    case FS_OPCODE_LINTERP:
 358       return "linterp";
 359
 360    case FS_OPCODE_PIXEL_X:
 361       return "pixel_x";
 362    case FS_OPCODE_PIXEL_Y:
 363       return "pixel_y";
 364
 365    case FS_OPCODE_GET_BUFFER_SIZE:
 366       return "fs_get_buffer_size";
 367
 368    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 369       return "uniform_pull_const";
 370    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 371       return "uniform_pull_const_gen7";
 372    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 373       return "varying_pull_const_gen4";
 374    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 375       return "varying_pull_const_gen7";
 376    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 377       return "varying_pull_const_logical";
 378
 379    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 380       return "mov_dispatch_to_flags";
 381    case FS_OPCODE_DISCARD_JUMP:
 382       return "discard_jump";
 383
 384    case FS_OPCODE_SET_SAMPLE_ID:
 385       return "set_sample_id";
 386
 387    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 388       return "pack_half_2x16_split";
 389    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 390       return "unpack_half_2x16_split_x";
 391    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 392       return "unpack_half_2x16_split_y";
 393
 394    case FS_OPCODE_PLACEHOLDER_HALT:
 395       return "placeholder_halt";
 396
 397    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 398       return "interp_sample";
 399    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 400       return "interp_shared_offset";
 401    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 402       return "interp_per_slot_offset";
 403
 404    case VS_OPCODE_URB_WRITE:
 405       return "vs_urb_write";
 406    case VS_OPCODE_PULL_CONSTANT_LOAD:
 407       return "pull_constant_load";
 408    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 409       return "pull_constant_load_gen7";
 410
 411    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 412       return "set_simd4x2_header_gen9";
 413
 414    case VS_OPCODE_GET_BUFFER_SIZE:
 415       return "vs_get_buffer_size";
 416
 417    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 418       return "unpack_flags_simd4x2";
 419
 420    case GS_OPCODE_URB_WRITE:
 421       return "gs_urb_write";
 422    case GS_OPCODE_URB_WRITE_ALLOCATE:
 423       return "gs_urb_write_allocate";
 424    case GS_OPCODE_THREAD_END:
 425       return "gs_thread_end";
 426    case GS_OPCODE_SET_WRITE_OFFSET:
 427       return "set_write_offset";
 428    case GS_OPCODE_SET_VERTEX_COUNT:
 429       return "set_vertex_count";
 430    case GS_OPCODE_SET_DWORD_2:
 431       return "set_dword_2";
 432    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 433       return "prepare_channel_masks";
 434    case GS_OPCODE_SET_CHANNEL_MASKS:
 435       return "set_channel_masks";
 436    case GS_OPCODE_GET_INSTANCE_ID:
 437       return "get_instance_id";
 438    case GS_OPCODE_FF_SYNC:
 439       return "ff_sync";
 440    case GS_OPCODE_SET_PRIMITIVE_ID:
 441       return "set_primitive_id";
 442    case GS_OPCODE_SVB_WRITE:
 443       return "gs_svb_write";
 444    case GS_OPCODE_SVB_SET_DST_INDEX:
 445       return "gs_svb_set_dst_index";
 446    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 447       return "gs_ff_sync_set_primitives";
 448    case CS_OPCODE_CS_TERMINATE:
 449       return "cs_terminate";
 450    case SHADER_OPCODE_BARRIER:
 451       return "barrier";
 452    case SHADER_OPCODE_MULH:
 453       return "mulh";
 454    case SHADER_OPCODE_MOV_INDIRECT:
 455       return "mov_indirect";
 456
 457    case VEC4_OPCODE_URB_READ:
 458       return "urb_read";
 459    case TCS_OPCODE_GET_INSTANCE_ID:
 460       return "tcs_get_instance_id";
 461    case TCS_OPCODE_URB_WRITE:
 462       return "tcs_urb_write";
 463    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 464       return "tcs_set_input_urb_offsets";
 465    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 466       return "tcs_set_output_urb_offsets";
 467    case TCS_OPCODE_GET_PRIMITIVE_ID:
 468       return "tcs_get_primitive_id";
 469    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 470       return "tcs_create_barrier_header";
 471    case TCS_OPCODE_SRC0_010_IS_ZERO:
 472       return "tcs_src0<0,1,0>_is_zero";
 473    case TCS_OPCODE_RELEASE_INPUT:
 474       return "tcs_release_input";
 475    case TCS_OPCODE_THREAD_END:
 476       return "tcs_thread_end";
 477    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 478       return "tes_create_input_read_header";
 479    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 480       return "tes_add_indirect_urb_offset";
 481    case TES_OPCODE_GET_PRIMITIVE_ID:
 482       return "tes_get_primitive_id";
 483    }
 484
 485    unreachable("not reached");
 486 }
 487
 488 bool
 489 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 490 {
 491    union {
 492       unsigned ud;
 493       int d;
 494       float f;
 495       double df;
 496    } imm, sat_imm = { 0 };
 497
 498    const unsigned size = type_sz(type);
 499
 500    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 501     * irrelevant, so just check the size of the type and copy from/to an
 502     * appropriately sized field.
 503     */
 504    if (size < 8)
 505       imm.ud = reg->ud;
 506    else
 507       imm.df = reg->df;
 508
 509    switch (type) {
 510    case BRW_REGISTER_TYPE_UD:
 511    case BRW_REGISTER_TYPE_D:
 512    case BRW_REGISTER_TYPE_UW:
 513    case BRW_REGISTER_TYPE_W:
 514    case BRW_REGISTER_TYPE_UQ:
 515    case BRW_REGISTER_TYPE_Q:
 516       /* Nothing to do. */
 517       return false;
 518    case BRW_REGISTER_TYPE_F:
 519       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 520       break;
 521    case BRW_REGISTER_TYPE_DF:
 522       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 523       break;
 524    case BRW_REGISTER_TYPE_UB:
 525    case BRW_REGISTER_TYPE_B:
 526       unreachable("no UB/B immediates");
 527    case BRW_REGISTER_TYPE_V:
 528    case BRW_REGISTER_TYPE_UV:
 529    case BRW_REGISTER_TYPE_VF:
 530       unreachable("unimplemented: saturate vector immediate");
 531    case BRW_REGISTER_TYPE_HF:
 532       unreachable("unimplemented: saturate HF immediate");
 533    }
 534
 535    if (size < 8) {
 536       if (imm.ud != sat_imm.ud) {
 537          reg->ud = sat_imm.ud;
 538          return true;
 539       }
 540    } else {
 541       if (imm.df != sat_imm.df) {
 542          reg->df = sat_imm.df;
 543          return true;
 544       }
 545    }
 546    return false;
 547 }
 548
 549 bool
 550 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 551 {
 552    switch (type) {
 553    case BRW_REGISTER_TYPE_D:
 554    case BRW_REGISTER_TYPE_UD:
 555       reg->d = -reg->d;
 556       return true;
 557    case BRW_REGISTER_TYPE_W:
 558    case BRW_REGISTER_TYPE_UW:
 559       reg->d = -(int16_t)reg->ud;
 560       return true;
 561    case BRW_REGISTER_TYPE_F:
 562       reg->f = -reg->f;
 563       return true;
 564    case BRW_REGISTER_TYPE_VF:
 565       reg->ud ^= 0x80808080;
 566       return true;
 567    case BRW_REGISTER_TYPE_DF:
 568       reg->df = -reg->df;
 569       return true;
 570    case BRW_REGISTER_TYPE_UQ:
 571    case BRW_REGISTER_TYPE_Q:
 572       reg->d64 = -reg->d64;
 573       return true;
 574    case BRW_REGISTER_TYPE_UB:
 575    case BRW_REGISTER_TYPE_B:
 576       unreachable("no UB/B immediates");
 577    case BRW_REGISTER_TYPE_UV:
 578    case BRW_REGISTER_TYPE_V:
 579       assert(!"unimplemented: negate UV/V immediate");
 580    case BRW_REGISTER_TYPE_HF:
 581       assert(!"unimplemented: negate HF immediate");
 582    }
 583
 584    return false;
 585 }
 586
 587 bool
 588 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 589 {
 590    switch (type) {
 591    case BRW_REGISTER_TYPE_D:
 592       reg->d = abs(reg->d);
 593       return true;
 594    case BRW_REGISTER_TYPE_W:
 595       reg->d = abs((int16_t)reg->ud);
 596       return true;
 597    case BRW_REGISTER_TYPE_F:
 598       reg->f = fabsf(reg->f);
 599       return true;
 600    case BRW_REGISTER_TYPE_DF:
 601       reg->df = fabs(reg->df);
 602       return true;
 603    case BRW_REGISTER_TYPE_VF:
 604       reg->ud &= ~0x80808080;
 605       return true;
 606    case BRW_REGISTER_TYPE_Q:
 607       reg->d64 = imaxabs(reg->d64);
 608       return true;
 609    case BRW_REGISTER_TYPE_UB:
 610    case BRW_REGISTER_TYPE_B:
 611       unreachable("no UB/B immediates");
 612    case BRW_REGISTER_TYPE_UQ:
 613    case BRW_REGISTER_TYPE_UD:
 614    case BRW_REGISTER_TYPE_UW:
 615    case BRW_REGISTER_TYPE_UV:
 616       /* Presumably the absolute value modifier on an unsigned source is a
 617        * nop, but it would be nice to confirm.
 618        */
 619       assert(!"unimplemented: abs unsigned immediate");
 620    case BRW_REGISTER_TYPE_V:
 621       assert(!"unimplemented: abs V immediate");
 622    case BRW_REGISTER_TYPE_HF:
 623       assert(!"unimplemented: abs HF immediate");
 624    }
 625
 626    return false;
 627 }
 628
 629 /**
 630  * Get the appropriate atomic op for an image atomic intrinsic.
 631  */
 632 unsigned
 633 get_atomic_counter_op(nir_intrinsic_op op)
 634 {
 635    switch (op) {
 636    case nir_intrinsic_atomic_counter_inc:
 637       return BRW_AOP_INC;
 638    case nir_intrinsic_atomic_counter_dec:
 639       return BRW_AOP_PREDEC;
 640    case nir_intrinsic_atomic_counter_add:
 641       return BRW_AOP_ADD;
 642    case nir_intrinsic_atomic_counter_min:
 643       return BRW_AOP_UMIN;
 644    case nir_intrinsic_atomic_counter_max:
 645       return BRW_AOP_UMAX;
 646    case nir_intrinsic_atomic_counter_and:
 647       return BRW_AOP_AND;
 648    case nir_intrinsic_atomic_counter_or:
 649       return BRW_AOP_OR;
 650    case nir_intrinsic_atomic_counter_xor:
 651       return BRW_AOP_XOR;
 652    case nir_intrinsic_atomic_counter_exchange:
 653       return BRW_AOP_MOV;
 654    case nir_intrinsic_atomic_counter_comp_swap:
 655       return BRW_AOP_CMPWR;
 656    default:
 657       unreachable("Not reachable.");
 658    }
 659 }
 660
 661 backend_shader::backend_shader(const struct brw_compiler *compiler,
 662                                void *log_data,
 663                                void *mem_ctx,
 664                                const nir_shader *shader,
 665                                struct brw_stage_prog_data *stage_prog_data)
 666    : compiler(compiler),
 667      log_data(log_data),
 668      devinfo(compiler->devinfo),
 669      nir(shader),
 670      stage_prog_data(stage_prog_data),
 671      mem_ctx(mem_ctx),
 672      cfg(NULL),
 673      stage(shader->info.stage)
 674 {
 675    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 676    stage_name = _mesa_shader_stage_to_string(stage);
 677    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 678 }
 679
 680 bool
 681 backend_reg::equals(const backend_reg &r) const
 682 {
 683    return brw_regs_equal(this, &r) && offset == r.offset;
 684 }
 685
 686 bool
 687 backend_reg::is_zero() const
 688 {
 689    if (file != IMM)
 690       return false;
 691
 692    switch (type) {
 693    case BRW_REGISTER_TYPE_F:
 694       return f == 0;
 695    case BRW_REGISTER_TYPE_DF:
 696       return df == 0;
 697    case BRW_REGISTER_TYPE_D:
 698    case BRW_REGISTER_TYPE_UD:
 699       return d == 0;
 700    case BRW_REGISTER_TYPE_UQ:
 701    case BRW_REGISTER_TYPE_Q:
 702       return u64 == 0;
 703    default:
 704       return false;
 705    }
 706 }
 707
 708 bool
 709 backend_reg::is_one() const
 710 {
 711    if (file != IMM)
 712       return false;
 713
 714    switch (type) {
 715    case BRW_REGISTER_TYPE_F:
 716       return f == 1.0f;
 717    case BRW_REGISTER_TYPE_DF:
 718       return df == 1.0;
 719    case BRW_REGISTER_TYPE_D:
 720    case BRW_REGISTER_TYPE_UD:
 721       return d == 1;
 722    case BRW_REGISTER_TYPE_UQ:
 723    case BRW_REGISTER_TYPE_Q:
 724       return u64 == 1;
 725    default:
 726       return false;
 727    }
 728 }
 729
 730 bool
 731 backend_reg::is_negative_one() const
 732 {
 733    if (file != IMM)
 734       return false;
 735
 736    switch (type) {
 737    case BRW_REGISTER_TYPE_F:
 738       return f == -1.0;
 739    case BRW_REGISTER_TYPE_DF:
 740       return df == -1.0;
 741    case BRW_REGISTER_TYPE_D:
 742       return d == -1;
 743    case BRW_REGISTER_TYPE_Q:
 744       return d64 == -1;
 745    default:
 746       return false;
 747    }
 748 }
 749
 750 bool
 751 backend_reg::is_null() const
 752 {
 753    return file == ARF && nr == BRW_ARF_NULL;
 754 }
 755
 756
 757 bool
 758 backend_reg::is_accumulator() const
 759 {
 760    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 761 }
 762
 763 bool
 764 backend_instruction::is_commutative() const
 765 {
 766    switch (opcode) {
 767    case BRW_OPCODE_AND:
 768    case BRW_OPCODE_OR:
 769    case BRW_OPCODE_XOR:
 770    case BRW_OPCODE_ADD:
 771    case BRW_OPCODE_MUL:
 772    case SHADER_OPCODE_MULH:
 773       return true;
 774    case BRW_OPCODE_SEL:
 775       /* MIN and MAX are commutative. */
 776       if (conditional_mod == BRW_CONDITIONAL_GE ||
 777           conditional_mod == BRW_CONDITIONAL_L) {
 778          return true;
 779       }
 780       /* fallthrough */
 781    default:
 782       return false;
 783    }
 784 }
 785
 786 bool
 787 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 788 {
 789    return ::is_3src(devinfo, opcode);
 790 }
 791
 792 bool
 793 backend_instruction::is_tex() const
 794 {
 795    return (opcode == SHADER_OPCODE_TEX ||
 796            opcode == FS_OPCODE_TXB ||
 797            opcode == SHADER_OPCODE_TXD ||
 798            opcode == SHADER_OPCODE_TXF ||
 799            opcode == SHADER_OPCODE_TXF_LZ ||
 800            opcode == SHADER_OPCODE_TXF_CMS ||
 801            opcode == SHADER_OPCODE_TXF_CMS_W ||
 802            opcode == SHADER_OPCODE_TXF_UMS ||
 803            opcode == SHADER_OPCODE_TXF_MCS ||
 804            opcode == SHADER_OPCODE_TXL ||
 805            opcode == SHADER_OPCODE_TXL_LZ ||
 806            opcode == SHADER_OPCODE_TXS ||
 807            opcode == SHADER_OPCODE_LOD ||
 808            opcode == SHADER_OPCODE_TG4 ||
 809            opcode == SHADER_OPCODE_TG4_OFFSET ||
 810            opcode == SHADER_OPCODE_SAMPLEINFO);
 811 }
 812
 813 bool
 814 backend_instruction::is_math() const
 815 {
 816    return (opcode == SHADER_OPCODE_RCP ||
 817            opcode == SHADER_OPCODE_RSQ ||
 818            opcode == SHADER_OPCODE_SQRT ||
 819            opcode == SHADER_OPCODE_EXP2 ||
 820            opcode == SHADER_OPCODE_LOG2 ||
 821            opcode == SHADER_OPCODE_SIN ||
 822            opcode == SHADER_OPCODE_COS ||
 823            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 824            opcode == SHADER_OPCODE_INT_REMAINDER ||
 825            opcode == SHADER_OPCODE_POW);
 826 }
 827
 828 bool
 829 backend_instruction::is_control_flow() const
 830 {
 831    switch (opcode) {
 832    case BRW_OPCODE_DO:
 833    case BRW_OPCODE_WHILE:
 834    case BRW_OPCODE_IF:
 835    case BRW_OPCODE_ELSE:
 836    case BRW_OPCODE_ENDIF:
 837    case BRW_OPCODE_BREAK:
 838    case BRW_OPCODE_CONTINUE:
 839       return true;
 840    default:
 841       return false;
 842    }
 843 }
 844
 845 bool
 846 backend_instruction::can_do_source_mods() const
 847 {
 848    switch (opcode) {
 849    case BRW_OPCODE_ADDC:
 850    case BRW_OPCODE_BFE:
 851    case BRW_OPCODE_BFI1:
 852    case BRW_OPCODE_BFI2:
 853    case BRW_OPCODE_BFREV:
 854    case BRW_OPCODE_CBIT:
 855    case BRW_OPCODE_FBH:
 856    case BRW_OPCODE_FBL:
 857    case BRW_OPCODE_SUBB:
 858       return false;
 859    default:
 860       return true;
 861    }
 862 }
 863
 864 bool
 865 backend_instruction::can_do_saturate() const
 866 {
 867    switch (opcode) {
 868    case BRW_OPCODE_ADD:
 869    case BRW_OPCODE_ASR:
 870    case BRW_OPCODE_AVG:
 871    case BRW_OPCODE_DP2:
 872    case BRW_OPCODE_DP3:
 873    case BRW_OPCODE_DP4:
 874    case BRW_OPCODE_DPH:
 875    case BRW_OPCODE_F16TO32:
 876    case BRW_OPCODE_F32TO16:
 877    case BRW_OPCODE_LINE:
 878    case BRW_OPCODE_LRP:
 879    case BRW_OPCODE_MAC:
 880    case BRW_OPCODE_MAD:
 881    case BRW_OPCODE_MATH:
 882    case BRW_OPCODE_MOV:
 883    case BRW_OPCODE_MUL:
 884    case SHADER_OPCODE_MULH:
 885    case BRW_OPCODE_PLN:
 886    case BRW_OPCODE_RNDD:
 887    case BRW_OPCODE_RNDE:
 888    case BRW_OPCODE_RNDU:
 889    case BRW_OPCODE_RNDZ:
 890    case BRW_OPCODE_SEL:
 891    case BRW_OPCODE_SHL:
 892    case BRW_OPCODE_SHR:
 893    case FS_OPCODE_LINTERP:
 894    case SHADER_OPCODE_COS:
 895    case SHADER_OPCODE_EXP2:
 896    case SHADER_OPCODE_LOG2:
 897    case SHADER_OPCODE_POW:
 898    case SHADER_OPCODE_RCP:
 899    case SHADER_OPCODE_RSQ:
 900    case SHADER_OPCODE_SIN:
 901    case SHADER_OPCODE_SQRT:
 902       return true;
 903    default:
 904       return false;
 905    }
 906 }
 907
 908 bool
 909 backend_instruction::can_do_cmod() const
 910 {
 911    switch (opcode) {
 912    case BRW_OPCODE_ADD:
 913    case BRW_OPCODE_ADDC:
 914    case BRW_OPCODE_AND:
 915    case BRW_OPCODE_ASR:
 916    case BRW_OPCODE_AVG:
 917    case BRW_OPCODE_CMP:
 918    case BRW_OPCODE_CMPN:
 919    case BRW_OPCODE_DP2:
 920    case BRW_OPCODE_DP3:
 921    case BRW_OPCODE_DP4:
 922    case BRW_OPCODE_DPH:
 923    case BRW_OPCODE_F16TO32:
 924    case BRW_OPCODE_F32TO16:
 925    case BRW_OPCODE_FRC:
 926    case BRW_OPCODE_LINE:
 927    case BRW_OPCODE_LRP:
 928    case BRW_OPCODE_LZD:
 929    case BRW_OPCODE_MAC:
 930    case BRW_OPCODE_MACH:
 931    case BRW_OPCODE_MAD:
 932    case BRW_OPCODE_MOV:
 933    case BRW_OPCODE_MUL:
 934    case BRW_OPCODE_NOT:
 935    case BRW_OPCODE_OR:
 936    case BRW_OPCODE_PLN:
 937    case BRW_OPCODE_RNDD:
 938    case BRW_OPCODE_RNDE:
 939    case BRW_OPCODE_RNDU:
 940    case BRW_OPCODE_RNDZ:
 941    case BRW_OPCODE_SAD2:
 942    case BRW_OPCODE_SADA2:
 943    case BRW_OPCODE_SHL:
 944    case BRW_OPCODE_SHR:
 945    case BRW_OPCODE_SUBB:
 946    case BRW_OPCODE_XOR:
 947    case FS_OPCODE_CINTERP:
 948    case FS_OPCODE_LINTERP:
 949       return true;
 950    default:
 951       return false;
 952    }
 953 }
 954
 955 bool
 956 backend_instruction::reads_accumulator_implicitly() const
 957 {
 958    switch (opcode) {
 959    case BRW_OPCODE_MAC:
 960    case BRW_OPCODE_MACH:
 961    case BRW_OPCODE_SADA2:
 962       return true;
 963    default:
 964       return false;
 965    }
 966 }
 967
 968 bool
 969 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 970 {
 971    return writes_accumulator ||
 972           (devinfo->gen < 6 &&
 973            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 974             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 975              opcode != FS_OPCODE_CINTERP)));
 976 }
 977
 978 bool
 979 backend_instruction::has_side_effects() const
 980 {
 981    switch (opcode) {
 982    case SHADER_OPCODE_UNTYPED_ATOMIC:
 983    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 984    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 985    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 986    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 987    case SHADER_OPCODE_TYPED_ATOMIC:
 988    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 989    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 990    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 991    case SHADER_OPCODE_MEMORY_FENCE:
 992    case SHADER_OPCODE_URB_WRITE_SIMD8:
 993    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 994    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 995    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 996    case FS_OPCODE_FB_WRITE:
 997    case FS_OPCODE_FB_WRITE_LOGICAL:
 998    case SHADER_OPCODE_BARRIER:
 999    case TCS_OPCODE_URB_WRITE:
1000    case TCS_OPCODE_RELEASE_INPUT:
1001       return true;
1002    default:
1003       return eot;
1004    }
1005 }
1006
1007 bool
1008 backend_instruction::is_volatile() const
1009 {
1010    switch (opcode) {
1011    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1012    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1013    case SHADER_OPCODE_TYPED_SURFACE_READ:
1014    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1015    case SHADER_OPCODE_URB_READ_SIMD8:
1016    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1017    case VEC4_OPCODE_URB_READ:
1018       return true;
1019    default:
1020       return false;
1021    }
1022 }
1023
1024 #ifndef NDEBUG
1025 static bool
1026 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1027 {
1028    bool found = false;
1029    foreach_inst_in_block (backend_instruction, i, block) {
1030       if (inst == i) {
1031          found = true;
1032       }
1033    }
1034    return found;
1035 }
1036 #endif
1037
1038 static void
1039 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1040 {
1041    for (bblock_t *block_iter = start_block->next();
1042         block_iter;
1043         block_iter = block_iter->next()) {
1044       block_iter->start_ip += ip_adjustment;
1045       block_iter->end_ip += ip_adjustment;
1046    }
1047 }
1048
1049 void
1050 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1051 {
1052    assert(this != inst);
1053
1054    if (!this->is_head_sentinel())
1055       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1056
1057    block->end_ip++;
1058
1059    adjust_later_block_ips(block, 1);
1060
1061    exec_node::insert_after(inst);
1062 }
1063
1064 void
1065 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1066 {
1067    assert(this != inst);
1068
1069    if (!this->is_tail_sentinel())
1070       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1071
1072    block->end_ip++;
1073
1074    adjust_later_block_ips(block, 1);
1075
1076    exec_node::insert_before(inst);
1077 }
1078
1079 void
1080 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1081 {
1082    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1083
1084    unsigned num_inst = list->length();
1085
1086    block->end_ip += num_inst;
1087
1088    adjust_later_block_ips(block, num_inst);
1089
1090    exec_node::insert_before(list);
1091 }
1092
1093 void
1094 backend_instruction::remove(bblock_t *block)
1095 {
1096    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1097
1098    adjust_later_block_ips(block, -1);
1099
1100    if (block->start_ip == block->end_ip) {
1101       block->cfg->remove_block(block);
1102    } else {
1103       block->end_ip--;
1104    }
1105
1106    exec_node::remove();
1107 }
1108
1109 void
1110 backend_shader::dump_instructions()
1111 {
1112    dump_instructions(NULL);
1113 }
1114
1115 void
1116 backend_shader::dump_instructions(const char *name)
1117 {
1118    FILE *file = stderr;
1119    if (name && geteuid() != 0) {
1120       file = fopen(name, "w");
1121       if (!file)
1122          file = stderr;
1123    }
1124
1125    if (cfg) {
1126       int ip = 0;
1127       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1128          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1129             fprintf(file, "%4d: ", ip++);
1130          dump_instruction(inst, file);
1131       }
1132    } else {
1133       int ip = 0;
1134       foreach_in_list(backend_instruction, inst, &instructions) {
1135          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1136             fprintf(file, "%4d: ", ip++);
1137          dump_instruction(inst, file);
1138       }
1139    }
1140
1141    if (file != stderr) {
1142       fclose(file);
1143    }
1144 }
1145
1146 void
1147 backend_shader::calculate_cfg()
1148 {
1149    if (this->cfg)
1150       return;
1151    cfg = new(mem_ctx) cfg_t(&this->instructions);
1152 }
1153
1154 extern "C" const unsigned *
1155 brw_compile_tes(const struct brw_compiler *compiler,
1156                 void *log_data,
1157                 void *mem_ctx,
1158                 const struct brw_tes_prog_key *key,
1159                 const struct brw_vue_map *input_vue_map,
1160                 struct brw_tes_prog_data *prog_data,
1161                 const nir_shader *src_shader,
1162                 struct gl_program *prog,
1163                 int shader_time_index,
1164                 unsigned *final_assembly_size,
1165                 char **error_str)
1166 {
1167    const struct gen_device_info *devinfo = compiler->devinfo;
1168    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1169
1170    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1171    nir->info.inputs_read = key->inputs_read;
1172    nir->info.patch_inputs_read = key->patch_inputs_read;
1173
1174    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1175    brw_nir_lower_tes_inputs(nir, input_vue_map);
1176    brw_nir_lower_vue_outputs(nir, is_scalar);
1177    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1178
1179    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1180                        nir->info.outputs_written,
1181                        nir->info.separate_shader);
1182
1183    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1184
1185    assert(output_size_bytes >= 1);
1186    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1187       if (error_str)
1188          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1189       return NULL;
1190    }
1191
1192    prog_data->base.clip_distance_mask =
1193       ((1 << nir->info.clip_distance_array_size) - 1);
1194    prog_data->base.cull_distance_mask =
1195       ((1 << nir->info.cull_distance_array_size) - 1) <<
1196       nir->info.clip_distance_array_size;
1197
1198    /* URB entry sizes are stored as a multiple of 64 bytes. */
1199    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1200
1201    /* On Cannonlake software shall not program an allocation size that
1202     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1203     */
1204    if (devinfo->gen == 10 &&
1205        prog_data->base.urb_entry_size % 3 == 0)
1206       prog_data->base.urb_entry_size++;
1207
1208    prog_data->base.urb_read_length = 0;
1209
1210    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1211    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1212                  TESS_SPACING_FRACTIONAL_ODD - 1);
1213    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1214                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1215
1216    prog_data->partitioning =
1217       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1218
1219    switch (nir->info.tess.primitive_mode) {
1220    case GL_QUADS:
1221       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1222       break;
1223    case GL_TRIANGLES:
1224       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1225       break;
1226    case GL_ISOLINES:
1227       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1228       break;
1229    default:
1230       unreachable("invalid domain shader primitive mode");
1231    }
1232
1233    if (nir->info.tess.point_mode) {
1234       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1235    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1236       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1237    } else {
1238       /* Hardware winding order is backwards from OpenGL */
1239       prog_data->output_topology =
1240          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1241                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1242    }
1243
1244    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1245       fprintf(stderr, "TES Input ");
1246       brw_print_vue_map(stderr, input_vue_map);
1247       fprintf(stderr, "TES Output ");
1248       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1249    }
1250
1251    if (is_scalar) {
1252       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1253                    &prog_data->base.base, NULL, nir, 8,
1254                    shader_time_index, input_vue_map);
1255       if (!v.run_tes()) {
1256          if (error_str)
1257             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1258          return NULL;
1259       }
1260
1261       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1262       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1263
1264       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1265                      &prog_data->base.base, v.promoted_constants, false,
1266                      MESA_SHADER_TESS_EVAL);
1267       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1268          g.enable_debug(ralloc_asprintf(mem_ctx,
1269                                         "%s tessellation evaluation shader %s",
1270                                         nir->info.label ? nir->info.label
1271                                                         : "unnamed",
1272                                         nir->info.name));
1273       }
1274
1275       g.generate_code(v.cfg, 8);
1276
1277       return g.get_assembly(final_assembly_size);
1278    } else {
1279       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1280                               nir, mem_ctx, shader_time_index);
1281       if (!v.run()) {
1282          if (error_str)
1283             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1284          return NULL;
1285       }
1286
1287       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1288          v.dump_instructions();
1289
1290       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1291                                         &prog_data->base, v.cfg,
1292                                         final_assembly_size);
1293    }
1294 }