src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "common/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_INT8:
  48       return BRW_REGISTER_TYPE_B;
  49    case GLSL_TYPE_UINT:
  50       return BRW_REGISTER_TYPE_UD;
  51    case GLSL_TYPE_UINT16:
  52       return BRW_REGISTER_TYPE_UW;
  53    case GLSL_TYPE_UINT8:
  54       return BRW_REGISTER_TYPE_UB;
  55    case GLSL_TYPE_ARRAY:
  56       return brw_type_for_base_type(type->fields.array);
  57    case GLSL_TYPE_STRUCT:
  58    case GLSL_TYPE_SAMPLER:
  59    case GLSL_TYPE_ATOMIC_UINT:
  60       /* These should be overridden with the type of the member when
  61        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  62        * way to trip up if we don't.
  63        */
  64       return BRW_REGISTER_TYPE_UD;
  65    case GLSL_TYPE_IMAGE:
  66       return BRW_REGISTER_TYPE_UD;
  67    case GLSL_TYPE_DOUBLE:
  68       return BRW_REGISTER_TYPE_DF;
  69    case GLSL_TYPE_UINT64:
  70       return BRW_REGISTER_TYPE_UQ;
  71    case GLSL_TYPE_INT64:
  72       return BRW_REGISTER_TYPE_Q;
  73    case GLSL_TYPE_VOID:
  74    case GLSL_TYPE_ERROR:
  75    case GLSL_TYPE_INTERFACE:
  76    case GLSL_TYPE_FUNCTION:
  77       unreachable("not reached");
  78    }
  79
  80    return BRW_REGISTER_TYPE_F;
  81 }
  82
  83 enum brw_conditional_mod
  84 brw_conditional_for_comparison(unsigned int op)
  85 {
  86    switch (op) {
  87    case ir_binop_less:
  88       return BRW_CONDITIONAL_L;
  89    case ir_binop_gequal:
  90       return BRW_CONDITIONAL_GE;
  91    case ir_binop_equal:
  92    case ir_binop_all_equal: /* same as equal for scalars */
  93       return BRW_CONDITIONAL_Z;
  94    case ir_binop_nequal:
  95    case ir_binop_any_nequal: /* same as nequal for scalars */
  96       return BRW_CONDITIONAL_NZ;
  97    default:
  98       unreachable("not reached: bad operation for comparison");
  99    }
 100 }
 101
 102 uint32_t
 103 brw_math_function(enum opcode op)
 104 {
 105    switch (op) {
 106    case SHADER_OPCODE_RCP:
 107       return BRW_MATH_FUNCTION_INV;
 108    case SHADER_OPCODE_RSQ:
 109       return BRW_MATH_FUNCTION_RSQ;
 110    case SHADER_OPCODE_SQRT:
 111       return BRW_MATH_FUNCTION_SQRT;
 112    case SHADER_OPCODE_EXP2:
 113       return BRW_MATH_FUNCTION_EXP;
 114    case SHADER_OPCODE_LOG2:
 115       return BRW_MATH_FUNCTION_LOG;
 116    case SHADER_OPCODE_POW:
 117       return BRW_MATH_FUNCTION_POW;
 118    case SHADER_OPCODE_SIN:
 119       return BRW_MATH_FUNCTION_SIN;
 120    case SHADER_OPCODE_COS:
 121       return BRW_MATH_FUNCTION_COS;
 122    case SHADER_OPCODE_INT_QUOTIENT:
 123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 124    case SHADER_OPCODE_INT_REMAINDER:
 125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 126    default:
 127       unreachable("not reached: unknown math function");
 128    }
 129 }
 130
 131 bool
 132 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 133 {
 134    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 135
 136    /* offset out of bounds; caller will handle it. */
 137    for (unsigned i = 0; i < num_components; i++)
 138       if (offsets[i] > 7 || offsets[i] < -8)
 139          return false;
 140
 141    /* Combine all three offsets into a single unsigned dword:
 142     *
 143     *    bits 11:8 - U Offset (X component)
 144     *    bits  7:4 - V Offset (Y component)
 145     *    bits  3:0 - R Offset (Z component)
 146     */
 147    *offset_bits = 0;
 148    for (unsigned i = 0; i < num_components; i++) {
 149       const unsigned shift = 4 * (2 - i);
 150       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 151    }
 152    return true;
 153 }
 154
 155 const char *
 156 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 157 {
 158    switch (op) {
 159    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 160       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 161        * start of a loop in the IR.
 162        */
 163       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 164          return "do";
 165
 166       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 167        * then to mark that we want to do the conversion.
 168        */
 169       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 170          return "f32to16";
 171
 172       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 173          return "f16to32";
 174
 175       assert(brw_opcode_desc(devinfo, op)->name);
 176       return brw_opcode_desc(devinfo, op)->name;
 177    case FS_OPCODE_FB_WRITE:
 178       return "fb_write";
 179    case FS_OPCODE_FB_WRITE_LOGICAL:
 180       return "fb_write_logical";
 181    case FS_OPCODE_REP_FB_WRITE:
 182       return "rep_fb_write";
 183    case FS_OPCODE_FB_READ:
 184       return "fb_read";
 185    case FS_OPCODE_FB_READ_LOGICAL:
 186       return "fb_read_logical";
 187
 188    case SHADER_OPCODE_RCP:
 189       return "rcp";
 190    case SHADER_OPCODE_RSQ:
 191       return "rsq";
 192    case SHADER_OPCODE_SQRT:
 193       return "sqrt";
 194    case SHADER_OPCODE_EXP2:
 195       return "exp2";
 196    case SHADER_OPCODE_LOG2:
 197       return "log2";
 198    case SHADER_OPCODE_POW:
 199       return "pow";
 200    case SHADER_OPCODE_INT_QUOTIENT:
 201       return "int_quot";
 202    case SHADER_OPCODE_INT_REMAINDER:
 203       return "int_rem";
 204    case SHADER_OPCODE_SIN:
 205       return "sin";
 206    case SHADER_OPCODE_COS:
 207       return "cos";
 208
 209    case SHADER_OPCODE_SEND:
 210       return "send";
 211
 212    case SHADER_OPCODE_TEX:
 213       return "tex";
 214    case SHADER_OPCODE_TEX_LOGICAL:
 215       return "tex_logical";
 216    case SHADER_OPCODE_TXD:
 217       return "txd";
 218    case SHADER_OPCODE_TXD_LOGICAL:
 219       return "txd_logical";
 220    case SHADER_OPCODE_TXF:
 221       return "txf";
 222    case SHADER_OPCODE_TXF_LOGICAL:
 223       return "txf_logical";
 224    case SHADER_OPCODE_TXF_LZ:
 225       return "txf_lz";
 226    case SHADER_OPCODE_TXL:
 227       return "txl";
 228    case SHADER_OPCODE_TXL_LOGICAL:
 229       return "txl_logical";
 230    case SHADER_OPCODE_TXL_LZ:
 231       return "txl_lz";
 232    case SHADER_OPCODE_TXS:
 233       return "txs";
 234    case SHADER_OPCODE_TXS_LOGICAL:
 235       return "txs_logical";
 236    case FS_OPCODE_TXB:
 237       return "txb";
 238    case FS_OPCODE_TXB_LOGICAL:
 239       return "txb_logical";
 240    case SHADER_OPCODE_TXF_CMS:
 241       return "txf_cms";
 242    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 243       return "txf_cms_logical";
 244    case SHADER_OPCODE_TXF_CMS_W:
 245       return "txf_cms_w";
 246    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 247       return "txf_cms_w_logical";
 248    case SHADER_OPCODE_TXF_UMS:
 249       return "txf_ums";
 250    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 251       return "txf_ums_logical";
 252    case SHADER_OPCODE_TXF_MCS:
 253       return "txf_mcs";
 254    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 255       return "txf_mcs_logical";
 256    case SHADER_OPCODE_LOD:
 257       return "lod";
 258    case SHADER_OPCODE_LOD_LOGICAL:
 259       return "lod_logical";
 260    case SHADER_OPCODE_TG4:
 261       return "tg4";
 262    case SHADER_OPCODE_TG4_LOGICAL:
 263       return "tg4_logical";
 264    case SHADER_OPCODE_TG4_OFFSET:
 265       return "tg4_offset";
 266    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 267       return "tg4_offset_logical";
 268    case SHADER_OPCODE_SAMPLEINFO:
 269       return "sampleinfo";
 270    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 271       return "sampleinfo_logical";
 272
 273    case SHADER_OPCODE_IMAGE_SIZE:
 274       return "image_size";
 275
 276    case SHADER_OPCODE_SHADER_TIME_ADD:
 277       return "shader_time_add";
 278
 279    case SHADER_OPCODE_UNTYPED_ATOMIC:
 280       return "untyped_atomic";
 281    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 282       return "untyped_atomic_logical";
 283    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT:
 284       return "untyped_atomic_float";
 285    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 286       return "untyped_atomic_float_logical";
 287    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 288       return "untyped_surface_read";
 289    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 290       return "untyped_surface_read_logical";
 291    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 292       return "untyped_surface_write";
 293    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 294       return "untyped_surface_write_logical";
 295    case SHADER_OPCODE_TYPED_ATOMIC:
 296       return "typed_atomic";
 297    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 298       return "typed_atomic_logical";
 299    case SHADER_OPCODE_TYPED_SURFACE_READ:
 300       return "typed_surface_read";
 301    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 302       return "typed_surface_read_logical";
 303    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 304       return "typed_surface_write";
 305    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 306       return "typed_surface_write_logical";
 307    case SHADER_OPCODE_MEMORY_FENCE:
 308       return "memory_fence";
 309    case SHADER_OPCODE_INTERLOCK:
 310       /* For an interlock we actually issue a memory fence via sendc. */
 311       return "interlock";
 312
 313    case SHADER_OPCODE_BYTE_SCATTERED_READ:
 314       return "byte_scattered_read";
 315    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 316       return "byte_scattered_read_logical";
 317    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
 318       return "byte_scattered_write";
 319    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 320       return "byte_scattered_write_logical";
 321
 322    case SHADER_OPCODE_LOAD_PAYLOAD:
 323       return "load_payload";
 324    case FS_OPCODE_PACK:
 325       return "pack";
 326
 327    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 328       return "gen4_scratch_read";
 329    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 330       return "gen4_scratch_write";
 331    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 332       return "gen7_scratch_read";
 333    case SHADER_OPCODE_URB_WRITE_SIMD8:
 334       return "gen8_urb_write_simd8";
 335    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 336       return "gen8_urb_write_simd8_per_slot";
 337    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 338       return "gen8_urb_write_simd8_masked";
 339    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 340       return "gen8_urb_write_simd8_masked_per_slot";
 341    case SHADER_OPCODE_URB_READ_SIMD8:
 342       return "urb_read_simd8";
 343    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 344       return "urb_read_simd8_per_slot";
 345
 346    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 347       return "find_live_channel";
 348    case SHADER_OPCODE_BROADCAST:
 349       return "broadcast";
 350    case SHADER_OPCODE_SHUFFLE:
 351       return "shuffle";
 352    case SHADER_OPCODE_SEL_EXEC:
 353       return "sel_exec";
 354    case SHADER_OPCODE_QUAD_SWIZZLE:
 355       return "quad_swizzle";
 356    case SHADER_OPCODE_CLUSTER_BROADCAST:
 357       return "cluster_broadcast";
 358
 359    case SHADER_OPCODE_GET_BUFFER_SIZE:
 360       return "get_buffer_size";
 361
 362    case VEC4_OPCODE_MOV_BYTES:
 363       return "mov_bytes";
 364    case VEC4_OPCODE_PACK_BYTES:
 365       return "pack_bytes";
 366    case VEC4_OPCODE_UNPACK_UNIFORM:
 367       return "unpack_uniform";
 368    case VEC4_OPCODE_DOUBLE_TO_F32:
 369       return "double_to_f32";
 370    case VEC4_OPCODE_DOUBLE_TO_D32:
 371       return "double_to_d32";
 372    case VEC4_OPCODE_DOUBLE_TO_U32:
 373       return "double_to_u32";
 374    case VEC4_OPCODE_TO_DOUBLE:
 375       return "single_to_double";
 376    case VEC4_OPCODE_PICK_LOW_32BIT:
 377       return "pick_low_32bit";
 378    case VEC4_OPCODE_PICK_HIGH_32BIT:
 379       return "pick_high_32bit";
 380    case VEC4_OPCODE_SET_LOW_32BIT:
 381       return "set_low_32bit";
 382    case VEC4_OPCODE_SET_HIGH_32BIT:
 383       return "set_high_32bit";
 384
 385    case FS_OPCODE_DDX_COARSE:
 386       return "ddx_coarse";
 387    case FS_OPCODE_DDX_FINE:
 388       return "ddx_fine";
 389    case FS_OPCODE_DDY_COARSE:
 390       return "ddy_coarse";
 391    case FS_OPCODE_DDY_FINE:
 392       return "ddy_fine";
 393
 394    case FS_OPCODE_LINTERP:
 395       return "linterp";
 396
 397    case FS_OPCODE_PIXEL_X:
 398       return "pixel_x";
 399    case FS_OPCODE_PIXEL_Y:
 400       return "pixel_y";
 401
 402    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 403       return "uniform_pull_const";
 404    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 405       return "uniform_pull_const_gen7";
 406    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 407       return "varying_pull_const_gen4";
 408    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 409       return "varying_pull_const_gen7";
 410    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 411       return "varying_pull_const_logical";
 412
 413    case FS_OPCODE_DISCARD_JUMP:
 414       return "discard_jump";
 415
 416    case FS_OPCODE_SET_SAMPLE_ID:
 417       return "set_sample_id";
 418
 419    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 420       return "pack_half_2x16_split";
 421
 422    case FS_OPCODE_PLACEHOLDER_HALT:
 423       return "placeholder_halt";
 424
 425    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 426       return "interp_sample";
 427    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 428       return "interp_shared_offset";
 429    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 430       return "interp_per_slot_offset";
 431
 432    case VS_OPCODE_URB_WRITE:
 433       return "vs_urb_write";
 434    case VS_OPCODE_PULL_CONSTANT_LOAD:
 435       return "pull_constant_load";
 436    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 437       return "pull_constant_load_gen7";
 438
 439    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 440       return "set_simd4x2_header_gen9";
 441
 442    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 443       return "unpack_flags_simd4x2";
 444
 445    case GS_OPCODE_URB_WRITE:
 446       return "gs_urb_write";
 447    case GS_OPCODE_URB_WRITE_ALLOCATE:
 448       return "gs_urb_write_allocate";
 449    case GS_OPCODE_THREAD_END:
 450       return "gs_thread_end";
 451    case GS_OPCODE_SET_WRITE_OFFSET:
 452       return "set_write_offset";
 453    case GS_OPCODE_SET_VERTEX_COUNT:
 454       return "set_vertex_count";
 455    case GS_OPCODE_SET_DWORD_2:
 456       return "set_dword_2";
 457    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 458       return "prepare_channel_masks";
 459    case GS_OPCODE_SET_CHANNEL_MASKS:
 460       return "set_channel_masks";
 461    case GS_OPCODE_GET_INSTANCE_ID:
 462       return "get_instance_id";
 463    case GS_OPCODE_FF_SYNC:
 464       return "ff_sync";
 465    case GS_OPCODE_SET_PRIMITIVE_ID:
 466       return "set_primitive_id";
 467    case GS_OPCODE_SVB_WRITE:
 468       return "gs_svb_write";
 469    case GS_OPCODE_SVB_SET_DST_INDEX:
 470       return "gs_svb_set_dst_index";
 471    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 472       return "gs_ff_sync_set_primitives";
 473    case CS_OPCODE_CS_TERMINATE:
 474       return "cs_terminate";
 475    case SHADER_OPCODE_BARRIER:
 476       return "barrier";
 477    case SHADER_OPCODE_MULH:
 478       return "mulh";
 479    case SHADER_OPCODE_MOV_INDIRECT:
 480       return "mov_indirect";
 481
 482    case VEC4_OPCODE_URB_READ:
 483       return "urb_read";
 484    case TCS_OPCODE_GET_INSTANCE_ID:
 485       return "tcs_get_instance_id";
 486    case TCS_OPCODE_URB_WRITE:
 487       return "tcs_urb_write";
 488    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 489       return "tcs_set_input_urb_offsets";
 490    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 491       return "tcs_set_output_urb_offsets";
 492    case TCS_OPCODE_GET_PRIMITIVE_ID:
 493       return "tcs_get_primitive_id";
 494    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 495       return "tcs_create_barrier_header";
 496    case TCS_OPCODE_SRC0_010_IS_ZERO:
 497       return "tcs_src0<0,1,0>_is_zero";
 498    case TCS_OPCODE_RELEASE_INPUT:
 499       return "tcs_release_input";
 500    case TCS_OPCODE_THREAD_END:
 501       return "tcs_thread_end";
 502    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 503       return "tes_create_input_read_header";
 504    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 505       return "tes_add_indirect_urb_offset";
 506    case TES_OPCODE_GET_PRIMITIVE_ID:
 507       return "tes_get_primitive_id";
 508
 509    case SHADER_OPCODE_RND_MODE:
 510       return "rnd_mode";
 511    }
 512
 513    unreachable("not reached");
 514 }
 515
 516 bool
 517 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 518 {
 519    union {
 520       unsigned ud;
 521       int d;
 522       float f;
 523       double df;
 524    } imm, sat_imm = { 0 };
 525
 526    const unsigned size = type_sz(type);
 527
 528    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 529     * irrelevant, so just check the size of the type and copy from/to an
 530     * appropriately sized field.
 531     */
 532    if (size < 8)
 533       imm.ud = reg->ud;
 534    else
 535       imm.df = reg->df;
 536
 537    switch (type) {
 538    case BRW_REGISTER_TYPE_UD:
 539    case BRW_REGISTER_TYPE_D:
 540    case BRW_REGISTER_TYPE_UW:
 541    case BRW_REGISTER_TYPE_W:
 542    case BRW_REGISTER_TYPE_UQ:
 543    case BRW_REGISTER_TYPE_Q:
 544       /* Nothing to do. */
 545       return false;
 546    case BRW_REGISTER_TYPE_F:
 547       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 548       break;
 549    case BRW_REGISTER_TYPE_DF:
 550       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 551       break;
 552    case BRW_REGISTER_TYPE_UB:
 553    case BRW_REGISTER_TYPE_B:
 554       unreachable("no UB/B immediates");
 555    case BRW_REGISTER_TYPE_V:
 556    case BRW_REGISTER_TYPE_UV:
 557    case BRW_REGISTER_TYPE_VF:
 558       unreachable("unimplemented: saturate vector immediate");
 559    case BRW_REGISTER_TYPE_HF:
 560       unreachable("unimplemented: saturate HF immediate");
 561    case BRW_REGISTER_TYPE_NF:
 562       unreachable("no NF immediates");
 563    }
 564
 565    if (size < 8) {
 566       if (imm.ud != sat_imm.ud) {
 567          reg->ud = sat_imm.ud;
 568          return true;
 569       }
 570    } else {
 571       if (imm.df != sat_imm.df) {
 572          reg->df = sat_imm.df;
 573          return true;
 574       }
 575    }
 576    return false;
 577 }
 578
 579 bool
 580 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 581 {
 582    switch (type) {
 583    case BRW_REGISTER_TYPE_D:
 584    case BRW_REGISTER_TYPE_UD:
 585       reg->d = -reg->d;
 586       return true;
 587    case BRW_REGISTER_TYPE_W:
 588    case BRW_REGISTER_TYPE_UW: {
 589       uint16_t value = -(int16_t)reg->ud;
 590       reg->ud = value | (uint32_t)value << 16;
 591       return true;
 592    }
 593    case BRW_REGISTER_TYPE_F:
 594       reg->f = -reg->f;
 595       return true;
 596    case BRW_REGISTER_TYPE_VF:
 597       reg->ud ^= 0x80808080;
 598       return true;
 599    case BRW_REGISTER_TYPE_DF:
 600       reg->df = -reg->df;
 601       return true;
 602    case BRW_REGISTER_TYPE_UQ:
 603    case BRW_REGISTER_TYPE_Q:
 604       reg->d64 = -reg->d64;
 605       return true;
 606    case BRW_REGISTER_TYPE_UB:
 607    case BRW_REGISTER_TYPE_B:
 608       unreachable("no UB/B immediates");
 609    case BRW_REGISTER_TYPE_UV:
 610    case BRW_REGISTER_TYPE_V:
 611       assert(!"unimplemented: negate UV/V immediate");
 612    case BRW_REGISTER_TYPE_HF:
 613       reg->ud ^= 0x80008000;
 614       return true;
 615    case BRW_REGISTER_TYPE_NF:
 616       unreachable("no NF immediates");
 617    }
 618
 619    return false;
 620 }
 621
 622 bool
 623 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 624 {
 625    switch (type) {
 626    case BRW_REGISTER_TYPE_D:
 627       reg->d = abs(reg->d);
 628       return true;
 629    case BRW_REGISTER_TYPE_W: {
 630       uint16_t value = abs((int16_t)reg->ud);
 631       reg->ud = value | (uint32_t)value << 16;
 632       return true;
 633    }
 634    case BRW_REGISTER_TYPE_F:
 635       reg->f = fabsf(reg->f);
 636       return true;
 637    case BRW_REGISTER_TYPE_DF:
 638       reg->df = fabs(reg->df);
 639       return true;
 640    case BRW_REGISTER_TYPE_VF:
 641       reg->ud &= ~0x80808080;
 642       return true;
 643    case BRW_REGISTER_TYPE_Q:
 644       reg->d64 = imaxabs(reg->d64);
 645       return true;
 646    case BRW_REGISTER_TYPE_UB:
 647    case BRW_REGISTER_TYPE_B:
 648       unreachable("no UB/B immediates");
 649    case BRW_REGISTER_TYPE_UQ:
 650    case BRW_REGISTER_TYPE_UD:
 651    case BRW_REGISTER_TYPE_UW:
 652    case BRW_REGISTER_TYPE_UV:
 653       /* Presumably the absolute value modifier on an unsigned source is a
 654        * nop, but it would be nice to confirm.
 655        */
 656       assert(!"unimplemented: abs unsigned immediate");
 657    case BRW_REGISTER_TYPE_V:
 658       assert(!"unimplemented: abs V immediate");
 659    case BRW_REGISTER_TYPE_HF:
 660       reg->ud &= ~0x80008000;
 661       return true;
 662    case BRW_REGISTER_TYPE_NF:
 663       unreachable("no NF immediates");
 664    }
 665
 666    return false;
 667 }
 668
 669 backend_shader::backend_shader(const struct brw_compiler *compiler,
 670                                void *log_data,
 671                                void *mem_ctx,
 672                                const nir_shader *shader,
 673                                struct brw_stage_prog_data *stage_prog_data)
 674    : compiler(compiler),
 675      log_data(log_data),
 676      devinfo(compiler->devinfo),
 677      nir(shader),
 678      stage_prog_data(stage_prog_data),
 679      mem_ctx(mem_ctx),
 680      cfg(NULL),
 681      stage(shader->info.stage)
 682 {
 683    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 684    stage_name = _mesa_shader_stage_to_string(stage);
 685    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 686 }
 687
 688 backend_shader::~backend_shader()
 689 {
 690 }
 691
 692 bool
 693 backend_reg::equals(const backend_reg &r) const
 694 {
 695    return brw_regs_equal(this, &r) && offset == r.offset;
 696 }
 697
 698 bool
 699 backend_reg::negative_equals(const backend_reg &r) const
 700 {
 701    return brw_regs_negative_equal(this, &r) && offset == r.offset;
 702 }
 703
 704 bool
 705 backend_reg::is_zero() const
 706 {
 707    if (file != IMM)
 708       return false;
 709
 710    switch (type) {
 711    case BRW_REGISTER_TYPE_F:
 712       return f == 0;
 713    case BRW_REGISTER_TYPE_DF:
 714       return df == 0;
 715    case BRW_REGISTER_TYPE_D:
 716    case BRW_REGISTER_TYPE_UD:
 717       return d == 0;
 718    case BRW_REGISTER_TYPE_UQ:
 719    case BRW_REGISTER_TYPE_Q:
 720       return u64 == 0;
 721    default:
 722       return false;
 723    }
 724 }
 725
 726 bool
 727 backend_reg::is_one() const
 728 {
 729    if (file != IMM)
 730       return false;
 731
 732    switch (type) {
 733    case BRW_REGISTER_TYPE_F:
 734       return f == 1.0f;
 735    case BRW_REGISTER_TYPE_DF:
 736       return df == 1.0;
 737    case BRW_REGISTER_TYPE_D:
 738    case BRW_REGISTER_TYPE_UD:
 739       return d == 1;
 740    case BRW_REGISTER_TYPE_UQ:
 741    case BRW_REGISTER_TYPE_Q:
 742       return u64 == 1;
 743    default:
 744       return false;
 745    }
 746 }
 747
 748 bool
 749 backend_reg::is_negative_one() const
 750 {
 751    if (file != IMM)
 752       return false;
 753
 754    switch (type) {
 755    case BRW_REGISTER_TYPE_F:
 756       return f == -1.0;
 757    case BRW_REGISTER_TYPE_DF:
 758       return df == -1.0;
 759    case BRW_REGISTER_TYPE_D:
 760       return d == -1;
 761    case BRW_REGISTER_TYPE_Q:
 762       return d64 == -1;
 763    default:
 764       return false;
 765    }
 766 }
 767
 768 bool
 769 backend_reg::is_null() const
 770 {
 771    return file == ARF && nr == BRW_ARF_NULL;
 772 }
 773
 774
 775 bool
 776 backend_reg::is_accumulator() const
 777 {
 778    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 779 }
 780
 781 bool
 782 backend_instruction::is_commutative() const
 783 {
 784    switch (opcode) {
 785    case BRW_OPCODE_AND:
 786    case BRW_OPCODE_OR:
 787    case BRW_OPCODE_XOR:
 788    case BRW_OPCODE_ADD:
 789    case BRW_OPCODE_MUL:
 790    case SHADER_OPCODE_MULH:
 791       return true;
 792    case BRW_OPCODE_SEL:
 793       /* MIN and MAX are commutative. */
 794       if (conditional_mod == BRW_CONDITIONAL_GE ||
 795           conditional_mod == BRW_CONDITIONAL_L) {
 796          return true;
 797       }
 798       /* fallthrough */
 799    default:
 800       return false;
 801    }
 802 }
 803
 804 bool
 805 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 806 {
 807    return ::is_3src(devinfo, opcode);
 808 }
 809
 810 bool
 811 backend_instruction::is_tex() const
 812 {
 813    return (opcode == SHADER_OPCODE_TEX ||
 814            opcode == FS_OPCODE_TXB ||
 815            opcode == SHADER_OPCODE_TXD ||
 816            opcode == SHADER_OPCODE_TXF ||
 817            opcode == SHADER_OPCODE_TXF_LZ ||
 818            opcode == SHADER_OPCODE_TXF_CMS ||
 819            opcode == SHADER_OPCODE_TXF_CMS_W ||
 820            opcode == SHADER_OPCODE_TXF_UMS ||
 821            opcode == SHADER_OPCODE_TXF_MCS ||
 822            opcode == SHADER_OPCODE_TXL ||
 823            opcode == SHADER_OPCODE_TXL_LZ ||
 824            opcode == SHADER_OPCODE_TXS ||
 825            opcode == SHADER_OPCODE_LOD ||
 826            opcode == SHADER_OPCODE_TG4 ||
 827            opcode == SHADER_OPCODE_TG4_OFFSET ||
 828            opcode == SHADER_OPCODE_SAMPLEINFO);
 829 }
 830
 831 bool
 832 backend_instruction::is_math() const
 833 {
 834    return (opcode == SHADER_OPCODE_RCP ||
 835            opcode == SHADER_OPCODE_RSQ ||
 836            opcode == SHADER_OPCODE_SQRT ||
 837            opcode == SHADER_OPCODE_EXP2 ||
 838            opcode == SHADER_OPCODE_LOG2 ||
 839            opcode == SHADER_OPCODE_SIN ||
 840            opcode == SHADER_OPCODE_COS ||
 841            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 842            opcode == SHADER_OPCODE_INT_REMAINDER ||
 843            opcode == SHADER_OPCODE_POW);
 844 }
 845
 846 bool
 847 backend_instruction::is_control_flow() const
 848 {
 849    switch (opcode) {
 850    case BRW_OPCODE_DO:
 851    case BRW_OPCODE_WHILE:
 852    case BRW_OPCODE_IF:
 853    case BRW_OPCODE_ELSE:
 854    case BRW_OPCODE_ENDIF:
 855    case BRW_OPCODE_BREAK:
 856    case BRW_OPCODE_CONTINUE:
 857       return true;
 858    default:
 859       return false;
 860    }
 861 }
 862
 863 bool
 864 backend_instruction::can_do_source_mods() const
 865 {
 866    switch (opcode) {
 867    case BRW_OPCODE_ADDC:
 868    case BRW_OPCODE_BFE:
 869    case BRW_OPCODE_BFI1:
 870    case BRW_OPCODE_BFI2:
 871    case BRW_OPCODE_BFREV:
 872    case BRW_OPCODE_CBIT:
 873    case BRW_OPCODE_FBH:
 874    case BRW_OPCODE_FBL:
 875    case BRW_OPCODE_SUBB:
 876    case SHADER_OPCODE_BROADCAST:
 877    case SHADER_OPCODE_CLUSTER_BROADCAST:
 878    case SHADER_OPCODE_MOV_INDIRECT:
 879       return false;
 880    default:
 881       return true;
 882    }
 883 }
 884
 885 bool
 886 backend_instruction::can_do_saturate() const
 887 {
 888    switch (opcode) {
 889    case BRW_OPCODE_ADD:
 890    case BRW_OPCODE_ASR:
 891    case BRW_OPCODE_AVG:
 892    case BRW_OPCODE_DP2:
 893    case BRW_OPCODE_DP3:
 894    case BRW_OPCODE_DP4:
 895    case BRW_OPCODE_DPH:
 896    case BRW_OPCODE_F16TO32:
 897    case BRW_OPCODE_F32TO16:
 898    case BRW_OPCODE_LINE:
 899    case BRW_OPCODE_LRP:
 900    case BRW_OPCODE_MAC:
 901    case BRW_OPCODE_MAD:
 902    case BRW_OPCODE_MATH:
 903    case BRW_OPCODE_MOV:
 904    case BRW_OPCODE_MUL:
 905    case SHADER_OPCODE_MULH:
 906    case BRW_OPCODE_PLN:
 907    case BRW_OPCODE_RNDD:
 908    case BRW_OPCODE_RNDE:
 909    case BRW_OPCODE_RNDU:
 910    case BRW_OPCODE_RNDZ:
 911    case BRW_OPCODE_SEL:
 912    case BRW_OPCODE_SHL:
 913    case BRW_OPCODE_SHR:
 914    case FS_OPCODE_LINTERP:
 915    case SHADER_OPCODE_COS:
 916    case SHADER_OPCODE_EXP2:
 917    case SHADER_OPCODE_LOG2:
 918    case SHADER_OPCODE_POW:
 919    case SHADER_OPCODE_RCP:
 920    case SHADER_OPCODE_RSQ:
 921    case SHADER_OPCODE_SIN:
 922    case SHADER_OPCODE_SQRT:
 923       return true;
 924    default:
 925       return false;
 926    }
 927 }
 928
 929 bool
 930 backend_instruction::can_do_cmod() const
 931 {
 932    switch (opcode) {
 933    case BRW_OPCODE_ADD:
 934    case BRW_OPCODE_ADDC:
 935    case BRW_OPCODE_AND:
 936    case BRW_OPCODE_ASR:
 937    case BRW_OPCODE_AVG:
 938    case BRW_OPCODE_CMP:
 939    case BRW_OPCODE_CMPN:
 940    case BRW_OPCODE_DP2:
 941    case BRW_OPCODE_DP3:
 942    case BRW_OPCODE_DP4:
 943    case BRW_OPCODE_DPH:
 944    case BRW_OPCODE_F16TO32:
 945    case BRW_OPCODE_F32TO16:
 946    case BRW_OPCODE_FRC:
 947    case BRW_OPCODE_LINE:
 948    case BRW_OPCODE_LRP:
 949    case BRW_OPCODE_LZD:
 950    case BRW_OPCODE_MAC:
 951    case BRW_OPCODE_MACH:
 952    case BRW_OPCODE_MAD:
 953    case BRW_OPCODE_MOV:
 954    case BRW_OPCODE_MUL:
 955    case BRW_OPCODE_NOT:
 956    case BRW_OPCODE_OR:
 957    case BRW_OPCODE_PLN:
 958    case BRW_OPCODE_RNDD:
 959    case BRW_OPCODE_RNDE:
 960    case BRW_OPCODE_RNDU:
 961    case BRW_OPCODE_RNDZ:
 962    case BRW_OPCODE_SAD2:
 963    case BRW_OPCODE_SADA2:
 964    case BRW_OPCODE_SHL:
 965    case BRW_OPCODE_SHR:
 966    case BRW_OPCODE_SUBB:
 967    case BRW_OPCODE_XOR:
 968    case FS_OPCODE_LINTERP:
 969       return true;
 970    default:
 971       return false;
 972    }
 973 }
 974
 975 bool
 976 backend_instruction::reads_accumulator_implicitly() const
 977 {
 978    switch (opcode) {
 979    case BRW_OPCODE_MAC:
 980    case BRW_OPCODE_MACH:
 981    case BRW_OPCODE_SADA2:
 982       return true;
 983    default:
 984       return false;
 985    }
 986 }
 987
 988 bool
 989 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 990 {
 991    return writes_accumulator ||
 992           (devinfo->gen < 6 &&
 993            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 994             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
 995           (opcode == FS_OPCODE_LINTERP &&
 996            (!devinfo->has_pln || devinfo->gen <= 6));
 997 }
 998
 999 bool
1000 backend_instruction::has_side_effects() const
1001 {
1002    switch (opcode) {
1003    case SHADER_OPCODE_SEND:
1004       return send_has_side_effects;
1005
1006    case SHADER_OPCODE_UNTYPED_ATOMIC:
1007    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1008    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT:
1009    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1010    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1011    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1012    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1013    case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
1014    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1015    case SHADER_OPCODE_TYPED_ATOMIC:
1016    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1017    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1018    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1019    case SHADER_OPCODE_MEMORY_FENCE:
1020    case SHADER_OPCODE_INTERLOCK:
1021    case SHADER_OPCODE_URB_WRITE_SIMD8:
1022    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1023    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1024    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1025    case FS_OPCODE_FB_WRITE:
1026    case FS_OPCODE_FB_WRITE_LOGICAL:
1027    case FS_OPCODE_REP_FB_WRITE:
1028    case SHADER_OPCODE_BARRIER:
1029    case TCS_OPCODE_URB_WRITE:
1030    case TCS_OPCODE_RELEASE_INPUT:
1031    case SHADER_OPCODE_RND_MODE:
1032       return true;
1033    default:
1034       return eot;
1035    }
1036 }
1037
1038 bool
1039 backend_instruction::is_volatile() const
1040 {
1041    switch (opcode) {
1042    case SHADER_OPCODE_SEND:
1043       return send_is_volatile;
1044
1045    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1046    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1047    case SHADER_OPCODE_TYPED_SURFACE_READ:
1048    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1049    case SHADER_OPCODE_BYTE_SCATTERED_READ:
1050    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1051    case SHADER_OPCODE_URB_READ_SIMD8:
1052    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1053    case VEC4_OPCODE_URB_READ:
1054       return true;
1055    default:
1056       return false;
1057    }
1058 }
1059
1060 #ifndef NDEBUG
1061 static bool
1062 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1063 {
1064    bool found = false;
1065    foreach_inst_in_block (backend_instruction, i, block) {
1066       if (inst == i) {
1067          found = true;
1068       }
1069    }
1070    return found;
1071 }
1072 #endif
1073
1074 static void
1075 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1076 {
1077    for (bblock_t *block_iter = start_block->next();
1078         block_iter;
1079         block_iter = block_iter->next()) {
1080       block_iter->start_ip += ip_adjustment;
1081       block_iter->end_ip += ip_adjustment;
1082    }
1083 }
1084
1085 void
1086 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1087 {
1088    assert(this != inst);
1089
1090    if (!this->is_head_sentinel())
1091       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1092
1093    block->end_ip++;
1094
1095    adjust_later_block_ips(block, 1);
1096
1097    exec_node::insert_after(inst);
1098 }
1099
1100 void
1101 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1102 {
1103    assert(this != inst);
1104
1105    if (!this->is_tail_sentinel())
1106       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1107
1108    block->end_ip++;
1109
1110    adjust_later_block_ips(block, 1);
1111
1112    exec_node::insert_before(inst);
1113 }
1114
1115 void
1116 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1117 {
1118    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1119
1120    unsigned num_inst = list->length();
1121
1122    block->end_ip += num_inst;
1123
1124    adjust_later_block_ips(block, num_inst);
1125
1126    exec_node::insert_before(list);
1127 }
1128
1129 void
1130 backend_instruction::remove(bblock_t *block)
1131 {
1132    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1133
1134    adjust_later_block_ips(block, -1);
1135
1136    if (block->start_ip == block->end_ip) {
1137       block->cfg->remove_block(block);
1138    } else {
1139       block->end_ip--;
1140    }
1141
1142    exec_node::remove();
1143 }
1144
1145 void
1146 backend_shader::dump_instructions()
1147 {
1148    dump_instructions(NULL);
1149 }
1150
1151 void
1152 backend_shader::dump_instructions(const char *name)
1153 {
1154    FILE *file = stderr;
1155    if (name && geteuid() != 0) {
1156       file = fopen(name, "w");
1157       if (!file)
1158          file = stderr;
1159    }
1160
1161    if (cfg) {
1162       int ip = 0;
1163       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1164          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1165             fprintf(file, "%4d: ", ip++);
1166          dump_instruction(inst, file);
1167       }
1168    } else {
1169       int ip = 0;
1170       foreach_in_list(backend_instruction, inst, &instructions) {
1171          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1172             fprintf(file, "%4d: ", ip++);
1173          dump_instruction(inst, file);
1174       }
1175    }
1176
1177    if (file != stderr) {
1178       fclose(file);
1179    }
1180 }
1181
1182 void
1183 backend_shader::calculate_cfg()
1184 {
1185    if (this->cfg)
1186       return;
1187    cfg = new(mem_ctx) cfg_t(&this->instructions);
1188 }
1189
1190 extern "C" const unsigned *
1191 brw_compile_tes(const struct brw_compiler *compiler,
1192                 void *log_data,
1193                 void *mem_ctx,
1194                 const struct brw_tes_prog_key *key,
1195                 const struct brw_vue_map *input_vue_map,
1196                 struct brw_tes_prog_data *prog_data,
1197                 nir_shader *nir,
1198                 struct gl_program *prog,
1199                 int shader_time_index,
1200                 char **error_str)
1201 {
1202    const struct gen_device_info *devinfo = compiler->devinfo;
1203    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1204    const unsigned *assembly;
1205
1206    nir->info.inputs_read = key->inputs_read;
1207    nir->info.patch_inputs_read = key->patch_inputs_read;
1208
1209    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1210    brw_nir_lower_tes_inputs(nir, input_vue_map);
1211    brw_nir_lower_vue_outputs(nir);
1212    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1213
1214    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1215                        nir->info.outputs_written,
1216                        nir->info.separate_shader);
1217
1218    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1219
1220    assert(output_size_bytes >= 1);
1221    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1222       if (error_str)
1223          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1224       return NULL;
1225    }
1226
1227    prog_data->base.clip_distance_mask =
1228       ((1 << nir->info.clip_distance_array_size) - 1);
1229    prog_data->base.cull_distance_mask =
1230       ((1 << nir->info.cull_distance_array_size) - 1) <<
1231       nir->info.clip_distance_array_size;
1232
1233    /* URB entry sizes are stored as a multiple of 64 bytes. */
1234    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1235
1236    /* On Cannonlake software shall not program an allocation size that
1237     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1238     */
1239    if (devinfo->gen == 10 &&
1240        prog_data->base.urb_entry_size % 3 == 0)
1241       prog_data->base.urb_entry_size++;
1242
1243    prog_data->base.urb_read_length = 0;
1244
1245    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1246    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1247                  TESS_SPACING_FRACTIONAL_ODD - 1);
1248    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1249                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1250
1251    prog_data->partitioning =
1252       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1253
1254    switch (nir->info.tess.primitive_mode) {
1255    case GL_QUADS:
1256       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1257       break;
1258    case GL_TRIANGLES:
1259       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1260       break;
1261    case GL_ISOLINES:
1262       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1263       break;
1264    default:
1265       unreachable("invalid domain shader primitive mode");
1266    }
1267
1268    if (nir->info.tess.point_mode) {
1269       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1270    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1271       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1272    } else {
1273       /* Hardware winding order is backwards from OpenGL */
1274       prog_data->output_topology =
1275          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1276                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1277    }
1278
1279    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1280       fprintf(stderr, "TES Input ");
1281       brw_print_vue_map(stderr, input_vue_map);
1282       fprintf(stderr, "TES Output ");
1283       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1284    }
1285
1286    if (is_scalar) {
1287       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1288                    &prog_data->base.base, NULL, nir, 8,
1289                    shader_time_index, input_vue_map);
1290       if (!v.run_tes()) {
1291          if (error_str)
1292             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1293          return NULL;
1294       }
1295
1296       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1297       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1298
1299       fs_generator g(compiler, log_data, mem_ctx,
1300                      &prog_data->base.base, v.promoted_constants, false,
1301                      MESA_SHADER_TESS_EVAL);
1302       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1303          g.enable_debug(ralloc_asprintf(mem_ctx,
1304                                         "%s tessellation evaluation shader %s",
1305                                         nir->info.label ? nir->info.label
1306                                                         : "unnamed",
1307                                         nir->info.name));
1308       }
1309
1310       g.generate_code(v.cfg, 8);
1311
1312       assembly = g.get_assembly();
1313    } else {
1314       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1315                               nir, mem_ctx, shader_time_index);
1316       if (!v.run()) {
1317          if (error_str)
1318             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1319          return NULL;
1320       }
1321
1322       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1323          v.dump_instructions();
1324
1325       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1326                                             &prog_data->base, v.cfg);
1327    }
1328
1329    return assembly;
1330 }