2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_vec4_builder.h"
29 #include "brw_vec4_live_variables.h"
30 #include "brw_vec4_vs.h"
31 #include "brw_dead_control_flow.h"
32 #include "common/gen_debug.h"
33 #include "program/prog_parameter.h"
35 #define MAX_INSTRUCTION (1 << 30)
44 memset(this, 0, sizeof(*this));
46 this->file
= BAD_FILE
;
49 src_reg::src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
)
55 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
56 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
58 this->swizzle
= BRW_SWIZZLE_XYZW
;
60 this->type
= brw_type_for_base_type(type
);
63 /** Generic unset register constructor. */
69 src_reg::src_reg(struct ::brw_reg reg
) :
76 src_reg::src_reg(const dst_reg
®
) :
79 this->reladdr
= reg
.reladdr
;
80 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
86 memset(this, 0, sizeof(*this));
87 this->file
= BAD_FILE
;
88 this->writemask
= WRITEMASK_XYZW
;
96 dst_reg::dst_reg(enum brw_reg_file file
, int nr
)
104 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
111 this->type
= brw_type_for_base_type(type
);
112 this->writemask
= writemask
;
115 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
123 this->writemask
= writemask
;
126 dst_reg::dst_reg(struct ::brw_reg reg
) :
130 this->reladdr
= NULL
;
133 dst_reg::dst_reg(const src_reg
®
) :
136 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
137 this->reladdr
= reg
.reladdr
;
141 dst_reg::equals(const dst_reg
&r
) const
143 return (this->backend_reg::equals(r
) &&
144 (reladdr
== r
.reladdr
||
145 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
149 vec4_instruction::is_send_from_grf()
152 case SHADER_OPCODE_SHADER_TIME_ADD
:
153 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
154 case SHADER_OPCODE_UNTYPED_ATOMIC
:
155 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
156 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
157 case SHADER_OPCODE_TYPED_ATOMIC
:
158 case SHADER_OPCODE_TYPED_SURFACE_READ
:
159 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
160 case VEC4_OPCODE_URB_READ
:
161 case TCS_OPCODE_URB_WRITE
:
162 case TCS_OPCODE_RELEASE_INPUT
:
163 case SHADER_OPCODE_BARRIER
:
171 * Returns true if this instruction's sources and destinations cannot
172 * safely be the same register.
174 * In most cases, a register can be written over safely by the same
175 * instruction that is its last use. For a single instruction, the
176 * sources are dereferenced before writing of the destination starts
179 * However, there are a few cases where this can be problematic:
181 * - Virtual opcodes that translate to multiple instructions in the
182 * code generator: if src == dst and one instruction writes the
183 * destination before a later instruction reads the source, then
184 * src will have been clobbered.
186 * The register allocator uses this information to set up conflicts between
187 * GRF sources and the destination.
190 vec4_instruction::has_source_and_destination_hazard() const
193 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
194 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
195 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
198 /* 8-wide compressed DF operations are executed as two 4-wide operations,
199 * so we have a src/dst hazard if the first half of the instruction
200 * overwrites the source of the second half. Prevent this by marking
201 * compressed instructions as having src/dst hazards, so the register
202 * allocator assigns safe register regions for dst and srcs.
204 return size_written
> REG_SIZE
;
209 vec4_instruction::size_read(unsigned arg
) const
212 case SHADER_OPCODE_SHADER_TIME_ADD
:
213 case SHADER_OPCODE_UNTYPED_ATOMIC
:
214 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
215 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
216 case SHADER_OPCODE_TYPED_ATOMIC
:
217 case SHADER_OPCODE_TYPED_SURFACE_READ
:
218 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
219 case TCS_OPCODE_URB_WRITE
:
221 return mlen
* REG_SIZE
;
223 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
225 return mlen
* REG_SIZE
;
231 switch (src
[arg
].file
) {
236 return 4 * type_sz(src
[arg
].type
);
238 /* XXX - Represent actual vertical stride. */
239 return exec_size
* type_sz(src
[arg
].type
);
244 vec4_instruction::can_do_source_mods(const struct gen_device_info
*devinfo
)
246 if (devinfo
->gen
== 6 && is_math())
249 if (is_send_from_grf())
252 if (!backend_instruction::can_do_source_mods())
259 vec4_instruction::can_do_writemask(const struct gen_device_info
*devinfo
)
262 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
263 case VEC4_OPCODE_DOUBLE_TO_F32
:
264 case VEC4_OPCODE_DOUBLE_TO_D32
:
265 case VEC4_OPCODE_DOUBLE_TO_U32
:
266 case VEC4_OPCODE_TO_DOUBLE
:
267 case VEC4_OPCODE_PICK_LOW_32BIT
:
268 case VEC4_OPCODE_PICK_HIGH_32BIT
:
269 case VEC4_OPCODE_SET_LOW_32BIT
:
270 case VEC4_OPCODE_SET_HIGH_32BIT
:
271 case VS_OPCODE_PULL_CONSTANT_LOAD
:
272 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
273 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
274 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
275 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
276 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
277 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
278 case VEC4_OPCODE_URB_READ
:
279 case SHADER_OPCODE_MOV_INDIRECT
:
282 /* The MATH instruction on Gen6 only executes in align1 mode, which does
283 * not support writemasking.
285 if (devinfo
->gen
== 6 && is_math())
296 vec4_instruction::can_change_types() const
298 return dst
.type
== src
[0].type
&&
299 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
300 (opcode
== BRW_OPCODE_MOV
||
301 (opcode
== BRW_OPCODE_SEL
&&
302 dst
.type
== src
[1].type
&&
303 predicate
!= BRW_PREDICATE_NONE
&&
304 !src
[1].abs
&& !src
[1].negate
));
308 * Returns how many MRFs an opcode will write over.
310 * Note that this is not the 0 or 1 implied writes in an actual gen
311 * instruction -- the generate_* functions generate additional MOVs
315 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
317 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
320 switch (inst
->opcode
) {
321 case SHADER_OPCODE_RCP
:
322 case SHADER_OPCODE_RSQ
:
323 case SHADER_OPCODE_SQRT
:
324 case SHADER_OPCODE_EXP2
:
325 case SHADER_OPCODE_LOG2
:
326 case SHADER_OPCODE_SIN
:
327 case SHADER_OPCODE_COS
:
329 case SHADER_OPCODE_INT_QUOTIENT
:
330 case SHADER_OPCODE_INT_REMAINDER
:
331 case SHADER_OPCODE_POW
:
332 case TCS_OPCODE_THREAD_END
:
334 case VS_OPCODE_URB_WRITE
:
336 case VS_OPCODE_PULL_CONSTANT_LOAD
:
338 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
340 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
342 case GS_OPCODE_URB_WRITE
:
343 case GS_OPCODE_URB_WRITE_ALLOCATE
:
344 case GS_OPCODE_THREAD_END
:
346 case GS_OPCODE_FF_SYNC
:
348 case TCS_OPCODE_URB_WRITE
:
350 case SHADER_OPCODE_SHADER_TIME_ADD
:
352 case SHADER_OPCODE_TEX
:
353 case SHADER_OPCODE_TXL
:
354 case SHADER_OPCODE_TXD
:
355 case SHADER_OPCODE_TXF
:
356 case SHADER_OPCODE_TXF_CMS
:
357 case SHADER_OPCODE_TXF_CMS_W
:
358 case SHADER_OPCODE_TXF_MCS
:
359 case SHADER_OPCODE_TXS
:
360 case SHADER_OPCODE_TG4
:
361 case SHADER_OPCODE_TG4_OFFSET
:
362 case SHADER_OPCODE_SAMPLEINFO
:
363 case VS_OPCODE_GET_BUFFER_SIZE
:
364 return inst
->header_size
;
366 unreachable("not reached");
371 src_reg::equals(const src_reg
&r
) const
373 return (this->backend_reg::equals(r
) &&
374 !reladdr
&& !r
.reladdr
);
378 vec4_visitor::opt_vector_float()
380 bool progress
= false;
382 foreach_block(block
, cfg
) {
383 int last_reg
= -1, last_offset
= -1;
384 enum brw_reg_file last_reg_file
= BAD_FILE
;
386 uint8_t imm
[4] = { 0 };
388 vec4_instruction
*imm_inst
[4];
389 unsigned writemask
= 0;
390 enum brw_reg_type dest_type
= BRW_REGISTER_TYPE_F
;
392 foreach_inst_in_block_safe(vec4_instruction
, inst
, block
) {
394 enum brw_reg_type need_type
;
396 /* Look for unconditional MOVs from an immediate with a partial
397 * writemask. Skip type-conversion MOVs other than integer 0,
398 * where the type doesn't matter. See if the immediate can be
399 * represented as a VF.
401 if (inst
->opcode
== BRW_OPCODE_MOV
&&
402 inst
->src
[0].file
== IMM
&&
403 inst
->predicate
== BRW_PREDICATE_NONE
&&
404 inst
->dst
.writemask
!= WRITEMASK_XYZW
&&
405 type_sz(inst
->src
[0].type
) < 8 &&
406 (inst
->src
[0].type
== inst
->dst
.type
|| inst
->src
[0].d
== 0)) {
408 vf
= brw_float_to_vf(inst
->src
[0].d
);
409 need_type
= BRW_REGISTER_TYPE_D
;
412 vf
= brw_float_to_vf(inst
->src
[0].f
);
413 need_type
= BRW_REGISTER_TYPE_F
;
419 /* If this wasn't a MOV, or the destination register doesn't match,
420 * or we have to switch destination types, then this breaks our
421 * sequence. Combine anything we've accumulated so far.
423 if (last_reg
!= inst
->dst
.nr
||
424 last_offset
!= inst
->dst
.offset
||
425 last_reg_file
!= inst
->dst
.file
||
426 (vf
> 0 && dest_type
!= need_type
)) {
428 if (inst_count
> 1) {
430 memcpy(&vf
, imm
, sizeof(vf
));
431 vec4_instruction
*mov
= MOV(imm_inst
[0]->dst
, brw_imm_vf(vf
));
432 mov
->dst
.type
= dest_type
;
433 mov
->dst
.writemask
= writemask
;
434 inst
->insert_before(block
, mov
);
436 for (int i
= 0; i
< inst_count
; i
++) {
437 imm_inst
[i
]->remove(block
);
446 dest_type
= BRW_REGISTER_TYPE_F
;
448 for (int i
= 0; i
< 4; i
++) {
453 /* Record this instruction's value (if it was representable). */
455 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
457 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
459 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
461 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
464 writemask
|= inst
->dst
.writemask
;
465 imm_inst
[inst_count
++] = inst
;
467 last_reg
= inst
->dst
.nr
;
468 last_offset
= inst
->dst
.offset
;
469 last_reg_file
= inst
->dst
.file
;
471 dest_type
= need_type
;
477 invalidate_live_intervals();
482 /* Replaces unused channels of a swizzle with channels that are used.
484 * For instance, this pass transforms
486 * mov vgrf4.yz, vgrf5.wxzy
490 * mov vgrf4.yz, vgrf5.xxzx
492 * This eliminates false uses of some channels, letting dead code elimination
493 * remove the instructions that wrote them.
496 vec4_visitor::opt_reduce_swizzle()
498 bool progress
= false;
500 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
501 if (inst
->dst
.file
== BAD_FILE
||
502 inst
->dst
.file
== ARF
||
503 inst
->dst
.file
== FIXED_GRF
||
504 inst
->is_send_from_grf())
509 /* Determine which channels of the sources are read. */
510 switch (inst
->opcode
) {
511 case VEC4_OPCODE_PACK_BYTES
:
513 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
514 * but all four of src1.
516 swizzle
= brw_swizzle_for_size(4);
519 swizzle
= brw_swizzle_for_size(3);
522 swizzle
= brw_swizzle_for_size(2);
525 case VEC4_OPCODE_TO_DOUBLE
:
526 case VEC4_OPCODE_DOUBLE_TO_F32
:
527 case VEC4_OPCODE_DOUBLE_TO_D32
:
528 case VEC4_OPCODE_DOUBLE_TO_U32
:
529 case VEC4_OPCODE_PICK_LOW_32BIT
:
530 case VEC4_OPCODE_PICK_HIGH_32BIT
:
531 case VEC4_OPCODE_SET_LOW_32BIT
:
532 case VEC4_OPCODE_SET_HIGH_32BIT
:
533 swizzle
= brw_swizzle_for_size(4);
537 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
541 /* Update sources' swizzles. */
542 for (int i
= 0; i
< 3; i
++) {
543 if (inst
->src
[i
].file
!= VGRF
&&
544 inst
->src
[i
].file
!= ATTR
&&
545 inst
->src
[i
].file
!= UNIFORM
)
548 const unsigned new_swizzle
=
549 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
550 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
551 inst
->src
[i
].swizzle
= new_swizzle
;
558 invalidate_live_intervals();
564 vec4_visitor::split_uniform_registers()
566 /* Prior to this, uniforms have been in an array sized according to
567 * the number of vector uniforms present, sparsely filled (so an
568 * aggregate results in reg indices being skipped over). Now we're
569 * going to cut those aggregates up so each .nr index is one
570 * vector. The goal is to make elimination of unused uniform
571 * components easier later.
573 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
574 for (int i
= 0 ; i
< 3; i
++) {
575 if (inst
->src
[i
].file
!= UNIFORM
)
578 assert(!inst
->src
[i
].reladdr
);
580 inst
->src
[i
].nr
+= inst
->src
[i
].offset
/ 16;
581 inst
->src
[i
].offset
%= 16;
587 vec4_visitor::pack_uniform_registers()
589 uint8_t chans_used
[this->uniforms
];
590 int new_loc
[this->uniforms
];
591 int new_chan
[this->uniforms
];
593 memset(chans_used
, 0, sizeof(chans_used
));
594 memset(new_loc
, 0, sizeof(new_loc
));
595 memset(new_chan
, 0, sizeof(new_chan
));
597 /* Find which uniform vectors are actually used by the program. We
598 * expect unused vector elements when we've moved array access out
599 * to pull constants, and from some GLSL code generators like wine.
601 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
603 switch (inst
->opcode
) {
604 case VEC4_OPCODE_PACK_BYTES
:
616 readmask
= inst
->dst
.writemask
;
620 for (int i
= 0 ; i
< 3; i
++) {
621 if (inst
->src
[i
].file
!= UNIFORM
)
624 assert(type_sz(inst
->src
[i
].type
) % 4 == 0);
625 unsigned channel_size
= type_sz(inst
->src
[i
].type
) / 4;
627 int reg
= inst
->src
[i
].nr
;
628 for (int c
= 0; c
< 4; c
++) {
629 if (!(readmask
& (1 << c
)))
632 unsigned channel
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1;
633 unsigned used
= MAX2(chans_used
[reg
], channel
* channel_size
);
635 chans_used
[reg
] = used
;
637 chans_used
[reg
+ 1] = used
- 4;
641 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
642 inst
->src
[0].file
== UNIFORM
) {
643 assert(inst
->src
[2].file
== BRW_IMMEDIATE_VALUE
);
644 assert(inst
->src
[0].subnr
== 0);
646 unsigned bytes_read
= inst
->src
[2].ud
;
647 assert(bytes_read
% 4 == 0);
648 unsigned vec4s_read
= DIV_ROUND_UP(bytes_read
, 16);
650 /* We just mark every register touched by a MOV_INDIRECT as being
651 * fully used. This ensures that it doesn't broken up piecewise by
652 * the next part of our packing algorithm.
654 int reg
= inst
->src
[0].nr
;
655 for (unsigned i
= 0; i
< vec4s_read
; i
++)
656 chans_used
[reg
+ i
] = 4;
660 int new_uniform_count
= 0;
662 /* Now, figure out a packing of the live uniform vectors into our
665 for (int src
= 0; src
< uniforms
; src
++) {
666 int size
= chans_used
[src
];
672 /* Find the lowest place we can slot this uniform in. */
673 for (dst
= 0; dst
< src
; dst
++) {
674 if (chans_used
[dst
] + size
<= 4)
683 new_chan
[src
] = chans_used
[dst
];
685 /* Move the references to the data */
686 for (int j
= 0; j
< size
; j
++) {
687 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
688 stage_prog_data
->param
[src
* 4 + j
];
691 chans_used
[dst
] += size
;
695 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
698 this->uniforms
= new_uniform_count
;
700 /* Now, update the instructions for our repacked uniforms. */
701 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
702 for (int i
= 0 ; i
< 3; i
++) {
703 int src
= inst
->src
[i
].nr
;
705 if (inst
->src
[i
].file
!= UNIFORM
)
708 inst
->src
[i
].nr
= new_loc
[src
];
709 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
710 new_chan
[src
], new_chan
[src
]);
716 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
718 * While GLSL IR also performs this optimization, we end up with it in
719 * our instruction stream for a couple of reasons. One is that we
720 * sometimes generate silly instructions, for example in array access
721 * where we'll generate "ADD offset, index, base" even if base is 0.
722 * The other is that GLSL IR's constant propagation doesn't track the
723 * components of aggregates, so some VS patterns (initialize matrix to
724 * 0, accumulate in vertex blending factors) end up breaking down to
725 * instructions involving 0.
728 vec4_visitor::opt_algebraic()
730 bool progress
= false;
732 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
733 switch (inst
->opcode
) {
735 if (inst
->src
[0].file
!= IMM
)
738 if (inst
->saturate
) {
739 if (inst
->dst
.type
!= inst
->src
[0].type
)
740 assert(!"unimplemented: saturate mixed types");
742 if (brw_saturate_immediate(inst
->dst
.type
,
743 &inst
->src
[0].as_brw_reg())) {
744 inst
->saturate
= false;
750 case VEC4_OPCODE_UNPACK_UNIFORM
:
751 if (inst
->src
[0].file
!= UNIFORM
) {
752 inst
->opcode
= BRW_OPCODE_MOV
;
758 if (inst
->src
[1].is_zero()) {
759 inst
->opcode
= BRW_OPCODE_MOV
;
760 inst
->src
[1] = src_reg();
766 if (inst
->src
[1].is_zero()) {
767 inst
->opcode
= BRW_OPCODE_MOV
;
768 switch (inst
->src
[0].type
) {
769 case BRW_REGISTER_TYPE_F
:
770 inst
->src
[0] = brw_imm_f(0.0f
);
772 case BRW_REGISTER_TYPE_D
:
773 inst
->src
[0] = brw_imm_d(0);
775 case BRW_REGISTER_TYPE_UD
:
776 inst
->src
[0] = brw_imm_ud(0u);
779 unreachable("not reached");
781 inst
->src
[1] = src_reg();
783 } else if (inst
->src
[1].is_one()) {
784 inst
->opcode
= BRW_OPCODE_MOV
;
785 inst
->src
[1] = src_reg();
787 } else if (inst
->src
[1].is_negative_one()) {
788 inst
->opcode
= BRW_OPCODE_MOV
;
789 inst
->src
[0].negate
= !inst
->src
[0].negate
;
790 inst
->src
[1] = src_reg();
795 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
797 inst
->src
[0].negate
&&
798 inst
->src
[1].is_zero()) {
799 inst
->src
[0].abs
= false;
800 inst
->src
[0].negate
= false;
801 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
806 case SHADER_OPCODE_BROADCAST
:
807 if (is_uniform(inst
->src
[0]) ||
808 inst
->src
[1].is_zero()) {
809 inst
->opcode
= BRW_OPCODE_MOV
;
810 inst
->src
[1] = src_reg();
811 inst
->force_writemask_all
= true;
822 invalidate_live_intervals();
828 * Only a limited number of hardware registers may be used for push
829 * constants, so this turns access to the overflowed constants into
833 vec4_visitor::move_push_constants_to_pull_constants()
835 int pull_constant_loc
[this->uniforms
];
837 /* Only allow 32 registers (256 uniform components) as push constants,
838 * which is the limit on gen6.
840 * If changing this value, note the limitation about total_regs in
843 int max_uniform_components
= 32 * 8;
844 if (this->uniforms
* 4 <= max_uniform_components
)
847 /* Make some sort of choice as to which uniforms get sent to pull
848 * constants. We could potentially do something clever here like
849 * look for the most infrequently used uniform vec4s, but leave
852 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
853 pull_constant_loc
[i
/ 4] = -1;
855 if (i
>= max_uniform_components
) {
856 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
858 /* Try to find an existing copy of this uniform in the pull
859 * constants if it was part of an array access already.
861 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
864 for (matches
= 0; matches
< 4; matches
++) {
865 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
870 pull_constant_loc
[i
/ 4] = j
/ 4;
875 if (pull_constant_loc
[i
/ 4] == -1) {
876 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
877 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
879 for (int j
= 0; j
< 4; j
++) {
880 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
887 /* Now actually rewrite usage of the things we've moved to pull
890 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
891 for (int i
= 0 ; i
< 3; i
++) {
892 if (inst
->src
[i
].file
!= UNIFORM
||
893 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
896 int uniform
= inst
->src
[i
].nr
;
898 const glsl_type
*temp_type
= type_sz(inst
->src
[i
].type
) == 8 ?
899 glsl_type::dvec4_type
: glsl_type::vec4_type
;
900 dst_reg temp
= dst_reg(this, temp_type
);
902 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
903 pull_constant_loc
[uniform
], src_reg());
905 inst
->src
[i
].file
= temp
.file
;
906 inst
->src
[i
].nr
= temp
.nr
;
907 inst
->src
[i
].offset
%= 16;
908 inst
->src
[i
].reladdr
= NULL
;
912 /* Repack push constants to remove the now-unused ones. */
913 pack_uniform_registers();
916 /* Conditions for which we want to avoid setting the dependency control bits */
918 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
920 #define IS_DWORD(reg) \
921 (reg.type == BRW_REGISTER_TYPE_UD || \
922 reg.type == BRW_REGISTER_TYPE_D)
924 #define IS_64BIT(reg) (reg.file != BAD_FILE && type_sz(reg.type) == 8)
926 /* From the Cherryview and Broadwell PRMs:
928 * "When source or destination datatype is 64b or operation is integer DWord
929 * multiply, DepCtrl must not be used."
931 * SKL PRMs don't include this restriction, however, gen7 seems to be
932 * affected, at least by the 64b restriction, since DepCtrl with double
933 * precision instructions seems to produce GPU hangs in some cases.
935 if (devinfo
->gen
== 8 || devinfo
->is_broxton
) {
936 if (inst
->opcode
== BRW_OPCODE_MUL
&&
937 IS_DWORD(inst
->src
[0]) &&
938 IS_DWORD(inst
->src
[1]))
942 if (devinfo
->gen
>= 7 && devinfo
->gen
<= 8) {
943 if (IS_64BIT(inst
->dst
) || IS_64BIT(inst
->src
[0]) ||
944 IS_64BIT(inst
->src
[1]) || IS_64BIT(inst
->src
[2]))
951 if (devinfo
->gen
>= 8) {
952 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
958 * In the presence of send messages, totally interrupt dependency
959 * control. They're long enough that the chance of dependency
960 * control around them just doesn't matter.
963 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
964 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
965 * completes the scoreboard clear must have a non-zero execution mask. This
966 * means, if any kind of predication can change the execution mask or channel
967 * enable of the last instruction, the optimization must be avoided. This is
968 * to avoid instructions being shot down the pipeline when no writes are
972 * Dependency control does not work well over math instructions.
973 * NB: Discovered empirically
975 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
979 * Sets the dependency control fields on instructions after register
980 * allocation and before the generator is run.
982 * When you have a sequence of instructions like:
984 * DP4 temp.x vertex uniform[0]
985 * DP4 temp.y vertex uniform[0]
986 * DP4 temp.z vertex uniform[0]
987 * DP4 temp.w vertex uniform[0]
989 * The hardware doesn't know that it can actually run the later instructions
990 * while the previous ones are in flight, producing stalls. However, we have
991 * manual fields we can set in the instructions that let it do so.
994 vec4_visitor::opt_set_dependency_control()
996 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
997 uint8_t grf_channels_written
[BRW_MAX_GRF
];
998 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
999 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
1001 assert(prog_data
->total_grf
||
1002 !"Must be called after register allocation");
1004 foreach_block (block
, cfg
) {
1005 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1006 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1008 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
1009 /* If we read from a register that we were doing dependency control
1010 * on, don't do dependency control across the read.
1012 for (int i
= 0; i
< 3; i
++) {
1013 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ REG_SIZE
;
1014 if (inst
->src
[i
].file
== VGRF
) {
1015 last_grf_write
[reg
] = NULL
;
1016 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1017 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1020 assert(inst
->src
[i
].file
!= MRF
);
1023 if (is_dep_ctrl_unsafe(inst
)) {
1024 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1025 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1029 /* Now, see if we can do dependency control for this instruction
1030 * against a previous one writing to its destination.
1032 int reg
= inst
->dst
.nr
+ inst
->dst
.offset
/ REG_SIZE
;
1033 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
1034 if (last_grf_write
[reg
] &&
1035 last_grf_write
[reg
]->dst
.offset
== inst
->dst
.offset
&&
1036 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
1037 last_grf_write
[reg
]->no_dd_clear
= true;
1038 inst
->no_dd_check
= true;
1040 grf_channels_written
[reg
] = 0;
1043 last_grf_write
[reg
] = inst
;
1044 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
1045 } else if (inst
->dst
.file
== MRF
) {
1046 if (last_mrf_write
[reg
] &&
1047 last_mrf_write
[reg
]->dst
.offset
== inst
->dst
.offset
&&
1048 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
1049 last_mrf_write
[reg
]->no_dd_clear
= true;
1050 inst
->no_dd_check
= true;
1052 mrf_channels_written
[reg
] = 0;
1055 last_mrf_write
[reg
] = inst
;
1056 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
1063 vec4_instruction::can_reswizzle(const struct gen_device_info
*devinfo
,
1068 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
1071 if (devinfo
->gen
== 6 && is_math() && swizzle
!= BRW_SWIZZLE_XYZW
)
1074 /* We can't swizzle implicit accumulator access. We'd have to
1075 * reswizzle the producer of the accumulator value in addition
1076 * to the consumer (i.e. both MUL and MACH). Just skip this.
1078 if (reads_accumulator_implicitly())
1081 if (!can_do_writemask(devinfo
) && dst_writemask
!= WRITEMASK_XYZW
)
1084 /* If this instruction sets anything not referenced by swizzle, then we'd
1085 * totally break it when we reswizzle.
1087 if (dst
.writemask
& ~swizzle_mask
)
1093 for (int i
= 0; i
< 3; i
++) {
1094 if (src
[i
].is_accumulator())
1102 * For any channels in the swizzle's source that were populated by this
1103 * instruction, rewrite the instruction to put the appropriate result directly
1104 * in those channels.
1106 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
1109 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
1111 /* Destination write mask doesn't correspond to source swizzle for the dot
1112 * product and pack_bytes instructions.
1114 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
1115 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
1116 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
1117 for (int i
= 0; i
< 3; i
++) {
1118 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
1121 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1125 /* Apply the specified swizzle and writemask to the original mask of
1126 * written components.
1128 dst
.writemask
= dst_writemask
&
1129 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1133 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1134 * just written and then MOVed into another reg and making the original write
1135 * of the GRF write directly to the final destination instead.
1138 vec4_visitor::opt_register_coalesce()
1140 bool progress
= false;
1143 calculate_live_intervals();
1145 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1149 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1150 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
1152 inst
->src
[0].file
!= VGRF
||
1153 inst
->dst
.type
!= inst
->src
[0].type
||
1154 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1157 /* Remove no-op MOVs */
1158 if (inst
->dst
.file
== inst
->src
[0].file
&&
1159 inst
->dst
.nr
== inst
->src
[0].nr
&&
1160 inst
->dst
.offset
== inst
->src
[0].offset
) {
1161 bool is_nop_mov
= true;
1163 for (unsigned c
= 0; c
< 4; c
++) {
1164 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1167 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1174 inst
->remove(block
);
1180 bool to_mrf
= (inst
->dst
.file
== MRF
);
1182 /* Can't coalesce this GRF if someone else was going to
1185 if (var_range_end(var_from_reg(alloc
, dst_reg(inst
->src
[0])), 8) > ip
)
1188 /* We need to check interference with the final destination between this
1189 * instruction and the earliest instruction involved in writing the GRF
1190 * we're eliminating. To do that, keep track of which of our source
1191 * channels we've seen initialized.
1193 const unsigned chans_needed
=
1194 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1195 inst
->dst
.writemask
);
1196 unsigned chans_remaining
= chans_needed
;
1198 /* Now walk up the instruction stream trying to see if we can rewrite
1199 * everything writing to the temporary to write into the destination
1202 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1203 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1205 _scan_inst
= scan_inst
;
1207 if (regions_overlap(inst
->src
[0], inst
->size_read(0),
1208 scan_inst
->dst
, scan_inst
->size_written
)) {
1209 /* Found something writing to the reg we want to coalesce away. */
1211 /* SEND instructions can't have MRF as a destination. */
1212 if (scan_inst
->mlen
)
1215 if (devinfo
->gen
== 6) {
1216 /* gen6 math instructions must have the destination be
1217 * VGRF, so no compute-to-MRF for them.
1219 if (scan_inst
->is_math()) {
1225 /* This doesn't handle saturation on the instruction we
1226 * want to coalesce away if the register types do not match.
1227 * But if scan_inst is a non type-converting 'mov', we can fix
1230 if (inst
->saturate
&&
1231 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1232 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1233 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1236 /* Only allow coalescing between registers of the same type size.
1237 * Otherwise we would need to make the pass aware of the fact that
1238 * channel sizes are different for single and double precision.
1240 if (type_sz(inst
->src
[0].type
) != type_sz(scan_inst
->src
[0].type
))
1243 /* Check that scan_inst writes the same amount of data as the
1244 * instruction, otherwise coalescing would lead to writing a
1245 * different (larger or smaller) region of the destination
1247 if (scan_inst
->size_written
!= inst
->size_written
)
1250 /* If we can't handle the swizzle, bail. */
1251 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1252 inst
->src
[0].swizzle
,
1257 /* This only handles coalescing writes of 8 channels (1 register
1258 * for single-precision and 2 registers for double-precision)
1259 * starting at the source offset of the copy instruction.
1261 if (DIV_ROUND_UP(scan_inst
->size_written
,
1262 type_sz(scan_inst
->dst
.type
)) > 8 ||
1263 scan_inst
->dst
.offset
!= inst
->src
[0].offset
)
1266 /* Mark which channels we found unconditional writes for. */
1267 if (!scan_inst
->predicate
)
1268 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1270 if (chans_remaining
== 0)
1274 /* You can't read from an MRF, so if someone else reads our MRF's
1275 * source GRF that we wanted to rewrite, that stops us. If it's a
1276 * GRF we're trying to coalesce to, we don't actually handle
1277 * rewriting sources so bail in that case as well.
1279 bool interfered
= false;
1280 for (int i
= 0; i
< 3; i
++) {
1281 if (regions_overlap(inst
->src
[0], inst
->size_read(0),
1282 scan_inst
->src
[i
], scan_inst
->size_read(i
)))
1288 /* If somebody else writes the same channels of our destination here,
1289 * we can't coalesce before that.
1291 if (regions_overlap(inst
->dst
, inst
->size_written
,
1292 scan_inst
->dst
, scan_inst
->size_written
) &&
1293 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1297 /* Check for reads of the register we're trying to coalesce into. We
1298 * can't go rewriting instructions above that to put some other value
1299 * in the register instead.
1301 if (to_mrf
&& scan_inst
->mlen
> 0) {
1302 if (inst
->dst
.nr
>= scan_inst
->base_mrf
&&
1303 inst
->dst
.nr
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1307 for (int i
= 0; i
< 3; i
++) {
1308 if (regions_overlap(inst
->dst
, inst
->size_written
,
1309 scan_inst
->src
[i
], scan_inst
->size_read(i
)))
1317 if (chans_remaining
== 0) {
1318 /* If we've made it here, we have an MOV we want to coalesce out, and
1319 * a scan_inst pointing to the earliest instruction involved in
1320 * computing the value. Now go rewrite the instruction stream
1323 vec4_instruction
*scan_inst
= _scan_inst
;
1324 while (scan_inst
!= inst
) {
1325 if (scan_inst
->dst
.file
== VGRF
&&
1326 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1327 scan_inst
->dst
.offset
== inst
->src
[0].offset
) {
1328 scan_inst
->reswizzle(inst
->dst
.writemask
,
1329 inst
->src
[0].swizzle
);
1330 scan_inst
->dst
.file
= inst
->dst
.file
;
1331 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1332 scan_inst
->dst
.offset
= inst
->dst
.offset
;
1333 if (inst
->saturate
&&
1334 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1335 /* If we have reached this point, scan_inst is a non
1336 * type-converting 'mov' and we can modify its register types
1337 * to match the ones in inst. Otherwise, we could have an
1338 * incorrect saturation result.
1340 scan_inst
->dst
.type
= inst
->dst
.type
;
1341 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1343 scan_inst
->saturate
|= inst
->saturate
;
1345 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1347 inst
->remove(block
);
1353 invalidate_live_intervals();
1359 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1360 * flow. We could probably do better here with some form of divergence
1364 vec4_visitor::eliminate_find_live_channel()
1366 bool progress
= false;
1369 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
1370 /* The optimization below assumes that channel zero is live on thread
1371 * dispatch, which may not be the case if the fixed function dispatches
1377 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1378 switch (inst
->opcode
) {
1384 case BRW_OPCODE_ENDIF
:
1385 case BRW_OPCODE_WHILE
:
1389 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1391 inst
->opcode
= BRW_OPCODE_MOV
;
1392 inst
->src
[0] = brw_imm_d(0);
1393 inst
->force_writemask_all
= true;
1407 * Splits virtual GRFs requesting more than one contiguous physical register.
1409 * We initially create large virtual GRFs for temporary structures, arrays,
1410 * and matrices, so that the visitor functions can add offsets to work their
1411 * way down to the actual member being accessed. But when it comes to
1412 * optimization, we'd like to treat each register as individual storage if
1415 * So far, the only thing that might prevent splitting is a send message from
1419 vec4_visitor::split_virtual_grfs()
1421 int num_vars
= this->alloc
.count
;
1422 int new_virtual_grf
[num_vars
];
1423 bool split_grf
[num_vars
];
1425 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1427 /* Try to split anything > 0 sized. */
1428 for (int i
= 0; i
< num_vars
; i
++) {
1429 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1432 /* Check that the instructions are compatible with the registers we're trying
1435 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1436 if (inst
->dst
.file
== VGRF
&& regs_written(inst
) > 1)
1437 split_grf
[inst
->dst
.nr
] = false;
1439 for (int i
= 0; i
< 3; i
++) {
1440 if (inst
->src
[i
].file
== VGRF
&& regs_read(inst
, i
) > 1)
1441 split_grf
[inst
->src
[i
].nr
] = false;
1445 /* Allocate new space for split regs. Note that the virtual
1446 * numbers will be contiguous.
1448 for (int i
= 0; i
< num_vars
; i
++) {
1452 new_virtual_grf
[i
] = alloc
.allocate(1);
1453 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1454 unsigned reg
= alloc
.allocate(1);
1455 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1458 this->alloc
.sizes
[i
] = 1;
1461 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1462 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1463 inst
->dst
.offset
/ REG_SIZE
!= 0) {
1464 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1465 inst
->dst
.offset
/ REG_SIZE
- 1);
1466 inst
->dst
.offset
%= REG_SIZE
;
1468 for (int i
= 0; i
< 3; i
++) {
1469 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1470 inst
->src
[i
].offset
/ REG_SIZE
!= 0) {
1471 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1472 inst
->src
[i
].offset
/ REG_SIZE
- 1);
1473 inst
->src
[i
].offset
%= REG_SIZE
;
1477 invalidate_live_intervals();
1481 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1483 dump_instruction(be_inst
, stderr
);
1487 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1489 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1491 if (inst
->predicate
) {
1492 fprintf(file
, "(%cf0.%d%s) ",
1493 inst
->predicate_inverse
? '-' : '+',
1495 pred_ctrl_align16
[inst
->predicate
]);
1498 fprintf(file
, "%s(%d)", brw_instruction_name(devinfo
, inst
->opcode
),
1501 fprintf(file
, ".sat");
1502 if (inst
->conditional_mod
) {
1503 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1504 if (!inst
->predicate
&&
1505 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1506 inst
->opcode
!= BRW_OPCODE_IF
&&
1507 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1508 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1513 switch (inst
->dst
.file
) {
1515 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
1518 fprintf(file
, "g%d", inst
->dst
.nr
);
1521 fprintf(file
, "m%d", inst
->dst
.nr
);
1524 switch (inst
->dst
.nr
) {
1526 fprintf(file
, "null");
1528 case BRW_ARF_ADDRESS
:
1529 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1531 case BRW_ARF_ACCUMULATOR
:
1532 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1535 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1538 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1543 fprintf(file
, "(null)");
1548 unreachable("not reached");
1550 if (inst
->dst
.offset
||
1551 (inst
->dst
.file
== VGRF
&&
1552 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
1553 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 16 : REG_SIZE
);
1554 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
1555 inst
->dst
.offset
% reg_size
);
1557 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1559 if (inst
->dst
.writemask
& 1)
1561 if (inst
->dst
.writemask
& 2)
1563 if (inst
->dst
.writemask
& 4)
1565 if (inst
->dst
.writemask
& 8)
1568 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1570 if (inst
->src
[0].file
!= BAD_FILE
)
1571 fprintf(file
, ", ");
1573 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1574 if (inst
->src
[i
].negate
)
1576 if (inst
->src
[i
].abs
)
1578 switch (inst
->src
[i
].file
) {
1580 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1583 fprintf(file
, "g%d.%d", inst
->src
[i
].nr
, inst
->src
[i
].subnr
);
1586 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1589 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1592 switch (inst
->src
[i
].type
) {
1593 case BRW_REGISTER_TYPE_F
:
1594 fprintf(file
, "%fF", inst
->src
[i
].f
);
1596 case BRW_REGISTER_TYPE_DF
:
1597 fprintf(file
, "%fDF", inst
->src
[i
].df
);
1599 case BRW_REGISTER_TYPE_D
:
1600 fprintf(file
, "%dD", inst
->src
[i
].d
);
1602 case BRW_REGISTER_TYPE_UD
:
1603 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1605 case BRW_REGISTER_TYPE_VF
:
1606 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1607 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1608 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1609 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1610 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1613 fprintf(file
, "???");
1618 switch (inst
->src
[i
].nr
) {
1620 fprintf(file
, "null");
1622 case BRW_ARF_ADDRESS
:
1623 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1625 case BRW_ARF_ACCUMULATOR
:
1626 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1629 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1632 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1637 fprintf(file
, "(null)");
1640 unreachable("not reached");
1643 if (inst
->src
[i
].offset
||
1644 (inst
->src
[i
].file
== VGRF
&&
1645 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
1646 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 16 : REG_SIZE
);
1647 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
1648 inst
->src
[i
].offset
% reg_size
);
1651 if (inst
->src
[i
].file
!= IMM
) {
1652 static const char *chans
[4] = {"x", "y", "z", "w"};
1654 for (int c
= 0; c
< 4; c
++) {
1655 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1659 if (inst
->src
[i
].abs
)
1662 if (inst
->src
[i
].file
!= IMM
) {
1663 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1666 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1667 fprintf(file
, ", ");
1670 if (inst
->force_writemask_all
)
1671 fprintf(file
, " NoMask");
1673 if (inst
->exec_size
!= 8)
1674 fprintf(file
, " group%d", inst
->group
);
1676 fprintf(file
, "\n");
1680 static inline struct brw_reg
1681 attribute_to_hw_reg(int attr
, brw_reg_type type
, bool interleaved
)
1685 unsigned width
= REG_SIZE
/ 2 / MAX2(4, type_sz(type
));
1687 reg
= stride(brw_vecn_grf(width
, attr
/ 2, (attr
% 2) * 4), 0, width
, 1);
1689 reg
= brw_vecn_grf(width
, attr
, 0);
1698 * Replace each register of type ATTR in this->instructions with a reference
1699 * to a fixed HW register.
1701 * If interleaved is true, then each attribute takes up half a register, with
1702 * register N containing attribute 2*N in its first half and attribute 2*N+1
1703 * in its second half (this corresponds to the payload setup used by geometry
1704 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1705 * false, then each attribute takes up a whole register, with register N
1706 * containing attribute N (this corresponds to the payload setup used by
1707 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1710 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1713 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1714 for (int i
= 0; i
< 3; i
++) {
1715 if (inst
->src
[i
].file
!= ATTR
)
1718 int grf
= attribute_map
[inst
->src
[i
].nr
+
1719 inst
->src
[i
].offset
/ REG_SIZE
];
1720 assert(inst
->src
[i
].offset
% REG_SIZE
== 0);
1722 /* All attributes used in the shader need to have been assigned a
1723 * hardware register by the caller
1727 struct brw_reg reg
=
1728 attribute_to_hw_reg(grf
, inst
->src
[i
].type
, interleaved
);
1729 reg
.swizzle
= inst
->src
[i
].swizzle
;
1730 if (inst
->src
[i
].abs
)
1732 if (inst
->src
[i
].negate
)
1741 vec4_vs_visitor::setup_attributes(int payload_reg
)
1744 int attribute_map
[VERT_ATTRIB_MAX
+ 2];
1745 memset(attribute_map
, 0, sizeof(attribute_map
));
1748 GLbitfield64 vs_inputs
= vs_prog_data
->inputs_read
;
1750 GLuint first
= ffsll(vs_inputs
) - 1;
1752 (vs_prog_data
->double_inputs_read
& BITFIELD64_BIT(first
)) ? 2 : 1;
1753 for (int c
= 0; c
< needed_slots
; c
++) {
1754 attribute_map
[first
+ c
] = payload_reg
+ nr_attributes
;
1756 vs_inputs
&= ~BITFIELD64_BIT(first
+ c
);
1760 /* VertexID is stored by the VF as the last vertex element, but we
1761 * don't represent it with a flag in inputs_read, so we call it
1764 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
||
1765 vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
) {
1766 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1770 if (vs_prog_data
->uses_drawid
) {
1771 attribute_map
[VERT_ATTRIB_MAX
+ 1] = payload_reg
+ nr_attributes
;
1775 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1777 return payload_reg
+ vs_prog_data
->nr_attribute_slots
;
1781 vec4_visitor::setup_uniforms(int reg
)
1783 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1785 /* The pre-gen6 VS requires that some push constants get loaded no
1786 * matter what, or the GPU would hang.
1788 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1789 stage_prog_data
->param
=
1790 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1791 for (unsigned int i
= 0; i
< 4; i
++) {
1792 unsigned int slot
= this->uniforms
* 4 + i
;
1793 static gl_constant_value zero
= { 0.0 };
1794 stage_prog_data
->param
[slot
] = &zero
;
1800 reg
+= ALIGN(uniforms
, 2) / 2;
1803 stage_prog_data
->nr_params
= this->uniforms
* 4;
1805 prog_data
->base
.curb_read_length
=
1806 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1812 vec4_vs_visitor::setup_payload(void)
1816 /* The payload always contains important data in g0, which contains
1817 * the URB handles that are passed on to the URB write at the end
1818 * of the thread. So, we always start push constants at g1.
1822 reg
= setup_uniforms(reg
);
1824 reg
= setup_attributes(reg
);
1826 this->first_non_payload_grf
= reg
;
1830 vec4_visitor::lower_minmax()
1832 assert(devinfo
->gen
< 6);
1834 bool progress
= false;
1836 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1837 const vec4_builder
ibld(this, block
, inst
);
1839 if (inst
->opcode
== BRW_OPCODE_SEL
&&
1840 inst
->predicate
== BRW_PREDICATE_NONE
) {
1841 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
1842 * the original SEL.L/GE instruction
1844 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
1845 inst
->conditional_mod
);
1846 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1847 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
1854 invalidate_live_intervals();
1860 vec4_visitor::get_timestamp()
1862 assert(devinfo
->gen
>= 7);
1864 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1869 BRW_REGISTER_TYPE_UD
,
1870 BRW_VERTICAL_STRIDE_0
,
1872 BRW_HORIZONTAL_STRIDE_4
,
1876 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1878 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1879 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1880 * even if it's not enabled in the dispatch.
1882 mov
->force_writemask_all
= true;
1884 return src_reg(dst
);
1888 vec4_visitor::emit_shader_time_begin()
1890 current_annotation
= "shader time start";
1891 shader_start_time
= get_timestamp();
1895 vec4_visitor::emit_shader_time_end()
1897 current_annotation
= "shader time end";
1898 src_reg shader_end_time
= get_timestamp();
1901 /* Check that there weren't any timestamp reset events (assuming these
1902 * were the only two timestamp reads that happened).
1904 src_reg reset_end
= shader_end_time
;
1905 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1906 vec4_instruction
*test
= emit(AND(dst_null_ud(), reset_end
, brw_imm_ud(1u)));
1907 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1909 emit(IF(BRW_PREDICATE_NORMAL
));
1911 /* Take the current timestamp and get the delta. */
1912 shader_start_time
.negate
= true;
1913 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1914 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1916 /* If there were no instructions between the two timestamp gets, the diff
1917 * is 2 cycles. Remove that overhead, so I can forget about that when
1918 * trying to determine the time taken for single instructions.
1920 emit(ADD(diff
, src_reg(diff
), brw_imm_ud(-2u)));
1922 emit_shader_time_write(0, src_reg(diff
));
1923 emit_shader_time_write(1, brw_imm_ud(1u));
1924 emit(BRW_OPCODE_ELSE
);
1925 emit_shader_time_write(2, brw_imm_ud(1u));
1926 emit(BRW_OPCODE_ENDIF
);
1930 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1933 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1935 dst_reg offset
= dst
;
1937 time
.offset
+= REG_SIZE
;
1939 offset
.type
= BRW_REGISTER_TYPE_UD
;
1940 int index
= shader_time_index
* 3 + shader_time_subindex
;
1941 emit(MOV(offset
, brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
)));
1943 time
.type
= BRW_REGISTER_TYPE_UD
;
1944 emit(MOV(time
, value
));
1946 vec4_instruction
*inst
=
1947 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1952 is_align1_df(vec4_instruction
*inst
)
1954 switch (inst
->opcode
) {
1955 case VEC4_OPCODE_DOUBLE_TO_F32
:
1956 case VEC4_OPCODE_DOUBLE_TO_D32
:
1957 case VEC4_OPCODE_DOUBLE_TO_U32
:
1958 case VEC4_OPCODE_TO_DOUBLE
:
1959 case VEC4_OPCODE_PICK_LOW_32BIT
:
1960 case VEC4_OPCODE_PICK_HIGH_32BIT
:
1961 case VEC4_OPCODE_SET_LOW_32BIT
:
1962 case VEC4_OPCODE_SET_HIGH_32BIT
:
1970 vec4_visitor::convert_to_hw_regs()
1972 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1973 for (int i
= 0; i
< 3; i
++) {
1974 struct src_reg
&src
= inst
->src
[i
];
1978 reg
= byte_offset(brw_vecn_grf(4, src
.nr
, 0), src
.offset
);
1979 reg
.type
= src
.type
;
1981 reg
.negate
= src
.negate
;
1986 reg
= stride(byte_offset(brw_vec4_grf(
1987 prog_data
->base
.dispatch_grf_start_reg
+
1988 src
.nr
/ 2, src
.nr
% 2 * 4),
1991 reg
.type
= src
.type
;
1993 reg
.negate
= src
.negate
;
1995 /* This should have been moved to pull constants. */
1996 assert(!src
.reladdr
);
2001 if (type_sz(src
.type
) == 8) {
2002 reg
= src
.as_brw_reg();
2011 /* Probably unused. */
2012 reg
= brw_null_reg();
2013 reg
= retype(reg
, src
.type
);
2018 unreachable("not reached");
2021 apply_logical_swizzle(®
, inst
, i
);
2024 /* From IVB PRM, vol4, part3, "General Restrictions on Regioning
2027 * "If ExecSize = Width and HorzStride ≠ 0, VertStride must be set
2028 * to Width * HorzStride."
2030 * We can break this rule with DF sources on DF align1
2031 * instructions, because the exec_size would be 4 and width is 4.
2032 * As we know we are not accessing to next GRF, it is safe to
2033 * set vstride to the formula given by the rule itself.
2035 if (is_align1_df(inst
) && (cvt(inst
->exec_size
) - 1) == src
.width
)
2036 src
.vstride
= src
.width
+ src
.hstride
;
2039 if (inst
->is_3src(devinfo
)) {
2040 /* 3-src instructions with scalar sources support arbitrary subnr,
2041 * but don't actually use swizzles. Convert swizzle into subnr.
2042 * Skip this for double-precision instructions: RepCtrl=1 is not
2043 * allowed for them and needs special handling.
2045 for (int i
= 0; i
< 3; i
++) {
2046 if (inst
->src
[i
].vstride
== BRW_VERTICAL_STRIDE_0
&&
2047 type_sz(inst
->src
[i
].type
) < 8) {
2048 assert(brw_is_single_value_swizzle(inst
->src
[i
].swizzle
));
2049 inst
->src
[i
].subnr
+= 4 * BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0);
2054 dst_reg
&dst
= inst
->dst
;
2057 switch (inst
->dst
.file
) {
2059 reg
= byte_offset(brw_vec8_grf(dst
.nr
, 0), dst
.offset
);
2060 reg
.type
= dst
.type
;
2061 reg
.writemask
= dst
.writemask
;
2065 reg
= byte_offset(brw_message_reg(dst
.nr
), dst
.offset
);
2066 assert((reg
.nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
2067 reg
.type
= dst
.type
;
2068 reg
.writemask
= dst
.writemask
;
2073 reg
= dst
.as_brw_reg();
2077 reg
= brw_null_reg();
2078 reg
= retype(reg
, dst
.type
);
2084 unreachable("not reached");
2092 stage_uses_interleaved_attributes(unsigned stage
,
2093 enum shader_dispatch_mode dispatch_mode
)
2096 case MESA_SHADER_TESS_EVAL
:
2098 case MESA_SHADER_GEOMETRY
:
2099 return dispatch_mode
!= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2106 * Get the closest native SIMD width supported by the hardware for instruction
2107 * \p inst. The instruction will be left untouched by
2108 * vec4_visitor::lower_simd_width() if the returned value matches the
2109 * instruction's original execution size.
2112 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
2113 enum shader_dispatch_mode dispatch_mode
,
2114 unsigned stage
, const vec4_instruction
*inst
)
2116 /* Do not split some instructions that require special handling */
2117 switch (inst
->opcode
) {
2118 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2119 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2120 return inst
->exec_size
;
2125 unsigned lowered_width
= MIN2(16, inst
->exec_size
);
2127 /* We need to split some cases of double-precision instructions that write
2128 * 2 registers. We only need to care about this in gen7 because that is the
2129 * only hardware that implements fp64 in Align16.
2131 if (devinfo
->gen
== 7 && inst
->size_written
> REG_SIZE
) {
2132 /* Align16 8-wide double-precision SEL does not work well. Verified
2135 if (inst
->opcode
== BRW_OPCODE_SEL
&& type_sz(inst
->dst
.type
) == 8)
2136 lowered_width
= MIN2(lowered_width
, 4);
2138 /* HSW PRM, 3D Media GPGPU Engine, Region Alignment Rules for Direct
2139 * Register Addressing:
2141 * "When destination spans two registers, the source MUST span two
2144 for (unsigned i
= 0; i
< 3; i
++) {
2145 if (inst
->src
[i
].file
== BAD_FILE
)
2147 if (inst
->size_read(i
) <= REG_SIZE
)
2148 lowered_width
= MIN2(lowered_width
, 4);
2150 /* Interleaved attribute setups use a vertical stride of 0, which
2151 * makes them hit the associated instruction decompression bug in gen7.
2152 * Split them to prevent this.
2154 if (inst
->src
[i
].file
== ATTR
&&
2155 stage_uses_interleaved_attributes(stage
, dispatch_mode
))
2156 lowered_width
= MIN2(lowered_width
, 4);
2160 /* IvyBridge can manage a maximum of 4 DFs per SIMD4x2 instruction, since
2161 * it doesn't support compression in Align16 mode, no matter if it has
2162 * force_writemask_all enabled or disabled (the latter is affected by the
2163 * compressed instruction bug in gen7, which is another reason to enforce
2166 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
2167 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8))
2168 lowered_width
= MIN2(lowered_width
, 4);
2170 return lowered_width
;
2174 dst_src_regions_overlap(vec4_instruction
*inst
)
2176 if (inst
->size_written
== 0)
2179 unsigned dst_start
= inst
->dst
.offset
;
2180 unsigned dst_end
= dst_start
+ inst
->size_written
- 1;
2181 for (int i
= 0; i
< 3; i
++) {
2182 if (inst
->src
[i
].file
== BAD_FILE
)
2185 if (inst
->dst
.file
!= inst
->src
[i
].file
||
2186 inst
->dst
.nr
!= inst
->src
[i
].nr
)
2189 unsigned src_start
= inst
->src
[i
].offset
;
2190 unsigned src_end
= src_start
+ inst
->size_read(i
) - 1;
2192 if ((dst_start
>= src_start
&& dst_start
<= src_end
) ||
2193 (dst_end
>= src_start
&& dst_end
<= src_end
) ||
2194 (dst_start
<= src_start
&& dst_end
>= src_end
)) {
2203 vec4_visitor::lower_simd_width()
2205 bool progress
= false;
2207 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2208 const unsigned lowered_width
=
2209 get_lowered_simd_width(devinfo
, prog_data
->dispatch_mode
, stage
, inst
);
2210 assert(lowered_width
<= inst
->exec_size
);
2211 if (lowered_width
== inst
->exec_size
)
2214 /* We need to deal with source / destination overlaps when splitting.
2215 * The hardware supports reading from and writing to the same register
2216 * in the same instruction, but we need to be careful that each split
2217 * instruction we produce does not corrupt the source of the next.
2219 * The easiest way to handle this is to make the split instructions write
2220 * to temporaries if there is an src/dst overlap and then move from the
2221 * temporaries to the original destination. We also need to consider
2222 * instructions that do partial writes via align1 opcodes, in which case
2223 * we need to make sure that the we initialize the temporary with the
2224 * value of the instruction's dst.
2226 bool needs_temp
= dst_src_regions_overlap(inst
);
2227 for (unsigned n
= 0; n
< inst
->exec_size
/ lowered_width
; n
++) {
2228 unsigned channel_offset
= lowered_width
* n
;
2230 unsigned size_written
= lowered_width
* type_sz(inst
->dst
.type
);
2232 /* Create the split instruction from the original so that we copy all
2233 * relevant instruction fields, then set the width and calculate the
2234 * new dst/src regions.
2236 vec4_instruction
*linst
= new(mem_ctx
) vec4_instruction(*inst
);
2237 linst
->exec_size
= lowered_width
;
2238 linst
->group
= channel_offset
;
2239 linst
->size_written
= size_written
;
2241 /* Compute split dst region */
2244 unsigned num_regs
= DIV_ROUND_UP(size_written
, REG_SIZE
);
2245 dst
= retype(dst_reg(VGRF
, alloc
.allocate(num_regs
)),
2247 if (inst
->is_align1_partial_write()) {
2248 vec4_instruction
*copy
= MOV(dst
, src_reg(inst
->dst
));
2249 copy
->exec_size
= lowered_width
;
2250 copy
->group
= channel_offset
;
2251 copy
->size_written
= size_written
;
2252 inst
->insert_before(block
, copy
);
2255 dst
= horiz_offset(inst
->dst
, channel_offset
);
2259 /* Compute split source regions */
2260 for (int i
= 0; i
< 3; i
++) {
2261 if (linst
->src
[i
].file
== BAD_FILE
)
2264 if (!is_uniform(linst
->src
[i
]))
2265 linst
->src
[i
] = horiz_offset(linst
->src
[i
], channel_offset
);
2268 inst
->insert_before(block
, linst
);
2270 /* If we used a temporary to store the result of the split
2271 * instruction, copy the result to the original destination
2274 vec4_instruction
*mov
=
2275 MOV(offset(inst
->dst
, lowered_width
, n
), src_reg(dst
));
2276 mov
->exec_size
= lowered_width
;
2277 mov
->group
= channel_offset
;
2278 mov
->size_written
= size_written
;
2279 mov
->predicate
= inst
->predicate
;
2280 inst
->insert_before(block
, mov
);
2284 inst
->remove(block
);
2289 invalidate_live_intervals();
2294 static brw_predicate
2295 scalarize_predicate(brw_predicate predicate
, unsigned writemask
)
2297 if (predicate
!= BRW_PREDICATE_NORMAL
)
2300 switch (writemask
) {
2302 return BRW_PREDICATE_ALIGN16_REPLICATE_X
;
2304 return BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
2306 return BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
2308 return BRW_PREDICATE_ALIGN16_REPLICATE_W
;
2310 unreachable("invalid writemask");
2314 /* Gen7 has a hardware decompression bug that we can exploit to represent
2315 * handful of additional swizzles natively.
2318 is_gen7_supported_64bit_swizzle(vec4_instruction
*inst
, unsigned arg
)
2320 switch (inst
->src
[arg
].swizzle
) {
2321 case BRW_SWIZZLE_XXXX
:
2322 case BRW_SWIZZLE_YYYY
:
2323 case BRW_SWIZZLE_ZZZZ
:
2324 case BRW_SWIZZLE_WWWW
:
2325 case BRW_SWIZZLE_XYXY
:
2326 case BRW_SWIZZLE_YXYX
:
2327 case BRW_SWIZZLE_ZWZW
:
2328 case BRW_SWIZZLE_WZWZ
:
2335 /* 64-bit sources use regions with a width of 2. These 2 elements in each row
2336 * can be addressed using 32-bit swizzles (which is what the hardware supports)
2337 * but it also means that the swizzle we apply on the first two components of a
2338 * dvec4 is coupled with the swizzle we use for the last 2. In other words,
2339 * only some specific swizzle combinations can be natively supported.
2341 * FIXME: we can go an step further and implement even more swizzle
2342 * variations using only partial scalarization.
2344 * For more details see:
2345 * https://bugs.freedesktop.org/show_bug.cgi?id=92760#c82
2348 vec4_visitor::is_supported_64bit_region(vec4_instruction
*inst
, unsigned arg
)
2350 const src_reg
&src
= inst
->src
[arg
];
2351 assert(type_sz(src
.type
) == 8);
2353 /* Uniform regions have a vstride=0. Because we use 2-wide rows with
2354 * 64-bit regions it means that we cannot access components Z/W, so
2355 * return false for any such case. Interleaved attributes will also be
2356 * mapped to GRF registers with a vstride of 0, so apply the same
2359 if ((is_uniform(src
) ||
2360 (stage_uses_interleaved_attributes(stage
, prog_data
->dispatch_mode
) &&
2361 src
.file
== ATTR
)) &&
2362 (brw_mask_for_swizzle(src
.swizzle
) & 12))
2365 switch (src
.swizzle
) {
2366 case BRW_SWIZZLE_XYZW
:
2367 case BRW_SWIZZLE_XXZZ
:
2368 case BRW_SWIZZLE_YYWW
:
2369 case BRW_SWIZZLE_YXWZ
:
2372 return devinfo
->gen
== 7 && is_gen7_supported_64bit_swizzle(inst
, arg
);
2377 vec4_visitor::scalarize_df()
2379 bool progress
= false;
2381 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2382 /* Skip DF instructions that operate in Align1 mode */
2383 if (is_align1_df(inst
))
2386 /* Check if this is a double-precision instruction */
2387 bool is_double
= type_sz(inst
->dst
.type
) == 8;
2388 for (int arg
= 0; !is_double
&& arg
< 3; arg
++) {
2389 is_double
= inst
->src
[arg
].file
!= BAD_FILE
&&
2390 type_sz(inst
->src
[arg
].type
) == 8;
2396 /* Skip the lowering for specific regioning scenarios that we can
2399 bool skip_lowering
= true;
2401 /* XY and ZW writemasks operate in 32-bit, which means that they don't
2402 * have a native 64-bit representation and they should always be split.
2404 if (inst
->dst
.writemask
== WRITEMASK_XY
||
2405 inst
->dst
.writemask
== WRITEMASK_ZW
) {
2406 skip_lowering
= false;
2408 for (unsigned i
= 0; i
< 3; i
++) {
2409 if (inst
->src
[i
].file
== BAD_FILE
|| type_sz(inst
->src
[i
].type
) < 8)
2411 skip_lowering
= skip_lowering
&& is_supported_64bit_region(inst
, i
);
2418 /* Generate scalar instructions for each enabled channel */
2419 for (unsigned chan
= 0; chan
< 4; chan
++) {
2420 unsigned chan_mask
= 1 << chan
;
2421 if (!(inst
->dst
.writemask
& chan_mask
))
2424 vec4_instruction
*scalar_inst
= new(mem_ctx
) vec4_instruction(*inst
);
2426 for (unsigned i
= 0; i
< 3; i
++) {
2427 unsigned swz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, chan
);
2428 scalar_inst
->src
[i
].swizzle
= BRW_SWIZZLE4(swz
, swz
, swz
, swz
);
2431 scalar_inst
->dst
.writemask
= chan_mask
;
2433 if (inst
->predicate
!= BRW_PREDICATE_NONE
) {
2434 scalar_inst
->predicate
=
2435 scalarize_predicate(inst
->predicate
, chan_mask
);
2438 inst
->insert_before(block
, scalar_inst
);
2441 inst
->remove(block
);
2446 invalidate_live_intervals();
2452 vec4_visitor::lower_64bit_mad_to_mul_add()
2454 bool progress
= false;
2456 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2457 if (inst
->opcode
!= BRW_OPCODE_MAD
)
2460 if (type_sz(inst
->dst
.type
) != 8)
2463 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
2465 /* Use the copy constructor so we copy all relevant instruction fields
2466 * from the original mad into the add and mul instructions
2468 vec4_instruction
*mul
= new(mem_ctx
) vec4_instruction(*inst
);
2469 mul
->opcode
= BRW_OPCODE_MUL
;
2471 mul
->src
[0] = inst
->src
[1];
2472 mul
->src
[1] = inst
->src
[2];
2473 mul
->src
[2].file
= BAD_FILE
;
2475 vec4_instruction
*add
= new(mem_ctx
) vec4_instruction(*inst
);
2476 add
->opcode
= BRW_OPCODE_ADD
;
2477 add
->src
[0] = src_reg(mul_dst
);
2478 add
->src
[1] = inst
->src
[0];
2479 add
->src
[2].file
= BAD_FILE
;
2481 inst
->insert_before(block
, mul
);
2482 inst
->insert_before(block
, add
);
2483 inst
->remove(block
);
2489 invalidate_live_intervals();
2494 /* The align16 hardware can only do 32-bit swizzle channels, so we need to
2495 * translate the logical 64-bit swizzle channels that we use in the Vec4 IR
2496 * to 32-bit swizzle channels in hardware registers.
2498 * @inst and @arg identify the original vec4 IR source operand we need to
2499 * translate the swizzle for and @hw_reg is the hardware register where we
2500 * will write the hardware swizzle to use.
2502 * This pass assumes that Align16/DF instructions have been fully scalarized
2503 * previously so there is just one 64-bit swizzle channel to deal with for any
2504 * given Vec4 IR source.
2507 vec4_visitor::apply_logical_swizzle(struct brw_reg
*hw_reg
,
2508 vec4_instruction
*inst
, int arg
)
2510 src_reg reg
= inst
->src
[arg
];
2512 if (reg
.file
== BAD_FILE
|| reg
.file
== BRW_IMMEDIATE_VALUE
)
2515 /* If this is not a 64-bit operand or this is a scalar instruction we don't
2516 * need to do anything about the swizzles.
2518 if(type_sz(reg
.type
) < 8 || is_align1_df(inst
)) {
2519 hw_reg
->swizzle
= reg
.swizzle
;
2523 /* Take the 64-bit logical swizzle channel and translate it to 32-bit */
2524 assert(brw_is_single_value_swizzle(reg
.swizzle
) ||
2525 is_supported_64bit_region(inst
, arg
));
2527 /* Apply the region <2, 2, 1> for GRF or <0, 2, 1> for uniforms, as align16
2528 * HW can only do 32-bit swizzle channels.
2530 hw_reg
->width
= BRW_WIDTH_2
;
2532 if (is_supported_64bit_region(inst
, arg
) &&
2533 !is_gen7_supported_64bit_swizzle(inst
, arg
)) {
2534 /* Supported 64-bit swizzles are those such that their first two
2535 * components, when expanded to 32-bit swizzles, match the semantics
2536 * of the original 64-bit swizzle with 2-wide row regioning.
2538 unsigned swizzle0
= BRW_GET_SWZ(reg
.swizzle
, 0);
2539 unsigned swizzle1
= BRW_GET_SWZ(reg
.swizzle
, 1);
2540 hw_reg
->swizzle
= BRW_SWIZZLE4(swizzle0
* 2, swizzle0
* 2 + 1,
2541 swizzle1
* 2, swizzle1
* 2 + 1);
2543 /* If we got here then we have one of the following:
2545 * 1. An unsupported swizzle, which should be single-value thanks to the
2546 * scalarization pass.
2548 * 2. A gen7 supported swizzle. These can be single-value or double-value
2549 * swizzles. If the latter, they are never cross-dvec2 channels. For
2550 * these we always need to activate the gen7 vstride=0 exploit.
2552 unsigned swizzle0
= BRW_GET_SWZ(reg
.swizzle
, 0);
2553 unsigned swizzle1
= BRW_GET_SWZ(reg
.swizzle
, 1);
2554 assert((swizzle0
< 2) == (swizzle1
< 2));
2556 /* To gain access to Z/W components we need to select the second half
2557 * of the register and then use a X/Y swizzle to select Z/W respectively.
2559 if (swizzle0
>= 2) {
2560 *hw_reg
= suboffset(*hw_reg
, 2);
2565 /* All gen7-specific supported swizzles require the vstride=0 exploit */
2566 if (devinfo
->gen
== 7 && is_gen7_supported_64bit_swizzle(inst
, arg
))
2567 hw_reg
->vstride
= BRW_VERTICAL_STRIDE_0
;
2569 /* Any 64-bit source with an offset at 16B is intended to address the
2570 * second half of a register and needs a vertical stride of 0 so we:
2572 * 1. Don't violate register region restrictions.
2573 * 2. Activate the gen7 instruction decompresion bug exploit when
2576 if (hw_reg
->subnr
% REG_SIZE
== 16) {
2577 assert(devinfo
->gen
== 7);
2578 hw_reg
->vstride
= BRW_VERTICAL_STRIDE_0
;
2581 hw_reg
->swizzle
= BRW_SWIZZLE4(swizzle0
* 2, swizzle0
* 2 + 1,
2582 swizzle1
* 2, swizzle1
* 2 + 1);
2589 if (shader_time_index
>= 0)
2590 emit_shader_time_begin();
2603 /* Before any optimization, push array accesses out to scratch
2604 * space where we need them to be. This pass may allocate new
2605 * virtual GRFs, so we want to do it early. It also makes sure
2606 * that we have reladdr computations available for CSE, since we'll
2607 * often do repeated subexpressions for those.
2609 move_grf_array_access_to_scratch();
2610 move_uniform_array_access_to_pull_constants();
2612 pack_uniform_registers();
2613 move_push_constants_to_pull_constants();
2614 split_virtual_grfs();
2616 #define OPT(pass, args...) ({ \
2618 bool this_progress = pass(args); \
2620 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
2621 char filename[64]; \
2622 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
2623 stage_abbrev, nir->info.name, iteration, pass_num); \
2625 backend_shader::dump_instructions(filename); \
2628 progress = progress || this_progress; \
2633 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
2635 snprintf(filename
, 64, "%s-%s-00-00-start",
2636 stage_abbrev
, nir
->info
.name
);
2638 backend_shader::dump_instructions(filename
);
2649 OPT(opt_predicated_break
, this);
2650 OPT(opt_reduce_swizzle
);
2651 OPT(dead_code_eliminate
);
2652 OPT(dead_control_flow_eliminate
, this);
2653 OPT(opt_copy_propagation
);
2654 OPT(opt_cmod_propagation
);
2657 OPT(opt_register_coalesce
);
2658 OPT(eliminate_find_live_channel
);
2663 if (OPT(opt_vector_float
)) {
2665 OPT(opt_copy_propagation
, false);
2666 OPT(opt_copy_propagation
, true);
2667 OPT(dead_code_eliminate
);
2670 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
2671 OPT(opt_cmod_propagation
);
2673 OPT(opt_copy_propagation
);
2674 OPT(dead_code_eliminate
);
2677 if (OPT(lower_simd_width
)) {
2678 OPT(opt_copy_propagation
);
2679 OPT(dead_code_eliminate
);
2685 OPT(lower_64bit_mad_to_mul_add
);
2687 /* Run this before payload setup because tesselation shaders
2688 * rely on it to prevent cross dvec2 regioning on DF attributes
2689 * that are setup so that XY are on the second half of register and
2690 * ZW are in the first half of the next.
2696 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
2697 /* Debug of register spilling: Go spill everything. */
2698 const int grf_count
= alloc
.count
;
2699 float spill_costs
[alloc
.count
];
2700 bool no_spill
[alloc
.count
];
2701 evaluate_spill_costs(spill_costs
, no_spill
);
2702 for (int i
= 0; i
< grf_count
; i
++) {
2708 /* We want to run this after spilling because 64-bit (un)spills need to
2709 * emit code to shuffle 64-bit data for the 32-bit scratch read/write
2710 * messages that can produce unsupported 64-bit swizzle regions.
2715 bool allocated_without_spills
= reg_allocate();
2717 if (!allocated_without_spills
) {
2718 compiler
->shader_perf_log(log_data
,
2719 "%s shader triggered register spilling. "
2720 "Try reducing the number of live vec4 values "
2721 "to improve performance.\n",
2724 while (!reg_allocate()) {
2729 /* We want to run this after spilling because 64-bit (un)spills need to
2730 * emit code to shuffle 64-bit data for the 32-bit scratch read/write
2731 * messages that can produce unsupported 64-bit swizzle regions.
2736 opt_schedule_instructions();
2738 opt_set_dependency_control();
2740 convert_to_hw_regs();
2742 if (last_scratch
> 0) {
2743 prog_data
->base
.total_scratch
=
2744 brw_get_scratch_size(last_scratch
* REG_SIZE
);
2750 } /* namespace brw */
2755 * Compile a vertex shader.
2757 * Returns the final assembly and the program's size.
2760 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
2762 const struct brw_vs_prog_key
*key
,
2763 struct brw_vs_prog_data
*prog_data
,
2764 const nir_shader
*src_shader
,
2765 gl_clip_plane
*clip_planes
,
2766 bool use_legacy_snorm_formula
,
2767 int shader_time_index
,
2768 unsigned *final_assembly_size
,
2771 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_VERTEX
];
2772 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
2773 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, is_scalar
);
2774 brw_nir_lower_vs_inputs(shader
, is_scalar
,
2775 use_legacy_snorm_formula
, key
->gl_attrib_wa_flags
);
2776 brw_nir_lower_vue_outputs(shader
, is_scalar
);
2777 shader
= brw_postprocess_nir(shader
, compiler
, is_scalar
);
2779 const unsigned *assembly
= NULL
;
2781 if (prog_data
->base
.vue_map
.varying_to_slot
[VARYING_SLOT_EDGE
] != -1) {
2782 /* If the output VUE map contains VARYING_SLOT_EDGE then we need to copy
2783 * the edge flag from VERT_ATTRIB_EDGEFLAG. This will be done
2784 * automatically by brw_vec4_visitor::emit_urb_slot but we need to
2785 * ensure that prog_data->inputs_read is accurate.
2788 assert(key
->copy_edgeflag
);
2789 prog_data
->inputs_read
|= VERT_BIT_EDGEFLAG
;
2792 prog_data
->inputs_read
= shader
->info
.inputs_read
;
2793 prog_data
->double_inputs_read
= shader
->info
.double_inputs_read
;
2795 prog_data
->base
.clip_distance_mask
=
2796 ((1 << shader
->info
.clip_distance_array_size
) - 1);
2797 prog_data
->base
.cull_distance_mask
=
2798 ((1 << shader
->info
.cull_distance_array_size
) - 1) <<
2799 shader
->info
.clip_distance_array_size
;
2801 unsigned nr_attribute_slots
= _mesa_bitcount_64(prog_data
->inputs_read
);
2803 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
2804 * incoming vertex attribute. So, add an extra slot.
2806 if (shader
->info
.system_values_read
&
2807 (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
) |
2808 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
2809 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
2810 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
2811 nr_attribute_slots
++;
2814 if (shader
->info
.system_values_read
&
2815 BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
))
2816 prog_data
->uses_basevertex
= true;
2818 if (shader
->info
.system_values_read
&
2819 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
))
2820 prog_data
->uses_baseinstance
= true;
2822 if (shader
->info
.system_values_read
&
2823 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
))
2824 prog_data
->uses_vertexid
= true;
2826 if (shader
->info
.system_values_read
&
2827 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))
2828 prog_data
->uses_instanceid
= true;
2830 /* gl_DrawID has its very own vec4 */
2831 if (shader
->info
.system_values_read
&
2832 BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
)) {
2833 prog_data
->uses_drawid
= true;
2834 nr_attribute_slots
++;
2837 unsigned nr_attributes
= nr_attribute_slots
-
2838 DIV_ROUND_UP(_mesa_bitcount_64(shader
->info
.double_inputs_read
), 2);
2840 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
2841 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
2842 * vec4 mode, the hardware appears to wedge unless we read something.
2845 prog_data
->base
.urb_read_length
=
2846 DIV_ROUND_UP(nr_attribute_slots
, 2);
2848 prog_data
->base
.urb_read_length
=
2849 DIV_ROUND_UP(MAX2(nr_attribute_slots
, 1), 2);
2851 prog_data
->nr_attributes
= nr_attributes
;
2852 prog_data
->nr_attribute_slots
= nr_attribute_slots
;
2854 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
2855 * (overwriting the original contents), we need to make sure the size is
2856 * the larger of the two.
2858 const unsigned vue_entries
=
2859 MAX2(nr_attribute_slots
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
2861 if (compiler
->devinfo
->gen
== 6)
2862 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2864 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2866 if (INTEL_DEBUG
& DEBUG_VS
) {
2867 fprintf(stderr
, "VS Output ");
2868 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
2872 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2874 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2875 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2876 shader
, 8, shader_time_index
);
2877 if (!v
.run_vs(clip_planes
)) {
2879 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2884 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
2886 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
2887 &prog_data
->base
.base
, v
.promoted_constants
,
2888 v
.runtime_check_aads_emit
, MESA_SHADER_VERTEX
);
2889 if (INTEL_DEBUG
& DEBUG_VS
) {
2890 const char *debug_name
=
2891 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2892 shader
->info
.label
? shader
->info
.label
:
2896 g
.enable_debug(debug_name
);
2898 g
.generate_code(v
.cfg
, 8);
2899 assembly
= g
.get_assembly(final_assembly_size
);
2903 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2905 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2906 shader
, clip_planes
, mem_ctx
,
2907 shader_time_index
, use_legacy_snorm_formula
);
2910 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2915 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2916 shader
, &prog_data
->base
, v
.cfg
,
2917 final_assembly_size
);