2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_vec4_builder.h"
29 #include "brw_vec4_live_variables.h"
30 #include "brw_vec4_vs.h"
31 #include "brw_dead_control_flow.h"
32 #include "common/gen_debug.h"
33 #include "program/prog_parameter.h"
35 #define MAX_INSTRUCTION (1 << 30)
44 memset(this, 0, sizeof(*this));
45 this->file
= BAD_FILE
;
46 this->type
= BRW_REGISTER_TYPE_UD
;
49 src_reg::src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
)
55 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
56 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
58 this->swizzle
= BRW_SWIZZLE_XYZW
;
60 this->type
= brw_type_for_base_type(type
);
63 /** Generic unset register constructor. */
69 src_reg::src_reg(struct ::brw_reg reg
) :
76 src_reg::src_reg(const dst_reg
®
) :
79 this->reladdr
= reg
.reladdr
;
80 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
86 memset(this, 0, sizeof(*this));
87 this->file
= BAD_FILE
;
88 this->type
= BRW_REGISTER_TYPE_UD
;
89 this->writemask
= WRITEMASK_XYZW
;
97 dst_reg::dst_reg(enum brw_reg_file file
, int nr
)
105 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
112 this->type
= brw_type_for_base_type(type
);
113 this->writemask
= writemask
;
116 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
124 this->writemask
= writemask
;
127 dst_reg::dst_reg(struct ::brw_reg reg
) :
131 this->reladdr
= NULL
;
134 dst_reg::dst_reg(const src_reg
®
) :
137 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
138 this->reladdr
= reg
.reladdr
;
142 dst_reg::equals(const dst_reg
&r
) const
144 return (this->backend_reg::equals(r
) &&
145 (reladdr
== r
.reladdr
||
146 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
150 vec4_instruction::is_send_from_grf()
153 case SHADER_OPCODE_SHADER_TIME_ADD
:
154 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
155 case SHADER_OPCODE_UNTYPED_ATOMIC
:
156 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
157 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
158 case SHADER_OPCODE_TYPED_ATOMIC
:
159 case SHADER_OPCODE_TYPED_SURFACE_READ
:
160 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
161 case VEC4_OPCODE_URB_READ
:
162 case TCS_OPCODE_URB_WRITE
:
163 case TCS_OPCODE_RELEASE_INPUT
:
164 case SHADER_OPCODE_BARRIER
:
172 * Returns true if this instruction's sources and destinations cannot
173 * safely be the same register.
175 * In most cases, a register can be written over safely by the same
176 * instruction that is its last use. For a single instruction, the
177 * sources are dereferenced before writing of the destination starts
180 * However, there are a few cases where this can be problematic:
182 * - Virtual opcodes that translate to multiple instructions in the
183 * code generator: if src == dst and one instruction writes the
184 * destination before a later instruction reads the source, then
185 * src will have been clobbered.
187 * The register allocator uses this information to set up conflicts between
188 * GRF sources and the destination.
191 vec4_instruction::has_source_and_destination_hazard() const
194 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
195 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
196 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
199 /* 8-wide compressed DF operations are executed as two 4-wide operations,
200 * so we have a src/dst hazard if the first half of the instruction
201 * overwrites the source of the second half. Prevent this by marking
202 * compressed instructions as having src/dst hazards, so the register
203 * allocator assigns safe register regions for dst and srcs.
205 return size_written
> REG_SIZE
;
210 vec4_instruction::size_read(unsigned arg
) const
213 case SHADER_OPCODE_SHADER_TIME_ADD
:
214 case SHADER_OPCODE_UNTYPED_ATOMIC
:
215 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
216 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
217 case SHADER_OPCODE_TYPED_ATOMIC
:
218 case SHADER_OPCODE_TYPED_SURFACE_READ
:
219 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
220 case TCS_OPCODE_URB_WRITE
:
222 return mlen
* REG_SIZE
;
224 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
226 return mlen
* REG_SIZE
;
232 switch (src
[arg
].file
) {
237 return 4 * type_sz(src
[arg
].type
);
239 /* XXX - Represent actual vertical stride. */
240 return exec_size
* type_sz(src
[arg
].type
);
245 vec4_instruction::can_do_source_mods(const struct gen_device_info
*devinfo
)
247 if (devinfo
->gen
== 6 && is_math())
250 if (is_send_from_grf())
253 if (!backend_instruction::can_do_source_mods())
260 vec4_instruction::can_do_writemask(const struct gen_device_info
*devinfo
)
263 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
264 case VEC4_OPCODE_DOUBLE_TO_F32
:
265 case VEC4_OPCODE_DOUBLE_TO_D32
:
266 case VEC4_OPCODE_DOUBLE_TO_U32
:
267 case VEC4_OPCODE_TO_DOUBLE
:
268 case VEC4_OPCODE_PICK_LOW_32BIT
:
269 case VEC4_OPCODE_PICK_HIGH_32BIT
:
270 case VEC4_OPCODE_SET_LOW_32BIT
:
271 case VEC4_OPCODE_SET_HIGH_32BIT
:
272 case VS_OPCODE_PULL_CONSTANT_LOAD
:
273 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
274 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
275 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
276 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
277 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
278 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
279 case VEC4_OPCODE_URB_READ
:
280 case SHADER_OPCODE_MOV_INDIRECT
:
283 /* The MATH instruction on Gen6 only executes in align1 mode, which does
284 * not support writemasking.
286 if (devinfo
->gen
== 6 && is_math())
297 vec4_instruction::can_change_types() const
299 return dst
.type
== src
[0].type
&&
300 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
301 (opcode
== BRW_OPCODE_MOV
||
302 (opcode
== BRW_OPCODE_SEL
&&
303 dst
.type
== src
[1].type
&&
304 predicate
!= BRW_PREDICATE_NONE
&&
305 !src
[1].abs
&& !src
[1].negate
));
309 * Returns how many MRFs an opcode will write over.
311 * Note that this is not the 0 or 1 implied writes in an actual gen
312 * instruction -- the generate_* functions generate additional MOVs
316 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
318 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
321 switch (inst
->opcode
) {
322 case SHADER_OPCODE_RCP
:
323 case SHADER_OPCODE_RSQ
:
324 case SHADER_OPCODE_SQRT
:
325 case SHADER_OPCODE_EXP2
:
326 case SHADER_OPCODE_LOG2
:
327 case SHADER_OPCODE_SIN
:
328 case SHADER_OPCODE_COS
:
330 case SHADER_OPCODE_INT_QUOTIENT
:
331 case SHADER_OPCODE_INT_REMAINDER
:
332 case SHADER_OPCODE_POW
:
333 case TCS_OPCODE_THREAD_END
:
335 case VS_OPCODE_URB_WRITE
:
337 case VS_OPCODE_PULL_CONSTANT_LOAD
:
339 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
341 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
343 case GS_OPCODE_URB_WRITE
:
344 case GS_OPCODE_URB_WRITE_ALLOCATE
:
345 case GS_OPCODE_THREAD_END
:
347 case GS_OPCODE_FF_SYNC
:
349 case TCS_OPCODE_URB_WRITE
:
351 case SHADER_OPCODE_SHADER_TIME_ADD
:
353 case SHADER_OPCODE_TEX
:
354 case SHADER_OPCODE_TXL
:
355 case SHADER_OPCODE_TXD
:
356 case SHADER_OPCODE_TXF
:
357 case SHADER_OPCODE_TXF_CMS
:
358 case SHADER_OPCODE_TXF_CMS_W
:
359 case SHADER_OPCODE_TXF_MCS
:
360 case SHADER_OPCODE_TXS
:
361 case SHADER_OPCODE_TG4
:
362 case SHADER_OPCODE_TG4_OFFSET
:
363 case SHADER_OPCODE_SAMPLEINFO
:
364 case VS_OPCODE_GET_BUFFER_SIZE
:
365 return inst
->header_size
;
367 unreachable("not reached");
372 src_reg::equals(const src_reg
&r
) const
374 return (this->backend_reg::equals(r
) &&
375 !reladdr
&& !r
.reladdr
);
379 vec4_visitor::opt_vector_float()
381 bool progress
= false;
383 foreach_block(block
, cfg
) {
384 int last_reg
= -1, last_offset
= -1;
385 enum brw_reg_file last_reg_file
= BAD_FILE
;
387 uint8_t imm
[4] = { 0 };
389 vec4_instruction
*imm_inst
[4];
390 unsigned writemask
= 0;
391 enum brw_reg_type dest_type
= BRW_REGISTER_TYPE_F
;
393 foreach_inst_in_block_safe(vec4_instruction
, inst
, block
) {
395 enum brw_reg_type need_type
;
397 /* Look for unconditional MOVs from an immediate with a partial
398 * writemask. Skip type-conversion MOVs other than integer 0,
399 * where the type doesn't matter. See if the immediate can be
400 * represented as a VF.
402 if (inst
->opcode
== BRW_OPCODE_MOV
&&
403 inst
->src
[0].file
== IMM
&&
404 inst
->predicate
== BRW_PREDICATE_NONE
&&
405 inst
->dst
.writemask
!= WRITEMASK_XYZW
&&
406 type_sz(inst
->src
[0].type
) < 8 &&
407 (inst
->src
[0].type
== inst
->dst
.type
|| inst
->src
[0].d
== 0)) {
409 vf
= brw_float_to_vf(inst
->src
[0].d
);
410 need_type
= BRW_REGISTER_TYPE_D
;
413 vf
= brw_float_to_vf(inst
->src
[0].f
);
414 need_type
= BRW_REGISTER_TYPE_F
;
420 /* If this wasn't a MOV, or the destination register doesn't match,
421 * or we have to switch destination types, then this breaks our
422 * sequence. Combine anything we've accumulated so far.
424 if (last_reg
!= inst
->dst
.nr
||
425 last_offset
!= inst
->dst
.offset
||
426 last_reg_file
!= inst
->dst
.file
||
427 (vf
> 0 && dest_type
!= need_type
)) {
429 if (inst_count
> 1) {
431 memcpy(&vf
, imm
, sizeof(vf
));
432 vec4_instruction
*mov
= MOV(imm_inst
[0]->dst
, brw_imm_vf(vf
));
433 mov
->dst
.type
= dest_type
;
434 mov
->dst
.writemask
= writemask
;
435 inst
->insert_before(block
, mov
);
437 for (int i
= 0; i
< inst_count
; i
++) {
438 imm_inst
[i
]->remove(block
);
447 dest_type
= BRW_REGISTER_TYPE_F
;
449 for (int i
= 0; i
< 4; i
++) {
454 /* Record this instruction's value (if it was representable). */
456 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
458 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
460 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
462 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
465 writemask
|= inst
->dst
.writemask
;
466 imm_inst
[inst_count
++] = inst
;
468 last_reg
= inst
->dst
.nr
;
469 last_offset
= inst
->dst
.offset
;
470 last_reg_file
= inst
->dst
.file
;
472 dest_type
= need_type
;
478 invalidate_live_intervals();
483 /* Replaces unused channels of a swizzle with channels that are used.
485 * For instance, this pass transforms
487 * mov vgrf4.yz, vgrf5.wxzy
491 * mov vgrf4.yz, vgrf5.xxzx
493 * This eliminates false uses of some channels, letting dead code elimination
494 * remove the instructions that wrote them.
497 vec4_visitor::opt_reduce_swizzle()
499 bool progress
= false;
501 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
502 if (inst
->dst
.file
== BAD_FILE
||
503 inst
->dst
.file
== ARF
||
504 inst
->dst
.file
== FIXED_GRF
||
505 inst
->is_send_from_grf())
510 /* Determine which channels of the sources are read. */
511 switch (inst
->opcode
) {
512 case VEC4_OPCODE_PACK_BYTES
:
514 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
515 * but all four of src1.
517 swizzle
= brw_swizzle_for_size(4);
520 swizzle
= brw_swizzle_for_size(3);
523 swizzle
= brw_swizzle_for_size(2);
526 case VEC4_OPCODE_TO_DOUBLE
:
527 case VEC4_OPCODE_DOUBLE_TO_F32
:
528 case VEC4_OPCODE_DOUBLE_TO_D32
:
529 case VEC4_OPCODE_DOUBLE_TO_U32
:
530 case VEC4_OPCODE_PICK_LOW_32BIT
:
531 case VEC4_OPCODE_PICK_HIGH_32BIT
:
532 case VEC4_OPCODE_SET_LOW_32BIT
:
533 case VEC4_OPCODE_SET_HIGH_32BIT
:
534 swizzle
= brw_swizzle_for_size(4);
538 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
542 /* Update sources' swizzles. */
543 for (int i
= 0; i
< 3; i
++) {
544 if (inst
->src
[i
].file
!= VGRF
&&
545 inst
->src
[i
].file
!= ATTR
&&
546 inst
->src
[i
].file
!= UNIFORM
)
549 const unsigned new_swizzle
=
550 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
551 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
552 inst
->src
[i
].swizzle
= new_swizzle
;
559 invalidate_live_intervals();
565 vec4_visitor::split_uniform_registers()
567 /* Prior to this, uniforms have been in an array sized according to
568 * the number of vector uniforms present, sparsely filled (so an
569 * aggregate results in reg indices being skipped over). Now we're
570 * going to cut those aggregates up so each .nr index is one
571 * vector. The goal is to make elimination of unused uniform
572 * components easier later.
574 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
575 for (int i
= 0 ; i
< 3; i
++) {
576 if (inst
->src
[i
].file
!= UNIFORM
)
579 assert(!inst
->src
[i
].reladdr
);
581 inst
->src
[i
].nr
+= inst
->src
[i
].offset
/ 16;
582 inst
->src
[i
].offset
%= 16;
587 /* This function returns the register number where we placed the uniform */
589 set_push_constant_loc(const int nr_uniforms
, int *new_uniform_count
,
590 const int src
, const int size
, const int channel_size
,
591 int *new_loc
, int *new_chan
,
595 /* Find the lowest place we can slot this uniform in. */
596 for (dst
= 0; dst
< nr_uniforms
; dst
++) {
597 if (ALIGN(new_chans_used
[dst
], channel_size
) + size
<= 4)
601 assert(dst
< nr_uniforms
);
604 new_chan
[src
] = ALIGN(new_chans_used
[dst
], channel_size
);
605 new_chans_used
[dst
] = ALIGN(new_chans_used
[dst
], channel_size
) + size
;
607 *new_uniform_count
= MAX2(*new_uniform_count
, dst
+ 1);
612 vec4_visitor::pack_uniform_registers()
614 uint8_t chans_used
[this->uniforms
];
615 int new_loc
[this->uniforms
];
616 int new_chan
[this->uniforms
];
617 bool is_aligned_to_dvec4
[this->uniforms
];
618 int new_chans_used
[this->uniforms
];
619 int channel_sizes
[this->uniforms
];
621 memset(chans_used
, 0, sizeof(chans_used
));
622 memset(new_loc
, 0, sizeof(new_loc
));
623 memset(new_chan
, 0, sizeof(new_chan
));
624 memset(new_chans_used
, 0, sizeof(new_chans_used
));
625 memset(is_aligned_to_dvec4
, 0, sizeof(is_aligned_to_dvec4
));
626 memset(channel_sizes
, 0, sizeof(channel_sizes
));
628 /* Find which uniform vectors are actually used by the program. We
629 * expect unused vector elements when we've moved array access out
630 * to pull constants, and from some GLSL code generators like wine.
632 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
634 switch (inst
->opcode
) {
635 case VEC4_OPCODE_PACK_BYTES
:
647 readmask
= inst
->dst
.writemask
;
651 for (int i
= 0 ; i
< 3; i
++) {
652 if (inst
->src
[i
].file
!= UNIFORM
)
655 assert(type_sz(inst
->src
[i
].type
) % 4 == 0);
656 int channel_size
= type_sz(inst
->src
[i
].type
) / 4;
658 int reg
= inst
->src
[i
].nr
;
659 for (int c
= 0; c
< 4; c
++) {
660 if (!(readmask
& (1 << c
)))
663 unsigned channel
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1;
664 unsigned used
= MAX2(chans_used
[reg
], channel
* channel_size
);
666 chans_used
[reg
] = used
;
667 channel_sizes
[reg
] = MAX2(channel_sizes
[reg
], channel_size
);
669 is_aligned_to_dvec4
[reg
] = true;
670 is_aligned_to_dvec4
[reg
+ 1] = true;
671 chans_used
[reg
+ 1] = used
- 4;
672 channel_sizes
[reg
+ 1] = MAX2(channel_sizes
[reg
+ 1], channel_size
);
677 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
678 inst
->src
[0].file
== UNIFORM
) {
679 assert(inst
->src
[2].file
== BRW_IMMEDIATE_VALUE
);
680 assert(inst
->src
[0].subnr
== 0);
682 unsigned bytes_read
= inst
->src
[2].ud
;
683 assert(bytes_read
% 4 == 0);
684 unsigned vec4s_read
= DIV_ROUND_UP(bytes_read
, 16);
686 /* We just mark every register touched by a MOV_INDIRECT as being
687 * fully used. This ensures that it doesn't broken up piecewise by
688 * the next part of our packing algorithm.
690 int reg
= inst
->src
[0].nr
;
691 for (unsigned i
= 0; i
< vec4s_read
; i
++)
692 chans_used
[reg
+ i
] = 4;
696 int new_uniform_count
= 0;
698 /* As the uniforms are going to be reordered, take the data from a temporary
699 * copy of the original param[].
701 uint32_t *param
= ralloc_array(NULL
, uint32_t, stage_prog_data
->nr_params
);
702 memcpy(param
, stage_prog_data
->param
,
703 sizeof(uint32_t) * stage_prog_data
->nr_params
);
705 /* Now, figure out a packing of the live uniform vectors into our
706 * push constants. Start with dvec{3,4} because they are aligned to
707 * dvec4 size (2 vec4).
709 for (int src
= 0; src
< uniforms
; src
++) {
710 int size
= chans_used
[src
];
712 if (size
== 0 || !is_aligned_to_dvec4
[src
])
715 /* dvec3 are aligned to dvec4 size, apply the alignment of the size
716 * to 4 to avoid moving last component of a dvec3 to the available
717 * location at the end of a previous dvec3. These available locations
718 * could be filled by smaller variables in next loop.
720 size
= ALIGN(size
, 4);
721 int dst
= set_push_constant_loc(uniforms
, &new_uniform_count
,
722 src
, size
, channel_sizes
[src
],
725 /* Move the references to the data */
726 for (int j
= 0; j
< size
; j
++) {
727 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
732 /* Continue with the rest of data, which is aligned to vec4. */
733 for (int src
= 0; src
< uniforms
; src
++) {
734 int size
= chans_used
[src
];
736 if (size
== 0 || is_aligned_to_dvec4
[src
])
739 int dst
= set_push_constant_loc(uniforms
, &new_uniform_count
,
740 src
, size
, channel_sizes
[src
],
743 /* Move the references to the data */
744 for (int j
= 0; j
< size
; j
++) {
745 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
751 this->uniforms
= new_uniform_count
;
753 /* Now, update the instructions for our repacked uniforms. */
754 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
755 for (int i
= 0 ; i
< 3; i
++) {
756 int src
= inst
->src
[i
].nr
;
758 if (inst
->src
[i
].file
!= UNIFORM
)
761 int chan
= new_chan
[src
] / channel_sizes
[src
];
762 inst
->src
[i
].nr
= new_loc
[src
];
763 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(chan
, chan
, chan
, chan
);
769 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
771 * While GLSL IR also performs this optimization, we end up with it in
772 * our instruction stream for a couple of reasons. One is that we
773 * sometimes generate silly instructions, for example in array access
774 * where we'll generate "ADD offset, index, base" even if base is 0.
775 * The other is that GLSL IR's constant propagation doesn't track the
776 * components of aggregates, so some VS patterns (initialize matrix to
777 * 0, accumulate in vertex blending factors) end up breaking down to
778 * instructions involving 0.
781 vec4_visitor::opt_algebraic()
783 bool progress
= false;
785 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
786 switch (inst
->opcode
) {
788 if (inst
->src
[0].file
!= IMM
)
791 if (inst
->saturate
) {
792 if (inst
->dst
.type
!= inst
->src
[0].type
)
793 assert(!"unimplemented: saturate mixed types");
795 if (brw_saturate_immediate(inst
->dst
.type
,
796 &inst
->src
[0].as_brw_reg())) {
797 inst
->saturate
= false;
803 case VEC4_OPCODE_UNPACK_UNIFORM
:
804 if (inst
->src
[0].file
!= UNIFORM
) {
805 inst
->opcode
= BRW_OPCODE_MOV
;
811 if (inst
->src
[1].is_zero()) {
812 inst
->opcode
= BRW_OPCODE_MOV
;
813 inst
->src
[1] = src_reg();
819 if (inst
->src
[1].is_zero()) {
820 inst
->opcode
= BRW_OPCODE_MOV
;
821 switch (inst
->src
[0].type
) {
822 case BRW_REGISTER_TYPE_F
:
823 inst
->src
[0] = brw_imm_f(0.0f
);
825 case BRW_REGISTER_TYPE_D
:
826 inst
->src
[0] = brw_imm_d(0);
828 case BRW_REGISTER_TYPE_UD
:
829 inst
->src
[0] = brw_imm_ud(0u);
832 unreachable("not reached");
834 inst
->src
[1] = src_reg();
836 } else if (inst
->src
[1].is_one()) {
837 inst
->opcode
= BRW_OPCODE_MOV
;
838 inst
->src
[1] = src_reg();
840 } else if (inst
->src
[1].is_negative_one()) {
841 inst
->opcode
= BRW_OPCODE_MOV
;
842 inst
->src
[0].negate
= !inst
->src
[0].negate
;
843 inst
->src
[1] = src_reg();
848 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
850 inst
->src
[0].negate
&&
851 inst
->src
[1].is_zero()) {
852 inst
->src
[0].abs
= false;
853 inst
->src
[0].negate
= false;
854 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
859 case SHADER_OPCODE_BROADCAST
:
860 if (is_uniform(inst
->src
[0]) ||
861 inst
->src
[1].is_zero()) {
862 inst
->opcode
= BRW_OPCODE_MOV
;
863 inst
->src
[1] = src_reg();
864 inst
->force_writemask_all
= true;
875 invalidate_live_intervals();
881 * Only a limited number of hardware registers may be used for push
882 * constants, so this turns access to the overflowed constants into
886 vec4_visitor::move_push_constants_to_pull_constants()
888 int pull_constant_loc
[this->uniforms
];
890 /* Only allow 32 registers (256 uniform components) as push constants,
891 * which is the limit on gen6.
893 * If changing this value, note the limitation about total_regs in
896 int max_uniform_components
= 32 * 8;
897 if (this->uniforms
* 4 <= max_uniform_components
)
900 /* Make some sort of choice as to which uniforms get sent to pull
901 * constants. We could potentially do something clever here like
902 * look for the most infrequently used uniform vec4s, but leave
905 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
906 pull_constant_loc
[i
/ 4] = -1;
908 if (i
>= max_uniform_components
) {
909 uint32_t *values
= &stage_prog_data
->param
[i
];
911 /* Try to find an existing copy of this uniform in the pull
912 * constants if it was part of an array access already.
914 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
917 for (matches
= 0; matches
< 4; matches
++) {
918 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
923 pull_constant_loc
[i
/ 4] = j
/ 4;
928 if (pull_constant_loc
[i
/ 4] == -1) {
929 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
930 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
932 for (int j
= 0; j
< 4; j
++) {
933 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
940 /* Now actually rewrite usage of the things we've moved to pull
943 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
944 for (int i
= 0 ; i
< 3; i
++) {
945 if (inst
->src
[i
].file
!= UNIFORM
||
946 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
949 int uniform
= inst
->src
[i
].nr
;
951 const glsl_type
*temp_type
= type_sz(inst
->src
[i
].type
) == 8 ?
952 glsl_type::dvec4_type
: glsl_type::vec4_type
;
953 dst_reg temp
= dst_reg(this, temp_type
);
955 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
956 pull_constant_loc
[uniform
], src_reg());
958 inst
->src
[i
].file
= temp
.file
;
959 inst
->src
[i
].nr
= temp
.nr
;
960 inst
->src
[i
].offset
%= 16;
961 inst
->src
[i
].reladdr
= NULL
;
965 /* Repack push constants to remove the now-unused ones. */
966 pack_uniform_registers();
969 /* Conditions for which we want to avoid setting the dependency control bits */
971 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
973 #define IS_DWORD(reg) \
974 (reg.type == BRW_REGISTER_TYPE_UD || \
975 reg.type == BRW_REGISTER_TYPE_D)
977 #define IS_64BIT(reg) (reg.file != BAD_FILE && type_sz(reg.type) == 8)
979 /* From the Cherryview and Broadwell PRMs:
981 * "When source or destination datatype is 64b or operation is integer DWord
982 * multiply, DepCtrl must not be used."
984 * SKL PRMs don't include this restriction, however, gen7 seems to be
985 * affected, at least by the 64b restriction, since DepCtrl with double
986 * precision instructions seems to produce GPU hangs in some cases.
988 if (devinfo
->gen
== 8 || gen_device_info_is_9lp(devinfo
)) {
989 if (inst
->opcode
== BRW_OPCODE_MUL
&&
990 IS_DWORD(inst
->src
[0]) &&
991 IS_DWORD(inst
->src
[1]))
995 if (devinfo
->gen
>= 7 && devinfo
->gen
<= 8) {
996 if (IS_64BIT(inst
->dst
) || IS_64BIT(inst
->src
[0]) ||
997 IS_64BIT(inst
->src
[1]) || IS_64BIT(inst
->src
[2]))
1004 if (devinfo
->gen
>= 8) {
1005 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
1011 * In the presence of send messages, totally interrupt dependency
1012 * control. They're long enough that the chance of dependency
1013 * control around them just doesn't matter.
1016 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
1017 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
1018 * completes the scoreboard clear must have a non-zero execution mask. This
1019 * means, if any kind of predication can change the execution mask or channel
1020 * enable of the last instruction, the optimization must be avoided. This is
1021 * to avoid instructions being shot down the pipeline when no writes are
1025 * Dependency control does not work well over math instructions.
1026 * NB: Discovered empirically
1028 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
1032 * Sets the dependency control fields on instructions after register
1033 * allocation and before the generator is run.
1035 * When you have a sequence of instructions like:
1037 * DP4 temp.x vertex uniform[0]
1038 * DP4 temp.y vertex uniform[0]
1039 * DP4 temp.z vertex uniform[0]
1040 * DP4 temp.w vertex uniform[0]
1042 * The hardware doesn't know that it can actually run the later instructions
1043 * while the previous ones are in flight, producing stalls. However, we have
1044 * manual fields we can set in the instructions that let it do so.
1047 vec4_visitor::opt_set_dependency_control()
1049 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
1050 uint8_t grf_channels_written
[BRW_MAX_GRF
];
1051 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
1052 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
1054 assert(prog_data
->total_grf
||
1055 !"Must be called after register allocation");
1057 foreach_block (block
, cfg
) {
1058 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1059 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1061 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
1062 /* If we read from a register that we were doing dependency control
1063 * on, don't do dependency control across the read.
1065 for (int i
= 0; i
< 3; i
++) {
1066 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ REG_SIZE
;
1067 if (inst
->src
[i
].file
== VGRF
) {
1068 last_grf_write
[reg
] = NULL
;
1069 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
1070 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1073 assert(inst
->src
[i
].file
!= MRF
);
1076 if (is_dep_ctrl_unsafe(inst
)) {
1077 memset(last_grf_write
, 0, sizeof(last_grf_write
));
1078 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
1082 /* Now, see if we can do dependency control for this instruction
1083 * against a previous one writing to its destination.
1085 int reg
= inst
->dst
.nr
+ inst
->dst
.offset
/ REG_SIZE
;
1086 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
1087 if (last_grf_write
[reg
] &&
1088 last_grf_write
[reg
]->dst
.offset
== inst
->dst
.offset
&&
1089 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
1090 last_grf_write
[reg
]->no_dd_clear
= true;
1091 inst
->no_dd_check
= true;
1093 grf_channels_written
[reg
] = 0;
1096 last_grf_write
[reg
] = inst
;
1097 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
1098 } else if (inst
->dst
.file
== MRF
) {
1099 if (last_mrf_write
[reg
] &&
1100 last_mrf_write
[reg
]->dst
.offset
== inst
->dst
.offset
&&
1101 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
1102 last_mrf_write
[reg
]->no_dd_clear
= true;
1103 inst
->no_dd_check
= true;
1105 mrf_channels_written
[reg
] = 0;
1108 last_mrf_write
[reg
] = inst
;
1109 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
1116 vec4_instruction::can_reswizzle(const struct gen_device_info
*devinfo
,
1121 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
1124 if (devinfo
->gen
== 6 && is_math() && swizzle
!= BRW_SWIZZLE_XYZW
)
1127 /* We can't swizzle implicit accumulator access. We'd have to
1128 * reswizzle the producer of the accumulator value in addition
1129 * to the consumer (i.e. both MUL and MACH). Just skip this.
1131 if (reads_accumulator_implicitly())
1134 if (!can_do_writemask(devinfo
) && dst_writemask
!= WRITEMASK_XYZW
)
1137 /* If this instruction sets anything not referenced by swizzle, then we'd
1138 * totally break it when we reswizzle.
1140 if (dst
.writemask
& ~swizzle_mask
)
1146 for (int i
= 0; i
< 3; i
++) {
1147 if (src
[i
].is_accumulator())
1155 * For any channels in the swizzle's source that were populated by this
1156 * instruction, rewrite the instruction to put the appropriate result directly
1157 * in those channels.
1159 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
1162 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
1164 /* Destination write mask doesn't correspond to source swizzle for the dot
1165 * product and pack_bytes instructions.
1167 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
1168 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
1169 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
1170 for (int i
= 0; i
< 3; i
++) {
1171 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
1174 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1178 /* Apply the specified swizzle and writemask to the original mask of
1179 * written components.
1181 dst
.writemask
= dst_writemask
&
1182 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1186 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1187 * just written and then MOVed into another reg and making the original write
1188 * of the GRF write directly to the final destination instead.
1191 vec4_visitor::opt_register_coalesce()
1193 bool progress
= false;
1196 calculate_live_intervals();
1198 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1202 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1203 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
1205 inst
->src
[0].file
!= VGRF
||
1206 inst
->dst
.type
!= inst
->src
[0].type
||
1207 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1210 /* Remove no-op MOVs */
1211 if (inst
->dst
.file
== inst
->src
[0].file
&&
1212 inst
->dst
.nr
== inst
->src
[0].nr
&&
1213 inst
->dst
.offset
== inst
->src
[0].offset
) {
1214 bool is_nop_mov
= true;
1216 for (unsigned c
= 0; c
< 4; c
++) {
1217 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1220 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1227 inst
->remove(block
);
1233 bool to_mrf
= (inst
->dst
.file
== MRF
);
1235 /* Can't coalesce this GRF if someone else was going to
1238 if (var_range_end(var_from_reg(alloc
, dst_reg(inst
->src
[0])), 8) > ip
)
1241 /* We need to check interference with the final destination between this
1242 * instruction and the earliest instruction involved in writing the GRF
1243 * we're eliminating. To do that, keep track of which of our source
1244 * channels we've seen initialized.
1246 const unsigned chans_needed
=
1247 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1248 inst
->dst
.writemask
);
1249 unsigned chans_remaining
= chans_needed
;
1251 /* Now walk up the instruction stream trying to see if we can rewrite
1252 * everything writing to the temporary to write into the destination
1255 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1256 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1258 _scan_inst
= scan_inst
;
1260 if (regions_overlap(inst
->src
[0], inst
->size_read(0),
1261 scan_inst
->dst
, scan_inst
->size_written
)) {
1262 /* Found something writing to the reg we want to coalesce away. */
1264 /* SEND instructions can't have MRF as a destination. */
1265 if (scan_inst
->mlen
)
1268 if (devinfo
->gen
== 6) {
1269 /* gen6 math instructions must have the destination be
1270 * VGRF, so no compute-to-MRF for them.
1272 if (scan_inst
->is_math()) {
1278 /* This doesn't handle saturation on the instruction we
1279 * want to coalesce away if the register types do not match.
1280 * But if scan_inst is a non type-converting 'mov', we can fix
1283 if (inst
->saturate
&&
1284 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1285 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1286 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1289 /* Only allow coalescing between registers of the same type size.
1290 * Otherwise we would need to make the pass aware of the fact that
1291 * channel sizes are different for single and double precision.
1293 if (type_sz(inst
->src
[0].type
) != type_sz(scan_inst
->src
[0].type
))
1296 /* Check that scan_inst writes the same amount of data as the
1297 * instruction, otherwise coalescing would lead to writing a
1298 * different (larger or smaller) region of the destination
1300 if (scan_inst
->size_written
!= inst
->size_written
)
1303 /* If we can't handle the swizzle, bail. */
1304 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1305 inst
->src
[0].swizzle
,
1310 /* This only handles coalescing writes of 8 channels (1 register
1311 * for single-precision and 2 registers for double-precision)
1312 * starting at the source offset of the copy instruction.
1314 if (DIV_ROUND_UP(scan_inst
->size_written
,
1315 type_sz(scan_inst
->dst
.type
)) > 8 ||
1316 scan_inst
->dst
.offset
!= inst
->src
[0].offset
)
1319 /* Mark which channels we found unconditional writes for. */
1320 if (!scan_inst
->predicate
)
1321 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1323 if (chans_remaining
== 0)
1327 /* You can't read from an MRF, so if someone else reads our MRF's
1328 * source GRF that we wanted to rewrite, that stops us. If it's a
1329 * GRF we're trying to coalesce to, we don't actually handle
1330 * rewriting sources so bail in that case as well.
1332 bool interfered
= false;
1333 for (int i
= 0; i
< 3; i
++) {
1334 if (regions_overlap(inst
->src
[0], inst
->size_read(0),
1335 scan_inst
->src
[i
], scan_inst
->size_read(i
)))
1341 /* If somebody else writes the same channels of our destination here,
1342 * we can't coalesce before that.
1344 if (regions_overlap(inst
->dst
, inst
->size_written
,
1345 scan_inst
->dst
, scan_inst
->size_written
) &&
1346 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1350 /* Check for reads of the register we're trying to coalesce into. We
1351 * can't go rewriting instructions above that to put some other value
1352 * in the register instead.
1354 if (to_mrf
&& scan_inst
->mlen
> 0) {
1355 if (inst
->dst
.nr
>= scan_inst
->base_mrf
&&
1356 inst
->dst
.nr
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1360 for (int i
= 0; i
< 3; i
++) {
1361 if (regions_overlap(inst
->dst
, inst
->size_written
,
1362 scan_inst
->src
[i
], scan_inst
->size_read(i
)))
1370 if (chans_remaining
== 0) {
1371 /* If we've made it here, we have an MOV we want to coalesce out, and
1372 * a scan_inst pointing to the earliest instruction involved in
1373 * computing the value. Now go rewrite the instruction stream
1376 vec4_instruction
*scan_inst
= _scan_inst
;
1377 while (scan_inst
!= inst
) {
1378 if (scan_inst
->dst
.file
== VGRF
&&
1379 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1380 scan_inst
->dst
.offset
== inst
->src
[0].offset
) {
1381 scan_inst
->reswizzle(inst
->dst
.writemask
,
1382 inst
->src
[0].swizzle
);
1383 scan_inst
->dst
.file
= inst
->dst
.file
;
1384 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1385 scan_inst
->dst
.offset
= inst
->dst
.offset
;
1386 if (inst
->saturate
&&
1387 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1388 /* If we have reached this point, scan_inst is a non
1389 * type-converting 'mov' and we can modify its register types
1390 * to match the ones in inst. Otherwise, we could have an
1391 * incorrect saturation result.
1393 scan_inst
->dst
.type
= inst
->dst
.type
;
1394 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1396 scan_inst
->saturate
|= inst
->saturate
;
1398 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1400 inst
->remove(block
);
1406 invalidate_live_intervals();
1412 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1413 * flow. We could probably do better here with some form of divergence
1417 vec4_visitor::eliminate_find_live_channel()
1419 bool progress
= false;
1422 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
1423 /* The optimization below assumes that channel zero is live on thread
1424 * dispatch, which may not be the case if the fixed function dispatches
1430 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1431 switch (inst
->opcode
) {
1437 case BRW_OPCODE_ENDIF
:
1438 case BRW_OPCODE_WHILE
:
1442 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1444 inst
->opcode
= BRW_OPCODE_MOV
;
1445 inst
->src
[0] = brw_imm_d(0);
1446 inst
->force_writemask_all
= true;
1460 * Splits virtual GRFs requesting more than one contiguous physical register.
1462 * We initially create large virtual GRFs for temporary structures, arrays,
1463 * and matrices, so that the visitor functions can add offsets to work their
1464 * way down to the actual member being accessed. But when it comes to
1465 * optimization, we'd like to treat each register as individual storage if
1468 * So far, the only thing that might prevent splitting is a send message from
1472 vec4_visitor::split_virtual_grfs()
1474 int num_vars
= this->alloc
.count
;
1475 int new_virtual_grf
[num_vars
];
1476 bool split_grf
[num_vars
];
1478 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1480 /* Try to split anything > 0 sized. */
1481 for (int i
= 0; i
< num_vars
; i
++) {
1482 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1485 /* Check that the instructions are compatible with the registers we're trying
1488 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1489 if (inst
->dst
.file
== VGRF
&& regs_written(inst
) > 1)
1490 split_grf
[inst
->dst
.nr
] = false;
1492 for (int i
= 0; i
< 3; i
++) {
1493 if (inst
->src
[i
].file
== VGRF
&& regs_read(inst
, i
) > 1)
1494 split_grf
[inst
->src
[i
].nr
] = false;
1498 /* Allocate new space for split regs. Note that the virtual
1499 * numbers will be contiguous.
1501 for (int i
= 0; i
< num_vars
; i
++) {
1505 new_virtual_grf
[i
] = alloc
.allocate(1);
1506 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1507 unsigned reg
= alloc
.allocate(1);
1508 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1511 this->alloc
.sizes
[i
] = 1;
1514 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1515 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1516 inst
->dst
.offset
/ REG_SIZE
!= 0) {
1517 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1518 inst
->dst
.offset
/ REG_SIZE
- 1);
1519 inst
->dst
.offset
%= REG_SIZE
;
1521 for (int i
= 0; i
< 3; i
++) {
1522 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1523 inst
->src
[i
].offset
/ REG_SIZE
!= 0) {
1524 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1525 inst
->src
[i
].offset
/ REG_SIZE
- 1);
1526 inst
->src
[i
].offset
%= REG_SIZE
;
1530 invalidate_live_intervals();
1534 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1536 dump_instruction(be_inst
, stderr
);
1540 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1542 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1544 if (inst
->predicate
) {
1545 fprintf(file
, "(%cf0.%d%s) ",
1546 inst
->predicate_inverse
? '-' : '+',
1548 pred_ctrl_align16
[inst
->predicate
]);
1551 fprintf(file
, "%s(%d)", brw_instruction_name(devinfo
, inst
->opcode
),
1554 fprintf(file
, ".sat");
1555 if (inst
->conditional_mod
) {
1556 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1557 if (!inst
->predicate
&&
1558 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1559 inst
->opcode
!= BRW_OPCODE_IF
&&
1560 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1561 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1566 switch (inst
->dst
.file
) {
1568 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
1571 fprintf(file
, "g%d", inst
->dst
.nr
);
1574 fprintf(file
, "m%d", inst
->dst
.nr
);
1577 switch (inst
->dst
.nr
) {
1579 fprintf(file
, "null");
1581 case BRW_ARF_ADDRESS
:
1582 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1584 case BRW_ARF_ACCUMULATOR
:
1585 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1588 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1591 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1596 fprintf(file
, "(null)");
1601 unreachable("not reached");
1603 if (inst
->dst
.offset
||
1604 (inst
->dst
.file
== VGRF
&&
1605 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
1606 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 16 : REG_SIZE
);
1607 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
1608 inst
->dst
.offset
% reg_size
);
1610 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1612 if (inst
->dst
.writemask
& 1)
1614 if (inst
->dst
.writemask
& 2)
1616 if (inst
->dst
.writemask
& 4)
1618 if (inst
->dst
.writemask
& 8)
1621 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->dst
.type
));
1623 if (inst
->src
[0].file
!= BAD_FILE
)
1624 fprintf(file
, ", ");
1626 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1627 if (inst
->src
[i
].negate
)
1629 if (inst
->src
[i
].abs
)
1631 switch (inst
->src
[i
].file
) {
1633 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1636 fprintf(file
, "g%d.%d", inst
->src
[i
].nr
, inst
->src
[i
].subnr
);
1639 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1642 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1645 switch (inst
->src
[i
].type
) {
1646 case BRW_REGISTER_TYPE_F
:
1647 fprintf(file
, "%fF", inst
->src
[i
].f
);
1649 case BRW_REGISTER_TYPE_DF
:
1650 fprintf(file
, "%fDF", inst
->src
[i
].df
);
1652 case BRW_REGISTER_TYPE_D
:
1653 fprintf(file
, "%dD", inst
->src
[i
].d
);
1655 case BRW_REGISTER_TYPE_UD
:
1656 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1658 case BRW_REGISTER_TYPE_VF
:
1659 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1660 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1661 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1662 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1663 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1666 fprintf(file
, "???");
1671 switch (inst
->src
[i
].nr
) {
1673 fprintf(file
, "null");
1675 case BRW_ARF_ADDRESS
:
1676 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1678 case BRW_ARF_ACCUMULATOR
:
1679 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1682 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1685 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1690 fprintf(file
, "(null)");
1693 unreachable("not reached");
1696 if (inst
->src
[i
].offset
||
1697 (inst
->src
[i
].file
== VGRF
&&
1698 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
1699 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 16 : REG_SIZE
);
1700 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
1701 inst
->src
[i
].offset
% reg_size
);
1704 if (inst
->src
[i
].file
!= IMM
) {
1705 static const char *chans
[4] = {"x", "y", "z", "w"};
1707 for (int c
= 0; c
< 4; c
++) {
1708 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1712 if (inst
->src
[i
].abs
)
1715 if (inst
->src
[i
].file
!= IMM
) {
1716 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
1719 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1720 fprintf(file
, ", ");
1723 if (inst
->force_writemask_all
)
1724 fprintf(file
, " NoMask");
1726 if (inst
->exec_size
!= 8)
1727 fprintf(file
, " group%d", inst
->group
);
1729 fprintf(file
, "\n");
1734 vec4_vs_visitor::setup_attributes(int payload_reg
)
1736 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1737 for (int i
= 0; i
< 3; i
++) {
1738 if (inst
->src
[i
].file
== ATTR
) {
1739 assert(inst
->src
[i
].offset
% REG_SIZE
== 0);
1740 int grf
= payload_reg
+ inst
->src
[i
].nr
+
1741 inst
->src
[i
].offset
/ REG_SIZE
;
1743 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1744 reg
.swizzle
= inst
->src
[i
].swizzle
;
1745 reg
.type
= inst
->src
[i
].type
;
1746 reg
.abs
= inst
->src
[i
].abs
;
1747 reg
.negate
= inst
->src
[i
].negate
;
1753 return payload_reg
+ vs_prog_data
->nr_attribute_slots
;
1757 vec4_visitor::setup_uniforms(int reg
)
1759 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1761 /* The pre-gen6 VS requires that some push constants get loaded no
1762 * matter what, or the GPU would hang.
1764 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1765 brw_stage_prog_data_add_params(stage_prog_data
, 4);
1766 for (unsigned int i
= 0; i
< 4; i
++) {
1767 unsigned int slot
= this->uniforms
* 4 + i
;
1768 stage_prog_data
->param
[slot
] = BRW_PARAM_BUILTIN_ZERO
;
1774 reg
+= ALIGN(uniforms
, 2) / 2;
1777 for (int i
= 0; i
< 4; i
++)
1778 reg
+= stage_prog_data
->ubo_ranges
[i
].length
;
1780 stage_prog_data
->nr_params
= this->uniforms
* 4;
1782 prog_data
->base
.curb_read_length
=
1783 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1789 vec4_vs_visitor::setup_payload(void)
1793 /* The payload always contains important data in g0, which contains
1794 * the URB handles that are passed on to the URB write at the end
1795 * of the thread. So, we always start push constants at g1.
1799 reg
= setup_uniforms(reg
);
1801 reg
= setup_attributes(reg
);
1803 this->first_non_payload_grf
= reg
;
1807 vec4_visitor::lower_minmax()
1809 assert(devinfo
->gen
< 6);
1811 bool progress
= false;
1813 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1814 const vec4_builder
ibld(this, block
, inst
);
1816 if (inst
->opcode
== BRW_OPCODE_SEL
&&
1817 inst
->predicate
== BRW_PREDICATE_NONE
) {
1818 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
1819 * the original SEL.L/GE instruction
1821 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
1822 inst
->conditional_mod
);
1823 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1824 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
1831 invalidate_live_intervals();
1837 vec4_visitor::get_timestamp()
1839 assert(devinfo
->gen
>= 7);
1841 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1846 BRW_REGISTER_TYPE_UD
,
1847 BRW_VERTICAL_STRIDE_0
,
1849 BRW_HORIZONTAL_STRIDE_4
,
1853 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1855 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1856 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1857 * even if it's not enabled in the dispatch.
1859 mov
->force_writemask_all
= true;
1861 return src_reg(dst
);
1865 vec4_visitor::emit_shader_time_begin()
1867 current_annotation
= "shader time start";
1868 shader_start_time
= get_timestamp();
1872 vec4_visitor::emit_shader_time_end()
1874 current_annotation
= "shader time end";
1875 src_reg shader_end_time
= get_timestamp();
1878 /* Check that there weren't any timestamp reset events (assuming these
1879 * were the only two timestamp reads that happened).
1881 src_reg reset_end
= shader_end_time
;
1882 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1883 vec4_instruction
*test
= emit(AND(dst_null_ud(), reset_end
, brw_imm_ud(1u)));
1884 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1886 emit(IF(BRW_PREDICATE_NORMAL
));
1888 /* Take the current timestamp and get the delta. */
1889 shader_start_time
.negate
= true;
1890 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1891 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1893 /* If there were no instructions between the two timestamp gets, the diff
1894 * is 2 cycles. Remove that overhead, so I can forget about that when
1895 * trying to determine the time taken for single instructions.
1897 emit(ADD(diff
, src_reg(diff
), brw_imm_ud(-2u)));
1899 emit_shader_time_write(0, src_reg(diff
));
1900 emit_shader_time_write(1, brw_imm_ud(1u));
1901 emit(BRW_OPCODE_ELSE
);
1902 emit_shader_time_write(2, brw_imm_ud(1u));
1903 emit(BRW_OPCODE_ENDIF
);
1907 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1910 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1912 dst_reg offset
= dst
;
1914 time
.offset
+= REG_SIZE
;
1916 offset
.type
= BRW_REGISTER_TYPE_UD
;
1917 int index
= shader_time_index
* 3 + shader_time_subindex
;
1918 emit(MOV(offset
, brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
)));
1920 time
.type
= BRW_REGISTER_TYPE_UD
;
1921 emit(MOV(time
, value
));
1923 vec4_instruction
*inst
=
1924 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1929 is_align1_df(vec4_instruction
*inst
)
1931 switch (inst
->opcode
) {
1932 case VEC4_OPCODE_DOUBLE_TO_F32
:
1933 case VEC4_OPCODE_DOUBLE_TO_D32
:
1934 case VEC4_OPCODE_DOUBLE_TO_U32
:
1935 case VEC4_OPCODE_TO_DOUBLE
:
1936 case VEC4_OPCODE_PICK_LOW_32BIT
:
1937 case VEC4_OPCODE_PICK_HIGH_32BIT
:
1938 case VEC4_OPCODE_SET_LOW_32BIT
:
1939 case VEC4_OPCODE_SET_HIGH_32BIT
:
1947 vec4_visitor::convert_to_hw_regs()
1949 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1950 for (int i
= 0; i
< 3; i
++) {
1951 class src_reg
&src
= inst
->src
[i
];
1955 reg
= byte_offset(brw_vecn_grf(4, src
.nr
, 0), src
.offset
);
1956 reg
.type
= src
.type
;
1958 reg
.negate
= src
.negate
;
1963 reg
= stride(byte_offset(brw_vec4_grf(
1964 prog_data
->base
.dispatch_grf_start_reg
+
1965 src
.nr
/ 2, src
.nr
% 2 * 4),
1968 reg
.type
= src
.type
;
1970 reg
.negate
= src
.negate
;
1972 /* This should have been moved to pull constants. */
1973 assert(!src
.reladdr
);
1978 if (type_sz(src
.type
) == 8) {
1979 reg
= src
.as_brw_reg();
1988 /* Probably unused. */
1989 reg
= brw_null_reg();
1990 reg
= retype(reg
, src
.type
);
1995 unreachable("not reached");
1998 apply_logical_swizzle(®
, inst
, i
);
2001 /* From IVB PRM, vol4, part3, "General Restrictions on Regioning
2004 * "If ExecSize = Width and HorzStride ≠ 0, VertStride must be set
2005 * to Width * HorzStride."
2007 * We can break this rule with DF sources on DF align1
2008 * instructions, because the exec_size would be 4 and width is 4.
2009 * As we know we are not accessing to next GRF, it is safe to
2010 * set vstride to the formula given by the rule itself.
2012 if (is_align1_df(inst
) && (cvt(inst
->exec_size
) - 1) == src
.width
)
2013 src
.vstride
= src
.width
+ src
.hstride
;
2016 if (inst
->is_3src(devinfo
)) {
2017 /* 3-src instructions with scalar sources support arbitrary subnr,
2018 * but don't actually use swizzles. Convert swizzle into subnr.
2019 * Skip this for double-precision instructions: RepCtrl=1 is not
2020 * allowed for them and needs special handling.
2022 for (int i
= 0; i
< 3; i
++) {
2023 if (inst
->src
[i
].vstride
== BRW_VERTICAL_STRIDE_0
&&
2024 type_sz(inst
->src
[i
].type
) < 8) {
2025 assert(brw_is_single_value_swizzle(inst
->src
[i
].swizzle
));
2026 inst
->src
[i
].subnr
+= 4 * BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0);
2031 dst_reg
&dst
= inst
->dst
;
2034 switch (inst
->dst
.file
) {
2036 reg
= byte_offset(brw_vec8_grf(dst
.nr
, 0), dst
.offset
);
2037 reg
.type
= dst
.type
;
2038 reg
.writemask
= dst
.writemask
;
2042 reg
= byte_offset(brw_message_reg(dst
.nr
), dst
.offset
);
2043 assert((reg
.nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
2044 reg
.type
= dst
.type
;
2045 reg
.writemask
= dst
.writemask
;
2050 reg
= dst
.as_brw_reg();
2054 reg
= brw_null_reg();
2055 reg
= retype(reg
, dst
.type
);
2061 unreachable("not reached");
2069 stage_uses_interleaved_attributes(unsigned stage
,
2070 enum shader_dispatch_mode dispatch_mode
)
2073 case MESA_SHADER_TESS_EVAL
:
2075 case MESA_SHADER_GEOMETRY
:
2076 return dispatch_mode
!= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2083 * Get the closest native SIMD width supported by the hardware for instruction
2084 * \p inst. The instruction will be left untouched by
2085 * vec4_visitor::lower_simd_width() if the returned value matches the
2086 * instruction's original execution size.
2089 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
2090 enum shader_dispatch_mode dispatch_mode
,
2091 unsigned stage
, const vec4_instruction
*inst
)
2093 /* Do not split some instructions that require special handling */
2094 switch (inst
->opcode
) {
2095 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2096 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2097 return inst
->exec_size
;
2102 unsigned lowered_width
= MIN2(16, inst
->exec_size
);
2104 /* We need to split some cases of double-precision instructions that write
2105 * 2 registers. We only need to care about this in gen7 because that is the
2106 * only hardware that implements fp64 in Align16.
2108 if (devinfo
->gen
== 7 && inst
->size_written
> REG_SIZE
) {
2109 /* Align16 8-wide double-precision SEL does not work well. Verified
2112 if (inst
->opcode
== BRW_OPCODE_SEL
&& type_sz(inst
->dst
.type
) == 8)
2113 lowered_width
= MIN2(lowered_width
, 4);
2115 /* HSW PRM, 3D Media GPGPU Engine, Region Alignment Rules for Direct
2116 * Register Addressing:
2118 * "When destination spans two registers, the source MUST span two
2121 for (unsigned i
= 0; i
< 3; i
++) {
2122 if (inst
->src
[i
].file
== BAD_FILE
)
2124 if (inst
->size_read(i
) <= REG_SIZE
)
2125 lowered_width
= MIN2(lowered_width
, 4);
2127 /* Interleaved attribute setups use a vertical stride of 0, which
2128 * makes them hit the associated instruction decompression bug in gen7.
2129 * Split them to prevent this.
2131 if (inst
->src
[i
].file
== ATTR
&&
2132 stage_uses_interleaved_attributes(stage
, dispatch_mode
))
2133 lowered_width
= MIN2(lowered_width
, 4);
2137 /* IvyBridge can manage a maximum of 4 DFs per SIMD4x2 instruction, since
2138 * it doesn't support compression in Align16 mode, no matter if it has
2139 * force_writemask_all enabled or disabled (the latter is affected by the
2140 * compressed instruction bug in gen7, which is another reason to enforce
2143 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
2144 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8))
2145 lowered_width
= MIN2(lowered_width
, 4);
2147 return lowered_width
;
2151 dst_src_regions_overlap(vec4_instruction
*inst
)
2153 if (inst
->size_written
== 0)
2156 unsigned dst_start
= inst
->dst
.offset
;
2157 unsigned dst_end
= dst_start
+ inst
->size_written
- 1;
2158 for (int i
= 0; i
< 3; i
++) {
2159 if (inst
->src
[i
].file
== BAD_FILE
)
2162 if (inst
->dst
.file
!= inst
->src
[i
].file
||
2163 inst
->dst
.nr
!= inst
->src
[i
].nr
)
2166 unsigned src_start
= inst
->src
[i
].offset
;
2167 unsigned src_end
= src_start
+ inst
->size_read(i
) - 1;
2169 if ((dst_start
>= src_start
&& dst_start
<= src_end
) ||
2170 (dst_end
>= src_start
&& dst_end
<= src_end
) ||
2171 (dst_start
<= src_start
&& dst_end
>= src_end
)) {
2180 vec4_visitor::lower_simd_width()
2182 bool progress
= false;
2184 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2185 const unsigned lowered_width
=
2186 get_lowered_simd_width(devinfo
, prog_data
->dispatch_mode
, stage
, inst
);
2187 assert(lowered_width
<= inst
->exec_size
);
2188 if (lowered_width
== inst
->exec_size
)
2191 /* We need to deal with source / destination overlaps when splitting.
2192 * The hardware supports reading from and writing to the same register
2193 * in the same instruction, but we need to be careful that each split
2194 * instruction we produce does not corrupt the source of the next.
2196 * The easiest way to handle this is to make the split instructions write
2197 * to temporaries if there is an src/dst overlap and then move from the
2198 * temporaries to the original destination. We also need to consider
2199 * instructions that do partial writes via align1 opcodes, in which case
2200 * we need to make sure that the we initialize the temporary with the
2201 * value of the instruction's dst.
2203 bool needs_temp
= dst_src_regions_overlap(inst
);
2204 for (unsigned n
= 0; n
< inst
->exec_size
/ lowered_width
; n
++) {
2205 unsigned channel_offset
= lowered_width
* n
;
2207 unsigned size_written
= lowered_width
* type_sz(inst
->dst
.type
);
2209 /* Create the split instruction from the original so that we copy all
2210 * relevant instruction fields, then set the width and calculate the
2211 * new dst/src regions.
2213 vec4_instruction
*linst
= new(mem_ctx
) vec4_instruction(*inst
);
2214 linst
->exec_size
= lowered_width
;
2215 linst
->group
= channel_offset
;
2216 linst
->size_written
= size_written
;
2218 /* Compute split dst region */
2221 unsigned num_regs
= DIV_ROUND_UP(size_written
, REG_SIZE
);
2222 dst
= retype(dst_reg(VGRF
, alloc
.allocate(num_regs
)),
2224 if (inst
->is_align1_partial_write()) {
2225 vec4_instruction
*copy
= MOV(dst
, src_reg(inst
->dst
));
2226 copy
->exec_size
= lowered_width
;
2227 copy
->group
= channel_offset
;
2228 copy
->size_written
= size_written
;
2229 inst
->insert_before(block
, copy
);
2232 dst
= horiz_offset(inst
->dst
, channel_offset
);
2236 /* Compute split source regions */
2237 for (int i
= 0; i
< 3; i
++) {
2238 if (linst
->src
[i
].file
== BAD_FILE
)
2241 if (!is_uniform(linst
->src
[i
]))
2242 linst
->src
[i
] = horiz_offset(linst
->src
[i
], channel_offset
);
2245 inst
->insert_before(block
, linst
);
2247 /* If we used a temporary to store the result of the split
2248 * instruction, copy the result to the original destination
2251 vec4_instruction
*mov
=
2252 MOV(offset(inst
->dst
, lowered_width
, n
), src_reg(dst
));
2253 mov
->exec_size
= lowered_width
;
2254 mov
->group
= channel_offset
;
2255 mov
->size_written
= size_written
;
2256 mov
->predicate
= inst
->predicate
;
2257 inst
->insert_before(block
, mov
);
2261 inst
->remove(block
);
2266 invalidate_live_intervals();
2271 static brw_predicate
2272 scalarize_predicate(brw_predicate predicate
, unsigned writemask
)
2274 if (predicate
!= BRW_PREDICATE_NORMAL
)
2277 switch (writemask
) {
2279 return BRW_PREDICATE_ALIGN16_REPLICATE_X
;
2281 return BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
2283 return BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
2285 return BRW_PREDICATE_ALIGN16_REPLICATE_W
;
2287 unreachable("invalid writemask");
2291 /* Gen7 has a hardware decompression bug that we can exploit to represent
2292 * handful of additional swizzles natively.
2295 is_gen7_supported_64bit_swizzle(vec4_instruction
*inst
, unsigned arg
)
2297 switch (inst
->src
[arg
].swizzle
) {
2298 case BRW_SWIZZLE_XXXX
:
2299 case BRW_SWIZZLE_YYYY
:
2300 case BRW_SWIZZLE_ZZZZ
:
2301 case BRW_SWIZZLE_WWWW
:
2302 case BRW_SWIZZLE_XYXY
:
2303 case BRW_SWIZZLE_YXYX
:
2304 case BRW_SWIZZLE_ZWZW
:
2305 case BRW_SWIZZLE_WZWZ
:
2312 /* 64-bit sources use regions with a width of 2. These 2 elements in each row
2313 * can be addressed using 32-bit swizzles (which is what the hardware supports)
2314 * but it also means that the swizzle we apply on the first two components of a
2315 * dvec4 is coupled with the swizzle we use for the last 2. In other words,
2316 * only some specific swizzle combinations can be natively supported.
2318 * FIXME: we can go an step further and implement even more swizzle
2319 * variations using only partial scalarization.
2321 * For more details see:
2322 * https://bugs.freedesktop.org/show_bug.cgi?id=92760#c82
2325 vec4_visitor::is_supported_64bit_region(vec4_instruction
*inst
, unsigned arg
)
2327 const src_reg
&src
= inst
->src
[arg
];
2328 assert(type_sz(src
.type
) == 8);
2330 /* Uniform regions have a vstride=0. Because we use 2-wide rows with
2331 * 64-bit regions it means that we cannot access components Z/W, so
2332 * return false for any such case. Interleaved attributes will also be
2333 * mapped to GRF registers with a vstride of 0, so apply the same
2336 if ((is_uniform(src
) ||
2337 (stage_uses_interleaved_attributes(stage
, prog_data
->dispatch_mode
) &&
2338 src
.file
== ATTR
)) &&
2339 (brw_mask_for_swizzle(src
.swizzle
) & 12))
2342 switch (src
.swizzle
) {
2343 case BRW_SWIZZLE_XYZW
:
2344 case BRW_SWIZZLE_XXZZ
:
2345 case BRW_SWIZZLE_YYWW
:
2346 case BRW_SWIZZLE_YXWZ
:
2349 return devinfo
->gen
== 7 && is_gen7_supported_64bit_swizzle(inst
, arg
);
2354 vec4_visitor::scalarize_df()
2356 bool progress
= false;
2358 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2359 /* Skip DF instructions that operate in Align1 mode */
2360 if (is_align1_df(inst
))
2363 /* Check if this is a double-precision instruction */
2364 bool is_double
= type_sz(inst
->dst
.type
) == 8;
2365 for (int arg
= 0; !is_double
&& arg
< 3; arg
++) {
2366 is_double
= inst
->src
[arg
].file
!= BAD_FILE
&&
2367 type_sz(inst
->src
[arg
].type
) == 8;
2373 /* Skip the lowering for specific regioning scenarios that we can
2376 bool skip_lowering
= true;
2378 /* XY and ZW writemasks operate in 32-bit, which means that they don't
2379 * have a native 64-bit representation and they should always be split.
2381 if (inst
->dst
.writemask
== WRITEMASK_XY
||
2382 inst
->dst
.writemask
== WRITEMASK_ZW
) {
2383 skip_lowering
= false;
2385 for (unsigned i
= 0; i
< 3; i
++) {
2386 if (inst
->src
[i
].file
== BAD_FILE
|| type_sz(inst
->src
[i
].type
) < 8)
2388 skip_lowering
= skip_lowering
&& is_supported_64bit_region(inst
, i
);
2395 /* Generate scalar instructions for each enabled channel */
2396 for (unsigned chan
= 0; chan
< 4; chan
++) {
2397 unsigned chan_mask
= 1 << chan
;
2398 if (!(inst
->dst
.writemask
& chan_mask
))
2401 vec4_instruction
*scalar_inst
= new(mem_ctx
) vec4_instruction(*inst
);
2403 for (unsigned i
= 0; i
< 3; i
++) {
2404 unsigned swz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, chan
);
2405 scalar_inst
->src
[i
].swizzle
= BRW_SWIZZLE4(swz
, swz
, swz
, swz
);
2408 scalar_inst
->dst
.writemask
= chan_mask
;
2410 if (inst
->predicate
!= BRW_PREDICATE_NONE
) {
2411 scalar_inst
->predicate
=
2412 scalarize_predicate(inst
->predicate
, chan_mask
);
2415 inst
->insert_before(block
, scalar_inst
);
2418 inst
->remove(block
);
2423 invalidate_live_intervals();
2429 vec4_visitor::lower_64bit_mad_to_mul_add()
2431 bool progress
= false;
2433 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
2434 if (inst
->opcode
!= BRW_OPCODE_MAD
)
2437 if (type_sz(inst
->dst
.type
) != 8)
2440 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
2442 /* Use the copy constructor so we copy all relevant instruction fields
2443 * from the original mad into the add and mul instructions
2445 vec4_instruction
*mul
= new(mem_ctx
) vec4_instruction(*inst
);
2446 mul
->opcode
= BRW_OPCODE_MUL
;
2448 mul
->src
[0] = inst
->src
[1];
2449 mul
->src
[1] = inst
->src
[2];
2450 mul
->src
[2].file
= BAD_FILE
;
2452 vec4_instruction
*add
= new(mem_ctx
) vec4_instruction(*inst
);
2453 add
->opcode
= BRW_OPCODE_ADD
;
2454 add
->src
[0] = src_reg(mul_dst
);
2455 add
->src
[1] = inst
->src
[0];
2456 add
->src
[2].file
= BAD_FILE
;
2458 inst
->insert_before(block
, mul
);
2459 inst
->insert_before(block
, add
);
2460 inst
->remove(block
);
2466 invalidate_live_intervals();
2471 /* The align16 hardware can only do 32-bit swizzle channels, so we need to
2472 * translate the logical 64-bit swizzle channels that we use in the Vec4 IR
2473 * to 32-bit swizzle channels in hardware registers.
2475 * @inst and @arg identify the original vec4 IR source operand we need to
2476 * translate the swizzle for and @hw_reg is the hardware register where we
2477 * will write the hardware swizzle to use.
2479 * This pass assumes that Align16/DF instructions have been fully scalarized
2480 * previously so there is just one 64-bit swizzle channel to deal with for any
2481 * given Vec4 IR source.
2484 vec4_visitor::apply_logical_swizzle(struct brw_reg
*hw_reg
,
2485 vec4_instruction
*inst
, int arg
)
2487 src_reg reg
= inst
->src
[arg
];
2489 if (reg
.file
== BAD_FILE
|| reg
.file
== BRW_IMMEDIATE_VALUE
)
2492 /* If this is not a 64-bit operand or this is a scalar instruction we don't
2493 * need to do anything about the swizzles.
2495 if(type_sz(reg
.type
) < 8 || is_align1_df(inst
)) {
2496 hw_reg
->swizzle
= reg
.swizzle
;
2500 /* Take the 64-bit logical swizzle channel and translate it to 32-bit */
2501 assert(brw_is_single_value_swizzle(reg
.swizzle
) ||
2502 is_supported_64bit_region(inst
, arg
));
2504 /* Apply the region <2, 2, 1> for GRF or <0, 2, 1> for uniforms, as align16
2505 * HW can only do 32-bit swizzle channels.
2507 hw_reg
->width
= BRW_WIDTH_2
;
2509 if (is_supported_64bit_region(inst
, arg
) &&
2510 !is_gen7_supported_64bit_swizzle(inst
, arg
)) {
2511 /* Supported 64-bit swizzles are those such that their first two
2512 * components, when expanded to 32-bit swizzles, match the semantics
2513 * of the original 64-bit swizzle with 2-wide row regioning.
2515 unsigned swizzle0
= BRW_GET_SWZ(reg
.swizzle
, 0);
2516 unsigned swizzle1
= BRW_GET_SWZ(reg
.swizzle
, 1);
2517 hw_reg
->swizzle
= BRW_SWIZZLE4(swizzle0
* 2, swizzle0
* 2 + 1,
2518 swizzle1
* 2, swizzle1
* 2 + 1);
2520 /* If we got here then we have one of the following:
2522 * 1. An unsupported swizzle, which should be single-value thanks to the
2523 * scalarization pass.
2525 * 2. A gen7 supported swizzle. These can be single-value or double-value
2526 * swizzles. If the latter, they are never cross-dvec2 channels. For
2527 * these we always need to activate the gen7 vstride=0 exploit.
2529 unsigned swizzle0
= BRW_GET_SWZ(reg
.swizzle
, 0);
2530 unsigned swizzle1
= BRW_GET_SWZ(reg
.swizzle
, 1);
2531 assert((swizzle0
< 2) == (swizzle1
< 2));
2533 /* To gain access to Z/W components we need to select the second half
2534 * of the register and then use a X/Y swizzle to select Z/W respectively.
2536 if (swizzle0
>= 2) {
2537 *hw_reg
= suboffset(*hw_reg
, 2);
2542 /* All gen7-specific supported swizzles require the vstride=0 exploit */
2543 if (devinfo
->gen
== 7 && is_gen7_supported_64bit_swizzle(inst
, arg
))
2544 hw_reg
->vstride
= BRW_VERTICAL_STRIDE_0
;
2546 /* Any 64-bit source with an offset at 16B is intended to address the
2547 * second half of a register and needs a vertical stride of 0 so we:
2549 * 1. Don't violate register region restrictions.
2550 * 2. Activate the gen7 instruction decompresion bug exploit when
2553 if (hw_reg
->subnr
% REG_SIZE
== 16) {
2554 assert(devinfo
->gen
== 7);
2555 hw_reg
->vstride
= BRW_VERTICAL_STRIDE_0
;
2558 hw_reg
->swizzle
= BRW_SWIZZLE4(swizzle0
* 2, swizzle0
* 2 + 1,
2559 swizzle1
* 2, swizzle1
* 2 + 1);
2566 if (shader_time_index
>= 0)
2567 emit_shader_time_begin();
2580 /* Before any optimization, push array accesses out to scratch
2581 * space where we need them to be. This pass may allocate new
2582 * virtual GRFs, so we want to do it early. It also makes sure
2583 * that we have reladdr computations available for CSE, since we'll
2584 * often do repeated subexpressions for those.
2586 move_grf_array_access_to_scratch();
2587 move_uniform_array_access_to_pull_constants();
2589 pack_uniform_registers();
2590 move_push_constants_to_pull_constants();
2591 split_virtual_grfs();
2593 #define OPT(pass, args...) ({ \
2595 bool this_progress = pass(args); \
2597 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
2598 char filename[64]; \
2599 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
2600 stage_abbrev, nir->info.name, iteration, pass_num); \
2602 backend_shader::dump_instructions(filename); \
2605 progress = progress || this_progress; \
2610 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
2612 snprintf(filename
, 64, "%s-%s-00-00-start",
2613 stage_abbrev
, nir
->info
.name
);
2615 backend_shader::dump_instructions(filename
);
2626 OPT(opt_predicated_break
, this);
2627 OPT(opt_reduce_swizzle
);
2628 OPT(dead_code_eliminate
);
2629 OPT(dead_control_flow_eliminate
, this);
2630 OPT(opt_copy_propagation
);
2631 OPT(opt_cmod_propagation
);
2634 OPT(opt_register_coalesce
);
2635 OPT(eliminate_find_live_channel
);
2640 if (OPT(opt_vector_float
)) {
2642 OPT(opt_copy_propagation
, false);
2643 OPT(opt_copy_propagation
, true);
2644 OPT(dead_code_eliminate
);
2647 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
2648 OPT(opt_cmod_propagation
);
2650 OPT(opt_copy_propagation
);
2651 OPT(dead_code_eliminate
);
2654 if (OPT(lower_simd_width
)) {
2655 OPT(opt_copy_propagation
);
2656 OPT(dead_code_eliminate
);
2662 OPT(lower_64bit_mad_to_mul_add
);
2664 /* Run this before payload setup because tesselation shaders
2665 * rely on it to prevent cross dvec2 regioning on DF attributes
2666 * that are setup so that XY are on the second half of register and
2667 * ZW are in the first half of the next.
2673 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
2674 /* Debug of register spilling: Go spill everything. */
2675 const int grf_count
= alloc
.count
;
2676 float spill_costs
[alloc
.count
];
2677 bool no_spill
[alloc
.count
];
2678 evaluate_spill_costs(spill_costs
, no_spill
);
2679 for (int i
= 0; i
< grf_count
; i
++) {
2685 /* We want to run this after spilling because 64-bit (un)spills need to
2686 * emit code to shuffle 64-bit data for the 32-bit scratch read/write
2687 * messages that can produce unsupported 64-bit swizzle regions.
2692 bool allocated_without_spills
= reg_allocate();
2694 if (!allocated_without_spills
) {
2695 compiler
->shader_perf_log(log_data
,
2696 "%s shader triggered register spilling. "
2697 "Try reducing the number of live vec4 values "
2698 "to improve performance.\n",
2701 while (!reg_allocate()) {
2706 /* We want to run this after spilling because 64-bit (un)spills need to
2707 * emit code to shuffle 64-bit data for the 32-bit scratch read/write
2708 * messages that can produce unsupported 64-bit swizzle regions.
2713 opt_schedule_instructions();
2715 opt_set_dependency_control();
2717 convert_to_hw_regs();
2719 if (last_scratch
> 0) {
2720 prog_data
->base
.total_scratch
=
2721 brw_get_scratch_size(last_scratch
* REG_SIZE
);
2727 } /* namespace brw */
2732 * Compile a vertex shader.
2734 * Returns the final assembly and the program's size.
2737 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
2739 const struct brw_vs_prog_key
*key
,
2740 struct brw_vs_prog_data
*prog_data
,
2741 const nir_shader
*src_shader
,
2742 bool use_legacy_snorm_formula
,
2743 int shader_time_index
,
2746 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_VERTEX
];
2747 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
2748 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, is_scalar
);
2750 const unsigned *assembly
= NULL
;
2752 if (prog_data
->base
.vue_map
.varying_to_slot
[VARYING_SLOT_EDGE
] != -1) {
2753 /* If the output VUE map contains VARYING_SLOT_EDGE then we need to copy
2754 * the edge flag from VERT_ATTRIB_EDGEFLAG. This will be done
2755 * automatically by brw_vec4_visitor::emit_urb_slot but we need to
2756 * ensure that prog_data->inputs_read is accurate.
2758 * In order to make late NIR passes aware of the change, we actually
2759 * whack shader->info.inputs_read instead. This is safe because we just
2760 * made a copy of the shader.
2763 assert(key
->copy_edgeflag
);
2764 shader
->info
.inputs_read
|= VERT_BIT_EDGEFLAG
;
2767 prog_data
->inputs_read
= shader
->info
.inputs_read
;
2768 prog_data
->double_inputs_read
= shader
->info
.double_inputs_read
;
2770 brw_nir_lower_vs_inputs(shader
, use_legacy_snorm_formula
,
2771 key
->gl_attrib_wa_flags
);
2772 brw_nir_lower_vue_outputs(shader
, is_scalar
);
2773 shader
= brw_postprocess_nir(shader
, compiler
, is_scalar
);
2775 prog_data
->base
.clip_distance_mask
=
2776 ((1 << shader
->info
.clip_distance_array_size
) - 1);
2777 prog_data
->base
.cull_distance_mask
=
2778 ((1 << shader
->info
.cull_distance_array_size
) - 1) <<
2779 shader
->info
.clip_distance_array_size
;
2781 unsigned nr_attribute_slots
= _mesa_bitcount_64(prog_data
->inputs_read
);
2783 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
2784 * incoming vertex attribute. So, add an extra slot.
2786 if (shader
->info
.system_values_read
&
2787 (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
) |
2788 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
2789 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
2790 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
2791 nr_attribute_slots
++;
2794 if (shader
->info
.system_values_read
&
2795 BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
))
2796 prog_data
->uses_basevertex
= true;
2798 if (shader
->info
.system_values_read
&
2799 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
))
2800 prog_data
->uses_baseinstance
= true;
2802 if (shader
->info
.system_values_read
&
2803 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
))
2804 prog_data
->uses_vertexid
= true;
2806 if (shader
->info
.system_values_read
&
2807 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))
2808 prog_data
->uses_instanceid
= true;
2810 /* gl_DrawID has its very own vec4 */
2811 if (shader
->info
.system_values_read
&
2812 BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
)) {
2813 prog_data
->uses_drawid
= true;
2814 nr_attribute_slots
++;
2817 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
2818 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
2819 * vec4 mode, the hardware appears to wedge unless we read something.
2822 prog_data
->base
.urb_read_length
=
2823 DIV_ROUND_UP(nr_attribute_slots
, 2);
2825 prog_data
->base
.urb_read_length
=
2826 DIV_ROUND_UP(MAX2(nr_attribute_slots
, 1), 2);
2828 prog_data
->nr_attribute_slots
= nr_attribute_slots
;
2830 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
2831 * (overwriting the original contents), we need to make sure the size is
2832 * the larger of the two.
2834 const unsigned vue_entries
=
2835 MAX2(nr_attribute_slots
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
2837 if (compiler
->devinfo
->gen
== 6) {
2838 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2840 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2841 /* On Cannonlake software shall not program an allocation size that
2842 * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
2844 if (compiler
->devinfo
->gen
== 10 &&
2845 prog_data
->base
.urb_entry_size
% 3 == 0)
2846 prog_data
->base
.urb_entry_size
++;
2849 if (INTEL_DEBUG
& DEBUG_VS
) {
2850 fprintf(stderr
, "VS Output ");
2851 brw_print_vue_map(stderr
, &prog_data
->base
.vue_map
);
2855 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2857 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2858 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2859 shader
, 8, shader_time_index
);
2862 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2867 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
2869 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
2870 &prog_data
->base
.base
, v
.promoted_constants
,
2871 v
.runtime_check_aads_emit
, MESA_SHADER_VERTEX
);
2872 if (INTEL_DEBUG
& DEBUG_VS
) {
2873 const char *debug_name
=
2874 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2875 shader
->info
.label
? shader
->info
.label
:
2879 g
.enable_debug(debug_name
);
2881 g
.generate_code(v
.cfg
, 8);
2882 assembly
= g
.get_assembly(&prog_data
->base
.base
.program_size
);
2886 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2888 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2890 shader_time_index
, use_legacy_snorm_formula
);
2893 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2898 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2899 shader
, &prog_data
->base
, v
.cfg
,
2900 &prog_data
->base
.base
.program_size
);