src/intel/compiler/brw_vec4_cse.cpp

   1 /*
   2  * Copyright © 2012, 2013, 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_vec4.h"
  25 #include "brw_vec4_live_variables.h"
  26 #include "brw_cfg.h"
  27
  28 using namespace brw;
  29
  30 /** @file brw_vec4_cse.cpp
  31  *
  32  * Support for local common subexpression elimination.
  33  *
  34  * See Muchnick's Advanced Compiler Design and Implementation, section
  35  * 13.1 (p378).
  36  */
  37
  38 namespace {
  39 struct aeb_entry : public exec_node {
  40    /** The instruction that generates the expression value. */
  41    vec4_instruction *generator;
  42
  43    /** The temporary where the value is stored. */
  44    src_reg tmp;
  45 };
  46 }
  47
  48 static bool
  49 is_expression(const vec4_instruction *const inst)
  50 {
  51    switch (inst->opcode) {
  52    case BRW_OPCODE_MOV:
  53    case BRW_OPCODE_SEL:
  54    case BRW_OPCODE_NOT:
  55    case BRW_OPCODE_AND:
  56    case BRW_OPCODE_OR:
  57    case BRW_OPCODE_XOR:
  58    case BRW_OPCODE_SHR:
  59    case BRW_OPCODE_SHL:
  60    case BRW_OPCODE_ASR:
  61    case BRW_OPCODE_CMP:
  62    case BRW_OPCODE_CMPN:
  63    case BRW_OPCODE_ADD:
  64    case BRW_OPCODE_MUL:
  65    case SHADER_OPCODE_MULH:
  66    case BRW_OPCODE_FRC:
  67    case BRW_OPCODE_RNDU:
  68    case BRW_OPCODE_RNDD:
  69    case BRW_OPCODE_RNDE:
  70    case BRW_OPCODE_RNDZ:
  71    case BRW_OPCODE_LINE:
  72    case BRW_OPCODE_PLN:
  73    case BRW_OPCODE_MAD:
  74    case BRW_OPCODE_LRP:
  75    case VEC4_OPCODE_UNPACK_UNIFORM:
  76    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
  77    case SHADER_OPCODE_BROADCAST:
  78    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
  79    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
  80       return true;
  81    case SHADER_OPCODE_RCP:
  82    case SHADER_OPCODE_RSQ:
  83    case SHADER_OPCODE_SQRT:
  84    case SHADER_OPCODE_EXP2:
  85    case SHADER_OPCODE_LOG2:
  86    case SHADER_OPCODE_POW:
  87    case SHADER_OPCODE_INT_QUOTIENT:
  88    case SHADER_OPCODE_INT_REMAINDER:
  89    case SHADER_OPCODE_SIN:
  90    case SHADER_OPCODE_COS:
  91       return inst->mlen == 0;
  92    default:
  93       return false;
  94    }
  95 }
  96
  97 static bool
  98 operands_match(const vec4_instruction *a, const vec4_instruction *b)
  99 {
 100    const src_reg *xs = a->src;
 101    const src_reg *ys = b->src;
 102
 103    if (a->opcode == BRW_OPCODE_MAD) {
 104       return xs[0].equals(ys[0]) &&
 105              ((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) ||
 106               (xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
 107    } else if (!a->is_commutative()) {
 108       return xs[0].equals(ys[0]) && xs[1].equals(ys[1]) && xs[2].equals(ys[2]);
 109    } else {
 110       return (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
 111              (xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
 112    }
 113 }
 114
 115 /**
 116  * Checks if instructions match, exactly for sources, but loosely for
 117  * destination writemasks.
 118  *
 119  * \param 'a' is the generating expression from the AEB entry.
 120  * \param 'b' is the second occurrence of the expression that we're
 121  *        considering eliminating.
 122  */
 123 static bool
 124 instructions_match(vec4_instruction *a, vec4_instruction *b)
 125 {
 126    return a->opcode == b->opcode &&
 127           a->saturate == b->saturate &&
 128           a->predicate == b->predicate &&
 129           a->predicate_inverse == b->predicate_inverse &&
 130           a->conditional_mod == b->conditional_mod &&
 131           a->flag_subreg == b->flag_subreg &&
 132           a->dst.type == b->dst.type &&
 133           a->offset == b->offset &&
 134           a->mlen == b->mlen &&
 135           a->base_mrf == b->base_mrf &&
 136           a->header_size == b->header_size &&
 137           a->shadow_compare == b->shadow_compare &&
 138           ((a->dst.writemask & b->dst.writemask) == a->dst.writemask) &&
 139           a->force_writemask_all == b->force_writemask_all &&
 140           a->size_written == b->size_written &&
 141           a->exec_size == b->exec_size &&
 142           a->group == b->group &&
 143           operands_match(a, b);
 144 }
 145
 146 bool
 147 vec4_visitor::opt_cse_local(bblock_t *block)
 148 {
 149    bool progress = false;
 150    exec_list aeb;
 151
 152    void *cse_ctx = ralloc_context(NULL);
 153
 154    int ip = block->start_ip;
 155    foreach_inst_in_block (vec4_instruction, inst, block) {
 156       /* Skip some cases. */
 157       if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
 158           ((inst->dst.file != ARF && inst->dst.file != FIXED_GRF) ||
 159            inst->dst.is_null()))
 160       {
 161          bool found = false;
 162
 163          foreach_in_list_use_after(aeb_entry, entry, &aeb) {
 164             /* Match current instruction's expression against those in AEB. */
 165             if (!(entry->generator->dst.is_null() && !inst->dst.is_null()) &&
 166                 instructions_match(inst, entry->generator)) {
 167                found = true;
 168                progress = true;
 169                break;
 170             }
 171          }
 172
 173          if (!found) {
 174             if (inst->opcode != BRW_OPCODE_MOV ||
 175                 (inst->opcode == BRW_OPCODE_MOV &&
 176                  inst->src[0].file == IMM &&
 177                  inst->src[0].type == BRW_REGISTER_TYPE_VF)) {
 178                /* Our first sighting of this expression.  Create an entry. */
 179                aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
 180                entry->tmp = src_reg(); /* file will be BAD_FILE */
 181                entry->generator = inst;
 182                aeb.push_tail(entry);
 183             }
 184          } else {
 185             /* This is at least our second sighting of this expression.
 186              * If we don't have a temporary already, make one.
 187              */
 188             bool no_existing_temp = entry->tmp.file == BAD_FILE;
 189             if (no_existing_temp && !entry->generator->dst.is_null()) {
 190                entry->tmp = retype(src_reg(VGRF, alloc.allocate(
 191                                               regs_written(entry->generator)),
 192                                            NULL), inst->dst.type);
 193
 194                const unsigned width = entry->generator->exec_size;
 195                unsigned component_size = width * type_sz(entry->tmp.type);
 196                unsigned num_copy_movs =
 197                   DIV_ROUND_UP(entry->generator->size_written, component_size);
 198                for (unsigned i = 0; i < num_copy_movs; ++i) {
 199                   vec4_instruction *copy =
 200                      MOV(offset(entry->generator->dst, width, i),
 201                          offset(entry->tmp, width, i));
 202                   copy->exec_size = width;
 203                   copy->group = entry->generator->group;
 204                   copy->force_writemask_all =
 205                      entry->generator->force_writemask_all;
 206                   entry->generator->insert_after(block, copy);
 207                }
 208
 209                entry->generator->dst = dst_reg(entry->tmp);
 210             }
 211
 212             /* dest <- temp */
 213             if (!inst->dst.is_null()) {
 214                assert(inst->dst.type == entry->tmp.type);
 215                const unsigned width = inst->exec_size;
 216                unsigned component_size = width * type_sz(inst->dst.type);
 217                unsigned num_copy_movs =
 218                   DIV_ROUND_UP(inst->size_written, component_size);
 219                for (unsigned i = 0; i < num_copy_movs; ++i) {
 220                   vec4_instruction *copy =
 221                      MOV(offset(inst->dst, width, i),
 222                          offset(entry->tmp, width, i));
 223                   copy->exec_size = inst->exec_size;
 224                   copy->group = inst->group;
 225                   copy->force_writemask_all = inst->force_writemask_all;
 226                   inst->insert_before(block, copy);
 227                }
 228             }
 229
 230             /* Set our iterator so that next time through the loop inst->next
 231              * will get the instruction in the basic block after the one we've
 232              * removed.
 233              */
 234             vec4_instruction *prev = (vec4_instruction *)inst->prev;
 235
 236             inst->remove(block);
 237             inst = prev;
 238          }
 239       }
 240
 241       foreach_in_list_safe(aeb_entry, entry, &aeb) {
 242          /* Kill all AEB entries that write a different value to or read from
 243           * the flag register if we just wrote it.
 244           */
 245          if (inst->writes_flag()) {
 246             if (entry->generator->reads_flag() ||
 247                 (entry->generator->writes_flag() &&
 248                  !instructions_match(inst, entry->generator))) {
 249                entry->remove();
 250                ralloc_free(entry);
 251                continue;
 252             }
 253          }
 254
 255          for (int i = 0; i < 3; i++) {
 256             src_reg *src = &entry->generator->src[i];
 257
 258             /* Kill all AEB entries that use the destination we just
 259              * overwrote.
 260              */
 261             if (inst->dst.file == entry->generator->src[i].file &&
 262                 inst->dst.nr == entry->generator->src[i].nr) {
 263                entry->remove();
 264                ralloc_free(entry);
 265                break;
 266             }
 267
 268             /* Kill any AEB entries using registers that don't get reused any
 269              * more -- a sure sign they'll fail operands_match().
 270              */
 271             if (src->file == VGRF) {
 272                if (var_range_end(var_from_reg(alloc, dst_reg(*src)), 8) < ip) {
 273                   entry->remove();
 274                   ralloc_free(entry);
 275                   break;
 276                }
 277             }
 278          }
 279       }
 280
 281       ip++;
 282    }
 283
 284    ralloc_free(cse_ctx);
 285
 286    return progress;
 287 }
 288
 289 bool
 290 vec4_visitor::opt_cse()
 291 {
 292    bool progress = false;
 293
 294    calculate_live_intervals();
 295
 296    foreach_block (block, cfg) {
 297       progress = opt_cse_local(block) || progress;
 298    }
 299
 300    if (progress)
 301       invalidate_live_intervals();
 302
 303    return progress;
 304 }