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[mesa.git] / src / intel / compiler / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25 #include "brw_eu.h"
26 #include "common/gen_debug.h"
27
28 using namespace brw;
29
30 static void
31 generate_math1_gen4(struct brw_codegen *p,
32 vec4_instruction *inst,
33 struct brw_reg dst,
34 struct brw_reg src)
35 {
36 gen4_math(p,
37 dst,
38 brw_math_function(inst->opcode),
39 inst->base_mrf,
40 src,
41 BRW_MATH_PRECISION_FULL);
42 }
43
44 static void
45 check_gen6_math_src_arg(struct brw_reg src)
46 {
47 /* Source swizzles are ignored. */
48 assert(!src.abs);
49 assert(!src.negate);
50 assert(src.swizzle == BRW_SWIZZLE_XYZW);
51 }
52
53 static void
54 generate_math_gen6(struct brw_codegen *p,
55 vec4_instruction *inst,
56 struct brw_reg dst,
57 struct brw_reg src0,
58 struct brw_reg src1)
59 {
60 /* Can't do writemask because math can't be align16. */
61 assert(dst.writemask == WRITEMASK_XYZW);
62 /* Source swizzles are ignored. */
63 check_gen6_math_src_arg(src0);
64 if (src1.file == BRW_GENERAL_REGISTER_FILE)
65 check_gen6_math_src_arg(src1);
66
67 brw_set_default_access_mode(p, BRW_ALIGN_1);
68 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
69 brw_set_default_access_mode(p, BRW_ALIGN_16);
70 }
71
72 static void
73 generate_math2_gen4(struct brw_codegen *p,
74 vec4_instruction *inst,
75 struct brw_reg dst,
76 struct brw_reg src0,
77 struct brw_reg src1)
78 {
79 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
80 * "Message Payload":
81 *
82 * "Operand0[7]. For the INT DIV functions, this operand is the
83 * denominator."
84 * ...
85 * "Operand1[7]. For the INT DIV functions, this operand is the
86 * numerator."
87 */
88 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
89 struct brw_reg &op0 = is_int_div ? src1 : src0;
90 struct brw_reg &op1 = is_int_div ? src0 : src1;
91
92 brw_push_insn_state(p);
93 brw_set_default_saturate(p, false);
94 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
95 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
96 brw_pop_insn_state(p);
97
98 gen4_math(p,
99 dst,
100 brw_math_function(inst->opcode),
101 inst->base_mrf,
102 op0,
103 BRW_MATH_PRECISION_FULL);
104 }
105
106 static void
107 generate_tex(struct brw_codegen *p,
108 struct brw_vue_prog_data *prog_data,
109 gl_shader_stage stage,
110 vec4_instruction *inst,
111 struct brw_reg dst,
112 struct brw_reg src,
113 struct brw_reg surface_index,
114 struct brw_reg sampler_index)
115 {
116 const struct gen_device_info *devinfo = p->devinfo;
117 int msg_type = -1;
118
119 if (devinfo->gen >= 5) {
120 switch (inst->opcode) {
121 case SHADER_OPCODE_TEX:
122 case SHADER_OPCODE_TXL:
123 if (inst->shadow_compare) {
124 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
125 } else {
126 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
127 }
128 break;
129 case SHADER_OPCODE_TXD:
130 if (inst->shadow_compare) {
131 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
132 assert(devinfo->gen >= 8 || devinfo->is_haswell);
133 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
134 } else {
135 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
136 }
137 break;
138 case SHADER_OPCODE_TXF:
139 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
140 break;
141 case SHADER_OPCODE_TXF_CMS_W:
142 assert(devinfo->gen >= 9);
143 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
144 break;
145 case SHADER_OPCODE_TXF_CMS:
146 if (devinfo->gen >= 7)
147 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
148 else
149 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
150 break;
151 case SHADER_OPCODE_TXF_MCS:
152 assert(devinfo->gen >= 7);
153 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
154 break;
155 case SHADER_OPCODE_TXS:
156 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
157 break;
158 case SHADER_OPCODE_TG4:
159 if (inst->shadow_compare) {
160 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
161 } else {
162 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
163 }
164 break;
165 case SHADER_OPCODE_TG4_OFFSET:
166 if (inst->shadow_compare) {
167 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
168 } else {
169 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
170 }
171 break;
172 case SHADER_OPCODE_SAMPLEINFO:
173 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
174 break;
175 default:
176 unreachable("should not get here: invalid vec4 texture opcode");
177 }
178 } else {
179 switch (inst->opcode) {
180 case SHADER_OPCODE_TEX:
181 case SHADER_OPCODE_TXL:
182 if (inst->shadow_compare) {
183 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
184 assert(inst->mlen == 3);
185 } else {
186 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
187 assert(inst->mlen == 2);
188 }
189 break;
190 case SHADER_OPCODE_TXD:
191 /* There is no sample_d_c message; comparisons are done manually. */
192 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
193 assert(inst->mlen == 4);
194 break;
195 case SHADER_OPCODE_TXF:
196 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
197 assert(inst->mlen == 2);
198 break;
199 case SHADER_OPCODE_TXS:
200 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
201 assert(inst->mlen == 2);
202 break;
203 default:
204 unreachable("should not get here: invalid vec4 texture opcode");
205 }
206 }
207
208 assert(msg_type != -1);
209
210 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
211
212 /* Load the message header if present. If there's a texture offset, we need
213 * to set it up explicitly and load the offset bitfield. Otherwise, we can
214 * use an implied move from g0 to the first message register.
215 */
216 if (inst->header_size != 0) {
217 if (devinfo->gen < 6 && !inst->offset) {
218 /* Set up an implied move from g0 to the MRF. */
219 src = brw_vec8_grf(0, 0);
220 } else {
221 struct brw_reg header =
222 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
223 uint32_t dw2 = 0;
224
225 /* Explicitly set up the message header by copying g0 to the MRF. */
226 brw_push_insn_state(p);
227 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
228 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
229
230 brw_set_default_access_mode(p, BRW_ALIGN_1);
231
232 if (inst->offset)
233 /* Set the texel offset bits in DWord 2. */
234 dw2 = inst->offset;
235
236 if (devinfo->gen >= 9)
237 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
238 * based on bit 22 in the header.
239 */
240 dw2 |= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2;
241
242 /* The VS, DS, and FS stages have the g0.2 payload delivered as 0,
243 * so header0.2 is 0 when g0 is copied. The HS and GS stages do
244 * not, so we must set to to 0 to avoid setting undesirable bits
245 * in the message header.
246 */
247 if (dw2 ||
248 stage == MESA_SHADER_TESS_CTRL ||
249 stage == MESA_SHADER_GEOMETRY) {
250 brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
251 }
252
253 brw_adjust_sampler_state_pointer(p, header, sampler_index);
254 brw_pop_insn_state(p);
255 }
256 }
257
258 uint32_t return_format;
259
260 switch (dst.type) {
261 case BRW_REGISTER_TYPE_D:
262 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
263 break;
264 case BRW_REGISTER_TYPE_UD:
265 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
266 break;
267 default:
268 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
269 break;
270 }
271
272 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
273 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
274 ? prog_data->base.binding_table.gather_texture_start
275 : prog_data->base.binding_table.texture_start;
276
277 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
278 sampler_index.file == BRW_IMMEDIATE_VALUE) {
279 uint32_t surface = surface_index.ud;
280 uint32_t sampler = sampler_index.ud;
281
282 brw_SAMPLE(p,
283 dst,
284 inst->base_mrf,
285 src,
286 surface + base_binding_table_index,
287 sampler % 16,
288 msg_type,
289 1, /* response length */
290 inst->mlen,
291 inst->header_size != 0,
292 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
293 return_format);
294
295 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
296 } else {
297 /* Non-constant sampler index. */
298
299 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
300 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
301 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
302
303 brw_push_insn_state(p);
304 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
305 brw_set_default_access_mode(p, BRW_ALIGN_1);
306
307 if (brw_regs_equal(&surface_reg, &sampler_reg)) {
308 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
309 } else {
310 if (sampler_reg.file == BRW_IMMEDIATE_VALUE) {
311 brw_OR(p, addr, surface_reg, brw_imm_ud(sampler_reg.ud << 8));
312 } else {
313 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
314 brw_OR(p, addr, addr, surface_reg);
315 }
316 }
317 if (base_binding_table_index)
318 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
319 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
320
321 brw_pop_insn_state(p);
322
323 if (inst->base_mrf != -1)
324 gen6_resolve_implied_move(p, &src, inst->base_mrf);
325
326 /* dst = send(offset, a0.0 | <descriptor>) */
327 brw_send_indirect_message(
328 p, BRW_SFID_SAMPLER, dst, src, addr,
329 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
330 brw_sampler_desc(devinfo,
331 0 /* surface */,
332 0 /* sampler */,
333 msg_type,
334 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
335 return_format));
336
337 /* visitor knows more than we do about the surface limit required,
338 * so has already done marking.
339 */
340 }
341 }
342
343 static void
344 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
345 {
346 brw_urb_WRITE(p,
347 brw_null_reg(), /* dest */
348 inst->base_mrf, /* starting mrf reg nr */
349 brw_vec8_grf(0, 0), /* src */
350 inst->urb_write_flags,
351 inst->mlen,
352 0, /* response len */
353 inst->offset, /* urb destination offset */
354 BRW_URB_SWIZZLE_INTERLEAVE);
355 }
356
357 static void
358 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
359 {
360 struct brw_reg src = brw_message_reg(inst->base_mrf);
361 brw_urb_WRITE(p,
362 brw_null_reg(), /* dest */
363 inst->base_mrf, /* starting mrf reg nr */
364 src,
365 inst->urb_write_flags,
366 inst->mlen,
367 0, /* response len */
368 inst->offset, /* urb destination offset */
369 BRW_URB_SWIZZLE_INTERLEAVE);
370 }
371
372 static void
373 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst)
374 {
375 struct brw_reg src = brw_message_reg(inst->base_mrf);
376
377 /* We pass the temporary passed in src0 as the writeback register */
378 brw_urb_WRITE(p,
379 inst->src[0].as_brw_reg(), /* dest */
380 inst->base_mrf, /* starting mrf reg nr */
381 src,
382 BRW_URB_WRITE_ALLOCATE_COMPLETE,
383 inst->mlen,
384 1, /* response len */
385 inst->offset, /* urb destination offset */
386 BRW_URB_SWIZZLE_INTERLEAVE);
387
388 /* Now put allocated urb handle in dst.0 */
389 brw_push_insn_state(p);
390 brw_set_default_access_mode(p, BRW_ALIGN_1);
391 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
392 brw_MOV(p, get_element_ud(inst->dst.as_brw_reg(), 0),
393 get_element_ud(inst->src[0].as_brw_reg(), 0));
394 brw_pop_insn_state(p);
395 }
396
397 static void
398 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
399 {
400 struct brw_reg src = brw_message_reg(inst->base_mrf);
401 brw_urb_WRITE(p,
402 brw_null_reg(), /* dest */
403 inst->base_mrf, /* starting mrf reg nr */
404 src,
405 BRW_URB_WRITE_EOT | inst->urb_write_flags,
406 inst->mlen,
407 0, /* response len */
408 0, /* urb destination offset */
409 BRW_URB_SWIZZLE_INTERLEAVE);
410 }
411
412 static void
413 generate_gs_set_write_offset(struct brw_codegen *p,
414 struct brw_reg dst,
415 struct brw_reg src0,
416 struct brw_reg src1)
417 {
418 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
419 * Header: M0.3):
420 *
421 * Slot 0 Offset. This field, after adding to the Global Offset field
422 * in the message descriptor, specifies the offset (in 256-bit units)
423 * from the start of the URB entry, as referenced by URB Handle 0, at
424 * which the data will be accessed.
425 *
426 * Similar text describes DWORD M0.4, which is slot 1 offset.
427 *
428 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
429 * of the register for geometry shader invocations 0 and 1) by the
430 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
431 *
432 * We can do this with the following EU instruction:
433 *
434 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
435 */
436 brw_push_insn_state(p);
437 brw_set_default_access_mode(p, BRW_ALIGN_1);
438 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
439 assert(p->devinfo->gen >= 7 &&
440 src1.file == BRW_IMMEDIATE_VALUE &&
441 src1.type == BRW_REGISTER_TYPE_UD &&
442 src1.ud <= USHRT_MAX);
443 if (src0.file == BRW_IMMEDIATE_VALUE) {
444 brw_MOV(p, suboffset(stride(dst, 2, 2, 1), 3),
445 brw_imm_ud(src0.ud * src1.ud));
446 } else {
447 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
448 retype(src1, BRW_REGISTER_TYPE_UW));
449 }
450 brw_pop_insn_state(p);
451 }
452
453 static void
454 generate_gs_set_vertex_count(struct brw_codegen *p,
455 struct brw_reg dst,
456 struct brw_reg src)
457 {
458 brw_push_insn_state(p);
459 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
460
461 if (p->devinfo->gen >= 8) {
462 /* Move the vertex count into the second MRF for the EOT write. */
463 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
464 src);
465 } else {
466 /* If we think of the src and dst registers as composed of 8 DWORDs each,
467 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
468 * them to WORDs, and then pack them into DWORD 2 of dst.
469 *
470 * It's easier to get the EU to do this if we think of the src and dst
471 * registers as composed of 16 WORDS each; then, we want to pick up the
472 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
473 * of dst.
474 *
475 * We can do that by the following EU instruction:
476 *
477 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
478 */
479 brw_set_default_access_mode(p, BRW_ALIGN_1);
480 brw_MOV(p,
481 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
482 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
483 }
484 brw_pop_insn_state(p);
485 }
486
487 static void
488 generate_gs_svb_write(struct brw_codegen *p,
489 struct brw_vue_prog_data *prog_data,
490 vec4_instruction *inst,
491 struct brw_reg dst,
492 struct brw_reg src0,
493 struct brw_reg src1)
494 {
495 int binding = inst->sol_binding;
496 bool final_write = inst->sol_final_write;
497
498 brw_push_insn_state(p);
499 brw_set_default_exec_size(p, BRW_EXECUTE_4);
500 /* Copy Vertex data into M0.x */
501 brw_MOV(p, stride(dst, 4, 4, 1),
502 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
503 brw_pop_insn_state(p);
504
505 brw_push_insn_state(p);
506 /* Send SVB Write */
507 brw_svb_write(p,
508 final_write ? src1 : brw_null_reg(), /* dest == src1 */
509 1, /* msg_reg_nr */
510 dst, /* src0 == previous dst */
511 BRW_GEN6_SOL_BINDING_START + binding, /* binding_table_index */
512 final_write); /* send_commit_msg */
513
514 /* Finally, wait for the write commit to occur so that we can proceed to
515 * other things safely.
516 *
517 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
518 *
519 * The write commit does not modify the destination register, but
520 * merely clears the dependency associated with the destination
521 * register. Thus, a simple “mov” instruction using the register as a
522 * source is sufficient to wait for the write commit to occur.
523 */
524 if (final_write) {
525 brw_MOV(p, src1, src1);
526 }
527 brw_pop_insn_state(p);
528 }
529
530 static void
531 generate_gs_svb_set_destination_index(struct brw_codegen *p,
532 vec4_instruction *inst,
533 struct brw_reg dst,
534 struct brw_reg src)
535 {
536 int vertex = inst->sol_vertex;
537 brw_push_insn_state(p);
538 brw_set_default_access_mode(p, BRW_ALIGN_1);
539 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
540 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
541 brw_pop_insn_state(p);
542 }
543
544 static void
545 generate_gs_set_dword_2(struct brw_codegen *p,
546 struct brw_reg dst,
547 struct brw_reg src)
548 {
549 brw_push_insn_state(p);
550 brw_set_default_access_mode(p, BRW_ALIGN_1);
551 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
552 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
553 brw_pop_insn_state(p);
554 }
555
556 static void
557 generate_gs_prepare_channel_masks(struct brw_codegen *p,
558 struct brw_reg dst)
559 {
560 /* We want to left shift just DWORD 4 (the x component belonging to the
561 * second geometry shader invocation) by 4 bits. So generate the
562 * instruction:
563 *
564 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
565 */
566 dst = suboffset(vec1(dst), 4);
567 brw_push_insn_state(p);
568 brw_set_default_access_mode(p, BRW_ALIGN_1);
569 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
570 brw_SHL(p, dst, dst, brw_imm_ud(4));
571 brw_pop_insn_state(p);
572 }
573
574 static void
575 generate_gs_set_channel_masks(struct brw_codegen *p,
576 struct brw_reg dst,
577 struct brw_reg src)
578 {
579 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
580 * Header: M0.5):
581 *
582 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
583 *
584 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
585 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
586 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
587 * channel enable to determine the final channel enable. For the
588 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
589 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
590 * in the writeback message. For the URB_WRITE_OWORD &
591 * URB_WRITE_HWORD messages, when final channel enable is 1 it
592 * indicates that Vertex 1 DATA [3] will be written to the surface.
593 *
594 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
595 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
596 *
597 * 14 Vertex 1 DATA [2] Channel Mask
598 * 13 Vertex 1 DATA [1] Channel Mask
599 * 12 Vertex 1 DATA [0] Channel Mask
600 * 11 Vertex 0 DATA [3] Channel Mask
601 * 10 Vertex 0 DATA [2] Channel Mask
602 * 9 Vertex 0 DATA [1] Channel Mask
603 * 8 Vertex 0 DATA [0] Channel Mask
604 *
605 * (This is from a section of the PRM that is agnostic to the particular
606 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
607 * geometry shader invocations 0 and 1, respectively). Since we have the
608 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
609 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
610 * DWORD 4, we just need to OR them together and store the result in bits
611 * 15:8 of DWORD 5.
612 *
613 * It's easier to get the EU to do this if we think of the src and dst
614 * registers as composed of 32 bytes each; then, we want to pick up the
615 * contents of bytes 0 and 16 from src, OR them together, and store them in
616 * byte 21.
617 *
618 * We can do that by the following EU instruction:
619 *
620 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
621 *
622 * Note: this relies on the source register having zeros in (a) bits 7:4 of
623 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
624 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
625 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
626 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
627 * contain valid channel mask values (which are in the range 0x0-0xf).
628 */
629 dst = retype(dst, BRW_REGISTER_TYPE_UB);
630 src = retype(src, BRW_REGISTER_TYPE_UB);
631 brw_push_insn_state(p);
632 brw_set_default_access_mode(p, BRW_ALIGN_1);
633 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
634 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
635 brw_pop_insn_state(p);
636 }
637
638 static void
639 generate_gs_get_instance_id(struct brw_codegen *p,
640 struct brw_reg dst)
641 {
642 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
643 * and store into dst.0 & dst.4. So generate the instruction:
644 *
645 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
646 */
647 brw_push_insn_state(p);
648 brw_set_default_access_mode(p, BRW_ALIGN_1);
649 dst = retype(dst, BRW_REGISTER_TYPE_UD);
650 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
651 brw_SHR(p, dst, stride(r0, 1, 4, 0),
652 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
653 brw_pop_insn_state(p);
654 }
655
656 static void
657 generate_gs_ff_sync_set_primitives(struct brw_codegen *p,
658 struct brw_reg dst,
659 struct brw_reg src0,
660 struct brw_reg src1,
661 struct brw_reg src2)
662 {
663 brw_push_insn_state(p);
664 brw_set_default_access_mode(p, BRW_ALIGN_1);
665 /* Save src0 data in 16:31 bits of dst.0 */
666 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
667 brw_imm_ud(0xffffu));
668 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
669 /* Save src1 data in 0:15 bits of dst.0 */
670 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
671 brw_imm_ud(0xffffu));
672 brw_OR(p, suboffset(vec1(dst), 0),
673 suboffset(vec1(dst), 0),
674 suboffset(vec1(src2), 0));
675 brw_pop_insn_state(p);
676 }
677
678 static void
679 generate_gs_ff_sync(struct brw_codegen *p,
680 vec4_instruction *inst,
681 struct brw_reg dst,
682 struct brw_reg src0,
683 struct brw_reg src1)
684 {
685 /* This opcode uses an implied MRF register for:
686 * - the header of the ff_sync message. And as such it is expected to be
687 * initialized to r0 before calling here.
688 * - the destination where we will write the allocated URB handle.
689 */
690 struct brw_reg header =
691 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
692
693 /* Overwrite dword 0 of the header (SO vertices to write) and
694 * dword 1 (number of primitives written).
695 */
696 brw_push_insn_state(p);
697 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
698 brw_set_default_access_mode(p, BRW_ALIGN_1);
699 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
700 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
701 brw_pop_insn_state(p);
702
703 /* Allocate URB handle in dst */
704 brw_ff_sync(p,
705 dst,
706 0,
707 header,
708 1, /* allocate */
709 1, /* response length */
710 0 /* eot */);
711
712 /* Now put allocated urb handle in header.0 */
713 brw_push_insn_state(p);
714 brw_set_default_access_mode(p, BRW_ALIGN_1);
715 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
716 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
717
718 /* src1 is not an immediate when we use transform feedback */
719 if (src1.file != BRW_IMMEDIATE_VALUE) {
720 brw_set_default_exec_size(p, BRW_EXECUTE_4);
721 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
722 }
723
724 brw_pop_insn_state(p);
725 }
726
727 static void
728 generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst)
729 {
730 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
731 struct brw_reg src = brw_vec8_grf(0, 0);
732 brw_push_insn_state(p);
733 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
734 brw_set_default_access_mode(p, BRW_ALIGN_1);
735 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
736 brw_pop_insn_state(p);
737 }
738
739 static void
740 generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst)
741 {
742 const struct gen_device_info *devinfo = p->devinfo;
743 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
744
745 /* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
746 *
747 * Since we operate in SIMD4x2 mode, we need run half as many threads
748 * as necessary. So we assign (2i + 1, 2i) as the thread counts. We
749 * shift right by one less to accomplish the multiplication by two.
750 */
751 dst = retype(dst, BRW_REGISTER_TYPE_UD);
752 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
753
754 brw_push_insn_state(p);
755 brw_set_default_access_mode(p, BRW_ALIGN_1);
756
757 const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
758 const int shift = ivb ? 16 : 17;
759
760 brw_AND(p, get_element_ud(dst, 0), get_element_ud(r0, 2), brw_imm_ud(mask));
761 brw_SHR(p, get_element_ud(dst, 0), get_element_ud(dst, 0),
762 brw_imm_ud(shift - 1));
763 brw_ADD(p, get_element_ud(dst, 4), get_element_ud(dst, 0), brw_imm_ud(1));
764
765 brw_pop_insn_state(p);
766 }
767
768 static void
769 generate_tcs_urb_write(struct brw_codegen *p,
770 vec4_instruction *inst,
771 struct brw_reg urb_header)
772 {
773 const struct gen_device_info *devinfo = p->devinfo;
774
775 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
776 brw_set_dest(p, send, brw_null_reg());
777 brw_set_src0(p, send, urb_header);
778 brw_set_desc(p, send, brw_message_desc(devinfo, inst->mlen, 0, true));
779
780 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
781 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_WRITE_OWORD);
782 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
783 if (inst->urb_write_flags & BRW_URB_WRITE_EOT) {
784 brw_inst_set_eot(devinfo, send, 1);
785 } else {
786 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
787 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
788 }
789
790 /* what happens to swizzles? */
791 }
792
793
794 static void
795 generate_tcs_input_urb_offsets(struct brw_codegen *p,
796 struct brw_reg dst,
797 struct brw_reg vertex,
798 struct brw_reg offset)
799 {
800 /* Generates an URB read/write message header for HS/DS operation.
801 * Inputs are a vertex index, and a byte offset from the beginning of
802 * the vertex. */
803
804 /* If `vertex` is not an immediate, we clobber a0.0 */
805
806 assert(vertex.file == BRW_IMMEDIATE_VALUE || vertex.file == BRW_GENERAL_REGISTER_FILE);
807 assert(vertex.type == BRW_REGISTER_TYPE_UD || vertex.type == BRW_REGISTER_TYPE_D);
808
809 assert(dst.file == BRW_GENERAL_REGISTER_FILE);
810
811 brw_push_insn_state(p);
812 brw_set_default_access_mode(p, BRW_ALIGN_1);
813 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
814 brw_MOV(p, dst, brw_imm_ud(0));
815
816 /* m0.5 bits 8-15 are channel enables */
817 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
818
819 /* m0.0-0.1: URB handles */
820 if (vertex.file == BRW_IMMEDIATE_VALUE) {
821 uint32_t vertex_index = vertex.ud;
822 struct brw_reg index_reg = brw_vec1_grf(
823 1 + (vertex_index >> 3), vertex_index & 7);
824
825 brw_MOV(p, vec2(get_element_ud(dst, 0)),
826 retype(index_reg, BRW_REGISTER_TYPE_UD));
827 } else {
828 /* Use indirect addressing. ICP Handles are DWords (single channels
829 * of a register) and start at g1.0.
830 *
831 * In order to start our region at g1.0, we add 8 to the vertex index,
832 * effectively skipping over the 8 channels in g0.0. This gives us a
833 * DWord offset to the ICP Handle.
834 *
835 * Indirect addressing works in terms of bytes, so we then multiply
836 * the DWord offset by 4 (by shifting left by 2).
837 */
838 struct brw_reg addr = brw_address_reg(0);
839
840 /* bottom half: m0.0 = g[1.0 + vertex.0]UD */
841 brw_ADD(p, addr, retype(get_element_ud(vertex, 0), BRW_REGISTER_TYPE_UW),
842 brw_imm_uw(0x8));
843 brw_SHL(p, addr, addr, brw_imm_uw(2));
844 brw_MOV(p, get_element_ud(dst, 0), deref_1ud(brw_indirect(0, 0), 0));
845
846 /* top half: m0.1 = g[1.0 + vertex.4]UD */
847 brw_ADD(p, addr, retype(get_element_ud(vertex, 4), BRW_REGISTER_TYPE_UW),
848 brw_imm_uw(0x8));
849 brw_SHL(p, addr, addr, brw_imm_uw(2));
850 brw_MOV(p, get_element_ud(dst, 1), deref_1ud(brw_indirect(0, 0), 0));
851 }
852
853 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
854 if (offset.file != ARF)
855 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
856
857 brw_pop_insn_state(p);
858 }
859
860
861 static void
862 generate_tcs_output_urb_offsets(struct brw_codegen *p,
863 struct brw_reg dst,
864 struct brw_reg write_mask,
865 struct brw_reg offset)
866 {
867 /* Generates an URB read/write message header for HS/DS operation, for the patch URB entry. */
868 assert(dst.file == BRW_GENERAL_REGISTER_FILE || dst.file == BRW_MESSAGE_REGISTER_FILE);
869
870 assert(write_mask.file == BRW_IMMEDIATE_VALUE);
871 assert(write_mask.type == BRW_REGISTER_TYPE_UD);
872
873 brw_push_insn_state(p);
874
875 brw_set_default_access_mode(p, BRW_ALIGN_1);
876 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
877 brw_MOV(p, dst, brw_imm_ud(0));
878
879 unsigned mask = write_mask.ud;
880
881 /* m0.5 bits 15:12 and 11:8 are channel enables */
882 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud((mask << 8) | (mask << 12)));
883
884 /* HS patch URB handle is delivered in r0.0 */
885 struct brw_reg urb_handle = brw_vec1_grf(0, 0);
886
887 /* m0.0-0.1: URB handles */
888 brw_MOV(p, vec2(get_element_ud(dst, 0)),
889 retype(urb_handle, BRW_REGISTER_TYPE_UD));
890
891 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
892 if (offset.file != ARF)
893 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
894
895 brw_pop_insn_state(p);
896 }
897
898 static void
899 generate_tes_create_input_read_header(struct brw_codegen *p,
900 struct brw_reg dst)
901 {
902 brw_push_insn_state(p);
903 brw_set_default_access_mode(p, BRW_ALIGN_1);
904 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
905
906 /* Initialize the register to 0 */
907 brw_MOV(p, dst, brw_imm_ud(0));
908
909 /* Enable all the channels in m0.5 bits 15:8 */
910 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
911
912 /* Copy g1.3 (the patch URB handle) to m0.0 and m0.1. For safety,
913 * mask out irrelevant "Reserved" bits, as they're not marked MBZ.
914 */
915 brw_AND(p, vec2(get_element_ud(dst, 0)),
916 retype(brw_vec1_grf(1, 3), BRW_REGISTER_TYPE_UD),
917 brw_imm_ud(0x1fff));
918 brw_pop_insn_state(p);
919 }
920
921 static void
922 generate_tes_add_indirect_urb_offset(struct brw_codegen *p,
923 struct brw_reg dst,
924 struct brw_reg header,
925 struct brw_reg offset)
926 {
927 brw_push_insn_state(p);
928 brw_set_default_access_mode(p, BRW_ALIGN_1);
929 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
930
931 brw_MOV(p, dst, header);
932 /* m0.3-0.4: 128-bit-granular offsets into the URB from the handles */
933 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
934
935 brw_pop_insn_state(p);
936 }
937
938 static void
939 generate_vec4_urb_read(struct brw_codegen *p,
940 vec4_instruction *inst,
941 struct brw_reg dst,
942 struct brw_reg header)
943 {
944 const struct gen_device_info *devinfo = p->devinfo;
945
946 assert(header.file == BRW_GENERAL_REGISTER_FILE);
947 assert(header.type == BRW_REGISTER_TYPE_UD);
948
949 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
950 brw_set_dest(p, send, dst);
951 brw_set_src0(p, send, header);
952
953 brw_set_desc(p, send, brw_message_desc(devinfo, 1, 1, true));
954
955 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
956 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
957 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
958 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
959
960 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
961 }
962
963 static void
964 generate_tcs_release_input(struct brw_codegen *p,
965 struct brw_reg header,
966 struct brw_reg vertex,
967 struct brw_reg is_unpaired)
968 {
969 const struct gen_device_info *devinfo = p->devinfo;
970
971 assert(vertex.file == BRW_IMMEDIATE_VALUE);
972 assert(vertex.type == BRW_REGISTER_TYPE_UD);
973
974 /* m0.0-0.1: URB handles */
975 struct brw_reg urb_handles =
976 retype(brw_vec2_grf(1 + (vertex.ud >> 3), vertex.ud & 7),
977 BRW_REGISTER_TYPE_UD);
978
979 brw_push_insn_state(p);
980 brw_set_default_access_mode(p, BRW_ALIGN_1);
981 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
982 brw_MOV(p, header, brw_imm_ud(0));
983 brw_MOV(p, vec2(get_element_ud(header, 0)), urb_handles);
984 brw_pop_insn_state(p);
985
986 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
987 brw_set_dest(p, send, brw_null_reg());
988 brw_set_src0(p, send, header);
989 brw_set_desc(p, send, brw_message_desc(devinfo, 1, 0, true));
990
991 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
992 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
993 brw_inst_set_urb_complete(devinfo, send, 1);
994 brw_inst_set_urb_swizzle_control(devinfo, send, is_unpaired.ud ?
995 BRW_URB_SWIZZLE_NONE :
996 BRW_URB_SWIZZLE_INTERLEAVE);
997 }
998
999 static void
1000 generate_tcs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
1001 {
1002 struct brw_reg header = brw_message_reg(inst->base_mrf);
1003
1004 brw_push_insn_state(p);
1005 brw_set_default_access_mode(p, BRW_ALIGN_1);
1006 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1007 brw_MOV(p, header, brw_imm_ud(0));
1008 brw_MOV(p, get_element_ud(header, 5), brw_imm_ud(WRITEMASK_X << 8));
1009 brw_MOV(p, get_element_ud(header, 0),
1010 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD));
1011 brw_MOV(p, brw_message_reg(inst->base_mrf + 1), brw_imm_ud(0u));
1012 brw_pop_insn_state(p);
1013
1014 brw_urb_WRITE(p,
1015 brw_null_reg(), /* dest */
1016 inst->base_mrf, /* starting mrf reg nr */
1017 header,
1018 BRW_URB_WRITE_EOT | BRW_URB_WRITE_OWORD |
1019 BRW_URB_WRITE_USE_CHANNEL_MASKS,
1020 inst->mlen,
1021 0, /* response len */
1022 0, /* urb destination offset */
1023 0);
1024 }
1025
1026 static void
1027 generate_tes_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
1028 {
1029 brw_push_insn_state(p);
1030 brw_set_default_access_mode(p, BRW_ALIGN_1);
1031 brw_MOV(p, dst, retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_D));
1032 brw_pop_insn_state(p);
1033 }
1034
1035 static void
1036 generate_tcs_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
1037 {
1038 brw_push_insn_state(p);
1039 brw_set_default_access_mode(p, BRW_ALIGN_1);
1040 brw_MOV(p, dst, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD));
1041 brw_pop_insn_state(p);
1042 }
1043
1044 static void
1045 generate_tcs_create_barrier_header(struct brw_codegen *p,
1046 struct brw_vue_prog_data *prog_data,
1047 struct brw_reg dst)
1048 {
1049 const struct gen_device_info *devinfo = p->devinfo;
1050 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
1051 struct brw_reg m0_2 = get_element_ud(dst, 2);
1052 unsigned instances = ((struct brw_tcs_prog_data *) prog_data)->instances;
1053
1054 brw_push_insn_state(p);
1055 brw_set_default_access_mode(p, BRW_ALIGN_1);
1056 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1057
1058 /* Zero the message header */
1059 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u));
1060
1061 /* Copy "Barrier ID" from r0.2, bits 16:13 (Gen7.5+) or 15:12 (Gen7) */
1062 brw_AND(p, m0_2,
1063 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
1064 brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13)));
1065
1066 /* Shift it up to bits 27:24. */
1067 brw_SHL(p, m0_2, get_element_ud(dst, 2), brw_imm_ud(ivb ? 12 : 11));
1068
1069 /* Set the Barrier Count and the enable bit */
1070 brw_OR(p, m0_2, m0_2, brw_imm_ud(instances << 9 | (1 << 15)));
1071
1072 brw_pop_insn_state(p);
1073 }
1074
1075 static void
1076 generate_oword_dual_block_offsets(struct brw_codegen *p,
1077 struct brw_reg m1,
1078 struct brw_reg index)
1079 {
1080 int second_vertex_offset;
1081
1082 if (p->devinfo->gen >= 6)
1083 second_vertex_offset = 1;
1084 else
1085 second_vertex_offset = 16;
1086
1087 m1 = retype(m1, BRW_REGISTER_TYPE_D);
1088
1089 /* Set up M1 (message payload). Only the block offsets in M1.0 and
1090 * M1.4 are used, and the rest are ignored.
1091 */
1092 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
1093 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
1094 struct brw_reg index_0 = suboffset(vec1(index), 0);
1095 struct brw_reg index_4 = suboffset(vec1(index), 4);
1096
1097 brw_push_insn_state(p);
1098 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1099 brw_set_default_access_mode(p, BRW_ALIGN_1);
1100
1101 brw_MOV(p, m1_0, index_0);
1102
1103 if (index.file == BRW_IMMEDIATE_VALUE) {
1104 index_4.ud += second_vertex_offset;
1105 brw_MOV(p, m1_4, index_4);
1106 } else {
1107 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
1108 }
1109
1110 brw_pop_insn_state(p);
1111 }
1112
1113 static void
1114 generate_unpack_flags(struct brw_codegen *p,
1115 struct brw_reg dst)
1116 {
1117 brw_push_insn_state(p);
1118 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1119 brw_set_default_access_mode(p, BRW_ALIGN_1);
1120
1121 struct brw_reg flags = brw_flag_reg(0, 0);
1122 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
1123 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
1124
1125 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
1126 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
1127 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
1128
1129 brw_pop_insn_state(p);
1130 }
1131
1132 static void
1133 generate_scratch_read(struct brw_codegen *p,
1134 vec4_instruction *inst,
1135 struct brw_reg dst,
1136 struct brw_reg index)
1137 {
1138 const struct gen_device_info *devinfo = p->devinfo;
1139 struct brw_reg header = brw_vec8_grf(0, 0);
1140
1141 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1142
1143 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1144 index);
1145
1146 uint32_t msg_type;
1147
1148 if (devinfo->gen >= 6)
1149 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1150 else if (devinfo->gen == 5 || devinfo->is_g4x)
1151 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1152 else
1153 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1154
1155 const unsigned target_cache =
1156 devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
1157 devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
1158 BRW_DATAPORT_READ_TARGET_RENDER_CACHE;
1159
1160 /* Each of the 8 channel enables is considered for whether each
1161 * dword is written.
1162 */
1163 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1164 brw_set_dest(p, send, dst);
1165 brw_set_src0(p, send, header);
1166 if (devinfo->gen < 6)
1167 brw_inst_set_cond_modifier(devinfo, send, inst->base_mrf);
1168 brw_set_dp_read_message(p, send,
1169 brw_scratch_surface_idx(p),
1170 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1171 msg_type, target_cache,
1172 2, /* mlen */
1173 true, /* header_present */
1174 1 /* rlen */);
1175 }
1176
1177 static void
1178 generate_scratch_write(struct brw_codegen *p,
1179 vec4_instruction *inst,
1180 struct brw_reg dst,
1181 struct brw_reg src,
1182 struct brw_reg index)
1183 {
1184 const struct gen_device_info *devinfo = p->devinfo;
1185 const unsigned target_cache =
1186 (devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
1187 devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
1188 BRW_DATAPORT_READ_TARGET_RENDER_CACHE);
1189 struct brw_reg header = brw_vec8_grf(0, 0);
1190 bool write_commit;
1191
1192 /* If the instruction is predicated, we'll predicate the send, not
1193 * the header setup.
1194 */
1195 brw_set_default_predicate_control(p, false);
1196
1197 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1198
1199 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1200 index);
1201
1202 brw_MOV(p,
1203 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
1204 retype(src, BRW_REGISTER_TYPE_D));
1205
1206 uint32_t msg_type;
1207
1208 if (devinfo->gen >= 7)
1209 msg_type = GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
1210 else if (devinfo->gen == 6)
1211 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1212 else
1213 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1214
1215 brw_set_default_predicate_control(p, inst->predicate);
1216
1217 /* Pre-gen6, we have to specify write commits to ensure ordering
1218 * between reads and writes within a thread. Afterwards, that's
1219 * guaranteed and write commits only matter for inter-thread
1220 * synchronization.
1221 */
1222 if (devinfo->gen >= 6) {
1223 write_commit = false;
1224 } else {
1225 /* The visitor set up our destination register to be g0. This
1226 * means that when the next read comes along, we will end up
1227 * reading from g0 and causing a block on the write commit. For
1228 * write-after-read, we are relying on the value of the previous
1229 * read being used (and thus blocking on completion) before our
1230 * write is executed. This means we have to be careful in
1231 * instruction scheduling to not violate this assumption.
1232 */
1233 write_commit = true;
1234 }
1235
1236 /* Each of the 8 channel enables is considered for whether each
1237 * dword is written.
1238 */
1239 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1240 brw_set_dest(p, send, dst);
1241 brw_set_src0(p, send, header);
1242 if (devinfo->gen < 6)
1243 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1244 brw_set_dp_write_message(p, send,
1245 brw_scratch_surface_idx(p),
1246 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1247 msg_type,
1248 target_cache,
1249 3, /* mlen */
1250 true, /* header present */
1251 false, /* not a render target write */
1252 write_commit, /* rlen */
1253 false, /* eot */
1254 write_commit);
1255 }
1256
1257 static void
1258 generate_pull_constant_load(struct brw_codegen *p,
1259 struct brw_vue_prog_data *prog_data,
1260 vec4_instruction *inst,
1261 struct brw_reg dst,
1262 struct brw_reg index,
1263 struct brw_reg offset)
1264 {
1265 const struct gen_device_info *devinfo = p->devinfo;
1266 const unsigned target_cache =
1267 (devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_SAMPLER_CACHE :
1268 BRW_DATAPORT_READ_TARGET_DATA_CACHE);
1269 assert(index.file == BRW_IMMEDIATE_VALUE &&
1270 index.type == BRW_REGISTER_TYPE_UD);
1271 uint32_t surf_index = index.ud;
1272
1273 struct brw_reg header = brw_vec8_grf(0, 0);
1274
1275 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1276
1277 if (devinfo->gen >= 6) {
1278 if (offset.file == BRW_IMMEDIATE_VALUE) {
1279 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1280 BRW_REGISTER_TYPE_D),
1281 brw_imm_d(offset.ud >> 4));
1282 } else {
1283 brw_SHR(p, retype(brw_message_reg(inst->base_mrf + 1),
1284 BRW_REGISTER_TYPE_D),
1285 offset, brw_imm_d(4));
1286 }
1287 } else {
1288 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1289 BRW_REGISTER_TYPE_D),
1290 offset);
1291 }
1292
1293 uint32_t msg_type;
1294
1295 if (devinfo->gen >= 6)
1296 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1297 else if (devinfo->gen == 5 || devinfo->is_g4x)
1298 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1299 else
1300 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1301
1302 /* Each of the 8 channel enables is considered for whether each
1303 * dword is written.
1304 */
1305 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1306 brw_set_dest(p, send, dst);
1307 brw_set_src0(p, send, header);
1308 if (devinfo->gen < 6)
1309 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1310 brw_set_dp_read_message(p, send,
1311 surf_index,
1312 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1313 msg_type,
1314 target_cache,
1315 2, /* mlen */
1316 true, /* header_present */
1317 1 /* rlen */);
1318 }
1319
1320 static void
1321 generate_get_buffer_size(struct brw_codegen *p,
1322 struct brw_vue_prog_data *prog_data,
1323 vec4_instruction *inst,
1324 struct brw_reg dst,
1325 struct brw_reg src,
1326 struct brw_reg surf_index)
1327 {
1328 assert(p->devinfo->gen >= 7);
1329 assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
1330 surf_index.file == BRW_IMMEDIATE_VALUE);
1331
1332 brw_SAMPLE(p,
1333 dst,
1334 inst->base_mrf,
1335 src,
1336 surf_index.ud,
1337 0,
1338 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
1339 1, /* response length */
1340 inst->mlen,
1341 inst->header_size > 0,
1342 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1343 BRW_SAMPLER_RETURN_FORMAT_SINT32);
1344
1345 brw_mark_surface_used(&prog_data->base, surf_index.ud);
1346 }
1347
1348 static void
1349 generate_pull_constant_load_gen7(struct brw_codegen *p,
1350 struct brw_vue_prog_data *prog_data,
1351 vec4_instruction *inst,
1352 struct brw_reg dst,
1353 struct brw_reg surf_index,
1354 struct brw_reg offset)
1355 {
1356 const struct gen_device_info *devinfo = p->devinfo;
1357 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1358
1359 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1360
1361 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1362 brw_inst_set_sfid(devinfo, insn, BRW_SFID_SAMPLER);
1363 brw_set_dest(p, insn, dst);
1364 brw_set_src0(p, insn, offset);
1365 brw_set_desc(p, insn,
1366 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
1367 brw_sampler_desc(devinfo, surf_index.ud,
1368 0, /* LD message ignores sampler unit */
1369 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1370 BRW_SAMPLER_SIMD_MODE_SIMD4X2, 0));
1371
1372 brw_mark_surface_used(&prog_data->base, surf_index.ud);
1373
1374 } else {
1375
1376 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1377
1378 brw_push_insn_state(p);
1379 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1380 brw_set_default_access_mode(p, BRW_ALIGN_1);
1381
1382 /* a0.0 = surf_index & 0xff */
1383 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1384 brw_inst_set_exec_size(devinfo, insn_and, BRW_EXECUTE_1);
1385 brw_set_dest(p, insn_and, addr);
1386 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1387 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1388
1389 brw_pop_insn_state(p);
1390
1391 /* dst = send(offset, a0.0 | <descriptor>) */
1392 brw_send_indirect_message(
1393 p, BRW_SFID_SAMPLER, dst, offset, addr,
1394 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
1395 brw_sampler_desc(devinfo,
1396 0 /* surface */,
1397 0 /* sampler */,
1398 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1399 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1400 0));
1401 }
1402 }
1403
1404 static void
1405 generate_set_simd4x2_header_gen9(struct brw_codegen *p,
1406 vec4_instruction *,
1407 struct brw_reg dst)
1408 {
1409 brw_push_insn_state(p);
1410 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1411
1412 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1413 brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1414
1415 brw_set_default_access_mode(p, BRW_ALIGN_1);
1416 brw_MOV(p, get_element_ud(dst, 2),
1417 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1418
1419 brw_pop_insn_state(p);
1420 }
1421
1422 static void
1423 generate_mov_indirect(struct brw_codegen *p,
1424 vec4_instruction *,
1425 struct brw_reg dst, struct brw_reg reg,
1426 struct brw_reg indirect)
1427 {
1428 assert(indirect.type == BRW_REGISTER_TYPE_UD);
1429 assert(p->devinfo->gen >= 6);
1430
1431 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr * (REG_SIZE / 2);
1432
1433 /* This instruction acts in align1 mode */
1434 assert(dst.writemask == WRITEMASK_XYZW);
1435
1436 if (indirect.file == BRW_IMMEDIATE_VALUE) {
1437 imm_byte_offset += indirect.ud;
1438
1439 reg.nr = imm_byte_offset / REG_SIZE;
1440 reg.subnr = (imm_byte_offset / (REG_SIZE / 2)) % 2;
1441 unsigned shift = (imm_byte_offset / 4) % 4;
1442 reg.swizzle += BRW_SWIZZLE4(shift, shift, shift, shift);
1443
1444 brw_MOV(p, dst, reg);
1445 } else {
1446 brw_push_insn_state(p);
1447 brw_set_default_access_mode(p, BRW_ALIGN_1);
1448 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1449
1450 struct brw_reg addr = vec8(brw_address_reg(0));
1451
1452 /* We need to move the indirect value into the address register. In
1453 * order to make things make some sense, we want to respect at least the
1454 * X component of the swizzle. In order to do that, we need to convert
1455 * the subnr (probably 0) to an align1 subnr and add in the swizzle.
1456 */
1457 assert(brw_is_single_value_swizzle(indirect.swizzle));
1458 indirect.subnr = (indirect.subnr * 4 + BRW_GET_SWZ(indirect.swizzle, 0));
1459
1460 /* We then use a region of <8,4,0>:uw to pick off the first 2 bytes of
1461 * the indirect and splat it out to all four channels of the given half
1462 * of a0.
1463 */
1464 indirect.subnr *= 2;
1465 indirect = stride(retype(indirect, BRW_REGISTER_TYPE_UW), 8, 4, 0);
1466 brw_ADD(p, addr, indirect, brw_imm_uw(imm_byte_offset));
1467
1468 /* Now we need to incorporate the swizzle from the source register */
1469 if (reg.swizzle != BRW_SWIZZLE_XXXX) {
1470 uint32_t uv_swiz = BRW_GET_SWZ(reg.swizzle, 0) << 2 |
1471 BRW_GET_SWZ(reg.swizzle, 1) << 6 |
1472 BRW_GET_SWZ(reg.swizzle, 2) << 10 |
1473 BRW_GET_SWZ(reg.swizzle, 3) << 14;
1474 uv_swiz |= uv_swiz << 16;
1475
1476 brw_ADD(p, addr, addr, brw_imm_uv(uv_swiz));
1477 }
1478
1479 brw_MOV(p, dst, retype(brw_VxH_indirect(0, 0), reg.type));
1480
1481 brw_pop_insn_state(p);
1482 }
1483 }
1484
1485 static void
1486 generate_code(struct brw_codegen *p,
1487 const struct brw_compiler *compiler,
1488 void *log_data,
1489 const nir_shader *nir,
1490 struct brw_vue_prog_data *prog_data,
1491 const struct cfg_t *cfg)
1492 {
1493 const struct gen_device_info *devinfo = p->devinfo;
1494 const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->info.stage);
1495 bool debug_flag = INTEL_DEBUG &
1496 intel_debug_flag_for_shader_stage(nir->info.stage);
1497 struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);
1498 int spill_count = 0, fill_count = 0;
1499 int loop_count = 0;
1500
1501 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1502 struct brw_reg src[3], dst;
1503
1504 if (unlikely(debug_flag))
1505 disasm_annotate(disasm_info, inst, p->next_insn_offset);
1506
1507 for (unsigned int i = 0; i < 3; i++) {
1508 src[i] = inst->src[i].as_brw_reg();
1509 }
1510 dst = inst->dst.as_brw_reg();
1511
1512 brw_set_default_predicate_control(p, inst->predicate);
1513 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1514 brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2);
1515 brw_set_default_saturate(p, inst->saturate);
1516 brw_set_default_mask_control(p, inst->force_writemask_all);
1517 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1518
1519 assert(inst->group % inst->exec_size == 0);
1520 assert(inst->group % 4 == 0);
1521
1522 /* There are some instructions where the destination is 64-bit
1523 * but we retype it to a smaller type. In that case, we cannot
1524 * double the exec_size.
1525 */
1526 const bool is_df = (get_exec_type_size(inst) == 8 ||
1527 inst->dst.type == BRW_REGISTER_TYPE_DF) &&
1528 inst->opcode != VEC4_OPCODE_PICK_LOW_32BIT &&
1529 inst->opcode != VEC4_OPCODE_PICK_HIGH_32BIT &&
1530 inst->opcode != VEC4_OPCODE_SET_LOW_32BIT &&
1531 inst->opcode != VEC4_OPCODE_SET_HIGH_32BIT;
1532
1533 unsigned exec_size = inst->exec_size;
1534 if (devinfo->gen == 7 && !devinfo->is_haswell && is_df)
1535 exec_size *= 2;
1536
1537 brw_set_default_exec_size(p, cvt(exec_size) - 1);
1538
1539 if (!inst->force_writemask_all)
1540 brw_set_default_group(p, inst->group);
1541
1542 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1543 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1544
1545 unsigned pre_emit_nr_insn = p->nr_insn;
1546
1547 switch (inst->opcode) {
1548 case VEC4_OPCODE_UNPACK_UNIFORM:
1549 case BRW_OPCODE_MOV:
1550 brw_MOV(p, dst, src[0]);
1551 break;
1552 case BRW_OPCODE_ADD:
1553 brw_ADD(p, dst, src[0], src[1]);
1554 break;
1555 case BRW_OPCODE_MUL:
1556 brw_MUL(p, dst, src[0], src[1]);
1557 break;
1558 case BRW_OPCODE_MACH:
1559 brw_MACH(p, dst, src[0], src[1]);
1560 break;
1561
1562 case BRW_OPCODE_MAD:
1563 assert(devinfo->gen >= 6);
1564 brw_MAD(p, dst, src[0], src[1], src[2]);
1565 break;
1566
1567 case BRW_OPCODE_FRC:
1568 brw_FRC(p, dst, src[0]);
1569 break;
1570 case BRW_OPCODE_RNDD:
1571 brw_RNDD(p, dst, src[0]);
1572 break;
1573 case BRW_OPCODE_RNDE:
1574 brw_RNDE(p, dst, src[0]);
1575 break;
1576 case BRW_OPCODE_RNDZ:
1577 brw_RNDZ(p, dst, src[0]);
1578 break;
1579
1580 case BRW_OPCODE_AND:
1581 brw_AND(p, dst, src[0], src[1]);
1582 break;
1583 case BRW_OPCODE_OR:
1584 brw_OR(p, dst, src[0], src[1]);
1585 break;
1586 case BRW_OPCODE_XOR:
1587 brw_XOR(p, dst, src[0], src[1]);
1588 break;
1589 case BRW_OPCODE_NOT:
1590 brw_NOT(p, dst, src[0]);
1591 break;
1592 case BRW_OPCODE_ASR:
1593 brw_ASR(p, dst, src[0], src[1]);
1594 break;
1595 case BRW_OPCODE_SHR:
1596 brw_SHR(p, dst, src[0], src[1]);
1597 break;
1598 case BRW_OPCODE_SHL:
1599 brw_SHL(p, dst, src[0], src[1]);
1600 break;
1601
1602 case BRW_OPCODE_CMP:
1603 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1604 break;
1605 case BRW_OPCODE_SEL:
1606 brw_SEL(p, dst, src[0], src[1]);
1607 break;
1608
1609 case BRW_OPCODE_DPH:
1610 brw_DPH(p, dst, src[0], src[1]);
1611 break;
1612
1613 case BRW_OPCODE_DP4:
1614 brw_DP4(p, dst, src[0], src[1]);
1615 break;
1616
1617 case BRW_OPCODE_DP3:
1618 brw_DP3(p, dst, src[0], src[1]);
1619 break;
1620
1621 case BRW_OPCODE_DP2:
1622 brw_DP2(p, dst, src[0], src[1]);
1623 break;
1624
1625 case BRW_OPCODE_F32TO16:
1626 assert(devinfo->gen >= 7);
1627 brw_F32TO16(p, dst, src[0]);
1628 break;
1629
1630 case BRW_OPCODE_F16TO32:
1631 assert(devinfo->gen >= 7);
1632 brw_F16TO32(p, dst, src[0]);
1633 break;
1634
1635 case BRW_OPCODE_LRP:
1636 assert(devinfo->gen >= 6);
1637 brw_LRP(p, dst, src[0], src[1], src[2]);
1638 break;
1639
1640 case BRW_OPCODE_BFREV:
1641 assert(devinfo->gen >= 7);
1642 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1643 retype(src[0], BRW_REGISTER_TYPE_UD));
1644 break;
1645 case BRW_OPCODE_FBH:
1646 assert(devinfo->gen >= 7);
1647 brw_FBH(p, retype(dst, src[0].type), src[0]);
1648 break;
1649 case BRW_OPCODE_FBL:
1650 assert(devinfo->gen >= 7);
1651 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD),
1652 retype(src[0], BRW_REGISTER_TYPE_UD));
1653 break;
1654 case BRW_OPCODE_LZD:
1655 brw_LZD(p, dst, src[0]);
1656 break;
1657 case BRW_OPCODE_CBIT:
1658 assert(devinfo->gen >= 7);
1659 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD),
1660 retype(src[0], BRW_REGISTER_TYPE_UD));
1661 break;
1662 case BRW_OPCODE_ADDC:
1663 assert(devinfo->gen >= 7);
1664 brw_ADDC(p, dst, src[0], src[1]);
1665 break;
1666 case BRW_OPCODE_SUBB:
1667 assert(devinfo->gen >= 7);
1668 brw_SUBB(p, dst, src[0], src[1]);
1669 break;
1670 case BRW_OPCODE_MAC:
1671 brw_MAC(p, dst, src[0], src[1]);
1672 break;
1673
1674 case BRW_OPCODE_BFE:
1675 assert(devinfo->gen >= 7);
1676 brw_BFE(p, dst, src[0], src[1], src[2]);
1677 break;
1678
1679 case BRW_OPCODE_BFI1:
1680 assert(devinfo->gen >= 7);
1681 brw_BFI1(p, dst, src[0], src[1]);
1682 break;
1683 case BRW_OPCODE_BFI2:
1684 assert(devinfo->gen >= 7);
1685 brw_BFI2(p, dst, src[0], src[1], src[2]);
1686 break;
1687
1688 case BRW_OPCODE_IF:
1689 if (!inst->src[0].is_null()) {
1690 /* The instruction has an embedded compare (only allowed on gen6) */
1691 assert(devinfo->gen == 6);
1692 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1693 } else {
1694 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1695 brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate);
1696 }
1697 break;
1698
1699 case BRW_OPCODE_ELSE:
1700 brw_ELSE(p);
1701 break;
1702 case BRW_OPCODE_ENDIF:
1703 brw_ENDIF(p);
1704 break;
1705
1706 case BRW_OPCODE_DO:
1707 brw_DO(p, BRW_EXECUTE_8);
1708 break;
1709
1710 case BRW_OPCODE_BREAK:
1711 brw_BREAK(p);
1712 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1713 break;
1714 case BRW_OPCODE_CONTINUE:
1715 brw_CONT(p);
1716 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1717 break;
1718
1719 case BRW_OPCODE_WHILE:
1720 brw_WHILE(p);
1721 loop_count++;
1722 break;
1723
1724 case SHADER_OPCODE_RCP:
1725 case SHADER_OPCODE_RSQ:
1726 case SHADER_OPCODE_SQRT:
1727 case SHADER_OPCODE_EXP2:
1728 case SHADER_OPCODE_LOG2:
1729 case SHADER_OPCODE_SIN:
1730 case SHADER_OPCODE_COS:
1731 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1732 if (devinfo->gen >= 7) {
1733 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1734 brw_null_reg());
1735 } else if (devinfo->gen == 6) {
1736 generate_math_gen6(p, inst, dst, src[0], brw_null_reg());
1737 } else {
1738 generate_math1_gen4(p, inst, dst, src[0]);
1739 }
1740 break;
1741
1742 case SHADER_OPCODE_POW:
1743 case SHADER_OPCODE_INT_QUOTIENT:
1744 case SHADER_OPCODE_INT_REMAINDER:
1745 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1746 if (devinfo->gen >= 7) {
1747 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1748 } else if (devinfo->gen == 6) {
1749 generate_math_gen6(p, inst, dst, src[0], src[1]);
1750 } else {
1751 generate_math2_gen4(p, inst, dst, src[0], src[1]);
1752 }
1753 break;
1754
1755 case SHADER_OPCODE_TEX:
1756 case SHADER_OPCODE_TXD:
1757 case SHADER_OPCODE_TXF:
1758 case SHADER_OPCODE_TXF_CMS:
1759 case SHADER_OPCODE_TXF_CMS_W:
1760 case SHADER_OPCODE_TXF_MCS:
1761 case SHADER_OPCODE_TXL:
1762 case SHADER_OPCODE_TXS:
1763 case SHADER_OPCODE_TG4:
1764 case SHADER_OPCODE_TG4_OFFSET:
1765 case SHADER_OPCODE_SAMPLEINFO:
1766 generate_tex(p, prog_data, nir->info.stage,
1767 inst, dst, src[0], src[1], src[2]);
1768 break;
1769
1770 case SHADER_OPCODE_GET_BUFFER_SIZE:
1771 generate_get_buffer_size(p, prog_data, inst, dst, src[0], src[1]);
1772 break;
1773
1774 case VS_OPCODE_URB_WRITE:
1775 generate_vs_urb_write(p, inst);
1776 break;
1777
1778 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1779 generate_scratch_read(p, inst, dst, src[0]);
1780 fill_count++;
1781 break;
1782
1783 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1784 generate_scratch_write(p, inst, dst, src[0], src[1]);
1785 spill_count++;
1786 break;
1787
1788 case VS_OPCODE_PULL_CONSTANT_LOAD:
1789 generate_pull_constant_load(p, prog_data, inst, dst, src[0], src[1]);
1790 break;
1791
1792 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1793 generate_pull_constant_load_gen7(p, prog_data, inst, dst, src[0], src[1]);
1794 break;
1795
1796 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
1797 generate_set_simd4x2_header_gen9(p, inst, dst);
1798 break;
1799
1800 case GS_OPCODE_URB_WRITE:
1801 generate_gs_urb_write(p, inst);
1802 break;
1803
1804 case GS_OPCODE_URB_WRITE_ALLOCATE:
1805 generate_gs_urb_write_allocate(p, inst);
1806 break;
1807
1808 case GS_OPCODE_SVB_WRITE:
1809 generate_gs_svb_write(p, prog_data, inst, dst, src[0], src[1]);
1810 break;
1811
1812 case GS_OPCODE_SVB_SET_DST_INDEX:
1813 generate_gs_svb_set_destination_index(p, inst, dst, src[0]);
1814 break;
1815
1816 case GS_OPCODE_THREAD_END:
1817 generate_gs_thread_end(p, inst);
1818 break;
1819
1820 case GS_OPCODE_SET_WRITE_OFFSET:
1821 generate_gs_set_write_offset(p, dst, src[0], src[1]);
1822 break;
1823
1824 case GS_OPCODE_SET_VERTEX_COUNT:
1825 generate_gs_set_vertex_count(p, dst, src[0]);
1826 break;
1827
1828 case GS_OPCODE_FF_SYNC:
1829 generate_gs_ff_sync(p, inst, dst, src[0], src[1]);
1830 break;
1831
1832 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1833 generate_gs_ff_sync_set_primitives(p, dst, src[0], src[1], src[2]);
1834 break;
1835
1836 case GS_OPCODE_SET_PRIMITIVE_ID:
1837 generate_gs_set_primitive_id(p, dst);
1838 break;
1839
1840 case GS_OPCODE_SET_DWORD_2:
1841 generate_gs_set_dword_2(p, dst, src[0]);
1842 break;
1843
1844 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1845 generate_gs_prepare_channel_masks(p, dst);
1846 break;
1847
1848 case GS_OPCODE_SET_CHANNEL_MASKS:
1849 generate_gs_set_channel_masks(p, dst, src[0]);
1850 break;
1851
1852 case GS_OPCODE_GET_INSTANCE_ID:
1853 generate_gs_get_instance_id(p, dst);
1854 break;
1855
1856 case SHADER_OPCODE_SHADER_TIME_ADD:
1857 brw_shader_time_add(p, src[0],
1858 prog_data->base.binding_table.shader_time_start);
1859 brw_mark_surface_used(&prog_data->base,
1860 prog_data->base.binding_table.shader_time_start);
1861 break;
1862
1863 case SHADER_OPCODE_UNTYPED_ATOMIC:
1864 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1865 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1866 !inst->dst.is_null(), inst->header_size);
1867 break;
1868
1869 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1870 assert(!inst->header_size);
1871 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1872 brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
1873 src[2].ud);
1874 break;
1875
1876 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1877 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1878 brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
1879 src[2].ud, inst->header_size);
1880 break;
1881
1882 case SHADER_OPCODE_TYPED_ATOMIC:
1883 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1884 brw_typed_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1885 !inst->dst.is_null(), inst->header_size);
1886 break;
1887
1888 case SHADER_OPCODE_TYPED_SURFACE_READ:
1889 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1890 brw_typed_surface_read(p, dst, src[0], src[1], inst->mlen,
1891 src[2].ud, inst->header_size);
1892 break;
1893
1894 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1895 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1896 brw_typed_surface_write(p, src[0], src[1], inst->mlen,
1897 src[2].ud, inst->header_size);
1898 break;
1899
1900 case SHADER_OPCODE_MEMORY_FENCE:
1901 brw_memory_fence(p, dst, BRW_OPCODE_SEND);
1902 break;
1903
1904 case SHADER_OPCODE_FIND_LIVE_CHANNEL: {
1905 const struct brw_reg mask =
1906 brw_stage_has_packed_dispatch(devinfo, nir->info.stage,
1907 &prog_data->base) ? brw_imm_ud(~0u) :
1908 brw_dmask_reg();
1909 brw_find_live_channel(p, dst, mask);
1910 break;
1911 }
1912
1913 case SHADER_OPCODE_BROADCAST:
1914 assert(inst->force_writemask_all);
1915 brw_broadcast(p, dst, src[0], src[1]);
1916 break;
1917
1918 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1919 generate_unpack_flags(p, dst);
1920 break;
1921
1922 case VEC4_OPCODE_MOV_BYTES: {
1923 /* Moves the low byte from each channel, using an Align1 access mode
1924 * and a <4,1,0> source region.
1925 */
1926 assert(src[0].type == BRW_REGISTER_TYPE_UB ||
1927 src[0].type == BRW_REGISTER_TYPE_B);
1928
1929 brw_set_default_access_mode(p, BRW_ALIGN_1);
1930 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1931 src[0].width = BRW_WIDTH_1;
1932 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1933 brw_MOV(p, dst, src[0]);
1934 brw_set_default_access_mode(p, BRW_ALIGN_16);
1935 break;
1936 }
1937
1938 case VEC4_OPCODE_DOUBLE_TO_F32:
1939 case VEC4_OPCODE_DOUBLE_TO_D32:
1940 case VEC4_OPCODE_DOUBLE_TO_U32: {
1941 assert(type_sz(src[0].type) == 8);
1942 assert(type_sz(dst.type) == 8);
1943
1944 brw_reg_type dst_type;
1945
1946 switch (inst->opcode) {
1947 case VEC4_OPCODE_DOUBLE_TO_F32:
1948 dst_type = BRW_REGISTER_TYPE_F;
1949 break;
1950 case VEC4_OPCODE_DOUBLE_TO_D32:
1951 dst_type = BRW_REGISTER_TYPE_D;
1952 break;
1953 case VEC4_OPCODE_DOUBLE_TO_U32:
1954 dst_type = BRW_REGISTER_TYPE_UD;
1955 break;
1956 default:
1957 unreachable("Not supported conversion");
1958 }
1959 dst = retype(dst, dst_type);
1960
1961 brw_set_default_access_mode(p, BRW_ALIGN_1);
1962
1963 /* When converting from DF->F, we set destination's stride as 2 as an
1964 * aligment requirement. But in IVB/BYT, each DF implicitly writes
1965 * two floats, being the first one the converted value. So we don't
1966 * need to explicitly set stride 2, but 1.
1967 */
1968 struct brw_reg spread_dst;
1969 if (devinfo->gen == 7 && !devinfo->is_haswell)
1970 spread_dst = stride(dst, 8, 4, 1);
1971 else
1972 spread_dst = stride(dst, 8, 4, 2);
1973
1974 brw_MOV(p, spread_dst, src[0]);
1975
1976 brw_set_default_access_mode(p, BRW_ALIGN_16);
1977 break;
1978 }
1979
1980 case VEC4_OPCODE_TO_DOUBLE: {
1981 assert(type_sz(src[0].type) == 4);
1982 assert(type_sz(dst.type) == 8);
1983
1984 brw_set_default_access_mode(p, BRW_ALIGN_1);
1985
1986 brw_MOV(p, dst, src[0]);
1987
1988 brw_set_default_access_mode(p, BRW_ALIGN_16);
1989 break;
1990 }
1991
1992 case VEC4_OPCODE_PICK_LOW_32BIT:
1993 case VEC4_OPCODE_PICK_HIGH_32BIT: {
1994 /* Stores the low/high 32-bit of each 64-bit element in src[0] into
1995 * dst using ALIGN1 mode and a <8,4,2>:UD region on the source.
1996 */
1997 assert(type_sz(src[0].type) == 8);
1998 assert(type_sz(dst.type) == 4);
1999
2000 brw_set_default_access_mode(p, BRW_ALIGN_1);
2001
2002 dst = retype(dst, BRW_REGISTER_TYPE_UD);
2003 dst.hstride = BRW_HORIZONTAL_STRIDE_1;
2004
2005 src[0] = retype(src[0], BRW_REGISTER_TYPE_UD);
2006 if (inst->opcode == VEC4_OPCODE_PICK_HIGH_32BIT)
2007 src[0] = suboffset(src[0], 1);
2008 src[0] = spread(src[0], 2);
2009 brw_MOV(p, dst, src[0]);
2010
2011 brw_set_default_access_mode(p, BRW_ALIGN_16);
2012 break;
2013 }
2014
2015 case VEC4_OPCODE_SET_LOW_32BIT:
2016 case VEC4_OPCODE_SET_HIGH_32BIT: {
2017 /* Reads consecutive 32-bit elements from src[0] and writes
2018 * them to the low/high 32-bit of each 64-bit element in dst.
2019 */
2020 assert(type_sz(src[0].type) == 4);
2021 assert(type_sz(dst.type) == 8);
2022
2023 brw_set_default_access_mode(p, BRW_ALIGN_1);
2024
2025 dst = retype(dst, BRW_REGISTER_TYPE_UD);
2026 if (inst->opcode == VEC4_OPCODE_SET_HIGH_32BIT)
2027 dst = suboffset(dst, 1);
2028 dst.hstride = BRW_HORIZONTAL_STRIDE_2;
2029
2030 src[0] = retype(src[0], BRW_REGISTER_TYPE_UD);
2031 brw_MOV(p, dst, src[0]);
2032
2033 brw_set_default_access_mode(p, BRW_ALIGN_16);
2034 break;
2035 }
2036
2037 case VEC4_OPCODE_PACK_BYTES: {
2038 /* Is effectively:
2039 *
2040 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
2041 *
2042 * but destinations' only regioning is horizontal stride, so instead we
2043 * have to use two instructions:
2044 *
2045 * mov(4) dst<1>:UB src<4,1,0>:UB
2046 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
2047 *
2048 * where they pack the four bytes from the low and high four DW.
2049 */
2050 assert(_mesa_is_pow_two(dst.writemask) &&
2051 dst.writemask != 0);
2052 unsigned offset = __builtin_ctz(dst.writemask);
2053
2054 dst.type = BRW_REGISTER_TYPE_UB;
2055
2056 brw_set_default_access_mode(p, BRW_ALIGN_1);
2057
2058 src[0].type = BRW_REGISTER_TYPE_UB;
2059 src[0].vstride = BRW_VERTICAL_STRIDE_4;
2060 src[0].width = BRW_WIDTH_1;
2061 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
2062 dst.subnr = offset * 4;
2063 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
2064 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
2065 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
2066 brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check);
2067
2068 src[0].subnr = 16;
2069 dst.subnr = 16 + offset * 4;
2070 insn = brw_MOV(p, dst, src[0]);
2071 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
2072 brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear);
2073 brw_inst_set_no_dd_check(p->devinfo, insn, true);
2074
2075 brw_set_default_access_mode(p, BRW_ALIGN_16);
2076 break;
2077 }
2078
2079 case TCS_OPCODE_URB_WRITE:
2080 generate_tcs_urb_write(p, inst, src[0]);
2081 break;
2082
2083 case VEC4_OPCODE_URB_READ:
2084 generate_vec4_urb_read(p, inst, dst, src[0]);
2085 break;
2086
2087 case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
2088 generate_tcs_input_urb_offsets(p, dst, src[0], src[1]);
2089 break;
2090
2091 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
2092 generate_tcs_output_urb_offsets(p, dst, src[0], src[1]);
2093 break;
2094
2095 case TCS_OPCODE_GET_INSTANCE_ID:
2096 generate_tcs_get_instance_id(p, dst);
2097 break;
2098
2099 case TCS_OPCODE_GET_PRIMITIVE_ID:
2100 generate_tcs_get_primitive_id(p, dst);
2101 break;
2102
2103 case TCS_OPCODE_CREATE_BARRIER_HEADER:
2104 generate_tcs_create_barrier_header(p, prog_data, dst);
2105 break;
2106
2107 case TES_OPCODE_CREATE_INPUT_READ_HEADER:
2108 generate_tes_create_input_read_header(p, dst);
2109 break;
2110
2111 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
2112 generate_tes_add_indirect_urb_offset(p, dst, src[0], src[1]);
2113 break;
2114
2115 case TES_OPCODE_GET_PRIMITIVE_ID:
2116 generate_tes_get_primitive_id(p, dst);
2117 break;
2118
2119 case TCS_OPCODE_SRC0_010_IS_ZERO:
2120 /* If src_reg had stride like fs_reg, we wouldn't need this. */
2121 brw_MOV(p, brw_null_reg(), stride(src[0], 0, 1, 0));
2122 break;
2123
2124 case TCS_OPCODE_RELEASE_INPUT:
2125 generate_tcs_release_input(p, dst, src[0], src[1]);
2126 break;
2127
2128 case TCS_OPCODE_THREAD_END:
2129 generate_tcs_thread_end(p, inst);
2130 break;
2131
2132 case SHADER_OPCODE_BARRIER:
2133 brw_barrier(p, src[0]);
2134 brw_WAIT(p);
2135 break;
2136
2137 case SHADER_OPCODE_MOV_INDIRECT:
2138 generate_mov_indirect(p, inst, dst, src[0], src[1]);
2139 break;
2140
2141 case BRW_OPCODE_DIM:
2142 assert(devinfo->is_haswell);
2143 assert(src[0].type == BRW_REGISTER_TYPE_DF);
2144 assert(dst.type == BRW_REGISTER_TYPE_DF);
2145 brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
2146 break;
2147
2148 default:
2149 unreachable("Unsupported opcode");
2150 }
2151
2152 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
2153 /* Handled dependency hints in the generator. */
2154
2155 assert(!inst->conditional_mod);
2156 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2157 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
2158 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2159 "emitting more than 1 instruction");
2160
2161 brw_inst *last = &p->store[pre_emit_nr_insn];
2162
2163 if (inst->conditional_mod)
2164 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2165 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2166 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2167 }
2168 }
2169
2170 brw_set_uip_jip(p, 0);
2171
2172 /* end of program sentinel */
2173 disasm_new_inst_group(disasm_info, p->next_insn_offset);
2174
2175 #ifndef NDEBUG
2176 bool validated =
2177 #else
2178 if (unlikely(debug_flag))
2179 #endif
2180 brw_validate_instructions(devinfo, p->store,
2181 0, p->next_insn_offset,
2182 disasm_info);
2183
2184 int before_size = p->next_insn_offset;
2185 brw_compact_instructions(p, 0, disasm_info);
2186 int after_size = p->next_insn_offset;
2187
2188 if (unlikely(debug_flag)) {
2189 fprintf(stderr, "Native code for %s %s shader %s:\n",
2190 nir->info.label ? nir->info.label : "unnamed",
2191 _mesa_shader_stage_to_string(nir->info.stage), nir->info.name);
2192
2193 fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles. %d:%d "
2194 "spills:fills. Compacted %d to %d bytes (%.0f%%)\n",
2195 stage_abbrev, before_size / 16, loop_count, cfg->cycle_count,
2196 spill_count, fill_count, before_size, after_size,
2197 100.0f * (before_size - after_size) / before_size);
2198
2199 dump_assembly(p->store, disasm_info);
2200 }
2201 ralloc_free(disasm_info);
2202 assert(validated);
2203
2204 compiler->shader_debug_log(log_data,
2205 "%s vec4 shader: %d inst, %d loops, %u cycles, "
2206 "%d:%d spills:fills, compacted %d to %d bytes.",
2207 stage_abbrev, before_size / 16,
2208 loop_count, cfg->cycle_count, spill_count,
2209 fill_count, before_size, after_size);
2210
2211 }
2212
2213 extern "C" const unsigned *
2214 brw_vec4_generate_assembly(const struct brw_compiler *compiler,
2215 void *log_data,
2216 void *mem_ctx,
2217 const nir_shader *nir,
2218 struct brw_vue_prog_data *prog_data,
2219 const struct cfg_t *cfg)
2220 {
2221 struct brw_codegen *p = rzalloc(mem_ctx, struct brw_codegen);
2222 brw_init_codegen(compiler->devinfo, p, mem_ctx);
2223 brw_set_default_access_mode(p, BRW_ALIGN_16);
2224
2225 generate_code(p, compiler, log_data, nir, prog_data, cfg);
2226
2227 return brw_get_program(p, &prog_data->base.program_size);
2228 }